?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ide: add ->dma_clear method and remove ->dma_timeout one
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ide / au1xxx-ide.c
blob0c08c5e01f2aadd8030cb86f4fa5f55a0aafa9f5
1 /*
2 * BRIEF MODULE DESCRIPTION
3 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
4 *
5 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option) any later
10 * version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
13 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
14 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
15 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
16 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
17 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
18 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
19 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
21 * POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along with
24 * this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
28 * Interface and Linux Device Driver" Application Note.
29 */
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/ide.h>
37 #include <linux/scatterlist.h>
38
39 #include <asm/mach-au1x00/au1xxx.h>
40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
41 #include <asm/mach-au1x00/au1xxx_ide.h>
42
43 #define DRV_NAME "au1200-ide"
44 #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
45
46 /* enable the burstmode in the dbdma */
47 #define IDE_AU1XXX_BURSTMODE 1
48
49 static _auide_hwif auide_hwif;
50
51 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
52
53 void auide_insw(unsigned long port, void *addr, u32 count)
54 {
55 _auide_hwif *ahwif = &auide_hwif;
56 chan_tab_t *ctp;
57 au1x_ddma_desc_t *dp;
58
59 if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
60 DDMA_FLAGS_NOIE)) {
61 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
62 return;
63 }
64 ctp = *((chan_tab_t **)ahwif->rx_chan);
65 dp = ctp->cur_ptr;
66 while (dp->dscr_cmd0 & DSCR_CMD0_V)
67 ;
68 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
69 }
70
71 void auide_outsw(unsigned long port, void *addr, u32 count)
72 {
73 _auide_hwif *ahwif = &auide_hwif;
74 chan_tab_t *ctp;
75 au1x_ddma_desc_t *dp;
76
77 if(!put_source_flags(ahwif->tx_chan, (void*)addr,
78 count << 1, DDMA_FLAGS_NOIE)) {
79 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
80 return;
81 }
82 ctp = *((chan_tab_t **)ahwif->tx_chan);
83 dp = ctp->cur_ptr;
84 while (dp->dscr_cmd0 & DSCR_CMD0_V)
85 ;
86 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
87 }
88
89 static void au1xxx_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
90 void *buf, unsigned int len)
91 {
92 auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
93 }
94
95 static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
96 void *buf, unsigned int len)
97 {
98 auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
99 }
100 #endif
101
102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
103 {
104 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
105
106 /* set pio mode! */
107 switch(pio) {
108 case 0:
109 mem_sttime = SBC_IDE_TIMING(PIO0);
110
111 /* set configuration for RCS2# */
112 mem_stcfg |= TS_MASK;
113 mem_stcfg &= ~TCSOE_MASK;
114 mem_stcfg &= ~TOECS_MASK;
115 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
116 break;
117
118 case 1:
119 mem_sttime = SBC_IDE_TIMING(PIO1);
120
121 /* set configuration for RCS2# */
122 mem_stcfg |= TS_MASK;
123 mem_stcfg &= ~TCSOE_MASK;
124 mem_stcfg &= ~TOECS_MASK;
125 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
126 break;
127
128 case 2:
129 mem_sttime = SBC_IDE_TIMING(PIO2);
130
131 /* set configuration for RCS2# */
132 mem_stcfg &= ~TS_MASK;
133 mem_stcfg &= ~TCSOE_MASK;
134 mem_stcfg &= ~TOECS_MASK;
135 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
136 break;
137
138 case 3:
139 mem_sttime = SBC_IDE_TIMING(PIO3);
140
141 /* set configuration for RCS2# */
142 mem_stcfg &= ~TS_MASK;
143 mem_stcfg &= ~TCSOE_MASK;
144 mem_stcfg &= ~TOECS_MASK;
145 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
146
147 break;
148
149 case 4:
150 mem_sttime = SBC_IDE_TIMING(PIO4);
151
152 /* set configuration for RCS2# */
153 mem_stcfg &= ~TS_MASK;
154 mem_stcfg &= ~TCSOE_MASK;
155 mem_stcfg &= ~TOECS_MASK;
156 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
157 break;
158 }
159
160 au_writel(mem_sttime,MEM_STTIME2);
161 au_writel(mem_stcfg,MEM_STCFG2);
162 }
163
164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
165 {
166 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
167
168 switch(speed) {
169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
170 case XFER_MW_DMA_2:
171 mem_sttime = SBC_IDE_TIMING(MDMA2);
172
173 /* set configuration for RCS2# */
174 mem_stcfg &= ~TS_MASK;
175 mem_stcfg &= ~TCSOE_MASK;
176 mem_stcfg &= ~TOECS_MASK;
177 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
178
179 break;
180 case XFER_MW_DMA_1:
181 mem_sttime = SBC_IDE_TIMING(MDMA1);
182
183 /* set configuration for RCS2# */
184 mem_stcfg &= ~TS_MASK;
185 mem_stcfg &= ~TCSOE_MASK;
186 mem_stcfg &= ~TOECS_MASK;
187 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
188
189 break;
190 case XFER_MW_DMA_0:
191 mem_sttime = SBC_IDE_TIMING(MDMA0);
192
193 /* set configuration for RCS2# */
194 mem_stcfg |= TS_MASK;
195 mem_stcfg &= ~TCSOE_MASK;
196 mem_stcfg &= ~TOECS_MASK;
197 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
198
199 break;
200 #endif
201 }
202
203 au_writel(mem_sttime,MEM_STTIME2);
204 au_writel(mem_stcfg,MEM_STCFG2);
205 }
206
207 /*
208 * Multi-Word DMA + DbDMA functions
209 */
210
211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
212 static int auide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
213 {
214 ide_hwif_t *hwif = drive->hwif;
215 _auide_hwif *ahwif = &auide_hwif;
216 struct scatterlist *sg;
217 int i = cmd->sg_nents, count = 0;
218 int iswrite = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
219
220 /* Save for interrupt context */
221 ahwif->drive = drive;
222
223 /* fill the descriptors */
224 sg = hwif->sg_table;
225 while (i && sg_dma_len(sg)) {
226 u32 cur_addr;
227 u32 cur_len;
228
229 cur_addr = sg_dma_address(sg);
230 cur_len = sg_dma_len(sg);
231
232 while (cur_len) {
233 u32 flags = DDMA_FLAGS_NOIE;
234 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
235
236 if (++count >= PRD_ENTRIES) {
237 printk(KERN_WARNING "%s: DMA table too small\n",
238 drive->name);
239 goto use_pio_instead;
240 }
241
242 /* Lets enable intr for the last descriptor only */
243 if (1==i)
244 flags = DDMA_FLAGS_IE;
245 else
246 flags = DDMA_FLAGS_NOIE;
247
248 if (iswrite) {
249 if(!put_source_flags(ahwif->tx_chan,
250 (void*) sg_virt(sg),
251 tc, flags)) {
252 printk(KERN_ERR "%s failed %d\n",
253 __func__, __LINE__);
254 }
255 } else
256 {
257 if(!put_dest_flags(ahwif->rx_chan,
258 (void*) sg_virt(sg),
259 tc, flags)) {
260 printk(KERN_ERR "%s failed %d\n",
261 __func__, __LINE__);
262 }
263 }
264
265 cur_addr += tc;
266 cur_len -= tc;
267 }
268 sg = sg_next(sg);
269 i--;
270 }
271
272 if (count)
273 return 1;
274
275 use_pio_instead:
276 ide_destroy_dmatable(drive);
277
278 return 0; /* revert to PIO for this request */
279 }
280
281 static int auide_dma_end(ide_drive_t *drive)
282 {
283 ide_destroy_dmatable(drive);
284
285 return 0;
286 }
287
288 static void auide_dma_start(ide_drive_t *drive )
289 {
290 }
291
292
293 static int auide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
294 {
295 if (auide_build_dmatable(drive, cmd) == 0) {
296 ide_map_sg(drive, cmd);
297 return 1;
298 }
299
300 drive->waiting_for_dma = 1;
301 return 0;
302 }
303
304 static int auide_dma_test_irq(ide_drive_t *drive)
305 {
306 /* If dbdma didn't execute the STOP command yet, the
307 * active bit is still set
308 */
309 drive->waiting_for_dma++;
310 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
311 printk(KERN_WARNING "%s: timeout waiting for ddma to \
312 complete\n", drive->name);
313 return 1;
314 }
315 udelay(10);
316 return 0;
317 }
318
319 static void auide_dma_host_set(ide_drive_t *drive, int on)
320 {
321 }
322
323 static void auide_ddma_tx_callback(int irq, void *param)
324 {
325 _auide_hwif *ahwif = (_auide_hwif*)param;
326 ahwif->drive->waiting_for_dma = 0;
327 }
328
329 static void auide_ddma_rx_callback(int irq, void *param)
330 {
331 _auide_hwif *ahwif = (_auide_hwif*)param;
332 ahwif->drive->waiting_for_dma = 0;
333 }
334
335 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
336
337 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
338 {
339 dev->dev_id = dev_id;
340 dev->dev_physaddr = (u32)IDE_PHYS_ADDR;
341 dev->dev_intlevel = 0;
342 dev->dev_intpolarity = 0;
343 dev->dev_tsize = tsize;
344 dev->dev_devwidth = devwidth;
345 dev->dev_flags = flags;
346 }
347
348 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
349 static const struct ide_dma_ops au1xxx_dma_ops = {
350 .dma_host_set = auide_dma_host_set,
351 .dma_setup = auide_dma_setup,
352 .dma_start = auide_dma_start,
353 .dma_end = auide_dma_end,
354 .dma_test_irq = auide_dma_test_irq,
355 .dma_lost_irq = ide_dma_lost_irq,
356 };
357
358 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
359 {
360 _auide_hwif *auide = &auide_hwif;
361 dbdev_tab_t source_dev_tab, target_dev_tab;
362 u32 dev_id, tsize, devwidth, flags;
363
364 dev_id = IDE_DDMA_REQ;
365
366 tsize = 8; /* 1 */
367 devwidth = 32; /* 16 */
368
369 #ifdef IDE_AU1XXX_BURSTMODE
370 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
371 #else
372 flags = DEV_FLAGS_SYNC;
373 #endif
374
375 /* setup dev_tab for tx channel */
376 auide_init_dbdma_dev( &source_dev_tab,
377 dev_id,
378 tsize, devwidth, DEV_FLAGS_OUT | flags);
379 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
380
381 auide_init_dbdma_dev( &source_dev_tab,
382 dev_id,
383 tsize, devwidth, DEV_FLAGS_IN | flags);
384 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
385
386 /* We also need to add a target device for the DMA */
387 auide_init_dbdma_dev( &target_dev_tab,
388 (u32)DSCR_CMD0_ALWAYS,
389 tsize, devwidth, DEV_FLAGS_ANYUSE);
390 auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
391
392 /* Get a channel for TX */
393 auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
394 auide->tx_dev_id,
395 auide_ddma_tx_callback,
396 (void*)auide);
397
398 /* Get a channel for RX */
399 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
400 auide->target_dev_id,
401 auide_ddma_rx_callback,
402 (void*)auide);
403
404 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
405 NUM_DESCRIPTORS);
406 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
407 NUM_DESCRIPTORS);
408
409 /* FIXME: check return value */
410 (void)ide_allocate_dma_engine(hwif);
411
412 au1xxx_dbdma_start( auide->tx_chan );
413 au1xxx_dbdma_start( auide->rx_chan );
414
415 return 0;
416 }
417 #else
418 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
419 {
420 _auide_hwif *auide = &auide_hwif;
421 dbdev_tab_t source_dev_tab;
422 int flags;
423
424 #ifdef IDE_AU1XXX_BURSTMODE
425 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
426 #else
427 flags = DEV_FLAGS_SYNC;
428 #endif
429
430 /* setup dev_tab for tx channel */
431 auide_init_dbdma_dev( &source_dev_tab,
432 (u32)DSCR_CMD0_ALWAYS,
433 8, 32, DEV_FLAGS_OUT | flags);
434 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
435
436 auide_init_dbdma_dev( &source_dev_tab,
437 (u32)DSCR_CMD0_ALWAYS,
438 8, 32, DEV_FLAGS_IN | flags);
439 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
440
441 /* Get a channel for TX */
442 auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
443 auide->tx_dev_id,
444 NULL,
445 (void*)auide);
446
447 /* Get a channel for RX */
448 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
449 DSCR_CMD0_ALWAYS,
450 NULL,
451 (void*)auide);
452
453 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
454 NUM_DESCRIPTORS);
455 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
456 NUM_DESCRIPTORS);
457
458 au1xxx_dbdma_start( auide->tx_chan );
459 au1xxx_dbdma_start( auide->rx_chan );
460
461 return 0;
462 }
463 #endif
464
465 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
466 {
467 int i;
468 unsigned long *ata_regs = hw->io_ports_array;
469
470 /* FIXME? */
471 for (i = 0; i < 8; i++)
472 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
473
474 /* set the Alternative Status register */
475 *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
476 }
477
478 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
479 static const struct ide_tp_ops au1xxx_tp_ops = {
480 .exec_command = ide_exec_command,
481 .read_status = ide_read_status,
482 .read_altstatus = ide_read_altstatus,
483
484 .set_irq = ide_set_irq,
485
486 .tf_load = ide_tf_load,
487 .tf_read = ide_tf_read,
488
489 .input_data = au1xxx_input_data,
490 .output_data = au1xxx_output_data,
491 };
492 #endif
493
494 static const struct ide_port_ops au1xxx_port_ops = {
495 .set_pio_mode = au1xxx_set_pio_mode,
496 .set_dma_mode = auide_set_dma_mode,
497 };
498
499 static const struct ide_port_info au1xxx_port_info = {
500 .init_dma = auide_ddma_init,
501 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
502 .tp_ops = &au1xxx_tp_ops,
503 #endif
504 .port_ops = &au1xxx_port_ops,
505 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
506 .dma_ops = &au1xxx_dma_ops,
507 #endif
508 .host_flags = IDE_HFLAG_POST_SET_MODE |
509 IDE_HFLAG_NO_IO_32BIT |
510 IDE_HFLAG_UNMASK_IRQS,
511 .pio_mask = ATA_PIO4,
512 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
513 .mwdma_mask = ATA_MWDMA2,
514 #endif
515 };
516
517 static int au_ide_probe(struct platform_device *dev)
518 {
519 _auide_hwif *ahwif = &auide_hwif;
520 struct resource *res;
521 struct ide_host *host;
522 int ret = 0;
523 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
524
525 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
526 char *mode = "MWDMA2";
527 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
528 char *mode = "PIO+DDMA(offload)";
529 #endif
530
531 memset(&auide_hwif, 0, sizeof(_auide_hwif));
532 ahwif->irq = platform_get_irq(dev, 0);
533
534 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
535
536 if (res == NULL) {
537 pr_debug("%s %d: no base address\n", DRV_NAME, dev->id);
538 ret = -ENODEV;
539 goto out;
540 }
541 if (ahwif->irq < 0) {
542 pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id);
543 ret = -ENODEV;
544 goto out;
545 }
546
547 if (!request_mem_region(res->start, res->end - res->start + 1,
548 dev->name)) {
549 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
550 ret = -EBUSY;
551 goto out;
552 }
553
554 ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
555 if (ahwif->regbase == 0) {
556 ret = -ENOMEM;
557 goto out;
558 }
559
560 memset(&hw, 0, sizeof(hw));
561 auide_setup_ports(&hw, ahwif);
562 hw.irq = ahwif->irq;
563 hw.dev = &dev->dev;
564 hw.chipset = ide_au1xxx;
565
566 ret = ide_host_add(&au1xxx_port_info, hws, &host);
567 if (ret)
568 goto out;
569
570 auide_hwif.hwif = host->ports[0];
571
572 platform_set_drvdata(dev, host);
573
574 printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
575
576 out:
577 return ret;
578 }
579
580 static int au_ide_remove(struct platform_device *dev)
581 {
582 struct resource *res;
583 struct ide_host *host = platform_get_drvdata(dev);
584 _auide_hwif *ahwif = &auide_hwif;
585
586 ide_host_remove(host);
587
588 iounmap((void *)ahwif->regbase);
589
590 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
591 release_mem_region(res->start, res->end - res->start + 1);
592
593 return 0;
594 }
595
596 static struct platform_driver au1200_ide_driver = {
597 .driver = {
598 .name = "au1200-ide",
599 .owner = THIS_MODULE,
600 },
601 .probe = au_ide_probe,
602 .remove = au_ide_remove,
603 };
604
605 static int __init au_ide_init(void)
606 {
607 return platform_driver_register(&au1200_ide_driver);
608 }
609
610 static void __exit au_ide_exit(void)
611 {
612 platform_driver_unregister(&au1200_ide_driver);
613 }
614
615 MODULE_LICENSE("GPL");
616 MODULE_DESCRIPTION("AU1200 IDE driver");
617
618 module_init(au_ide_init);
619 module_exit(au_ide_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree