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x86: call dmi-quirks for HP Laptops after early-quirks are executed
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / avr32 / mach-at32ap / at32ap700x.c
blob813b6844cdf67a1ec485ccc4f3839baa42c2682d
1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/gpio.h>
16 #include <linux/spi/spi.h>
17 #include <linux/usb/atmel_usba_udc.h>
18
19 #include <asm/atmel-mci.h>
20 #include <asm/io.h>
21 #include <asm/irq.h>
22
23 #include <mach/at32ap700x.h>
24 #include <mach/board.h>
25 #include <mach/hmatrix.h>
26 #include <mach/portmux.h>
27 #include <mach/sram.h>
28
29 #include <video/atmel_lcdc.h>
30
31 #include "clock.h"
32 #include "pio.h"
33 #include "pm.h"
34
35
36 #define PBMEM(base) \
37 { \
38 .start = base, \
39 .end = base + 0x3ff, \
40 .flags = IORESOURCE_MEM, \
41 }
42 #define IRQ(num) \
43 { \
44 .start = num, \
45 .end = num, \
46 .flags = IORESOURCE_IRQ, \
47 }
48 #define NAMED_IRQ(num, _name) \
49 { \
50 .start = num, \
51 .end = num, \
52 .name = _name, \
53 .flags = IORESOURCE_IRQ, \
54 }
55
56 /* REVISIT these assume *every* device supports DMA, but several
57 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
58 */
59 #define DEFINE_DEV(_name, _id) \
60 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
61 static struct platform_device _name##_id##_device = { \
62 .name = #_name, \
63 .id = _id, \
64 .dev = { \
65 .dma_mask = &_name##_id##_dma_mask, \
66 .coherent_dma_mask = DMA_32BIT_MASK, \
67 }, \
68 .resource = _name##_id##_resource, \
69 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
70 }
71 #define DEFINE_DEV_DATA(_name, _id) \
72 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
73 static struct platform_device _name##_id##_device = { \
74 .name = #_name, \
75 .id = _id, \
76 .dev = { \
77 .dma_mask = &_name##_id##_dma_mask, \
78 .platform_data = &_name##_id##_data, \
79 .coherent_dma_mask = DMA_32BIT_MASK, \
80 }, \
81 .resource = _name##_id##_resource, \
82 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
83 }
84
85 #define select_peripheral(port, pin_mask, periph, flags) \
86 at32_select_periph(GPIO_##port##_BASE, pin_mask, \
87 GPIO_##periph, flags)
88
89 #define DEV_CLK(_name, devname, bus, _index) \
90 static struct clk devname##_##_name = { \
91 .name = #_name, \
92 .dev = &devname##_device.dev, \
93 .parent = &bus##_clk, \
94 .mode = bus##_clk_mode, \
95 .get_rate = bus##_clk_get_rate, \
96 .index = _index, \
97 }
98
99 static DEFINE_SPINLOCK(pm_lock);
100
101 static struct clk osc0;
102 static struct clk osc1;
103
104 static unsigned long osc_get_rate(struct clk *clk)
105 {
106 return at32_board_osc_rates[clk->index];
107 }
108
109 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
110 {
111 unsigned long div, mul, rate;
112
113 div = PM_BFEXT(PLLDIV, control) + 1;
114 mul = PM_BFEXT(PLLMUL, control) + 1;
115
116 rate = clk->parent->get_rate(clk->parent);
117 rate = (rate + div / 2) / div;
118 rate *= mul;
119
120 return rate;
121 }
122
123 static long pll_set_rate(struct clk *clk, unsigned long rate,
124 u32 *pll_ctrl)
125 {
126 unsigned long mul;
127 unsigned long mul_best_fit = 0;
128 unsigned long div;
129 unsigned long div_min;
130 unsigned long div_max;
131 unsigned long div_best_fit = 0;
132 unsigned long base;
133 unsigned long pll_in;
134 unsigned long actual = 0;
135 unsigned long rate_error;
136 unsigned long rate_error_prev = ~0UL;
137 u32 ctrl;
138
139 /* Rate must be between 80 MHz and 200 Mhz. */
140 if (rate < 80000000UL || rate > 200000000UL)
141 return -EINVAL;
142
143 ctrl = PM_BF(PLLOPT, 4);
144 base = clk->parent->get_rate(clk->parent);
145
146 /* PLL input frequency must be between 6 MHz and 32 MHz. */
147 div_min = DIV_ROUND_UP(base, 32000000UL);
148 div_max = base / 6000000UL;
149
150 if (div_max < div_min)
151 return -EINVAL;
152
153 for (div = div_min; div <= div_max; div++) {
154 pll_in = (base + div / 2) / div;
155 mul = (rate + pll_in / 2) / pll_in;
156
157 if (mul == 0)
158 continue;
159
160 actual = pll_in * mul;
161 rate_error = abs(actual - rate);
162
163 if (rate_error < rate_error_prev) {
164 mul_best_fit = mul;
165 div_best_fit = div;
166 rate_error_prev = rate_error;
167 }
168
169 if (rate_error == 0)
170 break;
171 }
172
173 if (div_best_fit == 0)
174 return -EINVAL;
175
176 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
177 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
178 ctrl |= PM_BF(PLLCOUNT, 16);
179
180 if (clk->parent == &osc1)
181 ctrl |= PM_BIT(PLLOSC);
182
183 *pll_ctrl = ctrl;
184
185 return actual;
186 }
187
188 static unsigned long pll0_get_rate(struct clk *clk)
189 {
190 u32 control;
191
192 control = pm_readl(PLL0);
193
194 return pll_get_rate(clk, control);
195 }
196
197 static void pll1_mode(struct clk *clk, int enabled)
198 {
199 unsigned long timeout;
200 u32 status;
201 u32 ctrl;
202
203 ctrl = pm_readl(PLL1);
204
205 if (enabled) {
206 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
207 pr_debug("clk %s: failed to enable, rate not set\n",
208 clk->name);
209 return;
210 }
211
212 ctrl |= PM_BIT(PLLEN);
213 pm_writel(PLL1, ctrl);
214
215 /* Wait for PLL lock. */
216 for (timeout = 10000; timeout; timeout--) {
217 status = pm_readl(ISR);
218 if (status & PM_BIT(LOCK1))
219 break;
220 udelay(10);
221 }
222
223 if (!(status & PM_BIT(LOCK1)))
224 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
225 clk->name);
226 } else {
227 ctrl &= ~PM_BIT(PLLEN);
228 pm_writel(PLL1, ctrl);
229 }
230 }
231
232 static unsigned long pll1_get_rate(struct clk *clk)
233 {
234 u32 control;
235
236 control = pm_readl(PLL1);
237
238 return pll_get_rate(clk, control);
239 }
240
241 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
242 {
243 u32 ctrl = 0;
244 unsigned long actual_rate;
245
246 actual_rate = pll_set_rate(clk, rate, &ctrl);
247
248 if (apply) {
249 if (actual_rate != rate)
250 return -EINVAL;
251 if (clk->users > 0)
252 return -EBUSY;
253 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
254 clk->name, rate, actual_rate);
255 pm_writel(PLL1, ctrl);
256 }
257
258 return actual_rate;
259 }
260
261 static int pll1_set_parent(struct clk *clk, struct clk *parent)
262 {
263 u32 ctrl;
264
265 if (clk->users > 0)
266 return -EBUSY;
267
268 ctrl = pm_readl(PLL1);
269 WARN_ON(ctrl & PM_BIT(PLLEN));
270
271 if (parent == &osc0)
272 ctrl &= ~PM_BIT(PLLOSC);
273 else if (parent == &osc1)
274 ctrl |= PM_BIT(PLLOSC);
275 else
276 return -EINVAL;
277
278 pm_writel(PLL1, ctrl);
279 clk->parent = parent;
280
281 return 0;
282 }
283
284 /*
285 * The AT32AP7000 has five primary clock sources: One 32kHz
286 * oscillator, two crystal oscillators and two PLLs.
287 */
288 static struct clk osc32k = {
289 .name = "osc32k",
290 .get_rate = osc_get_rate,
291 .users = 1,
292 .index = 0,
293 };
294 static struct clk osc0 = {
295 .name = "osc0",
296 .get_rate = osc_get_rate,
297 .users = 1,
298 .index = 1,
299 };
300 static struct clk osc1 = {
301 .name = "osc1",
302 .get_rate = osc_get_rate,
303 .index = 2,
304 };
305 static struct clk pll0 = {
306 .name = "pll0",
307 .get_rate = pll0_get_rate,
308 .parent = &osc0,
309 };
310 static struct clk pll1 = {
311 .name = "pll1",
312 .mode = pll1_mode,
313 .get_rate = pll1_get_rate,
314 .set_rate = pll1_set_rate,
315 .set_parent = pll1_set_parent,
316 .parent = &osc0,
317 };
318
319 /*
320 * The main clock can be either osc0 or pll0. The boot loader may
321 * have chosen one for us, so we don't really know which one until we
322 * have a look at the SM.
323 */
324 static struct clk *main_clock;
325
326 /*
327 * Synchronous clocks are generated from the main clock. The clocks
328 * must satisfy the constraint
329 * fCPU >= fHSB >= fPB
330 * i.e. each clock must not be faster than its parent.
331 */
332 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
333 {
334 return main_clock->get_rate(main_clock) >> shift;
335 };
336
337 static void cpu_clk_mode(struct clk *clk, int enabled)
338 {
339 unsigned long flags;
340 u32 mask;
341
342 spin_lock_irqsave(&pm_lock, flags);
343 mask = pm_readl(CPU_MASK);
344 if (enabled)
345 mask |= 1 << clk->index;
346 else
347 mask &= ~(1 << clk->index);
348 pm_writel(CPU_MASK, mask);
349 spin_unlock_irqrestore(&pm_lock, flags);
350 }
351
352 static unsigned long cpu_clk_get_rate(struct clk *clk)
353 {
354 unsigned long cksel, shift = 0;
355
356 cksel = pm_readl(CKSEL);
357 if (cksel & PM_BIT(CPUDIV))
358 shift = PM_BFEXT(CPUSEL, cksel) + 1;
359
360 return bus_clk_get_rate(clk, shift);
361 }
362
363 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
364 {
365 u32 control;
366 unsigned long parent_rate, child_div, actual_rate, div;
367
368 parent_rate = clk->parent->get_rate(clk->parent);
369 control = pm_readl(CKSEL);
370
371 if (control & PM_BIT(HSBDIV))
372 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
373 else
374 child_div = 1;
375
376 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
377 actual_rate = parent_rate;
378 control &= ~PM_BIT(CPUDIV);
379 } else {
380 unsigned int cpusel;
381 div = (parent_rate + rate / 2) / rate;
382 if (div > child_div)
383 div = child_div;
384 cpusel = (div > 1) ? (fls(div) - 2) : 0;
385 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
386 actual_rate = parent_rate / (1 << (cpusel + 1));
387 }
388
389 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
390 clk->name, rate, actual_rate);
391
392 if (apply)
393 pm_writel(CKSEL, control);
394
395 return actual_rate;
396 }
397
398 static void hsb_clk_mode(struct clk *clk, int enabled)
399 {
400 unsigned long flags;
401 u32 mask;
402
403 spin_lock_irqsave(&pm_lock, flags);
404 mask = pm_readl(HSB_MASK);
405 if (enabled)
406 mask |= 1 << clk->index;
407 else
408 mask &= ~(1 << clk->index);
409 pm_writel(HSB_MASK, mask);
410 spin_unlock_irqrestore(&pm_lock, flags);
411 }
412
413 static unsigned long hsb_clk_get_rate(struct clk *clk)
414 {
415 unsigned long cksel, shift = 0;
416
417 cksel = pm_readl(CKSEL);
418 if (cksel & PM_BIT(HSBDIV))
419 shift = PM_BFEXT(HSBSEL, cksel) + 1;
420
421 return bus_clk_get_rate(clk, shift);
422 }
423
424 static void pba_clk_mode(struct clk *clk, int enabled)
425 {
426 unsigned long flags;
427 u32 mask;
428
429 spin_lock_irqsave(&pm_lock, flags);
430 mask = pm_readl(PBA_MASK);
431 if (enabled)
432 mask |= 1 << clk->index;
433 else
434 mask &= ~(1 << clk->index);
435 pm_writel(PBA_MASK, mask);
436 spin_unlock_irqrestore(&pm_lock, flags);
437 }
438
439 static unsigned long pba_clk_get_rate(struct clk *clk)
440 {
441 unsigned long cksel, shift = 0;
442
443 cksel = pm_readl(CKSEL);
444 if (cksel & PM_BIT(PBADIV))
445 shift = PM_BFEXT(PBASEL, cksel) + 1;
446
447 return bus_clk_get_rate(clk, shift);
448 }
449
450 static void pbb_clk_mode(struct clk *clk, int enabled)
451 {
452 unsigned long flags;
453 u32 mask;
454
455 spin_lock_irqsave(&pm_lock, flags);
456 mask = pm_readl(PBB_MASK);
457 if (enabled)
458 mask |= 1 << clk->index;
459 else
460 mask &= ~(1 << clk->index);
461 pm_writel(PBB_MASK, mask);
462 spin_unlock_irqrestore(&pm_lock, flags);
463 }
464
465 static unsigned long pbb_clk_get_rate(struct clk *clk)
466 {
467 unsigned long cksel, shift = 0;
468
469 cksel = pm_readl(CKSEL);
470 if (cksel & PM_BIT(PBBDIV))
471 shift = PM_BFEXT(PBBSEL, cksel) + 1;
472
473 return bus_clk_get_rate(clk, shift);
474 }
475
476 static struct clk cpu_clk = {
477 .name = "cpu",
478 .get_rate = cpu_clk_get_rate,
479 .set_rate = cpu_clk_set_rate,
480 .users = 1,
481 };
482 static struct clk hsb_clk = {
483 .name = "hsb",
484 .parent = &cpu_clk,
485 .get_rate = hsb_clk_get_rate,
486 };
487 static struct clk pba_clk = {
488 .name = "pba",
489 .parent = &hsb_clk,
490 .mode = hsb_clk_mode,
491 .get_rate = pba_clk_get_rate,
492 .index = 1,
493 };
494 static struct clk pbb_clk = {
495 .name = "pbb",
496 .parent = &hsb_clk,
497 .mode = hsb_clk_mode,
498 .get_rate = pbb_clk_get_rate,
499 .users = 1,
500 .index = 2,
501 };
502
503 /* --------------------------------------------------------------------
504 * Generic Clock operations
505 * -------------------------------------------------------------------- */
506
507 static void genclk_mode(struct clk *clk, int enabled)
508 {
509 u32 control;
510
511 control = pm_readl(GCCTRL(clk->index));
512 if (enabled)
513 control |= PM_BIT(CEN);
514 else
515 control &= ~PM_BIT(CEN);
516 pm_writel(GCCTRL(clk->index), control);
517 }
518
519 static unsigned long genclk_get_rate(struct clk *clk)
520 {
521 u32 control;
522 unsigned long div = 1;
523
524 control = pm_readl(GCCTRL(clk->index));
525 if (control & PM_BIT(DIVEN))
526 div = 2 * (PM_BFEXT(DIV, control) + 1);
527
528 return clk->parent->get_rate(clk->parent) / div;
529 }
530
531 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
532 {
533 u32 control;
534 unsigned long parent_rate, actual_rate, div;
535
536 parent_rate = clk->parent->get_rate(clk->parent);
537 control = pm_readl(GCCTRL(clk->index));
538
539 if (rate > 3 * parent_rate / 4) {
540 actual_rate = parent_rate;
541 control &= ~PM_BIT(DIVEN);
542 } else {
543 div = (parent_rate + rate) / (2 * rate) - 1;
544 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
545 actual_rate = parent_rate / (2 * (div + 1));
546 }
547
548 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
549 clk->name, rate, actual_rate);
550
551 if (apply)
552 pm_writel(GCCTRL(clk->index), control);
553
554 return actual_rate;
555 }
556
557 int genclk_set_parent(struct clk *clk, struct clk *parent)
558 {
559 u32 control;
560
561 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
562 clk->name, parent->name, clk->parent->name);
563
564 control = pm_readl(GCCTRL(clk->index));
565
566 if (parent == &osc1 || parent == &pll1)
567 control |= PM_BIT(OSCSEL);
568 else if (parent == &osc0 || parent == &pll0)
569 control &= ~PM_BIT(OSCSEL);
570 else
571 return -EINVAL;
572
573 if (parent == &pll0 || parent == &pll1)
574 control |= PM_BIT(PLLSEL);
575 else
576 control &= ~PM_BIT(PLLSEL);
577
578 pm_writel(GCCTRL(clk->index), control);
579 clk->parent = parent;
580
581 return 0;
582 }
583
584 static void __init genclk_init_parent(struct clk *clk)
585 {
586 u32 control;
587 struct clk *parent;
588
589 BUG_ON(clk->index > 7);
590
591 control = pm_readl(GCCTRL(clk->index));
592 if (control & PM_BIT(OSCSEL))
593 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
594 else
595 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
596
597 clk->parent = parent;
598 }
599
600 static struct dw_dma_platform_data dw_dmac0_data = {
601 .nr_channels = 3,
602 };
603
604 static struct resource dw_dmac0_resource[] = {
605 PBMEM(0xff200000),
606 IRQ(2),
607 };
608 DEFINE_DEV_DATA(dw_dmac, 0);
609 DEV_CLK(hclk, dw_dmac0, hsb, 10);
610
611 /* --------------------------------------------------------------------
612 * System peripherals
613 * -------------------------------------------------------------------- */
614 static struct resource at32_pm0_resource[] = {
615 {
616 .start = 0xfff00000,
617 .end = 0xfff0007f,
618 .flags = IORESOURCE_MEM,
619 },
620 IRQ(20),
621 };
622
623 static struct resource at32ap700x_rtc0_resource[] = {
624 {
625 .start = 0xfff00080,
626 .end = 0xfff000af,
627 .flags = IORESOURCE_MEM,
628 },
629 IRQ(21),
630 };
631
632 static struct resource at32_wdt0_resource[] = {
633 {
634 .start = 0xfff000b0,
635 .end = 0xfff000cf,
636 .flags = IORESOURCE_MEM,
637 },
638 };
639
640 static struct resource at32_eic0_resource[] = {
641 {
642 .start = 0xfff00100,
643 .end = 0xfff0013f,
644 .flags = IORESOURCE_MEM,
645 },
646 IRQ(19),
647 };
648
649 DEFINE_DEV(at32_pm, 0);
650 DEFINE_DEV(at32ap700x_rtc, 0);
651 DEFINE_DEV(at32_wdt, 0);
652 DEFINE_DEV(at32_eic, 0);
653
654 /*
655 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
656 * is always running.
657 */
658 static struct clk at32_pm_pclk = {
659 .name = "pclk",
660 .dev = &at32_pm0_device.dev,
661 .parent = &pbb_clk,
662 .mode = pbb_clk_mode,
663 .get_rate = pbb_clk_get_rate,
664 .users = 1,
665 .index = 0,
666 };
667
668 static struct resource intc0_resource[] = {
669 PBMEM(0xfff00400),
670 };
671 struct platform_device at32_intc0_device = {
672 .name = "intc",
673 .id = 0,
674 .resource = intc0_resource,
675 .num_resources = ARRAY_SIZE(intc0_resource),
676 };
677 DEV_CLK(pclk, at32_intc0, pbb, 1);
678
679 static struct clk ebi_clk = {
680 .name = "ebi",
681 .parent = &hsb_clk,
682 .mode = hsb_clk_mode,
683 .get_rate = hsb_clk_get_rate,
684 .users = 1,
685 };
686 static struct clk hramc_clk = {
687 .name = "hramc",
688 .parent = &hsb_clk,
689 .mode = hsb_clk_mode,
690 .get_rate = hsb_clk_get_rate,
691 .users = 1,
692 .index = 3,
693 };
694 static struct clk sdramc_clk = {
695 .name = "sdramc_clk",
696 .parent = &pbb_clk,
697 .mode = pbb_clk_mode,
698 .get_rate = pbb_clk_get_rate,
699 .users = 1,
700 .index = 14,
701 };
702
703 static struct resource smc0_resource[] = {
704 PBMEM(0xfff03400),
705 };
706 DEFINE_DEV(smc, 0);
707 DEV_CLK(pclk, smc0, pbb, 13);
708 DEV_CLK(mck, smc0, hsb, 0);
709
710 static struct platform_device pdc_device = {
711 .name = "pdc",
712 .id = 0,
713 };
714 DEV_CLK(hclk, pdc, hsb, 4);
715 DEV_CLK(pclk, pdc, pba, 16);
716
717 static struct clk pico_clk = {
718 .name = "pico",
719 .parent = &cpu_clk,
720 .mode = cpu_clk_mode,
721 .get_rate = cpu_clk_get_rate,
722 .users = 1,
723 };
724
725 /* --------------------------------------------------------------------
726 * HMATRIX
727 * -------------------------------------------------------------------- */
728
729 struct clk at32_hmatrix_clk = {
730 .name = "hmatrix_clk",
731 .parent = &pbb_clk,
732 .mode = pbb_clk_mode,
733 .get_rate = pbb_clk_get_rate,
734 .index = 2,
735 .users = 1,
736 };
737
738 /*
739 * Set bits in the HMATRIX Special Function Register (SFR) used by the
740 * External Bus Interface (EBI). This can be used to enable special
741 * features like CompactFlash support, NAND Flash support, etc. on
742 * certain chipselects.
743 */
744 static inline void set_ebi_sfr_bits(u32 mask)
745 {
746 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
747 }
748
749 /* --------------------------------------------------------------------
750 * Timer/Counter (TC)
751 * -------------------------------------------------------------------- */
752
753 static struct resource at32_tcb0_resource[] = {
754 PBMEM(0xfff00c00),
755 IRQ(22),
756 };
757 static struct platform_device at32_tcb0_device = {
758 .name = "atmel_tcb",
759 .id = 0,
760 .resource = at32_tcb0_resource,
761 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
762 };
763 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
764
765 static struct resource at32_tcb1_resource[] = {
766 PBMEM(0xfff01000),
767 IRQ(23),
768 };
769 static struct platform_device at32_tcb1_device = {
770 .name = "atmel_tcb",
771 .id = 1,
772 .resource = at32_tcb1_resource,
773 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
774 };
775 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
776
777 /* --------------------------------------------------------------------
778 * PIO
779 * -------------------------------------------------------------------- */
780
781 static struct resource pio0_resource[] = {
782 PBMEM(0xffe02800),
783 IRQ(13),
784 };
785 DEFINE_DEV(pio, 0);
786 DEV_CLK(mck, pio0, pba, 10);
787
788 static struct resource pio1_resource[] = {
789 PBMEM(0xffe02c00),
790 IRQ(14),
791 };
792 DEFINE_DEV(pio, 1);
793 DEV_CLK(mck, pio1, pba, 11);
794
795 static struct resource pio2_resource[] = {
796 PBMEM(0xffe03000),
797 IRQ(15),
798 };
799 DEFINE_DEV(pio, 2);
800 DEV_CLK(mck, pio2, pba, 12);
801
802 static struct resource pio3_resource[] = {
803 PBMEM(0xffe03400),
804 IRQ(16),
805 };
806 DEFINE_DEV(pio, 3);
807 DEV_CLK(mck, pio3, pba, 13);
808
809 static struct resource pio4_resource[] = {
810 PBMEM(0xffe03800),
811 IRQ(17),
812 };
813 DEFINE_DEV(pio, 4);
814 DEV_CLK(mck, pio4, pba, 14);
815
816 void __init at32_add_system_devices(void)
817 {
818 platform_device_register(&at32_pm0_device);
819 platform_device_register(&at32_intc0_device);
820 platform_device_register(&at32ap700x_rtc0_device);
821 platform_device_register(&at32_wdt0_device);
822 platform_device_register(&at32_eic0_device);
823 platform_device_register(&smc0_device);
824 platform_device_register(&pdc_device);
825 platform_device_register(&dw_dmac0_device);
826
827 platform_device_register(&at32_tcb0_device);
828 platform_device_register(&at32_tcb1_device);
829
830 platform_device_register(&pio0_device);
831 platform_device_register(&pio1_device);
832 platform_device_register(&pio2_device);
833 platform_device_register(&pio3_device);
834 platform_device_register(&pio4_device);
835 }
836
837 /* --------------------------------------------------------------------
838 * PSIF
839 * -------------------------------------------------------------------- */
840 static struct resource atmel_psif0_resource[] __initdata = {
841 {
842 .start = 0xffe03c00,
843 .end = 0xffe03cff,
844 .flags = IORESOURCE_MEM,
845 },
846 IRQ(18),
847 };
848 static struct clk atmel_psif0_pclk = {
849 .name = "pclk",
850 .parent = &pba_clk,
851 .mode = pba_clk_mode,
852 .get_rate = pba_clk_get_rate,
853 .index = 15,
854 };
855
856 static struct resource atmel_psif1_resource[] __initdata = {
857 {
858 .start = 0xffe03d00,
859 .end = 0xffe03dff,
860 .flags = IORESOURCE_MEM,
861 },
862 IRQ(18),
863 };
864 static struct clk atmel_psif1_pclk = {
865 .name = "pclk",
866 .parent = &pba_clk,
867 .mode = pba_clk_mode,
868 .get_rate = pba_clk_get_rate,
869 .index = 15,
870 };
871
872 struct platform_device *__init at32_add_device_psif(unsigned int id)
873 {
874 struct platform_device *pdev;
875 u32 pin_mask;
876
877 if (!(id == 0 || id == 1))
878 return NULL;
879
880 pdev = platform_device_alloc("atmel_psif", id);
881 if (!pdev)
882 return NULL;
883
884 switch (id) {
885 case 0:
886 pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */
887
888 if (platform_device_add_resources(pdev, atmel_psif0_resource,
889 ARRAY_SIZE(atmel_psif0_resource)))
890 goto err_add_resources;
891 atmel_psif0_pclk.dev = &pdev->dev;
892 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
893 break;
894 case 1:
895 pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */
896
897 if (platform_device_add_resources(pdev, atmel_psif1_resource,
898 ARRAY_SIZE(atmel_psif1_resource)))
899 goto err_add_resources;
900 atmel_psif1_pclk.dev = &pdev->dev;
901 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
902 break;
903 default:
904 return NULL;
905 }
906
907 platform_device_add(pdev);
908 return pdev;
909
910 err_add_resources:
911 platform_device_put(pdev);
912 return NULL;
913 }
914
915 /* --------------------------------------------------------------------
916 * USART
917 * -------------------------------------------------------------------- */
918
919 static struct atmel_uart_data atmel_usart0_data = {
920 .use_dma_tx = 1,
921 .use_dma_rx = 1,
922 };
923 static struct resource atmel_usart0_resource[] = {
924 PBMEM(0xffe00c00),
925 IRQ(6),
926 };
927 DEFINE_DEV_DATA(atmel_usart, 0);
928 DEV_CLK(usart, atmel_usart0, pba, 3);
929
930 static struct atmel_uart_data atmel_usart1_data = {
931 .use_dma_tx = 1,
932 .use_dma_rx = 1,
933 };
934 static struct resource atmel_usart1_resource[] = {
935 PBMEM(0xffe01000),
936 IRQ(7),
937 };
938 DEFINE_DEV_DATA(atmel_usart, 1);
939 DEV_CLK(usart, atmel_usart1, pba, 4);
940
941 static struct atmel_uart_data atmel_usart2_data = {
942 .use_dma_tx = 1,
943 .use_dma_rx = 1,
944 };
945 static struct resource atmel_usart2_resource[] = {
946 PBMEM(0xffe01400),
947 IRQ(8),
948 };
949 DEFINE_DEV_DATA(atmel_usart, 2);
950 DEV_CLK(usart, atmel_usart2, pba, 5);
951
952 static struct atmel_uart_data atmel_usart3_data = {
953 .use_dma_tx = 1,
954 .use_dma_rx = 1,
955 };
956 static struct resource atmel_usart3_resource[] = {
957 PBMEM(0xffe01800),
958 IRQ(9),
959 };
960 DEFINE_DEV_DATA(atmel_usart, 3);
961 DEV_CLK(usart, atmel_usart3, pba, 6);
962
963 static inline void configure_usart0_pins(void)
964 {
965 u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
966
967 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
968 }
969
970 static inline void configure_usart1_pins(void)
971 {
972 u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
973
974 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
975 }
976
977 static inline void configure_usart2_pins(void)
978 {
979 u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
980
981 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
982 }
983
984 static inline void configure_usart3_pins(void)
985 {
986 u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
987
988 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
989 }
990
991 static struct platform_device *__initdata at32_usarts[4];
992
993 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
994 {
995 struct platform_device *pdev;
996
997 switch (hw_id) {
998 case 0:
999 pdev = &atmel_usart0_device;
1000 configure_usart0_pins();
1001 break;
1002 case 1:
1003 pdev = &atmel_usart1_device;
1004 configure_usart1_pins();
1005 break;
1006 case 2:
1007 pdev = &atmel_usart2_device;
1008 configure_usart2_pins();
1009 break;
1010 case 3:
1011 pdev = &atmel_usart3_device;
1012 configure_usart3_pins();
1013 break;
1014 default:
1015 return;
1016 }
1017
1018 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1019 /* Addresses in the P4 segment are permanently mapped 1:1 */
1020 struct atmel_uart_data *data = pdev->dev.platform_data;
1021 data->regs = (void __iomem *)pdev->resource[0].start;
1022 }
1023
1024 pdev->id = line;
1025 at32_usarts[line] = pdev;
1026 }
1027
1028 struct platform_device *__init at32_add_device_usart(unsigned int id)
1029 {
1030 platform_device_register(at32_usarts[id]);
1031 return at32_usarts[id];
1032 }
1033
1034 struct platform_device *atmel_default_console_device;
1035
1036 void __init at32_setup_serial_console(unsigned int usart_id)
1037 {
1038 atmel_default_console_device = at32_usarts[usart_id];
1039 }
1040
1041 /* --------------------------------------------------------------------
1042 * Ethernet
1043 * -------------------------------------------------------------------- */
1044
1045 #ifdef CONFIG_CPU_AT32AP7000
1046 static struct eth_platform_data macb0_data;
1047 static struct resource macb0_resource[] = {
1048 PBMEM(0xfff01800),
1049 IRQ(25),
1050 };
1051 DEFINE_DEV_DATA(macb, 0);
1052 DEV_CLK(hclk, macb0, hsb, 8);
1053 DEV_CLK(pclk, macb0, pbb, 6);
1054
1055 static struct eth_platform_data macb1_data;
1056 static struct resource macb1_resource[] = {
1057 PBMEM(0xfff01c00),
1058 IRQ(26),
1059 };
1060 DEFINE_DEV_DATA(macb, 1);
1061 DEV_CLK(hclk, macb1, hsb, 9);
1062 DEV_CLK(pclk, macb1, pbb, 7);
1063
1064 struct platform_device *__init
1065 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1066 {
1067 struct platform_device *pdev;
1068 u32 pin_mask;
1069
1070 switch (id) {
1071 case 0:
1072 pdev = &macb0_device;
1073
1074 pin_mask = (1 << 3); /* TXD0 */
1075 pin_mask |= (1 << 4); /* TXD1 */
1076 pin_mask |= (1 << 7); /* TXEN */
1077 pin_mask |= (1 << 8); /* TXCK */
1078 pin_mask |= (1 << 9); /* RXD0 */
1079 pin_mask |= (1 << 10); /* RXD1 */
1080 pin_mask |= (1 << 13); /* RXER */
1081 pin_mask |= (1 << 15); /* RXDV */
1082 pin_mask |= (1 << 16); /* MDC */
1083 pin_mask |= (1 << 17); /* MDIO */
1084
1085 if (!data->is_rmii) {
1086 pin_mask |= (1 << 0); /* COL */
1087 pin_mask |= (1 << 1); /* CRS */
1088 pin_mask |= (1 << 2); /* TXER */
1089 pin_mask |= (1 << 5); /* TXD2 */
1090 pin_mask |= (1 << 6); /* TXD3 */
1091 pin_mask |= (1 << 11); /* RXD2 */
1092 pin_mask |= (1 << 12); /* RXD3 */
1093 pin_mask |= (1 << 14); /* RXCK */
1094 pin_mask |= (1 << 18); /* SPD */
1095 }
1096
1097 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1098
1099 break;
1100
1101 case 1:
1102 pdev = &macb1_device;
1103
1104 pin_mask = (1 << 13); /* TXD0 */
1105 pin_mask |= (1 << 14); /* TXD1 */
1106 pin_mask |= (1 << 11); /* TXEN */
1107 pin_mask |= (1 << 12); /* TXCK */
1108 pin_mask |= (1 << 10); /* RXD0 */
1109 pin_mask |= (1 << 6); /* RXD1 */
1110 pin_mask |= (1 << 5); /* RXER */
1111 pin_mask |= (1 << 4); /* RXDV */
1112 pin_mask |= (1 << 3); /* MDC */
1113 pin_mask |= (1 << 2); /* MDIO */
1114
1115 if (!data->is_rmii)
1116 pin_mask |= (1 << 15); /* SPD */
1117
1118 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1119
1120 if (!data->is_rmii) {
1121 pin_mask = (1 << 19); /* COL */
1122 pin_mask |= (1 << 23); /* CRS */
1123 pin_mask |= (1 << 26); /* TXER */
1124 pin_mask |= (1 << 27); /* TXD2 */
1125 pin_mask |= (1 << 28); /* TXD3 */
1126 pin_mask |= (1 << 29); /* RXD2 */
1127 pin_mask |= (1 << 30); /* RXD3 */
1128 pin_mask |= (1 << 24); /* RXCK */
1129
1130 select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1131 }
1132 break;
1133
1134 default:
1135 return NULL;
1136 }
1137
1138 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1139 platform_device_register(pdev);
1140
1141 return pdev;
1142 }
1143 #endif
1144
1145 /* --------------------------------------------------------------------
1146 * SPI
1147 * -------------------------------------------------------------------- */
1148 static struct resource atmel_spi0_resource[] = {
1149 PBMEM(0xffe00000),
1150 IRQ(3),
1151 };
1152 DEFINE_DEV(atmel_spi, 0);
1153 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1154
1155 static struct resource atmel_spi1_resource[] = {
1156 PBMEM(0xffe00400),
1157 IRQ(4),
1158 };
1159 DEFINE_DEV(atmel_spi, 1);
1160 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1161
1162 static void __init
1163 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1164 unsigned int n, const u8 *pins)
1165 {
1166 unsigned int pin, mode;
1167
1168 for (; n; n--, b++) {
1169 b->bus_num = bus_num;
1170 if (b->chip_select >= 4)
1171 continue;
1172 pin = (unsigned)b->controller_data;
1173 if (!pin) {
1174 pin = pins[b->chip_select];
1175 b->controller_data = (void *)pin;
1176 }
1177 mode = AT32_GPIOF_OUTPUT;
1178 if (!(b->mode & SPI_CS_HIGH))
1179 mode |= AT32_GPIOF_HIGH;
1180 at32_select_gpio(pin, mode);
1181 }
1182 }
1183
1184 struct platform_device *__init
1185 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1186 {
1187 /*
1188 * Manage the chipselects as GPIOs, normally using the same pins
1189 * the SPI controller expects; but boards can use other pins.
1190 */
1191 static u8 __initdata spi0_pins[] =
1192 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1193 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1194 static u8 __initdata spi1_pins[] =
1195 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1196 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1197 struct platform_device *pdev;
1198 u32 pin_mask;
1199
1200 switch (id) {
1201 case 0:
1202 pdev = &atmel_spi0_device;
1203 pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */
1204
1205 /* pullup MISO so a level is always defined */
1206 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1207 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1208
1209 at32_spi_setup_slaves(0, b, n, spi0_pins);
1210 break;
1211
1212 case 1:
1213 pdev = &atmel_spi1_device;
1214 pin_mask = (1 << 1) | (1 << 5); /* MOSI */
1215
1216 /* pullup MISO so a level is always defined */
1217 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1218 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1219
1220 at32_spi_setup_slaves(1, b, n, spi1_pins);
1221 break;
1222
1223 default:
1224 return NULL;
1225 }
1226
1227 spi_register_board_info(b, n);
1228 platform_device_register(pdev);
1229 return pdev;
1230 }
1231
1232 /* --------------------------------------------------------------------
1233 * TWI
1234 * -------------------------------------------------------------------- */
1235 static struct resource atmel_twi0_resource[] __initdata = {
1236 PBMEM(0xffe00800),
1237 IRQ(5),
1238 };
1239 static struct clk atmel_twi0_pclk = {
1240 .name = "twi_pclk",
1241 .parent = &pba_clk,
1242 .mode = pba_clk_mode,
1243 .get_rate = pba_clk_get_rate,
1244 .index = 2,
1245 };
1246
1247 struct platform_device *__init at32_add_device_twi(unsigned int id,
1248 struct i2c_board_info *b,
1249 unsigned int n)
1250 {
1251 struct platform_device *pdev;
1252 u32 pin_mask;
1253
1254 if (id != 0)
1255 return NULL;
1256
1257 pdev = platform_device_alloc("atmel_twi", id);
1258 if (!pdev)
1259 return NULL;
1260
1261 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1262 ARRAY_SIZE(atmel_twi0_resource)))
1263 goto err_add_resources;
1264
1265 pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */
1266
1267 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1268
1269 atmel_twi0_pclk.dev = &pdev->dev;
1270
1271 if (b)
1272 i2c_register_board_info(id, b, n);
1273
1274 platform_device_add(pdev);
1275 return pdev;
1276
1277 err_add_resources:
1278 platform_device_put(pdev);
1279 return NULL;
1280 }
1281
1282 /* --------------------------------------------------------------------
1283 * MMC
1284 * -------------------------------------------------------------------- */
1285 static struct resource atmel_mci0_resource[] __initdata = {
1286 PBMEM(0xfff02400),
1287 IRQ(28),
1288 };
1289 static struct clk atmel_mci0_pclk = {
1290 .name = "mci_clk",
1291 .parent = &pbb_clk,
1292 .mode = pbb_clk_mode,
1293 .get_rate = pbb_clk_get_rate,
1294 .index = 9,
1295 };
1296
1297 struct platform_device *__init
1298 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1299 {
1300 struct platform_device *pdev;
1301 struct dw_dma_slave *dws;
1302 u32 pioa_mask;
1303 u32 piob_mask;
1304
1305 if (id != 0 || !data)
1306 return NULL;
1307
1308 /* Must have at least one usable slot */
1309 if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1310 return NULL;
1311
1312 pdev = platform_device_alloc("atmel_mci", id);
1313 if (!pdev)
1314 goto fail;
1315
1316 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1317 ARRAY_SIZE(atmel_mci0_resource)))
1318 goto fail;
1319
1320 if (data->dma_slave)
1321 dws = kmemdup(to_dw_dma_slave(data->dma_slave),
1322 sizeof(struct dw_dma_slave), GFP_KERNEL);
1323 else
1324 dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
1325
1326 dws->slave.dev = &pdev->dev;
1327 dws->slave.dma_dev = &dw_dmac0_device.dev;
1328 dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
1329 dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
1330 | DWC_CFGH_DST_PER(1));
1331 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1332 | DWC_CFGL_HS_SRC_POL);
1333
1334 data->dma_slave = &dws->slave;
1335
1336 if (platform_device_add_data(pdev, data,
1337 sizeof(struct mci_platform_data)))
1338 goto fail;
1339
1340 /* CLK line is common to both slots */
1341 pioa_mask = 1 << 10;
1342
1343 switch (data->slot[0].bus_width) {
1344 case 4:
1345 pioa_mask |= 1 << 13; /* DATA1 */
1346 pioa_mask |= 1 << 14; /* DATA2 */
1347 pioa_mask |= 1 << 15; /* DATA3 */
1348 /* fall through */
1349 case 1:
1350 pioa_mask |= 1 << 11; /* CMD */
1351 pioa_mask |= 1 << 12; /* DATA0 */
1352
1353 if (gpio_is_valid(data->slot[0].detect_pin))
1354 at32_select_gpio(data->slot[0].detect_pin, 0);
1355 if (gpio_is_valid(data->slot[0].wp_pin))
1356 at32_select_gpio(data->slot[0].wp_pin, 0);
1357 break;
1358 case 0:
1359 /* Slot is unused */
1360 break;
1361 default:
1362 goto fail;
1363 }
1364
1365 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1366 piob_mask = 0;
1367
1368 switch (data->slot[1].bus_width) {
1369 case 4:
1370 piob_mask |= 1 << 8; /* DATA1 */
1371 piob_mask |= 1 << 9; /* DATA2 */
1372 piob_mask |= 1 << 10; /* DATA3 */
1373 /* fall through */
1374 case 1:
1375 piob_mask |= 1 << 6; /* CMD */
1376 piob_mask |= 1 << 7; /* DATA0 */
1377 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1378
1379 if (gpio_is_valid(data->slot[1].detect_pin))
1380 at32_select_gpio(data->slot[1].detect_pin, 0);
1381 if (gpio_is_valid(data->slot[1].wp_pin))
1382 at32_select_gpio(data->slot[1].wp_pin, 0);
1383 break;
1384 case 0:
1385 /* Slot is unused */
1386 break;
1387 default:
1388 if (!data->slot[0].bus_width)
1389 goto fail;
1390
1391 data->slot[1].bus_width = 0;
1392 break;
1393 }
1394
1395 atmel_mci0_pclk.dev = &pdev->dev;
1396
1397 platform_device_add(pdev);
1398 return pdev;
1399
1400 fail:
1401 platform_device_put(pdev);
1402 return NULL;
1403 }
1404
1405 /* --------------------------------------------------------------------
1406 * LCDC
1407 * -------------------------------------------------------------------- */
1408 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1409 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1410 static struct resource atmel_lcdfb0_resource[] = {
1411 {
1412 .start = 0xff000000,
1413 .end = 0xff000fff,
1414 .flags = IORESOURCE_MEM,
1415 },
1416 IRQ(1),
1417 {
1418 /* Placeholder for pre-allocated fb memory */
1419 .start = 0x00000000,
1420 .end = 0x00000000,
1421 .flags = 0,
1422 },
1423 };
1424 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1425 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1426 static struct clk atmel_lcdfb0_pixclk = {
1427 .name = "lcdc_clk",
1428 .dev = &atmel_lcdfb0_device.dev,
1429 .mode = genclk_mode,
1430 .get_rate = genclk_get_rate,
1431 .set_rate = genclk_set_rate,
1432 .set_parent = genclk_set_parent,
1433 .index = 7,
1434 };
1435
1436 struct platform_device *__init
1437 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1438 unsigned long fbmem_start, unsigned long fbmem_len,
1439 u64 pin_mask)
1440 {
1441 struct platform_device *pdev;
1442 struct atmel_lcdfb_info *info;
1443 struct fb_monspecs *monspecs;
1444 struct fb_videomode *modedb;
1445 unsigned int modedb_size;
1446 u32 portc_mask, portd_mask, porte_mask;
1447
1448 /*
1449 * Do a deep copy of the fb data, monspecs and modedb. Make
1450 * sure all allocations are done before setting up the
1451 * portmux.
1452 */
1453 monspecs = kmemdup(data->default_monspecs,
1454 sizeof(struct fb_monspecs), GFP_KERNEL);
1455 if (!monspecs)
1456 return NULL;
1457
1458 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1459 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1460 if (!modedb)
1461 goto err_dup_modedb;
1462 monspecs->modedb = modedb;
1463
1464 switch (id) {
1465 case 0:
1466 pdev = &atmel_lcdfb0_device;
1467
1468 if (pin_mask == 0ULL)
1469 /* Default to "full" lcdc control signals and 24bit */
1470 pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1471
1472 /* LCDC on port C */
1473 portc_mask = (pin_mask & 0xfff80000) >> 19;
1474 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1475
1476 /* LCDC on port D */
1477 portd_mask = pin_mask & 0x0003ffff;
1478 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1479
1480 /* LCDC on port E */
1481 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1482 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1483
1484 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1485 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1486 break;
1487
1488 default:
1489 goto err_invalid_id;
1490 }
1491
1492 if (fbmem_len) {
1493 pdev->resource[2].start = fbmem_start;
1494 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1495 pdev->resource[2].flags = IORESOURCE_MEM;
1496 }
1497
1498 info = pdev->dev.platform_data;
1499 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1500 info->default_monspecs = monspecs;
1501
1502 platform_device_register(pdev);
1503 return pdev;
1504
1505 err_invalid_id:
1506 kfree(modedb);
1507 err_dup_modedb:
1508 kfree(monspecs);
1509 return NULL;
1510 }
1511 #endif
1512
1513 /* --------------------------------------------------------------------
1514 * PWM
1515 * -------------------------------------------------------------------- */
1516 static struct resource atmel_pwm0_resource[] __initdata = {
1517 PBMEM(0xfff01400),
1518 IRQ(24),
1519 };
1520 static struct clk atmel_pwm0_mck = {
1521 .name = "pwm_clk",
1522 .parent = &pbb_clk,
1523 .mode = pbb_clk_mode,
1524 .get_rate = pbb_clk_get_rate,
1525 .index = 5,
1526 };
1527
1528 struct platform_device *__init at32_add_device_pwm(u32 mask)
1529 {
1530 struct platform_device *pdev;
1531 u32 pin_mask;
1532
1533 if (!mask)
1534 return NULL;
1535
1536 pdev = platform_device_alloc("atmel_pwm", 0);
1537 if (!pdev)
1538 return NULL;
1539
1540 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1541 ARRAY_SIZE(atmel_pwm0_resource)))
1542 goto out_free_pdev;
1543
1544 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1545 goto out_free_pdev;
1546
1547 pin_mask = 0;
1548 if (mask & (1 << 0))
1549 pin_mask |= (1 << 28);
1550 if (mask & (1 << 1))
1551 pin_mask |= (1 << 29);
1552 if (pin_mask > 0)
1553 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1554
1555 pin_mask = 0;
1556 if (mask & (1 << 2))
1557 pin_mask |= (1 << 21);
1558 if (mask & (1 << 3))
1559 pin_mask |= (1 << 22);
1560 if (pin_mask > 0)
1561 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1562
1563 atmel_pwm0_mck.dev = &pdev->dev;
1564
1565 platform_device_add(pdev);
1566
1567 return pdev;
1568
1569 out_free_pdev:
1570 platform_device_put(pdev);
1571 return NULL;
1572 }
1573
1574 /* --------------------------------------------------------------------
1575 * SSC
1576 * -------------------------------------------------------------------- */
1577 static struct resource ssc0_resource[] = {
1578 PBMEM(0xffe01c00),
1579 IRQ(10),
1580 };
1581 DEFINE_DEV(ssc, 0);
1582 DEV_CLK(pclk, ssc0, pba, 7);
1583
1584 static struct resource ssc1_resource[] = {
1585 PBMEM(0xffe02000),
1586 IRQ(11),
1587 };
1588 DEFINE_DEV(ssc, 1);
1589 DEV_CLK(pclk, ssc1, pba, 8);
1590
1591 static struct resource ssc2_resource[] = {
1592 PBMEM(0xffe02400),
1593 IRQ(12),
1594 };
1595 DEFINE_DEV(ssc, 2);
1596 DEV_CLK(pclk, ssc2, pba, 9);
1597
1598 struct platform_device *__init
1599 at32_add_device_ssc(unsigned int id, unsigned int flags)
1600 {
1601 struct platform_device *pdev;
1602 u32 pin_mask = 0;
1603
1604 switch (id) {
1605 case 0:
1606 pdev = &ssc0_device;
1607 if (flags & ATMEL_SSC_RF)
1608 pin_mask |= (1 << 21); /* RF */
1609 if (flags & ATMEL_SSC_RK)
1610 pin_mask |= (1 << 22); /* RK */
1611 if (flags & ATMEL_SSC_TK)
1612 pin_mask |= (1 << 23); /* TK */
1613 if (flags & ATMEL_SSC_TF)
1614 pin_mask |= (1 << 24); /* TF */
1615 if (flags & ATMEL_SSC_TD)
1616 pin_mask |= (1 << 25); /* TD */
1617 if (flags & ATMEL_SSC_RD)
1618 pin_mask |= (1 << 26); /* RD */
1619
1620 if (pin_mask > 0)
1621 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1622
1623 break;
1624 case 1:
1625 pdev = &ssc1_device;
1626 if (flags & ATMEL_SSC_RF)
1627 pin_mask |= (1 << 0); /* RF */
1628 if (flags & ATMEL_SSC_RK)
1629 pin_mask |= (1 << 1); /* RK */
1630 if (flags & ATMEL_SSC_TK)
1631 pin_mask |= (1 << 2); /* TK */
1632 if (flags & ATMEL_SSC_TF)
1633 pin_mask |= (1 << 3); /* TF */
1634 if (flags & ATMEL_SSC_TD)
1635 pin_mask |= (1 << 4); /* TD */
1636 if (flags & ATMEL_SSC_RD)
1637 pin_mask |= (1 << 5); /* RD */
1638
1639 if (pin_mask > 0)
1640 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1641
1642 break;
1643 case 2:
1644 pdev = &ssc2_device;
1645 if (flags & ATMEL_SSC_TD)
1646 pin_mask |= (1 << 13); /* TD */
1647 if (flags & ATMEL_SSC_RD)
1648 pin_mask |= (1 << 14); /* RD */
1649 if (flags & ATMEL_SSC_TK)
1650 pin_mask |= (1 << 15); /* TK */
1651 if (flags & ATMEL_SSC_TF)
1652 pin_mask |= (1 << 16); /* TF */
1653 if (flags & ATMEL_SSC_RF)
1654 pin_mask |= (1 << 17); /* RF */
1655 if (flags & ATMEL_SSC_RK)
1656 pin_mask |= (1 << 18); /* RK */
1657
1658 if (pin_mask > 0)
1659 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1660
1661 break;
1662 default:
1663 return NULL;
1664 }
1665
1666 platform_device_register(pdev);
1667 return pdev;
1668 }
1669
1670 /* --------------------------------------------------------------------
1671 * USB Device Controller
1672 * -------------------------------------------------------------------- */
1673 static struct resource usba0_resource[] __initdata = {
1674 {
1675 .start = 0xff300000,
1676 .end = 0xff3fffff,
1677 .flags = IORESOURCE_MEM,
1678 }, {
1679 .start = 0xfff03000,
1680 .end = 0xfff033ff,
1681 .flags = IORESOURCE_MEM,
1682 },
1683 IRQ(31),
1684 };
1685 static struct clk usba0_pclk = {
1686 .name = "pclk",
1687 .parent = &pbb_clk,
1688 .mode = pbb_clk_mode,
1689 .get_rate = pbb_clk_get_rate,
1690 .index = 12,
1691 };
1692 static struct clk usba0_hclk = {
1693 .name = "hclk",
1694 .parent = &hsb_clk,
1695 .mode = hsb_clk_mode,
1696 .get_rate = hsb_clk_get_rate,
1697 .index = 6,
1698 };
1699
1700 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1701 [idx] = { \
1702 .name = nam, \
1703 .index = idx, \
1704 .fifo_size = maxpkt, \
1705 .nr_banks = maxbk, \
1706 .can_dma = dma, \
1707 .can_isoc = isoc, \
1708 }
1709
1710 static struct usba_ep_data at32_usba_ep[] __initdata = {
1711 EP("ep0", 0, 64, 1, 0, 0),
1712 EP("ep1", 1, 512, 2, 1, 1),
1713 EP("ep2", 2, 512, 2, 1, 1),
1714 EP("ep3-int", 3, 64, 3, 1, 0),
1715 EP("ep4-int", 4, 64, 3, 1, 0),
1716 EP("ep5", 5, 1024, 3, 1, 1),
1717 EP("ep6", 6, 1024, 3, 1, 1),
1718 };
1719
1720 #undef EP
1721
1722 struct platform_device *__init
1723 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1724 {
1725 /*
1726 * pdata doesn't have room for any endpoints, so we need to
1727 * append room for the ones we need right after it.
1728 */
1729 struct {
1730 struct usba_platform_data pdata;
1731 struct usba_ep_data ep[7];
1732 } usba_data;
1733 struct platform_device *pdev;
1734
1735 if (id != 0)
1736 return NULL;
1737
1738 pdev = platform_device_alloc("atmel_usba_udc", 0);
1739 if (!pdev)
1740 return NULL;
1741
1742 if (platform_device_add_resources(pdev, usba0_resource,
1743 ARRAY_SIZE(usba0_resource)))
1744 goto out_free_pdev;
1745
1746 if (data)
1747 usba_data.pdata.vbus_pin = data->vbus_pin;
1748 else
1749 usba_data.pdata.vbus_pin = -EINVAL;
1750
1751 data = &usba_data.pdata;
1752 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1753 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1754
1755 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1756 goto out_free_pdev;
1757
1758 if (data->vbus_pin >= 0)
1759 at32_select_gpio(data->vbus_pin, 0);
1760
1761 usba0_pclk.dev = &pdev->dev;
1762 usba0_hclk.dev = &pdev->dev;
1763
1764 platform_device_add(pdev);
1765
1766 return pdev;
1767
1768 out_free_pdev:
1769 platform_device_put(pdev);
1770 return NULL;
1771 }
1772
1773 /* --------------------------------------------------------------------
1774 * IDE / CompactFlash
1775 * -------------------------------------------------------------------- */
1776 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1777 static struct resource at32_smc_cs4_resource[] __initdata = {
1778 {
1779 .start = 0x04000000,
1780 .end = 0x07ffffff,
1781 .flags = IORESOURCE_MEM,
1782 },
1783 IRQ(~0UL), /* Magic IRQ will be overridden */
1784 };
1785 static struct resource at32_smc_cs5_resource[] __initdata = {
1786 {
1787 .start = 0x20000000,
1788 .end = 0x23ffffff,
1789 .flags = IORESOURCE_MEM,
1790 },
1791 IRQ(~0UL), /* Magic IRQ will be overridden */
1792 };
1793
1794 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1795 unsigned int cs, unsigned int extint)
1796 {
1797 static unsigned int extint_pin_map[4] __initdata = {
1798 (1 << 25),
1799 (1 << 26),
1800 (1 << 27),
1801 (1 << 28),
1802 };
1803 static bool common_pins_initialized __initdata = false;
1804 unsigned int extint_pin;
1805 int ret;
1806 u32 pin_mask;
1807
1808 if (extint >= ARRAY_SIZE(extint_pin_map))
1809 return -EINVAL;
1810 extint_pin = extint_pin_map[extint];
1811
1812 switch (cs) {
1813 case 4:
1814 ret = platform_device_add_resources(pdev,
1815 at32_smc_cs4_resource,
1816 ARRAY_SIZE(at32_smc_cs4_resource));
1817 if (ret)
1818 return ret;
1819
1820 /* NCS4 -> OE_N */
1821 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1822 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1823 break;
1824 case 5:
1825 ret = platform_device_add_resources(pdev,
1826 at32_smc_cs5_resource,
1827 ARRAY_SIZE(at32_smc_cs5_resource));
1828 if (ret)
1829 return ret;
1830
1831 /* NCS5 -> OE_N */
1832 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1833 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1834 break;
1835 default:
1836 return -EINVAL;
1837 }
1838
1839 if (!common_pins_initialized) {
1840 pin_mask = (1 << 19); /* CFCE1 -> CS0_N */
1841 pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */
1842 pin_mask |= (1 << 23); /* CFRNW -> DIR */
1843 pin_mask |= (1 << 24); /* NWAIT <- IORDY */
1844
1845 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1846
1847 common_pins_initialized = true;
1848 }
1849
1850 select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1851
1852 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1853 pdev->resource[1].end = pdev->resource[1].start;
1854
1855 return 0;
1856 }
1857
1858 struct platform_device *__init
1859 at32_add_device_ide(unsigned int id, unsigned int extint,
1860 struct ide_platform_data *data)
1861 {
1862 struct platform_device *pdev;
1863
1864 pdev = platform_device_alloc("at32_ide", id);
1865 if (!pdev)
1866 goto fail;
1867
1868 if (platform_device_add_data(pdev, data,
1869 sizeof(struct ide_platform_data)))
1870 goto fail;
1871
1872 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1873 goto fail;
1874
1875 platform_device_add(pdev);
1876 return pdev;
1877
1878 fail:
1879 platform_device_put(pdev);
1880 return NULL;
1881 }
1882
1883 struct platform_device *__init
1884 at32_add_device_cf(unsigned int id, unsigned int extint,
1885 struct cf_platform_data *data)
1886 {
1887 struct platform_device *pdev;
1888
1889 pdev = platform_device_alloc("at32_cf", id);
1890 if (!pdev)
1891 goto fail;
1892
1893 if (platform_device_add_data(pdev, data,
1894 sizeof(struct cf_platform_data)))
1895 goto fail;
1896
1897 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1898 goto fail;
1899
1900 if (gpio_is_valid(data->detect_pin))
1901 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1902 if (gpio_is_valid(data->reset_pin))
1903 at32_select_gpio(data->reset_pin, 0);
1904 if (gpio_is_valid(data->vcc_pin))
1905 at32_select_gpio(data->vcc_pin, 0);
1906 /* READY is used as extint, so we can't select it as gpio */
1907
1908 platform_device_add(pdev);
1909 return pdev;
1910
1911 fail:
1912 platform_device_put(pdev);
1913 return NULL;
1914 }
1915 #endif
1916
1917 /* --------------------------------------------------------------------
1918 * NAND Flash / SmartMedia
1919 * -------------------------------------------------------------------- */
1920 static struct resource smc_cs3_resource[] __initdata = {
1921 {
1922 .start = 0x0c000000,
1923 .end = 0x0fffffff,
1924 .flags = IORESOURCE_MEM,
1925 }, {
1926 .start = 0xfff03c00,
1927 .end = 0xfff03fff,
1928 .flags = IORESOURCE_MEM,
1929 },
1930 };
1931
1932 struct platform_device *__init
1933 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1934 {
1935 struct platform_device *pdev;
1936
1937 if (id != 0 || !data)
1938 return NULL;
1939
1940 pdev = platform_device_alloc("atmel_nand", id);
1941 if (!pdev)
1942 goto fail;
1943
1944 if (platform_device_add_resources(pdev, smc_cs3_resource,
1945 ARRAY_SIZE(smc_cs3_resource)))
1946 goto fail;
1947
1948 if (platform_device_add_data(pdev, data,
1949 sizeof(struct atmel_nand_data)))
1950 goto fail;
1951
1952 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1953 if (data->enable_pin)
1954 at32_select_gpio(data->enable_pin,
1955 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1956 if (data->rdy_pin)
1957 at32_select_gpio(data->rdy_pin, 0);
1958 if (data->det_pin)
1959 at32_select_gpio(data->det_pin, 0);
1960
1961 platform_device_add(pdev);
1962 return pdev;
1963
1964 fail:
1965 platform_device_put(pdev);
1966 return NULL;
1967 }
1968
1969 /* --------------------------------------------------------------------
1970 * AC97C
1971 * -------------------------------------------------------------------- */
1972 static struct resource atmel_ac97c0_resource[] __initdata = {
1973 PBMEM(0xfff02800),
1974 IRQ(29),
1975 };
1976 static struct clk atmel_ac97c0_pclk = {
1977 .name = "pclk",
1978 .parent = &pbb_clk,
1979 .mode = pbb_clk_mode,
1980 .get_rate = pbb_clk_get_rate,
1981 .index = 10,
1982 };
1983
1984 struct platform_device *__init
1985 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
1986 {
1987 struct platform_device *pdev;
1988 struct ac97c_platform_data _data;
1989 u32 pin_mask;
1990
1991 if (id != 0)
1992 return NULL;
1993
1994 pdev = platform_device_alloc("atmel_ac97c", id);
1995 if (!pdev)
1996 return NULL;
1997
1998 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1999 ARRAY_SIZE(atmel_ac97c0_resource)))
2000 goto fail;
2001
2002 if (!data) {
2003 data = &_data;
2004 memset(data, 0, sizeof(struct ac97c_platform_data));
2005 data->reset_pin = GPIO_PIN_NONE;
2006 }
2007
2008 data->dma_rx_periph_id = 3;
2009 data->dma_tx_periph_id = 4;
2010 data->dma_controller_id = 0;
2011
2012 if (platform_device_add_data(pdev, data,
2013 sizeof(struct ac97c_platform_data)))
2014 goto fail;
2015
2016 pin_mask = (1 << 20) | (1 << 21); /* SDO & SYNC */
2017 pin_mask |= (1 << 22) | (1 << 23); /* SCLK & SDI */
2018
2019 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2020
2021 /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
2022 if (data->reset_pin != GPIO_PIN_NONE)
2023 at32_select_gpio(data->reset_pin, 0);
2024
2025 atmel_ac97c0_pclk.dev = &pdev->dev;
2026
2027 platform_device_add(pdev);
2028 return pdev;
2029
2030 fail:
2031 platform_device_put(pdev);
2032 return NULL;
2033 }
2034
2035 /* --------------------------------------------------------------------
2036 * ABDAC
2037 * -------------------------------------------------------------------- */
2038 static struct resource abdac0_resource[] __initdata = {
2039 PBMEM(0xfff02000),
2040 IRQ(27),
2041 };
2042 static struct clk abdac0_pclk = {
2043 .name = "pclk",
2044 .parent = &pbb_clk,
2045 .mode = pbb_clk_mode,
2046 .get_rate = pbb_clk_get_rate,
2047 .index = 8,
2048 };
2049 static struct clk abdac0_sample_clk = {
2050 .name = "sample_clk",
2051 .mode = genclk_mode,
2052 .get_rate = genclk_get_rate,
2053 .set_rate = genclk_set_rate,
2054 .set_parent = genclk_set_parent,
2055 .index = 6,
2056 };
2057
2058 struct platform_device *__init at32_add_device_abdac(unsigned int id)
2059 {
2060 struct platform_device *pdev;
2061 u32 pin_mask;
2062
2063 if (id != 0)
2064 return NULL;
2065
2066 pdev = platform_device_alloc("abdac", id);
2067 if (!pdev)
2068 return NULL;
2069
2070 if (platform_device_add_resources(pdev, abdac0_resource,
2071 ARRAY_SIZE(abdac0_resource)))
2072 goto err_add_resources;
2073
2074 pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
2075 pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
2076
2077 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2078
2079 abdac0_pclk.dev = &pdev->dev;
2080 abdac0_sample_clk.dev = &pdev->dev;
2081
2082 platform_device_add(pdev);
2083 return pdev;
2084
2085 err_add_resources:
2086 platform_device_put(pdev);
2087 return NULL;
2088 }
2089
2090 /* --------------------------------------------------------------------
2091 * GCLK
2092 * -------------------------------------------------------------------- */
2093 static struct clk gclk0 = {
2094 .name = "gclk0",
2095 .mode = genclk_mode,
2096 .get_rate = genclk_get_rate,
2097 .set_rate = genclk_set_rate,
2098 .set_parent = genclk_set_parent,
2099 .index = 0,
2100 };
2101 static struct clk gclk1 = {
2102 .name = "gclk1",
2103 .mode = genclk_mode,
2104 .get_rate = genclk_get_rate,
2105 .set_rate = genclk_set_rate,
2106 .set_parent = genclk_set_parent,
2107 .index = 1,
2108 };
2109 static struct clk gclk2 = {
2110 .name = "gclk2",
2111 .mode = genclk_mode,
2112 .get_rate = genclk_get_rate,
2113 .set_rate = genclk_set_rate,
2114 .set_parent = genclk_set_parent,
2115 .index = 2,
2116 };
2117 static struct clk gclk3 = {
2118 .name = "gclk3",
2119 .mode = genclk_mode,
2120 .get_rate = genclk_get_rate,
2121 .set_rate = genclk_set_rate,
2122 .set_parent = genclk_set_parent,
2123 .index = 3,
2124 };
2125 static struct clk gclk4 = {
2126 .name = "gclk4",
2127 .mode = genclk_mode,
2128 .get_rate = genclk_get_rate,
2129 .set_rate = genclk_set_rate,
2130 .set_parent = genclk_set_parent,
2131 .index = 4,
2132 };
2133
2134 static __initdata struct clk *init_clocks[] = {
2135 &osc32k,
2136 &osc0,
2137 &osc1,
2138 &pll0,
2139 &pll1,
2140 &cpu_clk,
2141 &hsb_clk,
2142 &pba_clk,
2143 &pbb_clk,
2144 &at32_pm_pclk,
2145 &at32_intc0_pclk,
2146 &at32_hmatrix_clk,
2147 &ebi_clk,
2148 &hramc_clk,
2149 &sdramc_clk,
2150 &smc0_pclk,
2151 &smc0_mck,
2152 &pdc_hclk,
2153 &pdc_pclk,
2154 &dw_dmac0_hclk,
2155 &pico_clk,
2156 &pio0_mck,
2157 &pio1_mck,
2158 &pio2_mck,
2159 &pio3_mck,
2160 &pio4_mck,
2161 &at32_tcb0_t0_clk,
2162 &at32_tcb1_t0_clk,
2163 &atmel_psif0_pclk,
2164 &atmel_psif1_pclk,
2165 &atmel_usart0_usart,
2166 &atmel_usart1_usart,
2167 &atmel_usart2_usart,
2168 &atmel_usart3_usart,
2169 &atmel_pwm0_mck,
2170 #if defined(CONFIG_CPU_AT32AP7000)
2171 &macb0_hclk,
2172 &macb0_pclk,
2173 &macb1_hclk,
2174 &macb1_pclk,
2175 #endif
2176 &atmel_spi0_spi_clk,
2177 &atmel_spi1_spi_clk,
2178 &atmel_twi0_pclk,
2179 &atmel_mci0_pclk,
2180 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2181 &atmel_lcdfb0_hck1,
2182 &atmel_lcdfb0_pixclk,
2183 #endif
2184 &ssc0_pclk,
2185 &ssc1_pclk,
2186 &ssc2_pclk,
2187 &usba0_hclk,
2188 &usba0_pclk,
2189 &atmel_ac97c0_pclk,
2190 &abdac0_pclk,
2191 &abdac0_sample_clk,
2192 &gclk0,
2193 &gclk1,
2194 &gclk2,
2195 &gclk3,
2196 &gclk4,
2197 };
2198
2199 void __init setup_platform(void)
2200 {
2201 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2202 int i;
2203
2204 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2205 main_clock = &pll0;
2206 cpu_clk.parent = &pll0;
2207 } else {
2208 main_clock = &osc0;
2209 cpu_clk.parent = &osc0;
2210 }
2211
2212 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2213 pll0.parent = &osc1;
2214 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2215 pll1.parent = &osc1;
2216
2217 genclk_init_parent(&gclk0);
2218 genclk_init_parent(&gclk1);
2219 genclk_init_parent(&gclk2);
2220 genclk_init_parent(&gclk3);
2221 genclk_init_parent(&gclk4);
2222 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2223 genclk_init_parent(&atmel_lcdfb0_pixclk);
2224 #endif
2225 genclk_init_parent(&abdac0_sample_clk);
2226
2227 /*
2228 * Build initial dynamic clock list by registering all clocks
2229 * from the array.
2230 * At the same time, turn on all clocks that have at least one
2231 * user already, and turn off everything else. We only do this
2232 * for module clocks, and even though it isn't particularly
2233 * pretty to check the address of the mode function, it should
2234 * do the trick...
2235 */
2236 for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2237 struct clk *clk = init_clocks[i];
2238
2239 /* first, register clock */
2240 at32_clk_register(clk);
2241
2242 if (clk->users == 0)
2243 continue;
2244
2245 if (clk->mode == &cpu_clk_mode)
2246 cpu_mask |= 1 << clk->index;
2247 else if (clk->mode == &hsb_clk_mode)
2248 hsb_mask |= 1 << clk->index;
2249 else if (clk->mode == &pba_clk_mode)
2250 pba_mask |= 1 << clk->index;
2251 else if (clk->mode == &pbb_clk_mode)
2252 pbb_mask |= 1 << clk->index;
2253 }
2254
2255 pm_writel(CPU_MASK, cpu_mask);
2256 pm_writel(HSB_MASK, hsb_mask);
2257 pm_writel(PBA_MASK, pba_mask);
2258 pm_writel(PBB_MASK, pbb_mask);
2259
2260 /* Initialize the port muxes */
2261 at32_init_pio(&pio0_device);
2262 at32_init_pio(&pio1_device);
2263 at32_init_pio(&pio2_device);
2264 at32_init_pio(&pio3_device);
2265 at32_init_pio(&pio4_device);
2266 }
2267
2268 struct gen_pool *sram_pool;
2269
2270 static int __init sram_init(void)
2271 {
2272 struct gen_pool *pool;
2273
2274 /* 1KiB granularity */
2275 pool = gen_pool_create(10, -1);
2276 if (!pool)
2277 goto fail;
2278
2279 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2280 goto err_pool_add;
2281
2282 sram_pool = pool;
2283 return 0;
2284
2285 err_pool_add:
2286 gen_pool_destroy(pool);
2287 fail:
2288 pr_err("Failed to create SRAM pool\n");
2289 return -ENOMEM;
2290 }
2291 core_initcall(sram_init);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree