drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 enum {
   5     RCS = 0x0,
   6     VCS,
   7     BCS,
   8     I915_NUM_RINGS,
   9 };
  10
  11 struct  intel_hw_status_page {
  12         u32     __iomem *page_addr;
  13         unsigned int    gfx_addr;
  14         struct          drm_i915_gem_object *obj;
  15 };
  16
  17 #define I915_RING_READ(reg) i915_gt_read(dev_priv, reg)
  18 #define I915_RING_WRITE(reg, val) i915_gt_write(dev_priv, reg, val)
  19
  20 #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
  21 #define I915_WRITE_TAIL(ring, val) I915_RING_WRITE(RING_TAIL((ring)->mmio_base), val)
  22
  23 #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
  24 #define I915_WRITE_START(ring, val) I915_RING_WRITE(RING_START((ring)->mmio_base), val)
  25
  26 #define I915_READ_HEAD(ring)  I915_RING_READ(RING_HEAD((ring)->mmio_base))
  27 #define I915_WRITE_HEAD(ring, val) I915_RING_WRITE(RING_HEAD((ring)->mmio_base), val)
  28
  29 #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
  30 #define I915_WRITE_CTL(ring, val) I915_RING_WRITE(RING_CTL((ring)->mmio_base), val)
  31
  32 #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
  33 #define I915_WRITE_IMR(ring, val) I915_RING_WRITE(RING_IMR((ring)->mmio_base), val)
  34
  35 #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
  36 #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
  37 #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base))
  38
  39 struct  intel_ring_buffer {
  40         const char      *name;
  41         enum intel_ring_id {
  42                 RING_RENDER = 0x1,
  43                 RING_BSD = 0x2,
  44                 RING_BLT = 0x4,
  45         } id;
  46         u32             mmio_base;
  47         void            __iomem *virtual_start;
  48         struct          drm_device *dev;
  49         struct          drm_i915_gem_object *obj;
  50
  51         u32             head;
  52         u32             tail;
  53         int             space;
  54         int             size;
  55         int             effective_size;
  56         struct intel_hw_status_page status_page;
  57
  58         spinlock_t      irq_lock;
  59         u32             irq_refcount;
  60         u32             irq_mask;
  61         u32             irq_seqno;              /* last seq seem at irq time */
  62         u32             trace_irq_seqno;
  63         u32             waiting_seqno;
  64         u32             sync_seqno[I915_NUM_RINGS-1];
  65         bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  66         void            (*irq_put)(struct intel_ring_buffer *ring);
  67
  68         int             (*init)(struct intel_ring_buffer *ring);
  69
  70         void            (*write_tail)(struct intel_ring_buffer *ring,
  71                                       u32 value);
  72         int __must_check (*flush)(struct intel_ring_buffer *ring,
  73                                   u32   invalidate_domains,
  74                                   u32   flush_domains);
  75         int             (*add_request)(struct intel_ring_buffer *ring,
  76                                        u32 *seqno);
  77         u32             (*get_seqno)(struct intel_ring_buffer *ring);
  78         int             (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
  79                                                u32 offset, u32 length);
  80         void            (*cleanup)(struct intel_ring_buffer *ring);
  81
  82         /**
  83          * List of objects currently involved in rendering from the
  84          * ringbuffer.
  85          *
  86          * Includes buffers having the contents of their GPU caches
  87          * flushed, not necessarily primitives.  last_rendering_seqno
  88          * represents when the rendering involved will be completed.
  89          *
  90          * A reference is held on the buffer while on this list.
  91          */
  92         struct list_head active_list;
  93
  94         /**
  95          * List of breadcrumbs associated with GPU requests currently
  96          * outstanding.
  97          */
  98         struct list_head request_list;
  99
 100         /**
 101          * List of objects currently pending a GPU write flush.
 102          *
 103          * All elements on this list will belong to either the
 104          * active_list or flushing_list, last_rendering_seqno can
 105          * be used to differentiate between the two elements.
 106          */
 107         struct list_head gpu_write_list;
 108
 109         /**
 110          * Do we have some not yet emitted requests outstanding?
 111          */
 112         u32 outstanding_lazy_request;
 113
 114         wait_queue_head_t irq_queue;
 115         drm_local_map_t map;
 116
 117         void *private;
 118 };
 119
 120 static inline u32
 121 intel_ring_sync_index(struct intel_ring_buffer *ring,
 122                       struct intel_ring_buffer *other)
 123 {
 124         int idx;
 125
 126         /*
 127          * cs -> 0 = vcs, 1 = bcs
 128          * vcs -> 0 = bcs, 1 = cs,
 129          * bcs -> 0 = cs, 1 = vcs.
 130          */
 131
 132         idx = (other - ring) - 1;
 133         if (idx < 0)
 134                 idx += I915_NUM_RINGS;
 135
 136         return idx;
 137 }
 138
 139 static inline u32
 140 intel_read_status_page(struct intel_ring_buffer *ring,
 141                        int reg)
 142 {
 143         return ioread32(ring->status_page.page_addr + reg);
 144 }
 145
 146 /**
 147  * Reads a dword out of the status page, which is written to from the command
 148  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 149  * MI_STORE_DATA_IMM.
 150  *
 151  * The following dwords have a reserved meaning:
 152  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 153  * 0x04: ring 0 head pointer
 154  * 0x05: ring 1 head pointer (915-class)
 155  * 0x06: ring 2 head pointer (915-class)
 156  * 0x10-0x1b: Context status DWords (GM45)
 157  * 0x1f: Last written status offset. (GM45)
 158  *
 159  * The area from dword 0x20 to 0x3ff is available for driver usage.
 160  */
 161 #define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg)
 162 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 163 #define I915_GEM_HWS_INDEX              0x20
 164 #define I915_BREADCRUMB_INDEX           0x21
 165
 166 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 167 int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
 168 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
 169
 170 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
 171                                    u32 data)
 172 {
 173         iowrite32(data, ring->virtual_start + ring->tail);
 174         ring->tail += 4;
 175 }
 176
 177 void intel_ring_advance(struct intel_ring_buffer *ring);
 178
 179 u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
 180 int intel_ring_sync(struct intel_ring_buffer *ring,
 181                     struct intel_ring_buffer *to,
 182                     u32 seqno);
 183
 184 int intel_init_render_ring_buffer(struct drm_device *dev);
 185 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 186 int intel_init_blt_ring_buffer(struct drm_device *dev);
 187
 188 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
 189 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 190
 191 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
 192 {
 193         if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
 194                 ring->trace_irq_seqno = seqno;
 195 }
 196
 197 /* DRI warts */
 198 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 199
 200 #endif /* _INTEL_RINGBUFFER_H_ */