?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
PCI SR-IOV: correct broken resource alignment calculations
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / spi / spi_bfin5xx.c
blobf014cc21e8131051542a0641129ce9018ec51020
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi.h>
23 #include <linux/workqueue.h>
24
25 #include <asm/dma.h>
26 #include <asm/portmux.h>
27 #include <asm/bfin5xx_spi.h>
28 #include <asm/cacheflush.h>
29
30 #define DRV_NAME "bfin-spi"
31 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
32 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
33 #define DRV_VERSION "1.0"
34
35 MODULE_AUTHOR(DRV_AUTHOR);
36 MODULE_DESCRIPTION(DRV_DESC);
37 MODULE_LICENSE("GPL");
38
39 #define START_STATE ((void *)0)
40 #define RUNNING_STATE ((void *)1)
41 #define DONE_STATE ((void *)2)
42 #define ERROR_STATE ((void *)-1)
43 #define QUEUE_RUNNING 0
44 #define QUEUE_STOPPED 1
45
46 /* Value to send if no TX value is supplied */
47 #define SPI_IDLE_TXVAL 0x0000
48
49 struct driver_data {
50 /* Driver model hookup */
51 struct platform_device *pdev;
52
53 /* SPI framework hookup */
54 struct spi_master *master;
55
56 /* Regs base of SPI controller */
57 void __iomem *regs_base;
58
59 /* Pin request list */
60 u16 *pin_req;
61
62 /* BFIN hookup */
63 struct bfin5xx_spi_master *master_info;
64
65 /* Driver message queue */
66 struct workqueue_struct *workqueue;
67 struct work_struct pump_messages;
68 spinlock_t lock;
69 struct list_head queue;
70 int busy;
71 int run;
72
73 /* Message Transfer pump */
74 struct tasklet_struct pump_transfers;
75
76 /* Current message transfer state info */
77 struct spi_message *cur_msg;
78 struct spi_transfer *cur_transfer;
79 struct chip_data *cur_chip;
80 size_t len_in_bytes;
81 size_t len;
82 void *tx;
83 void *tx_end;
84 void *rx;
85 void *rx_end;
86
87 /* DMA stuffs */
88 int dma_channel;
89 int dma_mapped;
90 int dma_requested;
91 dma_addr_t rx_dma;
92 dma_addr_t tx_dma;
93
94 size_t rx_map_len;
95 size_t tx_map_len;
96 u8 n_bytes;
97 int cs_change;
98 void (*write) (struct driver_data *);
99 void (*read) (struct driver_data *);
100 void (*duplex) (struct driver_data *);
101 };
102
103 struct chip_data {
104 u16 ctl_reg;
105 u16 baud;
106 u16 flag;
107
108 u8 chip_select_num;
109 u8 n_bytes;
110 u8 width; /* 0 or 1 */
111 u8 enable_dma;
112 u8 bits_per_word; /* 8 or 16 */
113 u8 cs_change_per_word;
114 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
115 u32 cs_gpio;
116 u16 idle_tx_val;
117 void (*write) (struct driver_data *);
118 void (*read) (struct driver_data *);
119 void (*duplex) (struct driver_data *);
120 };
121
122 #define DEFINE_SPI_REG(reg, off) \
123 static inline u16 read_##reg(struct driver_data *drv_data) \
124 { return bfin_read16(drv_data->regs_base + off); } \
125 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
126 { bfin_write16(drv_data->regs_base + off, v); }
127
128 DEFINE_SPI_REG(CTRL, 0x00)
129 DEFINE_SPI_REG(FLAG, 0x04)
130 DEFINE_SPI_REG(STAT, 0x08)
131 DEFINE_SPI_REG(TDBR, 0x0C)
132 DEFINE_SPI_REG(RDBR, 0x10)
133 DEFINE_SPI_REG(BAUD, 0x14)
134 DEFINE_SPI_REG(SHAW, 0x18)
135
136 static void bfin_spi_enable(struct driver_data *drv_data)
137 {
138 u16 cr;
139
140 cr = read_CTRL(drv_data);
141 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
142 }
143
144 static void bfin_spi_disable(struct driver_data *drv_data)
145 {
146 u16 cr;
147
148 cr = read_CTRL(drv_data);
149 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
150 }
151
152 /* Caculate the SPI_BAUD register value based on input HZ */
153 static u16 hz_to_spi_baud(u32 speed_hz)
154 {
155 u_long sclk = get_sclk();
156 u16 spi_baud = (sclk / (2 * speed_hz));
157
158 if ((sclk % (2 * speed_hz)) > 0)
159 spi_baud++;
160
161 if (spi_baud < MIN_SPI_BAUD_VAL)
162 spi_baud = MIN_SPI_BAUD_VAL;
163
164 return spi_baud;
165 }
166
167 static int bfin_spi_flush(struct driver_data *drv_data)
168 {
169 unsigned long limit = loops_per_jiffy << 1;
170
171 /* wait for stop and clear stat */
172 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
173 cpu_relax();
174
175 write_STAT(drv_data, BIT_STAT_CLR);
176
177 return limit;
178 }
179
180 /* Chip select operation functions for cs_change flag */
181 static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip)
182 {
183 if (likely(chip->chip_select_num)) {
184 u16 flag = read_FLAG(drv_data);
185
186 flag |= chip->flag;
187 flag &= ~(chip->flag << 8);
188
189 write_FLAG(drv_data, flag);
190 } else {
191 gpio_set_value(chip->cs_gpio, 0);
192 }
193 }
194
195 static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
196 {
197 if (likely(chip->chip_select_num)) {
198 u16 flag = read_FLAG(drv_data);
199
200 flag &= ~chip->flag;
201 flag |= (chip->flag << 8);
202
203 write_FLAG(drv_data, flag);
204 } else {
205 gpio_set_value(chip->cs_gpio, 1);
206 }
207
208 /* Move delay here for consistency */
209 if (chip->cs_chg_udelay)
210 udelay(chip->cs_chg_udelay);
211 }
212
213 /* stop controller and re-config current chip*/
214 static void bfin_spi_restore_state(struct driver_data *drv_data)
215 {
216 struct chip_data *chip = drv_data->cur_chip;
217
218 /* Clear status and disable clock */
219 write_STAT(drv_data, BIT_STAT_CLR);
220 bfin_spi_disable(drv_data);
221 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
222
223 /* Load the registers */
224 write_CTRL(drv_data, chip->ctl_reg);
225 write_BAUD(drv_data, chip->baud);
226
227 bfin_spi_enable(drv_data);
228 bfin_spi_cs_active(drv_data, chip);
229 }
230
231 /* used to kick off transfer in rx mode and read unwanted RX data */
232 static inline void bfin_spi_dummy_read(struct driver_data *drv_data)
233 {
234 (void) read_RDBR(drv_data);
235 }
236
237 static void bfin_spi_null_writer(struct driver_data *drv_data)
238 {
239 u8 n_bytes = drv_data->n_bytes;
240 u16 tx_val = drv_data->cur_chip->idle_tx_val;
241
242 /* clear RXS (we check for RXS inside the loop) */
243 bfin_spi_dummy_read(drv_data);
244
245 while (drv_data->tx < drv_data->tx_end) {
246 write_TDBR(drv_data, tx_val);
247 drv_data->tx += n_bytes;
248 /* wait until transfer finished.
249 checking SPIF or TXS may not guarantee transfer completion */
250 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
251 cpu_relax();
252 /* discard RX data and clear RXS */
253 bfin_spi_dummy_read(drv_data);
254 }
255 }
256
257 static void bfin_spi_null_reader(struct driver_data *drv_data)
258 {
259 u8 n_bytes = drv_data->n_bytes;
260 u16 tx_val = drv_data->cur_chip->idle_tx_val;
261
262 /* discard old RX data and clear RXS */
263 bfin_spi_dummy_read(drv_data);
264
265 while (drv_data->rx < drv_data->rx_end) {
266 write_TDBR(drv_data, tx_val);
267 drv_data->rx += n_bytes;
268 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
269 cpu_relax();
270 bfin_spi_dummy_read(drv_data);
271 }
272 }
273
274 static void bfin_spi_u8_writer(struct driver_data *drv_data)
275 {
276 /* clear RXS (we check for RXS inside the loop) */
277 bfin_spi_dummy_read(drv_data);
278
279 while (drv_data->tx < drv_data->tx_end) {
280 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
281 /* wait until transfer finished.
282 checking SPIF or TXS may not guarantee transfer completion */
283 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
284 cpu_relax();
285 /* discard RX data and clear RXS */
286 bfin_spi_dummy_read(drv_data);
287 }
288 }
289
290 static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data)
291 {
292 struct chip_data *chip = drv_data->cur_chip;
293
294 /* clear RXS (we check for RXS inside the loop) */
295 bfin_spi_dummy_read(drv_data);
296
297 while (drv_data->tx < drv_data->tx_end) {
298 bfin_spi_cs_active(drv_data, chip);
299 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
300 /* make sure transfer finished before deactiving CS */
301 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
302 cpu_relax();
303 bfin_spi_dummy_read(drv_data);
304 bfin_spi_cs_deactive(drv_data, chip);
305 }
306 }
307
308 static void bfin_spi_u8_reader(struct driver_data *drv_data)
309 {
310 u16 tx_val = drv_data->cur_chip->idle_tx_val;
311
312 /* discard old RX data and clear RXS */
313 bfin_spi_dummy_read(drv_data);
314
315 while (drv_data->rx < drv_data->rx_end) {
316 write_TDBR(drv_data, tx_val);
317 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
318 cpu_relax();
319 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
320 }
321 }
322
323 static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data)
324 {
325 struct chip_data *chip = drv_data->cur_chip;
326 u16 tx_val = chip->idle_tx_val;
327
328 /* discard old RX data and clear RXS */
329 bfin_spi_dummy_read(drv_data);
330
331 while (drv_data->rx < drv_data->rx_end) {
332 bfin_spi_cs_active(drv_data, chip);
333 write_TDBR(drv_data, tx_val);
334 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
335 cpu_relax();
336 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
337 bfin_spi_cs_deactive(drv_data, chip);
338 }
339 }
340
341 static void bfin_spi_u8_duplex(struct driver_data *drv_data)
342 {
343 /* discard old RX data and clear RXS */
344 bfin_spi_dummy_read(drv_data);
345
346 while (drv_data->rx < drv_data->rx_end) {
347 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
348 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
349 cpu_relax();
350 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
351 }
352 }
353
354 static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data)
355 {
356 struct chip_data *chip = drv_data->cur_chip;
357
358 /* discard old RX data and clear RXS */
359 bfin_spi_dummy_read(drv_data);
360
361 while (drv_data->rx < drv_data->rx_end) {
362 bfin_spi_cs_active(drv_data, chip);
363 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
364 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
365 cpu_relax();
366 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
367 bfin_spi_cs_deactive(drv_data, chip);
368 }
369 }
370
371 static void bfin_spi_u16_writer(struct driver_data *drv_data)
372 {
373 /* clear RXS (we check for RXS inside the loop) */
374 bfin_spi_dummy_read(drv_data);
375
376 while (drv_data->tx < drv_data->tx_end) {
377 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
378 drv_data->tx += 2;
379 /* wait until transfer finished.
380 checking SPIF or TXS may not guarantee transfer completion */
381 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
382 cpu_relax();
383 /* discard RX data and clear RXS */
384 bfin_spi_dummy_read(drv_data);
385 }
386 }
387
388 static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data)
389 {
390 struct chip_data *chip = drv_data->cur_chip;
391
392 /* clear RXS (we check for RXS inside the loop) */
393 bfin_spi_dummy_read(drv_data);
394
395 while (drv_data->tx < drv_data->tx_end) {
396 bfin_spi_cs_active(drv_data, chip);
397 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
398 drv_data->tx += 2;
399 /* make sure transfer finished before deactiving CS */
400 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
401 cpu_relax();
402 bfin_spi_dummy_read(drv_data);
403 bfin_spi_cs_deactive(drv_data, chip);
404 }
405 }
406
407 static void bfin_spi_u16_reader(struct driver_data *drv_data)
408 {
409 u16 tx_val = drv_data->cur_chip->idle_tx_val;
410
411 /* discard old RX data and clear RXS */
412 bfin_spi_dummy_read(drv_data);
413
414 while (drv_data->rx < drv_data->rx_end) {
415 write_TDBR(drv_data, tx_val);
416 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
417 cpu_relax();
418 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
419 drv_data->rx += 2;
420 }
421 }
422
423 static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data)
424 {
425 struct chip_data *chip = drv_data->cur_chip;
426 u16 tx_val = chip->idle_tx_val;
427
428 /* discard old RX data and clear RXS */
429 bfin_spi_dummy_read(drv_data);
430
431 while (drv_data->rx < drv_data->rx_end) {
432 bfin_spi_cs_active(drv_data, chip);
433 write_TDBR(drv_data, tx_val);
434 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
435 cpu_relax();
436 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
437 drv_data->rx += 2;
438 bfin_spi_cs_deactive(drv_data, chip);
439 }
440 }
441
442 static void bfin_spi_u16_duplex(struct driver_data *drv_data)
443 {
444 /* discard old RX data and clear RXS */
445 bfin_spi_dummy_read(drv_data);
446
447 while (drv_data->rx < drv_data->rx_end) {
448 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
449 drv_data->tx += 2;
450 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
451 cpu_relax();
452 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
453 drv_data->rx += 2;
454 }
455 }
456
457 static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data)
458 {
459 struct chip_data *chip = drv_data->cur_chip;
460
461 /* discard old RX data and clear RXS */
462 bfin_spi_dummy_read(drv_data);
463
464 while (drv_data->rx < drv_data->rx_end) {
465 bfin_spi_cs_active(drv_data, chip);
466 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
467 drv_data->tx += 2;
468 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
469 cpu_relax();
470 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
471 drv_data->rx += 2;
472 bfin_spi_cs_deactive(drv_data, chip);
473 }
474 }
475
476 /* test if ther is more transfer to be done */
477 static void *bfin_spi_next_transfer(struct driver_data *drv_data)
478 {
479 struct spi_message *msg = drv_data->cur_msg;
480 struct spi_transfer *trans = drv_data->cur_transfer;
481
482 /* Move to next transfer */
483 if (trans->transfer_list.next != &msg->transfers) {
484 drv_data->cur_transfer =
485 list_entry(trans->transfer_list.next,
486 struct spi_transfer, transfer_list);
487 return RUNNING_STATE;
488 } else
489 return DONE_STATE;
490 }
491
492 /*
493 * caller already set message->status;
494 * dma and pio irqs are blocked give finished message back
495 */
496 static void bfin_spi_giveback(struct driver_data *drv_data)
497 {
498 struct chip_data *chip = drv_data->cur_chip;
499 struct spi_transfer *last_transfer;
500 unsigned long flags;
501 struct spi_message *msg;
502
503 spin_lock_irqsave(&drv_data->lock, flags);
504 msg = drv_data->cur_msg;
505 drv_data->cur_msg = NULL;
506 drv_data->cur_transfer = NULL;
507 drv_data->cur_chip = NULL;
508 queue_work(drv_data->workqueue, &drv_data->pump_messages);
509 spin_unlock_irqrestore(&drv_data->lock, flags);
510
511 last_transfer = list_entry(msg->transfers.prev,
512 struct spi_transfer, transfer_list);
513
514 msg->state = NULL;
515
516 if (!drv_data->cs_change)
517 bfin_spi_cs_deactive(drv_data, chip);
518
519 /* Not stop spi in autobuffer mode */
520 if (drv_data->tx_dma != 0xFFFF)
521 bfin_spi_disable(drv_data);
522
523 if (msg->complete)
524 msg->complete(msg->context);
525 }
526
527 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
528 {
529 struct driver_data *drv_data = dev_id;
530 struct chip_data *chip = drv_data->cur_chip;
531 struct spi_message *msg = drv_data->cur_msg;
532 unsigned long timeout;
533 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
534 u16 spistat = read_STAT(drv_data);
535
536 dev_dbg(&drv_data->pdev->dev,
537 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
538 dmastat, spistat);
539
540 clear_dma_irqstat(drv_data->dma_channel);
541
542 /* Wait for DMA to complete */
543 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
544 cpu_relax();
545
546 /*
547 * wait for the last transaction shifted out. HRM states:
548 * at this point there may still be data in the SPI DMA FIFO waiting
549 * to be transmitted ... software needs to poll TXS in the SPI_STAT
550 * register until it goes low for 2 successive reads
551 */
552 if (drv_data->tx != NULL) {
553 while ((read_STAT(drv_data) & TXS) ||
554 (read_STAT(drv_data) & TXS))
555 cpu_relax();
556 }
557
558 dev_dbg(&drv_data->pdev->dev,
559 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
560 dmastat, read_STAT(drv_data));
561
562 timeout = jiffies + HZ;
563 while (!(read_STAT(drv_data) & SPIF))
564 if (!time_before(jiffies, timeout)) {
565 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
566 break;
567 } else
568 cpu_relax();
569
570 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
571 msg->state = ERROR_STATE;
572 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
573 } else {
574 msg->actual_length += drv_data->len_in_bytes;
575
576 if (drv_data->cs_change)
577 bfin_spi_cs_deactive(drv_data, chip);
578
579 /* Move to next transfer */
580 msg->state = bfin_spi_next_transfer(drv_data);
581 }
582
583 /* Schedule transfer tasklet */
584 tasklet_schedule(&drv_data->pump_transfers);
585
586 /* free the irq handler before next transfer */
587 dev_dbg(&drv_data->pdev->dev,
588 "disable dma channel irq%d\n",
589 drv_data->dma_channel);
590 dma_disable_irq(drv_data->dma_channel);
591
592 return IRQ_HANDLED;
593 }
594
595 static void bfin_spi_pump_transfers(unsigned long data)
596 {
597 struct driver_data *drv_data = (struct driver_data *)data;
598 struct spi_message *message = NULL;
599 struct spi_transfer *transfer = NULL;
600 struct spi_transfer *previous = NULL;
601 struct chip_data *chip = NULL;
602 u8 width;
603 u16 cr, dma_width, dma_config;
604 u32 tranf_success = 1;
605 u8 full_duplex = 0;
606
607 /* Get current state information */
608 message = drv_data->cur_msg;
609 transfer = drv_data->cur_transfer;
610 chip = drv_data->cur_chip;
611
612 /*
613 * if msg is error or done, report it back using complete() callback
614 */
615
616 /* Handle for abort */
617 if (message->state == ERROR_STATE) {
618 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
619 message->status = -EIO;
620 bfin_spi_giveback(drv_data);
621 return;
622 }
623
624 /* Handle end of message */
625 if (message->state == DONE_STATE) {
626 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
627 message->status = 0;
628 bfin_spi_giveback(drv_data);
629 return;
630 }
631
632 /* Delay if requested at end of transfer */
633 if (message->state == RUNNING_STATE) {
634 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
635 previous = list_entry(transfer->transfer_list.prev,
636 struct spi_transfer, transfer_list);
637 if (previous->delay_usecs)
638 udelay(previous->delay_usecs);
639 }
640
641 /* Setup the transfer state based on the type of transfer */
642 if (bfin_spi_flush(drv_data) == 0) {
643 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
644 message->status = -EIO;
645 bfin_spi_giveback(drv_data);
646 return;
647 }
648
649 if (transfer->len == 0) {
650 /* Move to next transfer of this msg */
651 message->state = bfin_spi_next_transfer(drv_data);
652 /* Schedule next transfer tasklet */
653 tasklet_schedule(&drv_data->pump_transfers);
654 }
655
656 if (transfer->tx_buf != NULL) {
657 drv_data->tx = (void *)transfer->tx_buf;
658 drv_data->tx_end = drv_data->tx + transfer->len;
659 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
660 transfer->tx_buf, drv_data->tx_end);
661 } else {
662 drv_data->tx = NULL;
663 }
664
665 if (transfer->rx_buf != NULL) {
666 full_duplex = transfer->tx_buf != NULL;
667 drv_data->rx = transfer->rx_buf;
668 drv_data->rx_end = drv_data->rx + transfer->len;
669 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
670 transfer->rx_buf, drv_data->rx_end);
671 } else {
672 drv_data->rx = NULL;
673 }
674
675 drv_data->rx_dma = transfer->rx_dma;
676 drv_data->tx_dma = transfer->tx_dma;
677 drv_data->len_in_bytes = transfer->len;
678 drv_data->cs_change = transfer->cs_change;
679
680 /* Bits per word setup */
681 switch (transfer->bits_per_word) {
682 case 8:
683 drv_data->n_bytes = 1;
684 width = CFG_SPI_WORDSIZE8;
685 drv_data->read = chip->cs_change_per_word ?
686 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
687 drv_data->write = chip->cs_change_per_word ?
688 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
689 drv_data->duplex = chip->cs_change_per_word ?
690 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
691 break;
692
693 case 16:
694 drv_data->n_bytes = 2;
695 width = CFG_SPI_WORDSIZE16;
696 drv_data->read = chip->cs_change_per_word ?
697 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
698 drv_data->write = chip->cs_change_per_word ?
699 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
700 drv_data->duplex = chip->cs_change_per_word ?
701 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
702 break;
703
704 default:
705 /* No change, the same as default setting */
706 drv_data->n_bytes = chip->n_bytes;
707 width = chip->width;
708 drv_data->write = drv_data->tx ? chip->write : bfin_spi_null_writer;
709 drv_data->read = drv_data->rx ? chip->read : bfin_spi_null_reader;
710 drv_data->duplex = chip->duplex ? chip->duplex : bfin_spi_null_writer;
711 break;
712 }
713 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
714 cr |= (width << 8);
715 write_CTRL(drv_data, cr);
716
717 if (width == CFG_SPI_WORDSIZE16) {
718 drv_data->len = (transfer->len) >> 1;
719 } else {
720 drv_data->len = transfer->len;
721 }
722 dev_dbg(&drv_data->pdev->dev,
723 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
724 drv_data->write, chip->write, bfin_spi_null_writer);
725
726 /* speed and width has been set on per message */
727 message->state = RUNNING_STATE;
728 dma_config = 0;
729
730 /* Speed setup (surely valid because already checked) */
731 if (transfer->speed_hz)
732 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
733 else
734 write_BAUD(drv_data, chip->baud);
735
736 write_STAT(drv_data, BIT_STAT_CLR);
737 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
738 if (drv_data->cs_change)
739 bfin_spi_cs_active(drv_data, chip);
740
741 dev_dbg(&drv_data->pdev->dev,
742 "now pumping a transfer: width is %d, len is %d\n",
743 width, transfer->len);
744
745 /*
746 * Try to map dma buffer and do a dma transfer. If successful use,
747 * different way to r/w according to the enable_dma settings and if
748 * we are not doing a full duplex transfer (since the hardware does
749 * not support full duplex DMA transfers).
750 */
751 if (!full_duplex && drv_data->cur_chip->enable_dma
752 && drv_data->len > 6) {
753
754 unsigned long dma_start_addr, flags;
755
756 disable_dma(drv_data->dma_channel);
757 clear_dma_irqstat(drv_data->dma_channel);
758
759 /* config dma channel */
760 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
761 set_dma_x_count(drv_data->dma_channel, drv_data->len);
762 if (width == CFG_SPI_WORDSIZE16) {
763 set_dma_x_modify(drv_data->dma_channel, 2);
764 dma_width = WDSIZE_16;
765 } else {
766 set_dma_x_modify(drv_data->dma_channel, 1);
767 dma_width = WDSIZE_8;
768 }
769
770 /* poll for SPI completion before start */
771 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
772 cpu_relax();
773
774 /* dirty hack for autobuffer DMA mode */
775 if (drv_data->tx_dma == 0xFFFF) {
776 dev_dbg(&drv_data->pdev->dev,
777 "doing autobuffer DMA out.\n");
778
779 /* no irq in autobuffer mode */
780 dma_config =
781 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
782 set_dma_config(drv_data->dma_channel, dma_config);
783 set_dma_start_addr(drv_data->dma_channel,
784 (unsigned long)drv_data->tx);
785 enable_dma(drv_data->dma_channel);
786
787 /* start SPI transfer */
788 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
789
790 /* just return here, there can only be one transfer
791 * in this mode
792 */
793 message->status = 0;
794 bfin_spi_giveback(drv_data);
795 return;
796 }
797
798 /* In dma mode, rx or tx must be NULL in one transfer */
799 dma_config = (RESTART | dma_width | DI_EN);
800 if (drv_data->rx != NULL) {
801 /* set transfer mode, and enable SPI */
802 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
803 drv_data->rx, drv_data->len_in_bytes);
804
805 /* invalidate caches, if needed */
806 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
807 invalidate_dcache_range((unsigned long) drv_data->rx,
808 (unsigned long) (drv_data->rx +
809 drv_data->len_in_bytes));
810
811 dma_config |= WNR;
812 dma_start_addr = (unsigned long)drv_data->rx;
813 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
814
815 } else if (drv_data->tx != NULL) {
816 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
817
818 /* flush caches, if needed */
819 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
820 flush_dcache_range((unsigned long) drv_data->tx,
821 (unsigned long) (drv_data->tx +
822 drv_data->len_in_bytes));
823
824 dma_start_addr = (unsigned long)drv_data->tx;
825 cr |= BIT_CTL_TIMOD_DMA_TX;
826
827 } else
828 BUG();
829
830 /* oh man, here there be monsters ... and i dont mean the
831 * fluffy cute ones from pixar, i mean the kind that'll eat
832 * your data, kick your dog, and love it all. do *not* try
833 * and change these lines unless you (1) heavily test DMA
834 * with SPI flashes on a loaded system (e.g. ping floods),
835 * (2) know just how broken the DMA engine interaction with
836 * the SPI peripheral is, and (3) have someone else to blame
837 * when you screw it all up anyways.
838 */
839 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
840 set_dma_config(drv_data->dma_channel, dma_config);
841 local_irq_save(flags);
842 SSYNC();
843 write_CTRL(drv_data, cr);
844 enable_dma(drv_data->dma_channel);
845 dma_enable_irq(drv_data->dma_channel);
846 local_irq_restore(flags);
847
848 } else {
849 /* IO mode write then read */
850 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
851
852 /* we always use SPI_WRITE mode. SPI_READ mode
853 seems to have problems with setting up the
854 output value in TDBR prior to the transfer. */
855 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
856
857 if (full_duplex) {
858 /* full duplex mode */
859 BUG_ON((drv_data->tx_end - drv_data->tx) !=
860 (drv_data->rx_end - drv_data->rx));
861 dev_dbg(&drv_data->pdev->dev,
862 "IO duplex: cr is 0x%x\n", cr);
863
864 drv_data->duplex(drv_data);
865
866 if (drv_data->tx != drv_data->tx_end)
867 tranf_success = 0;
868 } else if (drv_data->tx != NULL) {
869 /* write only half duplex */
870 dev_dbg(&drv_data->pdev->dev,
871 "IO write: cr is 0x%x\n", cr);
872
873 drv_data->write(drv_data);
874
875 if (drv_data->tx != drv_data->tx_end)
876 tranf_success = 0;
877 } else if (drv_data->rx != NULL) {
878 /* read only half duplex */
879 dev_dbg(&drv_data->pdev->dev,
880 "IO read: cr is 0x%x\n", cr);
881
882 drv_data->read(drv_data);
883 if (drv_data->rx != drv_data->rx_end)
884 tranf_success = 0;
885 }
886
887 if (!tranf_success) {
888 dev_dbg(&drv_data->pdev->dev,
889 "IO write error!\n");
890 message->state = ERROR_STATE;
891 } else {
892 /* Update total byte transfered */
893 message->actual_length += drv_data->len_in_bytes;
894 /* Move to next transfer of this msg */
895 message->state = bfin_spi_next_transfer(drv_data);
896 if (drv_data->cs_change)
897 bfin_spi_cs_deactive(drv_data, chip);
898 }
899 /* Schedule next transfer tasklet */
900 tasklet_schedule(&drv_data->pump_transfers);
901 }
902 }
903
904 /* pop a msg from queue and kick off real transfer */
905 static void bfin_spi_pump_messages(struct work_struct *work)
906 {
907 struct driver_data *drv_data;
908 unsigned long flags;
909
910 drv_data = container_of(work, struct driver_data, pump_messages);
911
912 /* Lock queue and check for queue work */
913 spin_lock_irqsave(&drv_data->lock, flags);
914 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
915 /* pumper kicked off but no work to do */
916 drv_data->busy = 0;
917 spin_unlock_irqrestore(&drv_data->lock, flags);
918 return;
919 }
920
921 /* Make sure we are not already running a message */
922 if (drv_data->cur_msg) {
923 spin_unlock_irqrestore(&drv_data->lock, flags);
924 return;
925 }
926
927 /* Extract head of queue */
928 drv_data->cur_msg = list_entry(drv_data->queue.next,
929 struct spi_message, queue);
930
931 /* Setup the SSP using the per chip configuration */
932 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
933 bfin_spi_restore_state(drv_data);
934
935 list_del_init(&drv_data->cur_msg->queue);
936
937 /* Initial message state */
938 drv_data->cur_msg->state = START_STATE;
939 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
940 struct spi_transfer, transfer_list);
941
942 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
943 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
944 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
945 drv_data->cur_chip->ctl_reg);
946
947 dev_dbg(&drv_data->pdev->dev,
948 "the first transfer len is %d\n",
949 drv_data->cur_transfer->len);
950
951 /* Mark as busy and launch transfers */
952 tasklet_schedule(&drv_data->pump_transfers);
953
954 drv_data->busy = 1;
955 spin_unlock_irqrestore(&drv_data->lock, flags);
956 }
957
958 /*
959 * got a msg to transfer, queue it in drv_data->queue.
960 * And kick off message pumper
961 */
962 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
963 {
964 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
965 unsigned long flags;
966
967 spin_lock_irqsave(&drv_data->lock, flags);
968
969 if (drv_data->run == QUEUE_STOPPED) {
970 spin_unlock_irqrestore(&drv_data->lock, flags);
971 return -ESHUTDOWN;
972 }
973
974 msg->actual_length = 0;
975 msg->status = -EINPROGRESS;
976 msg->state = START_STATE;
977
978 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
979 list_add_tail(&msg->queue, &drv_data->queue);
980
981 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
982 queue_work(drv_data->workqueue, &drv_data->pump_messages);
983
984 spin_unlock_irqrestore(&drv_data->lock, flags);
985
986 return 0;
987 }
988
989 #define MAX_SPI_SSEL 7
990
991 static u16 ssel[][MAX_SPI_SSEL] = {
992 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
993 P_SPI0_SSEL4, P_SPI0_SSEL5,
994 P_SPI0_SSEL6, P_SPI0_SSEL7},
995
996 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
997 P_SPI1_SSEL4, P_SPI1_SSEL5,
998 P_SPI1_SSEL6, P_SPI1_SSEL7},
999
1000 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1001 P_SPI2_SSEL4, P_SPI2_SSEL5,
1002 P_SPI2_SSEL6, P_SPI2_SSEL7},
1003 };
1004
1005 /* first setup for new devices */
1006 static int bfin_spi_setup(struct spi_device *spi)
1007 {
1008 struct bfin5xx_spi_chip *chip_info = NULL;
1009 struct chip_data *chip;
1010 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1011 int ret;
1012
1013 /* Abort device setup if requested features are not supported */
1014 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1015 dev_err(&spi->dev, "requested mode not fully supported\n");
1016 return -EINVAL;
1017 }
1018
1019 /* Zero (the default) here means 8 bits */
1020 if (!spi->bits_per_word)
1021 spi->bits_per_word = 8;
1022
1023 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1024 return -EINVAL;
1025
1026 /* Only alloc (or use chip_info) on first setup */
1027 chip = spi_get_ctldata(spi);
1028 if (chip == NULL) {
1029 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1030 if (!chip)
1031 return -ENOMEM;
1032
1033 chip->enable_dma = 0;
1034 chip_info = spi->controller_data;
1035 }
1036
1037 /* chip_info isn't always needed */
1038 if (chip_info) {
1039 /* Make sure people stop trying to set fields via ctl_reg
1040 * when they should actually be using common SPI framework.
1041 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1042 * Not sure if a user actually needs/uses any of these,
1043 * but let's assume (for now) they do.
1044 */
1045 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1046 dev_err(&spi->dev, "do not set bits in ctl_reg "
1047 "that the SPI framework manages\n");
1048 return -EINVAL;
1049 }
1050
1051 chip->enable_dma = chip_info->enable_dma != 0
1052 && drv_data->master_info->enable_dma;
1053 chip->ctl_reg = chip_info->ctl_reg;
1054 chip->bits_per_word = chip_info->bits_per_word;
1055 chip->cs_change_per_word = chip_info->cs_change_per_word;
1056 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1057 chip->cs_gpio = chip_info->cs_gpio;
1058 chip->idle_tx_val = chip_info->idle_tx_val;
1059 }
1060
1061 /* translate common spi framework into our register */
1062 if (spi->mode & SPI_CPOL)
1063 chip->ctl_reg |= CPOL;
1064 if (spi->mode & SPI_CPHA)
1065 chip->ctl_reg |= CPHA;
1066 if (spi->mode & SPI_LSB_FIRST)
1067 chip->ctl_reg |= LSBF;
1068 /* we dont support running in slave mode (yet?) */
1069 chip->ctl_reg |= MSTR;
1070
1071 /*
1072 * if any one SPI chip is registered and wants DMA, request the
1073 * DMA channel for it
1074 */
1075 if (chip->enable_dma && !drv_data->dma_requested) {
1076 /* register dma irq handler */
1077 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
1078 dev_dbg(&spi->dev,
1079 "Unable to request BlackFin SPI DMA channel\n");
1080 return -ENODEV;
1081 }
1082 if (set_dma_callback(drv_data->dma_channel,
1083 bfin_spi_dma_irq_handler, drv_data) < 0) {
1084 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1085 return -EPERM;
1086 }
1087 dma_disable_irq(drv_data->dma_channel);
1088 drv_data->dma_requested = 1;
1089 }
1090
1091 /*
1092 * Notice: for blackfin, the speed_hz is the value of register
1093 * SPI_BAUD, not the real baudrate
1094 */
1095 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1096 chip->flag = 1 << (spi->chip_select);
1097 chip->chip_select_num = spi->chip_select;
1098
1099 if (chip->chip_select_num == 0) {
1100 ret = gpio_request(chip->cs_gpio, spi->modalias);
1101 if (ret) {
1102 if (drv_data->dma_requested)
1103 free_dma(drv_data->dma_channel);
1104 return ret;
1105 }
1106 gpio_direction_output(chip->cs_gpio, 1);
1107 }
1108
1109 switch (chip->bits_per_word) {
1110 case 8:
1111 chip->n_bytes = 1;
1112 chip->width = CFG_SPI_WORDSIZE8;
1113 chip->read = chip->cs_change_per_word ?
1114 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
1115 chip->write = chip->cs_change_per_word ?
1116 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
1117 chip->duplex = chip->cs_change_per_word ?
1118 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
1119 break;
1120
1121 case 16:
1122 chip->n_bytes = 2;
1123 chip->width = CFG_SPI_WORDSIZE16;
1124 chip->read = chip->cs_change_per_word ?
1125 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
1126 chip->write = chip->cs_change_per_word ?
1127 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
1128 chip->duplex = chip->cs_change_per_word ?
1129 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
1130 break;
1131
1132 default:
1133 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1134 chip->bits_per_word);
1135 if (chip_info)
1136 kfree(chip);
1137 return -ENODEV;
1138 }
1139
1140 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1141 spi->modalias, chip->width, chip->enable_dma);
1142 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1143 chip->ctl_reg, chip->flag);
1144
1145 spi_set_ctldata(spi, chip);
1146
1147 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1148 if ((chip->chip_select_num > 0)
1149 && (chip->chip_select_num <= spi->master->num_chipselect))
1150 peripheral_request(ssel[spi->master->bus_num]
1151 [chip->chip_select_num-1], spi->modalias);
1152
1153 bfin_spi_cs_deactive(drv_data, chip);
1154
1155 return 0;
1156 }
1157
1158 /*
1159 * callback for spi framework.
1160 * clean driver specific data
1161 */
1162 static void bfin_spi_cleanup(struct spi_device *spi)
1163 {
1164 struct chip_data *chip = spi_get_ctldata(spi);
1165
1166 if (!chip)
1167 return;
1168
1169 if ((chip->chip_select_num > 0)
1170 && (chip->chip_select_num <= spi->master->num_chipselect))
1171 peripheral_free(ssel[spi->master->bus_num]
1172 [chip->chip_select_num-1]);
1173
1174 if (chip->chip_select_num == 0)
1175 gpio_free(chip->cs_gpio);
1176
1177 kfree(chip);
1178 }
1179
1180 static inline int bfin_spi_init_queue(struct driver_data *drv_data)
1181 {
1182 INIT_LIST_HEAD(&drv_data->queue);
1183 spin_lock_init(&drv_data->lock);
1184
1185 drv_data->run = QUEUE_STOPPED;
1186 drv_data->busy = 0;
1187
1188 /* init transfer tasklet */
1189 tasklet_init(&drv_data->pump_transfers,
1190 bfin_spi_pump_transfers, (unsigned long)drv_data);
1191
1192 /* init messages workqueue */
1193 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1194 drv_data->workqueue = create_singlethread_workqueue(
1195 dev_name(drv_data->master->dev.parent));
1196 if (drv_data->workqueue == NULL)
1197 return -EBUSY;
1198
1199 return 0;
1200 }
1201
1202 static inline int bfin_spi_start_queue(struct driver_data *drv_data)
1203 {
1204 unsigned long flags;
1205
1206 spin_lock_irqsave(&drv_data->lock, flags);
1207
1208 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1209 spin_unlock_irqrestore(&drv_data->lock, flags);
1210 return -EBUSY;
1211 }
1212
1213 drv_data->run = QUEUE_RUNNING;
1214 drv_data->cur_msg = NULL;
1215 drv_data->cur_transfer = NULL;
1216 drv_data->cur_chip = NULL;
1217 spin_unlock_irqrestore(&drv_data->lock, flags);
1218
1219 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1220
1221 return 0;
1222 }
1223
1224 static inline int bfin_spi_stop_queue(struct driver_data *drv_data)
1225 {
1226 unsigned long flags;
1227 unsigned limit = 500;
1228 int status = 0;
1229
1230 spin_lock_irqsave(&drv_data->lock, flags);
1231
1232 /*
1233 * This is a bit lame, but is optimized for the common execution path.
1234 * A wait_queue on the drv_data->busy could be used, but then the common
1235 * execution path (pump_messages) would be required to call wake_up or
1236 * friends on every SPI message. Do this instead
1237 */
1238 drv_data->run = QUEUE_STOPPED;
1239 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1240 spin_unlock_irqrestore(&drv_data->lock, flags);
1241 msleep(10);
1242 spin_lock_irqsave(&drv_data->lock, flags);
1243 }
1244
1245 if (!list_empty(&drv_data->queue) || drv_data->busy)
1246 status = -EBUSY;
1247
1248 spin_unlock_irqrestore(&drv_data->lock, flags);
1249
1250 return status;
1251 }
1252
1253 static inline int bfin_spi_destroy_queue(struct driver_data *drv_data)
1254 {
1255 int status;
1256
1257 status = bfin_spi_stop_queue(drv_data);
1258 if (status != 0)
1259 return status;
1260
1261 destroy_workqueue(drv_data->workqueue);
1262
1263 return 0;
1264 }
1265
1266 static int __init bfin_spi_probe(struct platform_device *pdev)
1267 {
1268 struct device *dev = &pdev->dev;
1269 struct bfin5xx_spi_master *platform_info;
1270 struct spi_master *master;
1271 struct driver_data *drv_data = 0;
1272 struct resource *res;
1273 int status = 0;
1274
1275 platform_info = dev->platform_data;
1276
1277 /* Allocate master with space for drv_data */
1278 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1279 if (!master) {
1280 dev_err(&pdev->dev, "can not alloc spi_master\n");
1281 return -ENOMEM;
1282 }
1283
1284 drv_data = spi_master_get_devdata(master);
1285 drv_data->master = master;
1286 drv_data->master_info = platform_info;
1287 drv_data->pdev = pdev;
1288 drv_data->pin_req = platform_info->pin_req;
1289
1290 master->bus_num = pdev->id;
1291 master->num_chipselect = platform_info->num_chipselect;
1292 master->cleanup = bfin_spi_cleanup;
1293 master->setup = bfin_spi_setup;
1294 master->transfer = bfin_spi_transfer;
1295
1296 /* Find and map our resources */
1297 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1298 if (res == NULL) {
1299 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1300 status = -ENOENT;
1301 goto out_error_get_res;
1302 }
1303
1304 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1305 if (drv_data->regs_base == NULL) {
1306 dev_err(dev, "Cannot map IO\n");
1307 status = -ENXIO;
1308 goto out_error_ioremap;
1309 }
1310
1311 drv_data->dma_channel = platform_get_irq(pdev, 0);
1312 if (drv_data->dma_channel < 0) {
1313 dev_err(dev, "No DMA channel specified\n");
1314 status = -ENOENT;
1315 goto out_error_no_dma_ch;
1316 }
1317
1318 /* Initial and start queue */
1319 status = bfin_spi_init_queue(drv_data);
1320 if (status != 0) {
1321 dev_err(dev, "problem initializing queue\n");
1322 goto out_error_queue_alloc;
1323 }
1324
1325 status = bfin_spi_start_queue(drv_data);
1326 if (status != 0) {
1327 dev_err(dev, "problem starting queue\n");
1328 goto out_error_queue_alloc;
1329 }
1330
1331 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1332 if (status != 0) {
1333 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1334 goto out_error_queue_alloc;
1335 }
1336
1337 /* Register with the SPI framework */
1338 platform_set_drvdata(pdev, drv_data);
1339 status = spi_register_master(master);
1340 if (status != 0) {
1341 dev_err(dev, "problem registering spi master\n");
1342 goto out_error_queue_alloc;
1343 }
1344
1345 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1346 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1347 drv_data->dma_channel);
1348 return status;
1349
1350 out_error_queue_alloc:
1351 bfin_spi_destroy_queue(drv_data);
1352 out_error_no_dma_ch:
1353 iounmap((void *) drv_data->regs_base);
1354 out_error_ioremap:
1355 out_error_get_res:
1356 spi_master_put(master);
1357
1358 return status;
1359 }
1360
1361 /* stop hardware and remove the driver */
1362 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1363 {
1364 struct driver_data *drv_data = platform_get_drvdata(pdev);
1365 int status = 0;
1366
1367 if (!drv_data)
1368 return 0;
1369
1370 /* Remove the queue */
1371 status = bfin_spi_destroy_queue(drv_data);
1372 if (status != 0)
1373 return status;
1374
1375 /* Disable the SSP at the peripheral and SOC level */
1376 bfin_spi_disable(drv_data);
1377
1378 /* Release DMA */
1379 if (drv_data->master_info->enable_dma) {
1380 if (dma_channel_active(drv_data->dma_channel))
1381 free_dma(drv_data->dma_channel);
1382 }
1383
1384 /* Disconnect from the SPI framework */
1385 spi_unregister_master(drv_data->master);
1386
1387 peripheral_free_list(drv_data->pin_req);
1388
1389 /* Prevent double remove */
1390 platform_set_drvdata(pdev, NULL);
1391
1392 return 0;
1393 }
1394
1395 #ifdef CONFIG_PM
1396 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1397 {
1398 struct driver_data *drv_data = platform_get_drvdata(pdev);
1399 int status = 0;
1400
1401 status = bfin_spi_stop_queue(drv_data);
1402 if (status != 0)
1403 return status;
1404
1405 /* stop hardware */
1406 bfin_spi_disable(drv_data);
1407
1408 return 0;
1409 }
1410
1411 static int bfin_spi_resume(struct platform_device *pdev)
1412 {
1413 struct driver_data *drv_data = platform_get_drvdata(pdev);
1414 int status = 0;
1415
1416 /* Enable the SPI interface */
1417 bfin_spi_enable(drv_data);
1418
1419 /* Start the queue running */
1420 status = bfin_spi_start_queue(drv_data);
1421 if (status != 0) {
1422 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1423 return status;
1424 }
1425
1426 return 0;
1427 }
1428 #else
1429 #define bfin_spi_suspend NULL
1430 #define bfin_spi_resume NULL
1431 #endif /* CONFIG_PM */
1432
1433 MODULE_ALIAS("platform:bfin-spi");
1434 static struct platform_driver bfin_spi_driver = {
1435 .driver = {
1436 .name = DRV_NAME,
1437 .owner = THIS_MODULE,
1438 },
1439 .suspend = bfin_spi_suspend,
1440 .resume = bfin_spi_resume,
1441 .remove = __devexit_p(bfin_spi_remove),
1442 };
1443
1444 static int __init bfin_spi_init(void)
1445 {
1446 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1447 }
1448 module_init(bfin_spi_init);
1449
1450 static void __exit bfin_spi_exit(void)
1451 {
1452 platform_driver_unregister(&bfin_spi_driver);
1453 }
1454 module_exit(bfin_spi_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree