arch/arm/mach-mx5/board-cpuimx51sd.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
   4  *
   5  * based on board-mx51_babbage.c which is
   6  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c.h>
  20 #include <linux/i2c/tsc2007.h>
  21 #include <linux/gpio.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/fsl_devices.h>
  27 #include <linux/i2c-gpio.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/can/platform/mcp251x.h>
  30
  31 #include <mach/eukrea-baseboards.h>
  32 #include <mach/common.h>
  33 #include <mach/hardware.h>
  34 #include <mach/iomux-mx51.h>
  35 #include <mach/mxc_ehci.h>
  36
  37 #include <asm/irq.h>
  38 #include <asm/setup.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/mach/arch.h>
  41 #include <asm/mach/time.h>
  42
  43 #include "devices-imx51.h"
  44 #include "devices.h"
  45 #include "cpu_op-mx51.h"
  46
  47 #define USBH1_RST               IMX_GPIO_NR(2, 28)
  48 #define ETH_RST                 IMX_GPIO_NR(2, 31)
  49 #define TSC2007_IRQGPIO         IMX_GPIO_NR(3, 12)
  50 #define CAN_IRQGPIO             IMX_GPIO_NR(1, 1)
  51 #define CAN_RST                 IMX_GPIO_NR(4, 15)
  52 #define CAN_NCS                 IMX_GPIO_NR(4, 24)
  53 #define CAN_RXOBF               IMX_GPIO_NR(1, 4)
  54 #define CAN_RX1BF               IMX_GPIO_NR(1, 6)
  55 #define CAN_TXORTS              IMX_GPIO_NR(1, 7)
  56 #define CAN_TX1RTS              IMX_GPIO_NR(1, 8)
  57 #define CAN_TX2RTS              IMX_GPIO_NR(1, 9)
  58 #define I2C_SCL                 IMX_GPIO_NR(4, 16)
  59 #define I2C_SDA                 IMX_GPIO_NR(4, 17)
  60
  61 /* USB_CTRL_1 */
  62 #define MX51_USB_CTRL_1_OFFSET          0x10
  63 #define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
  64
  65 #define MX51_USB_PLLDIV_12_MHZ          0x00
  66 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  67 #define MX51_USB_PLL_DIV_24_MHZ         0x02
  68
  69 static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
  70         /* UART1 */
  71         MX51_PAD_UART1_RXD__UART1_RXD,
  72         MX51_PAD_UART1_TXD__UART1_TXD,
  73         MX51_PAD_UART1_RTS__UART1_RTS,
  74         MX51_PAD_UART1_CTS__UART1_CTS,
  75
  76         /* USB HOST1 */
  77         MX51_PAD_USBH1_CLK__USBH1_CLK,
  78         MX51_PAD_USBH1_DIR__USBH1_DIR,
  79         MX51_PAD_USBH1_NXT__USBH1_NXT,
  80         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
  81         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
  82         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
  83         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
  84         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
  85         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
  86         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
  87         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
  88         MX51_PAD_USBH1_STP__USBH1_STP,
  89         MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
  90
  91         /* FEC */
  92         MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
  93
  94         /* HSI2C */
  95         MX51_PAD_I2C1_CLK__GPIO4_16,
  96         MX51_PAD_I2C1_DAT__GPIO4_17,
  97
  98         /* CAN */
  99         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
 100         MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
 101         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
 102         MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
 103         MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
 104         MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
 105         MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
 106         MX51_PAD_GPIO1_6__GPIO1_6,
 107         MX51_PAD_GPIO1_7__GPIO1_7,
 108         MX51_PAD_GPIO1_8__GPIO1_8,
 109         MX51_PAD_GPIO1_9__GPIO1_9,
 110
 111         /* Touchscreen */
 112         /* IRQ */
 113         _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
 114                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
 115                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 116 };
 117
 118 static const struct imxuart_platform_data uart_pdata __initconst = {
 119         .flags = IMXUART_HAVE_RTSCTS,
 120 };
 121
 122 static struct tsc2007_platform_data tsc2007_info = {
 123         .model                  = 2007,
 124         .x_plate_ohms           = 180,
 125 };
 126
 127 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
 128         {
 129                 I2C_BOARD_INFO("pcf8563", 0x51),
 130         }, {
 131                 I2C_BOARD_INFO("tsc2007", 0x49),
 132                 .type           = "tsc2007",
 133                 .platform_data  = &tsc2007_info,
 134                 .irq            = gpio_to_irq(TSC2007_IRQGPIO),
 135         },
 136 };
 137
 138 static const struct mxc_nand_platform_data
 139                 eukrea_cpuimx51sd_nand_board_info __initconst = {
 140         .width          = 1,
 141         .hw_ecc         = 1,
 142         .flash_bbt      = 1,
 143 };
 144
 145 /* This function is board specific as the bit mask for the plldiv will also
 146 be different for other Freescale SoCs, thus a common bitmask is not
 147 possible and cannot get place in /plat-mxc/ehci.c.*/
 148 static int initialize_otg_port(struct platform_device *pdev)
 149 {
 150         u32 v;
 151         void __iomem *usb_base;
 152         void __iomem *usbother_base;
 153
 154         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 155         if (!usb_base)
 156                 return -ENOMEM;
 157         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 158
 159         /* Set the PHY clock to 19.2MHz */
 160         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 161         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 162         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 163         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 164         iounmap(usb_base);
 165
 166         mdelay(10);
 167
 168         return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 169 }
 170
 171 static int initialize_usbh1_port(struct platform_device *pdev)
 172 {
 173         u32 v;
 174         void __iomem *usb_base;
 175         void __iomem *usbother_base;
 176
 177         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 178         if (!usb_base)
 179                 return -ENOMEM;
 180         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 181
 182         /* The clock for the USBH1 ULPI port will come from the PHY. */
 183         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 184         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
 185                         usbother_base + MX51_USB_CTRL_1_OFFSET);
 186         iounmap(usb_base);
 187
 188         mdelay(10);
 189
 190         return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
 191                         MXC_EHCI_ITC_NO_THRESHOLD);
 192 }
 193
 194 static struct mxc_usbh_platform_data dr_utmi_config = {
 195         .init           = initialize_otg_port,
 196         .portsc = MXC_EHCI_UTMI_16BIT,
 197 };
 198
 199 static struct fsl_usb2_platform_data usb_pdata = {
 200         .operating_mode = FSL_USB2_DR_DEVICE,
 201         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 202 };
 203
 204 static struct mxc_usbh_platform_data usbh1_config = {
 205         .init           = initialize_usbh1_port,
 206         .portsc = MXC_EHCI_MODE_ULPI,
 207 };
 208
 209 static int otg_mode_host;
 210
 211 static int __init eukrea_cpuimx51sd_otg_mode(char *options)
 212 {
 213         if (!strcmp(options, "host"))
 214                 otg_mode_host = 1;
 215         else if (!strcmp(options, "device"))
 216                 otg_mode_host = 0;
 217         else
 218                 pr_info("otg_mode neither \"host\" nor \"device\". "
 219                         "Defaulting to device\n");
 220         return 0;
 221 }
 222 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
 223
 224 static struct i2c_gpio_platform_data pdata = {
 225         .sda_pin                = I2C_SDA,
 226         .sda_is_open_drain      = 0,
 227         .scl_pin                = I2C_SCL,
 228         .scl_is_open_drain      = 0,
 229         .udelay                 = 2,
 230 };
 231
 232 static struct platform_device hsi2c_gpio_device = {
 233         .name                   = "i2c-gpio",
 234         .id                     = 0,
 235         .dev.platform_data      = &pdata,
 236 };
 237
 238 static struct mcp251x_platform_data mcp251x_info = {
 239         .oscillator_frequency = 24E6,
 240 };
 241
 242 static struct spi_board_info cpuimx51sd_spi_device[] = {
 243         {
 244                 .modalias        = "mcp2515",
 245                 .max_speed_hz    = 10000000,
 246                 .bus_num         = 0,
 247                 .mode           = SPI_MODE_0,
 248                 .chip_select     = 0,
 249                 .platform_data   = &mcp251x_info,
 250                 .irq             = gpio_to_irq(CAN_IRQGPIO)
 251         },
 252 };
 253
 254 static int cpuimx51sd_spi1_cs[] = {
 255         CAN_NCS,
 256 };
 257
 258 static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
 259         .chipselect     = cpuimx51sd_spi1_cs,
 260         .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
 261 };
 262
 263 static struct platform_device *platform_devices[] __initdata = {
 264         &hsi2c_gpio_device,
 265 };
 266
 267 static void __init eukrea_cpuimx51sd_init(void)
 268 {
 269         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
 270                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 271
 272 #if defined(CONFIG_CPU_FREQ_IMX)
 273         get_cpu_op = mx51_get_cpu_op;
 274 #endif
 275
 276         imx51_add_imx_uart(0, &uart_pdata);
 277         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
 278
 279         gpio_request(ETH_RST, "eth_rst");
 280         gpio_set_value(ETH_RST, 1);
 281         imx51_add_fec(NULL);
 282
 283         gpio_request(CAN_IRQGPIO, "can_irq");
 284         gpio_direction_input(CAN_IRQGPIO);
 285         gpio_free(CAN_IRQGPIO);
 286         gpio_request(CAN_NCS, "can_ncs");
 287         gpio_direction_output(CAN_NCS, 1);
 288         gpio_free(CAN_NCS);
 289         gpio_request(CAN_RST, "can_rst");
 290         gpio_direction_output(CAN_RST, 0);
 291         msleep(20);
 292         gpio_set_value(CAN_RST, 1);
 293         imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
 294         spi_register_board_info(cpuimx51sd_spi_device,
 295                                 ARRAY_SIZE(cpuimx51sd_spi_device));
 296
 297         gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
 298         gpio_direction_input(TSC2007_IRQGPIO);
 299         gpio_free(TSC2007_IRQGPIO);
 300
 301         i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
 302                         ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
 303         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 304
 305         if (otg_mode_host)
 306                 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
 307         else {
 308                 initialize_otg_port(NULL);
 309                 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
 310         }
 311
 312         gpio_request(USBH1_RST, "usb_rst");
 313         gpio_direction_output(USBH1_RST, 0);
 314         msleep(20);
 315         gpio_set_value(USBH1_RST, 1);
 316         mxc_register_device(&mxc_usbh1_device, &usbh1_config);
 317
 318 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
 319         eukrea_mbimxsd51_baseboard_init();
 320 #endif
 321 }
 322
 323 static void __init eukrea_cpuimx51sd_timer_init(void)
 324 {
 325         mx51_clocks_init(32768, 24000000, 22579200, 0);
 326 }
 327
 328 static struct sys_timer mxc_timer = {
 329         .init   = eukrea_cpuimx51sd_timer_init,
 330 };
 331
 332 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
 333         /* Maintainer: Eric Bénard <eric@eukrea.com> */
 334         .boot_params = MX51_PHYS_OFFSET + 0x100,
 335         .map_io = mx51_map_io,
 336         .init_early = imx51_init_early,
 337         .init_irq = mx51_init_irq,
 338         .timer = &mxc_timer,
 339         .init_machine = eukrea_cpuimx51sd_init,
 340 MACHINE_END