2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
45 static void intel_update_watermarks(struct drm_device
*dev
);
46 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
47 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t
;
73 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
76 int, int, intel_clock_t
*);
80 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
84 int target
, int refclk
, intel_clock_t
*best_clock
);
86 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
87 int target
, int refclk
, intel_clock_t
*best_clock
);
90 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
91 int target
, int refclk
, intel_clock_t
*best_clock
);
93 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
94 int target
, int refclk
, intel_clock_t
*best_clock
);
96 static inline u32
/* units of 100MHz */
97 intel_fdi_link_freq(struct drm_device
*dev
)
100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
101 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
106 static const intel_limit_t intel_limits_i8xx_dvo
= {
107 .dot
= { .min
= 25000, .max
= 350000 },
108 .vco
= { .min
= 930000, .max
= 1400000 },
109 .n
= { .min
= 3, .max
= 16 },
110 .m
= { .min
= 96, .max
= 140 },
111 .m1
= { .min
= 18, .max
= 26 },
112 .m2
= { .min
= 6, .max
= 16 },
113 .p
= { .min
= 4, .max
= 128 },
114 .p1
= { .min
= 2, .max
= 33 },
115 .p2
= { .dot_limit
= 165000,
116 .p2_slow
= 4, .p2_fast
= 2 },
117 .find_pll
= intel_find_best_PLL
,
120 static const intel_limit_t intel_limits_i8xx_lvds
= {
121 .dot
= { .min
= 25000, .max
= 350000 },
122 .vco
= { .min
= 930000, .max
= 1400000 },
123 .n
= { .min
= 3, .max
= 16 },
124 .m
= { .min
= 96, .max
= 140 },
125 .m1
= { .min
= 18, .max
= 26 },
126 .m2
= { .min
= 6, .max
= 16 },
127 .p
= { .min
= 4, .max
= 128 },
128 .p1
= { .min
= 1, .max
= 6 },
129 .p2
= { .dot_limit
= 165000,
130 .p2_slow
= 14, .p2_fast
= 7 },
131 .find_pll
= intel_find_best_PLL
,
134 static const intel_limit_t intel_limits_i9xx_sdvo
= {
135 .dot
= { .min
= 20000, .max
= 400000 },
136 .vco
= { .min
= 1400000, .max
= 2800000 },
137 .n
= { .min
= 1, .max
= 6 },
138 .m
= { .min
= 70, .max
= 120 },
139 .m1
= { .min
= 10, .max
= 22 },
140 .m2
= { .min
= 5, .max
= 9 },
141 .p
= { .min
= 5, .max
= 80 },
142 .p1
= { .min
= 1, .max
= 8 },
143 .p2
= { .dot_limit
= 200000,
144 .p2_slow
= 10, .p2_fast
= 5 },
145 .find_pll
= intel_find_best_PLL
,
148 static const intel_limit_t intel_limits_i9xx_lvds
= {
149 .dot
= { .min
= 20000, .max
= 400000 },
150 .vco
= { .min
= 1400000, .max
= 2800000 },
151 .n
= { .min
= 1, .max
= 6 },
152 .m
= { .min
= 70, .max
= 120 },
153 .m1
= { .min
= 10, .max
= 22 },
154 .m2
= { .min
= 5, .max
= 9 },
155 .p
= { .min
= 7, .max
= 98 },
156 .p1
= { .min
= 1, .max
= 8 },
157 .p2
= { .dot_limit
= 112000,
158 .p2_slow
= 14, .p2_fast
= 7 },
159 .find_pll
= intel_find_best_PLL
,
163 static const intel_limit_t intel_limits_g4x_sdvo
= {
164 .dot
= { .min
= 25000, .max
= 270000 },
165 .vco
= { .min
= 1750000, .max
= 3500000},
166 .n
= { .min
= 1, .max
= 4 },
167 .m
= { .min
= 104, .max
= 138 },
168 .m1
= { .min
= 17, .max
= 23 },
169 .m2
= { .min
= 5, .max
= 11 },
170 .p
= { .min
= 10, .max
= 30 },
171 .p1
= { .min
= 1, .max
= 3},
172 .p2
= { .dot_limit
= 270000,
176 .find_pll
= intel_g4x_find_best_PLL
,
179 static const intel_limit_t intel_limits_g4x_hdmi
= {
180 .dot
= { .min
= 22000, .max
= 400000 },
181 .vco
= { .min
= 1750000, .max
= 3500000},
182 .n
= { .min
= 1, .max
= 4 },
183 .m
= { .min
= 104, .max
= 138 },
184 .m1
= { .min
= 16, .max
= 23 },
185 .m2
= { .min
= 5, .max
= 11 },
186 .p
= { .min
= 5, .max
= 80 },
187 .p1
= { .min
= 1, .max
= 8},
188 .p2
= { .dot_limit
= 165000,
189 .p2_slow
= 10, .p2_fast
= 5 },
190 .find_pll
= intel_g4x_find_best_PLL
,
193 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
194 .dot
= { .min
= 20000, .max
= 115000 },
195 .vco
= { .min
= 1750000, .max
= 3500000 },
196 .n
= { .min
= 1, .max
= 3 },
197 .m
= { .min
= 104, .max
= 138 },
198 .m1
= { .min
= 17, .max
= 23 },
199 .m2
= { .min
= 5, .max
= 11 },
200 .p
= { .min
= 28, .max
= 112 },
201 .p1
= { .min
= 2, .max
= 8 },
202 .p2
= { .dot_limit
= 0,
203 .p2_slow
= 14, .p2_fast
= 14
205 .find_pll
= intel_g4x_find_best_PLL
,
208 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
209 .dot
= { .min
= 80000, .max
= 224000 },
210 .vco
= { .min
= 1750000, .max
= 3500000 },
211 .n
= { .min
= 1, .max
= 3 },
212 .m
= { .min
= 104, .max
= 138 },
213 .m1
= { .min
= 17, .max
= 23 },
214 .m2
= { .min
= 5, .max
= 11 },
215 .p
= { .min
= 14, .max
= 42 },
216 .p1
= { .min
= 2, .max
= 6 },
217 .p2
= { .dot_limit
= 0,
218 .p2_slow
= 7, .p2_fast
= 7
220 .find_pll
= intel_g4x_find_best_PLL
,
223 static const intel_limit_t intel_limits_g4x_display_port
= {
224 .dot
= { .min
= 161670, .max
= 227000 },
225 .vco
= { .min
= 1750000, .max
= 3500000},
226 .n
= { .min
= 1, .max
= 2 },
227 .m
= { .min
= 97, .max
= 108 },
228 .m1
= { .min
= 0x10, .max
= 0x12 },
229 .m2
= { .min
= 0x05, .max
= 0x06 },
230 .p
= { .min
= 10, .max
= 20 },
231 .p1
= { .min
= 1, .max
= 2},
232 .p2
= { .dot_limit
= 0,
233 .p2_slow
= 10, .p2_fast
= 10 },
234 .find_pll
= intel_find_pll_g4x_dp
,
237 static const intel_limit_t intel_limits_pineview_sdvo
= {
238 .dot
= { .min
= 20000, .max
= 400000},
239 .vco
= { .min
= 1700000, .max
= 3500000 },
240 /* Pineview's Ncounter is a ring counter */
241 .n
= { .min
= 3, .max
= 6 },
242 .m
= { .min
= 2, .max
= 256 },
243 /* Pineview only has one combined m divider, which we treat as m2. */
244 .m1
= { .min
= 0, .max
= 0 },
245 .m2
= { .min
= 0, .max
= 254 },
246 .p
= { .min
= 5, .max
= 80 },
247 .p1
= { .min
= 1, .max
= 8 },
248 .p2
= { .dot_limit
= 200000,
249 .p2_slow
= 10, .p2_fast
= 5 },
250 .find_pll
= intel_find_best_PLL
,
253 static const intel_limit_t intel_limits_pineview_lvds
= {
254 .dot
= { .min
= 20000, .max
= 400000 },
255 .vco
= { .min
= 1700000, .max
= 3500000 },
256 .n
= { .min
= 3, .max
= 6 },
257 .m
= { .min
= 2, .max
= 256 },
258 .m1
= { .min
= 0, .max
= 0 },
259 .m2
= { .min
= 0, .max
= 254 },
260 .p
= { .min
= 7, .max
= 112 },
261 .p1
= { .min
= 1, .max
= 8 },
262 .p2
= { .dot_limit
= 112000,
263 .p2_slow
= 14, .p2_fast
= 14 },
264 .find_pll
= intel_find_best_PLL
,
267 /* Ironlake / Sandybridge
269 * We calculate clock using (register_value + 2) for N/M1/M2, so here
270 * the range value for them is (actual_value - 2).
272 static const intel_limit_t intel_limits_ironlake_dac
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 1760000, .max
= 3510000 },
275 .n
= { .min
= 1, .max
= 5 },
276 .m
= { .min
= 79, .max
= 127 },
277 .m1
= { .min
= 12, .max
= 22 },
278 .m2
= { .min
= 5, .max
= 9 },
279 .p
= { .min
= 5, .max
= 80 },
280 .p1
= { .min
= 1, .max
= 8 },
281 .p2
= { .dot_limit
= 225000,
282 .p2_slow
= 10, .p2_fast
= 5 },
283 .find_pll
= intel_g4x_find_best_PLL
,
286 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
287 .dot
= { .min
= 25000, .max
= 350000 },
288 .vco
= { .min
= 1760000, .max
= 3510000 },
289 .n
= { .min
= 1, .max
= 3 },
290 .m
= { .min
= 79, .max
= 118 },
291 .m1
= { .min
= 12, .max
= 22 },
292 .m2
= { .min
= 5, .max
= 9 },
293 .p
= { .min
= 28, .max
= 112 },
294 .p1
= { .min
= 2, .max
= 8 },
295 .p2
= { .dot_limit
= 225000,
296 .p2_slow
= 14, .p2_fast
= 14 },
297 .find_pll
= intel_g4x_find_best_PLL
,
300 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
301 .dot
= { .min
= 25000, .max
= 350000 },
302 .vco
= { .min
= 1760000, .max
= 3510000 },
303 .n
= { .min
= 1, .max
= 3 },
304 .m
= { .min
= 79, .max
= 127 },
305 .m1
= { .min
= 12, .max
= 22 },
306 .m2
= { .min
= 5, .max
= 9 },
307 .p
= { .min
= 14, .max
= 56 },
308 .p1
= { .min
= 2, .max
= 8 },
309 .p2
= { .dot_limit
= 225000,
310 .p2_slow
= 7, .p2_fast
= 7 },
311 .find_pll
= intel_g4x_find_best_PLL
,
314 /* LVDS 100mhz refclk limits. */
315 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
316 .dot
= { .min
= 25000, .max
= 350000 },
317 .vco
= { .min
= 1760000, .max
= 3510000 },
318 .n
= { .min
= 1, .max
= 2 },
319 .m
= { .min
= 79, .max
= 126 },
320 .m1
= { .min
= 12, .max
= 22 },
321 .m2
= { .min
= 5, .max
= 9 },
322 .p
= { .min
= 28, .max
= 112 },
323 .p1
= { .min
= 2,.max
= 8 },
324 .p2
= { .dot_limit
= 225000,
325 .p2_slow
= 14, .p2_fast
= 14 },
326 .find_pll
= intel_g4x_find_best_PLL
,
329 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
330 .dot
= { .min
= 25000, .max
= 350000 },
331 .vco
= { .min
= 1760000, .max
= 3510000 },
332 .n
= { .min
= 1, .max
= 3 },
333 .m
= { .min
= 79, .max
= 126 },
334 .m1
= { .min
= 12, .max
= 22 },
335 .m2
= { .min
= 5, .max
= 9 },
336 .p
= { .min
= 14, .max
= 42 },
337 .p1
= { .min
= 2,.max
= 6 },
338 .p2
= { .dot_limit
= 225000,
339 .p2_slow
= 7, .p2_fast
= 7 },
340 .find_pll
= intel_g4x_find_best_PLL
,
343 static const intel_limit_t intel_limits_ironlake_display_port
= {
344 .dot
= { .min
= 25000, .max
= 350000 },
345 .vco
= { .min
= 1760000, .max
= 3510000},
346 .n
= { .min
= 1, .max
= 2 },
347 .m
= { .min
= 81, .max
= 90 },
348 .m1
= { .min
= 12, .max
= 22 },
349 .m2
= { .min
= 5, .max
= 9 },
350 .p
= { .min
= 10, .max
= 20 },
351 .p1
= { .min
= 1, .max
= 2},
352 .p2
= { .dot_limit
= 0,
353 .p2_slow
= 10, .p2_fast
= 10 },
354 .find_pll
= intel_find_pll_ironlake_dp
,
357 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
360 struct drm_device
*dev
= crtc
->dev
;
361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
362 const intel_limit_t
*limit
;
364 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
365 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
366 LVDS_CLKB_POWER_UP
) {
367 /* LVDS dual channel */
368 if (refclk
== 100000)
369 limit
= &intel_limits_ironlake_dual_lvds_100m
;
371 limit
= &intel_limits_ironlake_dual_lvds
;
373 if (refclk
== 100000)
374 limit
= &intel_limits_ironlake_single_lvds_100m
;
376 limit
= &intel_limits_ironlake_single_lvds
;
378 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
380 limit
= &intel_limits_ironlake_display_port
;
382 limit
= &intel_limits_ironlake_dac
;
387 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
389 struct drm_device
*dev
= crtc
->dev
;
390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
391 const intel_limit_t
*limit
;
393 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
394 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
396 /* LVDS with dual channel */
397 limit
= &intel_limits_g4x_dual_channel_lvds
;
399 /* LVDS with dual channel */
400 limit
= &intel_limits_g4x_single_channel_lvds
;
401 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
402 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
403 limit
= &intel_limits_g4x_hdmi
;
404 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
405 limit
= &intel_limits_g4x_sdvo
;
406 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
407 limit
= &intel_limits_g4x_display_port
;
408 } else /* The option is for other outputs */
409 limit
= &intel_limits_i9xx_sdvo
;
414 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
416 struct drm_device
*dev
= crtc
->dev
;
417 const intel_limit_t
*limit
;
419 if (HAS_PCH_SPLIT(dev
))
420 limit
= intel_ironlake_limit(crtc
, refclk
);
421 else if (IS_G4X(dev
)) {
422 limit
= intel_g4x_limit(crtc
);
423 } else if (IS_PINEVIEW(dev
)) {
424 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
425 limit
= &intel_limits_pineview_lvds
;
427 limit
= &intel_limits_pineview_sdvo
;
428 } else if (!IS_GEN2(dev
)) {
429 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
430 limit
= &intel_limits_i9xx_lvds
;
432 limit
= &intel_limits_i9xx_sdvo
;
434 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
435 limit
= &intel_limits_i8xx_lvds
;
437 limit
= &intel_limits_i8xx_dvo
;
442 /* m1 is reserved as 0 in Pineview, n is a ring counter */
443 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
445 clock
->m
= clock
->m2
+ 2;
446 clock
->p
= clock
->p1
* clock
->p2
;
447 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
448 clock
->dot
= clock
->vco
/ clock
->p
;
451 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
453 if (IS_PINEVIEW(dev
)) {
454 pineview_clock(refclk
, clock
);
457 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
458 clock
->p
= clock
->p1
* clock
->p2
;
459 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
460 clock
->dot
= clock
->vco
/ clock
->p
;
464 * Returns whether any output on the specified pipe is of the specified type
466 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
468 struct drm_device
*dev
= crtc
->dev
;
469 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
470 struct intel_encoder
*encoder
;
472 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
473 if (encoder
->base
.crtc
== crtc
&& encoder
->type
== type
)
479 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
481 * Returns whether the given set of divisors are valid for a given refclk with
482 * the given connectors.
485 static bool intel_PLL_is_valid(struct drm_device
*dev
,
486 const intel_limit_t
*limit
,
487 const intel_clock_t
*clock
)
489 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
490 INTELPllInvalid ("p1 out of range\n");
491 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
492 INTELPllInvalid ("p out of range\n");
493 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
494 INTELPllInvalid ("m2 out of range\n");
495 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
496 INTELPllInvalid ("m1 out of range\n");
497 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
498 INTELPllInvalid ("m1 <= m2\n");
499 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
500 INTELPllInvalid ("m out of range\n");
501 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
502 INTELPllInvalid ("n out of range\n");
503 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
504 INTELPllInvalid ("vco out of range\n");
505 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
506 * connector, etc., rather than just a single range.
508 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
509 INTELPllInvalid ("dot out of range\n");
515 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
516 int target
, int refclk
, intel_clock_t
*best_clock
)
519 struct drm_device
*dev
= crtc
->dev
;
520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
524 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
525 (I915_READ(LVDS
)) != 0) {
527 * For LVDS, if the panel is on, just rely on its current
528 * settings for dual-channel. We haven't figured out how to
529 * reliably set up different single/dual channel state, if we
532 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
534 clock
.p2
= limit
->p2
.p2_fast
;
536 clock
.p2
= limit
->p2
.p2_slow
;
538 if (target
< limit
->p2
.dot_limit
)
539 clock
.p2
= limit
->p2
.p2_slow
;
541 clock
.p2
= limit
->p2
.p2_fast
;
544 memset (best_clock
, 0, sizeof (*best_clock
));
546 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
548 for (clock
.m2
= limit
->m2
.min
;
549 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
550 /* m1 is always 0 in Pineview */
551 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
553 for (clock
.n
= limit
->n
.min
;
554 clock
.n
<= limit
->n
.max
; clock
.n
++) {
555 for (clock
.p1
= limit
->p1
.min
;
556 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
559 intel_clock(dev
, refclk
, &clock
);
560 if (!intel_PLL_is_valid(dev
, limit
,
564 this_err
= abs(clock
.dot
- target
);
565 if (this_err
< err
) {
574 return (err
!= target
);
578 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
579 int target
, int refclk
, intel_clock_t
*best_clock
)
581 struct drm_device
*dev
= crtc
->dev
;
582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
586 /* approximately equals target * 0.00585 */
587 int err_most
= (target
>> 8) + (target
>> 9);
590 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
593 if (HAS_PCH_SPLIT(dev
))
597 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
599 clock
.p2
= limit
->p2
.p2_fast
;
601 clock
.p2
= limit
->p2
.p2_slow
;
603 if (target
< limit
->p2
.dot_limit
)
604 clock
.p2
= limit
->p2
.p2_slow
;
606 clock
.p2
= limit
->p2
.p2_fast
;
609 memset(best_clock
, 0, sizeof(*best_clock
));
610 max_n
= limit
->n
.max
;
611 /* based on hardware requirement, prefer smaller n to precision */
612 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
613 /* based on hardware requirement, prefere larger m1,m2 */
614 for (clock
.m1
= limit
->m1
.max
;
615 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
616 for (clock
.m2
= limit
->m2
.max
;
617 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
618 for (clock
.p1
= limit
->p1
.max
;
619 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
622 intel_clock(dev
, refclk
, &clock
);
623 if (!intel_PLL_is_valid(dev
, limit
,
627 this_err
= abs(clock
.dot
- target
);
628 if (this_err
< err_most
) {
642 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
643 int target
, int refclk
, intel_clock_t
*best_clock
)
645 struct drm_device
*dev
= crtc
->dev
;
648 if (target
< 200000) {
661 intel_clock(dev
, refclk
, &clock
);
662 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
666 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
668 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
669 int target
, int refclk
, intel_clock_t
*best_clock
)
672 if (target
< 200000) {
685 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
686 clock
.p
= (clock
.p1
* clock
.p2
);
687 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
689 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
694 * intel_wait_for_vblank - wait for vblank on a given pipe
696 * @pipe: pipe to wait for
698 * Wait for vblank to occur on a given pipe. Needed for various bits of
701 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
704 int pipestat_reg
= PIPESTAT(pipe
);
706 /* Clear existing vblank status. Note this will clear any other
707 * sticky status fields as well.
709 * This races with i915_driver_irq_handler() with the result
710 * that either function could miss a vblank event. Here it is not
711 * fatal, as we will either wait upon the next vblank interrupt or
712 * timeout. Generally speaking intel_wait_for_vblank() is only
713 * called during modeset at which time the GPU should be idle and
714 * should *not* be performing page flips and thus not waiting on
716 * Currently, the result of us stealing a vblank from the irq
717 * handler is that a single frame will be skipped during swapbuffers.
719 I915_WRITE(pipestat_reg
,
720 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
722 /* Wait for vblank interrupt bit to set */
723 if (wait_for(I915_READ(pipestat_reg
) &
724 PIPE_VBLANK_INTERRUPT_STATUS
,
726 DRM_DEBUG_KMS("vblank wait timed out\n");
730 * intel_wait_for_pipe_off - wait for pipe to turn off
732 * @pipe: pipe to wait for
734 * After disabling a pipe, we can't wait for vblank in the usual way,
735 * spinning on the vblank interrupt status bit, since we won't actually
736 * see an interrupt when the pipe is disabled.
739 * wait for the pipe register state bit to turn off
742 * wait for the display line value to settle (it usually
743 * ends up stopping at the start of the next frame).
746 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
750 if (INTEL_INFO(dev
)->gen
>= 4) {
751 int reg
= PIPECONF(pipe
);
753 /* Wait for the Pipe State to go off */
754 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
756 DRM_DEBUG_KMS("pipe_off wait timed out\n");
759 int reg
= PIPEDSL(pipe
);
760 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
762 /* Wait for the display line to settle */
764 last_line
= I915_READ(reg
) & DSL_LINEMASK
;
766 } while (((I915_READ(reg
) & DSL_LINEMASK
) != last_line
) &&
767 time_after(timeout
, jiffies
));
768 if (time_after(jiffies
, timeout
))
769 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 static const char *state_string(bool enabled
)
775 return enabled
? "on" : "off";
778 /* Only for pre-ILK configs */
779 static void assert_pll(struct drm_i915_private
*dev_priv
,
780 enum pipe pipe
, bool state
)
787 val
= I915_READ(reg
);
788 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
789 WARN(cur_state
!= state
,
790 "PLL state assertion failure (expected %s, current %s)\n",
791 state_string(state
), state_string(cur_state
));
793 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
794 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
797 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
798 enum pipe pipe
, bool state
)
804 reg
= PCH_DPLL(pipe
);
805 val
= I915_READ(reg
);
806 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
807 WARN(cur_state
!= state
,
808 "PCH PLL state assertion failure (expected %s, current %s)\n",
809 state_string(state
), state_string(cur_state
));
811 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
812 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
815 enum pipe pipe
, bool state
)
821 reg
= FDI_TX_CTL(pipe
);
822 val
= I915_READ(reg
);
823 cur_state
= !!(val
& FDI_TX_ENABLE
);
824 WARN(cur_state
!= state
,
825 "FDI TX state assertion failure (expected %s, current %s)\n",
826 state_string(state
), state_string(cur_state
));
828 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
829 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
832 enum pipe pipe
, bool state
)
838 reg
= FDI_RX_CTL(pipe
);
839 val
= I915_READ(reg
);
840 cur_state
= !!(val
& FDI_RX_ENABLE
);
841 WARN(cur_state
!= state
,
842 "FDI RX state assertion failure (expected %s, current %s)\n",
843 state_string(state
), state_string(cur_state
));
845 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
846 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
854 /* ILK FDI PLL is always enabled */
855 if (dev_priv
->info
->gen
== 5)
858 reg
= FDI_TX_CTL(pipe
);
859 val
= I915_READ(reg
);
860 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
863 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
869 reg
= FDI_RX_CTL(pipe
);
870 val
= I915_READ(reg
);
871 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
874 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
877 int pp_reg
, lvds_reg
;
879 enum pipe panel_pipe
= PIPE_A
;
880 bool locked
= locked
;
882 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
883 pp_reg
= PCH_PP_CONTROL
;
890 val
= I915_READ(pp_reg
);
891 if (!(val
& PANEL_POWER_ON
) ||
892 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
895 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
898 WARN(panel_pipe
== pipe
&& locked
,
899 "panel assertion failure, pipe %c regs locked\n",
903 static void assert_pipe(struct drm_i915_private
*dev_priv
,
904 enum pipe pipe
, bool state
)
910 reg
= PIPECONF(pipe
);
911 val
= I915_READ(reg
);
912 cur_state
= !!(val
& PIPECONF_ENABLE
);
913 WARN(cur_state
!= state
,
914 "pipe %c assertion failure (expected %s, current %s)\n",
915 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
917 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
918 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
920 static void assert_plane_enabled(struct drm_i915_private
*dev_priv
,
926 reg
= DSPCNTR(plane
);
927 val
= I915_READ(reg
);
928 WARN(!(val
& DISPLAY_PLANE_ENABLE
),
929 "plane %c assertion failure, should be active but is disabled\n",
933 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
940 /* Planes are fixed to pipes on ILK+ */
941 if (HAS_PCH_SPLIT(dev_priv
->dev
))
944 /* Need to check both planes against the pipe */
945 for (i
= 0; i
< 2; i
++) {
947 val
= I915_READ(reg
);
948 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
949 DISPPLANE_SEL_PIPE_SHIFT
;
950 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
951 "plane %c assertion failure, should be off on pipe %c but is still active\n",
952 plane_name(i
), pipe_name(pipe
));
956 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
961 val
= I915_READ(PCH_DREF_CONTROL
);
962 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
963 DREF_SUPERSPREAD_SOURCE_MASK
));
964 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
967 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
974 reg
= TRANSCONF(pipe
);
975 val
= I915_READ(reg
);
976 enabled
= !!(val
& TRANS_ENABLE
);
978 "transcoder assertion failed, should be off on pipe %c but is still active\n",
982 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
983 enum pipe pipe
, int reg
)
985 u32 val
= I915_READ(reg
);
986 WARN(DP_PIPE_ENABLED(val
, pipe
),
987 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
988 reg
, pipe_name(pipe
));
991 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
992 enum pipe pipe
, int reg
)
994 u32 val
= I915_READ(reg
);
995 WARN(HDMI_PIPE_ENABLED(val
, pipe
),
996 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
997 reg
, pipe_name(pipe
));
1000 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1006 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
);
1007 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
);
1008 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
);
1011 val
= I915_READ(reg
);
1012 WARN(ADPA_PIPE_ENABLED(val
, pipe
),
1013 "PCH VGA enabled on transcoder %c, should be disabled\n",
1017 val
= I915_READ(reg
);
1018 WARN(LVDS_PIPE_ENABLED(val
, pipe
),
1019 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1022 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1023 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1024 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1028 * intel_enable_pll - enable a PLL
1029 * @dev_priv: i915 private structure
1030 * @pipe: pipe PLL to enable
1032 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1033 * make sure the PLL reg is writable first though, since the panel write
1034 * protect mechanism may be enabled.
1036 * Note! This is for pre-ILK only.
1038 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1043 /* No really, not for ILK+ */
1044 BUG_ON(dev_priv
->info
->gen
>= 5);
1046 /* PLL is protected by panel, make sure we can write it */
1047 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1048 assert_panel_unlocked(dev_priv
, pipe
);
1051 val
= I915_READ(reg
);
1052 val
|= DPLL_VCO_ENABLE
;
1054 /* We do this three times for luck */
1055 I915_WRITE(reg
, val
);
1057 udelay(150); /* wait for warmup */
1058 I915_WRITE(reg
, val
);
1060 udelay(150); /* wait for warmup */
1061 I915_WRITE(reg
, val
);
1063 udelay(150); /* wait for warmup */
1067 * intel_disable_pll - disable a PLL
1068 * @dev_priv: i915 private structure
1069 * @pipe: pipe PLL to disable
1071 * Disable the PLL for @pipe, making sure the pipe is off first.
1073 * Note! This is for pre-ILK only.
1075 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1080 /* Don't disable pipe A or pipe A PLLs if needed */
1081 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1084 /* Make sure the pipe isn't still relying on us */
1085 assert_pipe_disabled(dev_priv
, pipe
);
1088 val
= I915_READ(reg
);
1089 val
&= ~DPLL_VCO_ENABLE
;
1090 I915_WRITE(reg
, val
);
1095 * intel_enable_pch_pll - enable PCH PLL
1096 * @dev_priv: i915 private structure
1097 * @pipe: pipe PLL to enable
1099 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1100 * drives the transcoder clock.
1102 static void intel_enable_pch_pll(struct drm_i915_private
*dev_priv
,
1108 /* PCH only available on ILK+ */
1109 BUG_ON(dev_priv
->info
->gen
< 5);
1111 /* PCH refclock must be enabled first */
1112 assert_pch_refclk_enabled(dev_priv
);
1114 reg
= PCH_DPLL(pipe
);
1115 val
= I915_READ(reg
);
1116 val
|= DPLL_VCO_ENABLE
;
1117 I915_WRITE(reg
, val
);
1122 static void intel_disable_pch_pll(struct drm_i915_private
*dev_priv
,
1128 /* PCH only available on ILK+ */
1129 BUG_ON(dev_priv
->info
->gen
< 5);
1131 /* Make sure transcoder isn't still depending on us */
1132 assert_transcoder_disabled(dev_priv
, pipe
);
1134 reg
= PCH_DPLL(pipe
);
1135 val
= I915_READ(reg
);
1136 val
&= ~DPLL_VCO_ENABLE
;
1137 I915_WRITE(reg
, val
);
1142 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1148 /* PCH only available on ILK+ */
1149 BUG_ON(dev_priv
->info
->gen
< 5);
1151 /* Make sure PCH DPLL is enabled */
1152 assert_pch_pll_enabled(dev_priv
, pipe
);
1154 /* FDI must be feeding us bits for PCH ports */
1155 assert_fdi_tx_enabled(dev_priv
, pipe
);
1156 assert_fdi_rx_enabled(dev_priv
, pipe
);
1158 reg
= TRANSCONF(pipe
);
1159 val
= I915_READ(reg
);
1161 * make the BPC in transcoder be consistent with
1162 * that in pipeconf reg.
1164 val
&= ~PIPE_BPC_MASK
;
1165 val
|= I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
;
1166 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1167 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1168 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1171 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1177 /* FDI relies on the transcoder */
1178 assert_fdi_tx_disabled(dev_priv
, pipe
);
1179 assert_fdi_rx_disabled(dev_priv
, pipe
);
1181 /* Ports must be off as well */
1182 assert_pch_ports_disabled(dev_priv
, pipe
);
1184 reg
= TRANSCONF(pipe
);
1185 val
= I915_READ(reg
);
1186 val
&= ~TRANS_ENABLE
;
1187 I915_WRITE(reg
, val
);
1188 /* wait for PCH transcoder off, transcoder state */
1189 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1190 DRM_ERROR("failed to disable transcoder\n");
1194 * intel_enable_pipe - enable a pipe, asserting requirements
1195 * @dev_priv: i915 private structure
1196 * @pipe: pipe to enable
1197 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1199 * Enable @pipe, making sure that various hardware specific requirements
1200 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1202 * @pipe should be %PIPE_A or %PIPE_B.
1204 * Will wait until the pipe is actually running (i.e. first vblank) before
1207 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1214 * A pipe without a PLL won't actually be able to drive bits from
1215 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1218 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1219 assert_pll_enabled(dev_priv
, pipe
);
1222 /* if driving the PCH, we need FDI enabled */
1223 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1224 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1226 /* FIXME: assert CPU port conditions for SNB+ */
1229 reg
= PIPECONF(pipe
);
1230 val
= I915_READ(reg
);
1231 if (val
& PIPECONF_ENABLE
)
1234 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1235 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1239 * intel_disable_pipe - disable a pipe, asserting requirements
1240 * @dev_priv: i915 private structure
1241 * @pipe: pipe to disable
1243 * Disable @pipe, making sure that various hardware specific requirements
1244 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1246 * @pipe should be %PIPE_A or %PIPE_B.
1248 * Will wait until the pipe has shut down before returning.
1250 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1257 * Make sure planes won't keep trying to pump pixels to us,
1258 * or we might hang the display.
1260 assert_planes_disabled(dev_priv
, pipe
);
1262 /* Don't disable pipe A or pipe A PLLs if needed */
1263 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1266 reg
= PIPECONF(pipe
);
1267 val
= I915_READ(reg
);
1268 if ((val
& PIPECONF_ENABLE
) == 0)
1271 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1272 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1276 * intel_enable_plane - enable a display plane on a given pipe
1277 * @dev_priv: i915 private structure
1278 * @plane: plane to enable
1279 * @pipe: pipe being fed
1281 * Enable @plane on @pipe, making sure that @pipe is running first.
1283 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1284 enum plane plane
, enum pipe pipe
)
1289 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1290 assert_pipe_enabled(dev_priv
, pipe
);
1292 reg
= DSPCNTR(plane
);
1293 val
= I915_READ(reg
);
1294 if (val
& DISPLAY_PLANE_ENABLE
)
1297 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1298 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1302 * Plane regs are double buffered, going from enabled->disabled needs a
1303 * trigger in order to latch. The display address reg provides this.
1305 static void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1308 u32 reg
= DSPADDR(plane
);
1309 I915_WRITE(reg
, I915_READ(reg
));
1313 * intel_disable_plane - disable a display plane
1314 * @dev_priv: i915 private structure
1315 * @plane: plane to disable
1316 * @pipe: pipe consuming the data
1318 * Disable @plane; should be an independent operation.
1320 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1321 enum plane plane
, enum pipe pipe
)
1326 reg
= DSPCNTR(plane
);
1327 val
= I915_READ(reg
);
1328 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1331 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1332 intel_flush_display_plane(dev_priv
, plane
);
1333 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1336 static void disable_pch_dp(struct drm_i915_private
*dev_priv
,
1337 enum pipe pipe
, int reg
)
1339 u32 val
= I915_READ(reg
);
1340 if (DP_PIPE_ENABLED(val
, pipe
))
1341 I915_WRITE(reg
, val
& ~DP_PORT_EN
);
1344 static void disable_pch_hdmi(struct drm_i915_private
*dev_priv
,
1345 enum pipe pipe
, int reg
)
1347 u32 val
= I915_READ(reg
);
1348 if (HDMI_PIPE_ENABLED(val
, pipe
))
1349 I915_WRITE(reg
, val
& ~PORT_ENABLE
);
1352 /* Disable any ports connected to this transcoder */
1353 static void intel_disable_pch_ports(struct drm_i915_private
*dev_priv
,
1358 val
= I915_READ(PCH_PP_CONTROL
);
1359 I915_WRITE(PCH_PP_CONTROL
, val
| PANEL_UNLOCK_REGS
);
1361 disable_pch_dp(dev_priv
, pipe
, PCH_DP_B
);
1362 disable_pch_dp(dev_priv
, pipe
, PCH_DP_C
);
1363 disable_pch_dp(dev_priv
, pipe
, PCH_DP_D
);
1366 val
= I915_READ(reg
);
1367 if (ADPA_PIPE_ENABLED(val
, pipe
))
1368 I915_WRITE(reg
, val
& ~ADPA_DAC_ENABLE
);
1371 val
= I915_READ(reg
);
1372 if (LVDS_PIPE_ENABLED(val
, pipe
)) {
1373 I915_WRITE(reg
, val
& ~LVDS_PORT_EN
);
1378 disable_pch_hdmi(dev_priv
, pipe
, HDMIB
);
1379 disable_pch_hdmi(dev_priv
, pipe
, HDMIC
);
1380 disable_pch_hdmi(dev_priv
, pipe
, HDMID
);
1383 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1385 struct drm_device
*dev
= crtc
->dev
;
1386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1387 struct drm_framebuffer
*fb
= crtc
->fb
;
1388 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1389 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1390 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1392 u32 fbc_ctl
, fbc_ctl2
;
1394 if (fb
->pitch
== dev_priv
->cfb_pitch
&&
1395 obj
->fence_reg
== dev_priv
->cfb_fence
&&
1396 intel_crtc
->plane
== dev_priv
->cfb_plane
&&
1397 I915_READ(FBC_CONTROL
) & FBC_CTL_EN
)
1400 i8xx_disable_fbc(dev
);
1402 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1404 if (fb
->pitch
< dev_priv
->cfb_pitch
)
1405 dev_priv
->cfb_pitch
= fb
->pitch
;
1407 /* FBC_CTL wants 64B units */
1408 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1409 dev_priv
->cfb_fence
= obj
->fence_reg
;
1410 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1411 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1413 /* Clear old tags */
1414 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1415 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1418 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1419 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1420 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1421 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1422 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1425 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1427 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1428 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1429 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1430 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1431 fbc_ctl
|= dev_priv
->cfb_fence
;
1432 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1434 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1435 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1438 void i8xx_disable_fbc(struct drm_device
*dev
)
1440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1443 /* Disable compression */
1444 fbc_ctl
= I915_READ(FBC_CONTROL
);
1445 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
1448 fbc_ctl
&= ~FBC_CTL_EN
;
1449 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1451 /* Wait for compressing bit to clear */
1452 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
1453 DRM_DEBUG_KMS("FBC idle timed out\n");
1457 DRM_DEBUG_KMS("disabled FBC\n");
1460 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1464 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1467 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1469 struct drm_device
*dev
= crtc
->dev
;
1470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1471 struct drm_framebuffer
*fb
= crtc
->fb
;
1472 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1473 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1474 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1475 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1476 unsigned long stall_watermark
= 200;
1479 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1480 if (dpfc_ctl
& DPFC_CTL_EN
) {
1481 if (dev_priv
->cfb_pitch
== dev_priv
->cfb_pitch
/ 64 - 1 &&
1482 dev_priv
->cfb_fence
== obj
->fence_reg
&&
1483 dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1484 dev_priv
->cfb_y
== crtc
->y
)
1487 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
& ~DPFC_CTL_EN
);
1488 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1491 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1492 dev_priv
->cfb_fence
= obj
->fence_reg
;
1493 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1494 dev_priv
->cfb_y
= crtc
->y
;
1496 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1497 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
1498 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1499 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1501 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1504 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1505 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1506 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1507 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1510 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1512 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1515 void g4x_disable_fbc(struct drm_device
*dev
)
1517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1520 /* Disable compression */
1521 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1522 if (dpfc_ctl
& DPFC_CTL_EN
) {
1523 dpfc_ctl
&= ~DPFC_CTL_EN
;
1524 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1526 DRM_DEBUG_KMS("disabled FBC\n");
1530 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1534 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1537 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
1539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1542 /* Make sure blitter notifies FBC of writes */
1543 gen6_gt_force_wake_get(dev_priv
);
1544 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
1545 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
1546 GEN6_BLITTER_LOCK_SHIFT
;
1547 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1548 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
1549 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1550 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
1551 GEN6_BLITTER_LOCK_SHIFT
);
1552 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1553 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
1554 gen6_gt_force_wake_put(dev_priv
);
1557 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1559 struct drm_device
*dev
= crtc
->dev
;
1560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1561 struct drm_framebuffer
*fb
= crtc
->fb
;
1562 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1563 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1564 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1565 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1566 unsigned long stall_watermark
= 200;
1569 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1570 if (dpfc_ctl
& DPFC_CTL_EN
) {
1571 if (dev_priv
->cfb_pitch
== dev_priv
->cfb_pitch
/ 64 - 1 &&
1572 dev_priv
->cfb_fence
== obj
->fence_reg
&&
1573 dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1574 dev_priv
->cfb_offset
== obj
->gtt_offset
&&
1575 dev_priv
->cfb_y
== crtc
->y
)
1578 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
& ~DPFC_CTL_EN
);
1579 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1582 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1583 dev_priv
->cfb_fence
= obj
->fence_reg
;
1584 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1585 dev_priv
->cfb_offset
= obj
->gtt_offset
;
1586 dev_priv
->cfb_y
= crtc
->y
;
1588 dpfc_ctl
&= DPFC_RESERVED
;
1589 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
1590 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
1591 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
);
1592 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1594 I915_WRITE(ILK_DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1597 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1598 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1599 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1600 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
1601 I915_WRITE(ILK_FBC_RT_BASE
, obj
->gtt_offset
| ILK_FBC_RT_VALID
);
1603 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
1606 I915_WRITE(SNB_DPFC_CTL_SA
,
1607 SNB_CPU_FENCE_ENABLE
| dev_priv
->cfb_fence
);
1608 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
1609 sandybridge_blit_fbc_update(dev
);
1612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1615 void ironlake_disable_fbc(struct drm_device
*dev
)
1617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1620 /* Disable compression */
1621 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1622 if (dpfc_ctl
& DPFC_CTL_EN
) {
1623 dpfc_ctl
&= ~DPFC_CTL_EN
;
1624 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1626 DRM_DEBUG_KMS("disabled FBC\n");
1630 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
1632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1634 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
1637 bool intel_fbc_enabled(struct drm_device
*dev
)
1639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1641 if (!dev_priv
->display
.fbc_enabled
)
1644 return dev_priv
->display
.fbc_enabled(dev
);
1647 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1649 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1651 if (!dev_priv
->display
.enable_fbc
)
1654 dev_priv
->display
.enable_fbc(crtc
, interval
);
1657 void intel_disable_fbc(struct drm_device
*dev
)
1659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1661 if (!dev_priv
->display
.disable_fbc
)
1664 dev_priv
->display
.disable_fbc(dev
);
1668 * intel_update_fbc - enable/disable FBC as needed
1669 * @dev: the drm_device
1671 * Set up the framebuffer compression hardware at mode set time. We
1672 * enable it if possible:
1673 * - plane A only (on pre-965)
1674 * - no pixel mulitply/line duplication
1675 * - no alpha buffer discard
1677 * - framebuffer <= 2048 in width, 1536 in height
1679 * We can't assume that any compression will take place (worst case),
1680 * so the compressed buffer has to be the same size as the uncompressed
1681 * one. It also must reside (along with the line length buffer) in
1684 * We need to enable/disable FBC on a global basis.
1686 static void intel_update_fbc(struct drm_device
*dev
)
1688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1689 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
1690 struct intel_crtc
*intel_crtc
;
1691 struct drm_framebuffer
*fb
;
1692 struct intel_framebuffer
*intel_fb
;
1693 struct drm_i915_gem_object
*obj
;
1695 DRM_DEBUG_KMS("\n");
1697 if (!i915_powersave
)
1700 if (!I915_HAS_FBC(dev
))
1704 * If FBC is already on, we just have to verify that we can
1705 * keep it that way...
1706 * Need to disable if:
1707 * - more than one pipe is active
1708 * - changing FBC params (stride, fence, mode)
1709 * - new fb is too large to fit in compressed buffer
1710 * - going to an unsupported config (interlace, pixel multiply, etc.)
1712 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1713 if (tmp_crtc
->enabled
&& tmp_crtc
->fb
) {
1715 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1716 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
1723 if (!crtc
|| crtc
->fb
== NULL
) {
1724 DRM_DEBUG_KMS("no output, disabling\n");
1725 dev_priv
->no_fbc_reason
= FBC_NO_OUTPUT
;
1729 intel_crtc
= to_intel_crtc(crtc
);
1731 intel_fb
= to_intel_framebuffer(fb
);
1732 obj
= intel_fb
->obj
;
1734 if (!i915_enable_fbc
) {
1735 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1736 dev_priv
->no_fbc_reason
= FBC_MODULE_PARAM
;
1739 if (intel_fb
->obj
->base
.size
> dev_priv
->cfb_size
) {
1740 DRM_DEBUG_KMS("framebuffer too large, disabling "
1742 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1745 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
1746 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1747 DRM_DEBUG_KMS("mode incompatible with compression, "
1749 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1752 if ((crtc
->mode
.hdisplay
> 2048) ||
1753 (crtc
->mode
.vdisplay
> 1536)) {
1754 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1755 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1758 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && intel_crtc
->plane
!= 0) {
1759 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1760 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1763 if (obj
->tiling_mode
!= I915_TILING_X
) {
1764 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1765 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1769 /* If the kernel debugger is active, always disable compression */
1770 if (in_dbg_master())
1773 intel_enable_fbc(crtc
, 500);
1777 /* Multiple disables should be harmless */
1778 if (intel_fbc_enabled(dev
)) {
1779 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1780 intel_disable_fbc(dev
);
1785 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1786 struct drm_i915_gem_object
*obj
,
1787 struct intel_ring_buffer
*pipelined
)
1789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1793 switch (obj
->tiling_mode
) {
1794 case I915_TILING_NONE
:
1795 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1796 alignment
= 128 * 1024;
1797 else if (INTEL_INFO(dev
)->gen
>= 4)
1798 alignment
= 4 * 1024;
1800 alignment
= 64 * 1024;
1803 /* pin() will align the object as required by fence */
1807 /* FIXME: Is this true? */
1808 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1814 dev_priv
->mm
.interruptible
= false;
1815 ret
= i915_gem_object_pin(obj
, alignment
, true);
1817 goto err_interruptible
;
1819 ret
= i915_gem_object_set_to_display_plane(obj
, pipelined
);
1823 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1824 * fence, whereas 965+ only requires a fence if using
1825 * framebuffer compression. For simplicity, we always install
1826 * a fence as the cost is not that onerous.
1828 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
1829 ret
= i915_gem_object_get_fence(obj
, pipelined
);
1834 dev_priv
->mm
.interruptible
= true;
1838 i915_gem_object_unpin(obj
);
1840 dev_priv
->mm
.interruptible
= true;
1844 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1846 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1847 int x
, int y
, enum mode_set_atomic state
)
1849 struct drm_device
*dev
= crtc
->dev
;
1850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1851 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1852 struct intel_framebuffer
*intel_fb
;
1853 struct drm_i915_gem_object
*obj
;
1854 int plane
= intel_crtc
->plane
;
1855 unsigned long Start
, Offset
;
1864 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1868 intel_fb
= to_intel_framebuffer(fb
);
1869 obj
= intel_fb
->obj
;
1871 reg
= DSPCNTR(plane
);
1872 dspcntr
= I915_READ(reg
);
1873 /* Mask out pixel format bits in case we change it */
1874 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1875 switch (fb
->bits_per_pixel
) {
1877 dspcntr
|= DISPPLANE_8BPP
;
1880 if (fb
->depth
== 15)
1881 dspcntr
|= DISPPLANE_15_16BPP
;
1883 dspcntr
|= DISPPLANE_16BPP
;
1887 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1890 DRM_ERROR("Unknown color depth\n");
1893 if (INTEL_INFO(dev
)->gen
>= 4) {
1894 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1895 dspcntr
|= DISPPLANE_TILED
;
1897 dspcntr
&= ~DISPPLANE_TILED
;
1900 if (HAS_PCH_SPLIT(dev
))
1902 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1904 I915_WRITE(reg
, dspcntr
);
1906 Start
= obj
->gtt_offset
;
1907 Offset
= y
* fb
->pitch
+ x
* (fb
->bits_per_pixel
/ 8);
1909 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1910 Start
, Offset
, x
, y
, fb
->pitch
);
1911 I915_WRITE(DSPSTRIDE(plane
), fb
->pitch
);
1912 if (INTEL_INFO(dev
)->gen
>= 4) {
1913 I915_WRITE(DSPSURF(plane
), Start
);
1914 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
1915 I915_WRITE(DSPADDR(plane
), Offset
);
1917 I915_WRITE(DSPADDR(plane
), Start
+ Offset
);
1920 intel_update_fbc(dev
);
1921 intel_increase_pllclock(crtc
);
1927 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1928 struct drm_framebuffer
*old_fb
)
1930 struct drm_device
*dev
= crtc
->dev
;
1931 struct drm_i915_master_private
*master_priv
;
1932 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1937 DRM_DEBUG_KMS("No FB bound\n");
1941 switch (intel_crtc
->plane
) {
1949 mutex_lock(&dev
->struct_mutex
);
1950 ret
= intel_pin_and_fence_fb_obj(dev
,
1951 to_intel_framebuffer(crtc
->fb
)->obj
,
1954 mutex_unlock(&dev
->struct_mutex
);
1959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1960 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
1962 wait_event(dev_priv
->pending_flip_queue
,
1963 atomic_read(&dev_priv
->mm
.wedged
) ||
1964 atomic_read(&obj
->pending_flip
) == 0);
1966 /* Big Hammer, we also need to ensure that any pending
1967 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1968 * current scanout is retired before unpinning the old
1971 * This should only fail upon a hung GPU, in which case we
1972 * can safely continue.
1974 ret
= i915_gem_object_flush_gpu(obj
);
1978 ret
= intel_pipe_set_base_atomic(crtc
, crtc
->fb
, x
, y
,
1979 LEAVE_ATOMIC_MODE_SET
);
1981 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
1982 mutex_unlock(&dev
->struct_mutex
);
1987 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1988 i915_gem_object_unpin(to_intel_framebuffer(old_fb
)->obj
);
1991 mutex_unlock(&dev
->struct_mutex
);
1993 if (!dev
->primary
->master
)
1996 master_priv
= dev
->primary
->master
->driver_priv
;
1997 if (!master_priv
->sarea_priv
)
2000 if (intel_crtc
->pipe
) {
2001 master_priv
->sarea_priv
->pipeB_x
= x
;
2002 master_priv
->sarea_priv
->pipeB_y
= y
;
2004 master_priv
->sarea_priv
->pipeA_x
= x
;
2005 master_priv
->sarea_priv
->pipeA_y
= y
;
2011 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2013 struct drm_device
*dev
= crtc
->dev
;
2014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2017 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2018 dpa_ctl
= I915_READ(DP_A
);
2019 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2021 if (clock
< 200000) {
2023 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2024 /* workaround for 160Mhz:
2025 1) program 0x4600c bits 15:0 = 0x8124
2026 2) program 0x46010 bit 0 = 1
2027 3) program 0x46034 bit 24 = 1
2028 4) program 0x64000 bit 14 = 1
2030 temp
= I915_READ(0x4600c);
2032 I915_WRITE(0x4600c, temp
| 0x8124);
2034 temp
= I915_READ(0x46010);
2035 I915_WRITE(0x46010, temp
| 1);
2037 temp
= I915_READ(0x46034);
2038 I915_WRITE(0x46034, temp
| (1 << 24));
2040 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2042 I915_WRITE(DP_A
, dpa_ctl
);
2048 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2050 struct drm_device
*dev
= crtc
->dev
;
2051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2052 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2053 int pipe
= intel_crtc
->pipe
;
2056 /* enable normal train */
2057 reg
= FDI_TX_CTL(pipe
);
2058 temp
= I915_READ(reg
);
2059 if (IS_IVYBRIDGE(dev
)) {
2060 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2061 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2063 temp
&= ~FDI_LINK_TRAIN_NONE
;
2064 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2066 I915_WRITE(reg
, temp
);
2068 reg
= FDI_RX_CTL(pipe
);
2069 temp
= I915_READ(reg
);
2070 if (HAS_PCH_CPT(dev
)) {
2071 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2072 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2074 temp
&= ~FDI_LINK_TRAIN_NONE
;
2075 temp
|= FDI_LINK_TRAIN_NONE
;
2077 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2079 /* wait one idle pattern time */
2083 /* IVB wants error correction enabled */
2084 if (IS_IVYBRIDGE(dev
))
2085 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2086 FDI_FE_ERRC_ENABLE
);
2089 /* The FDI link training functions for ILK/Ibexpeak. */
2090 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2092 struct drm_device
*dev
= crtc
->dev
;
2093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2094 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2095 int pipe
= intel_crtc
->pipe
;
2096 int plane
= intel_crtc
->plane
;
2097 u32 reg
, temp
, tries
;
2099 /* FDI needs bits from pipe & plane first */
2100 assert_pipe_enabled(dev_priv
, pipe
);
2101 assert_plane_enabled(dev_priv
, plane
);
2103 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2105 reg
= FDI_RX_IMR(pipe
);
2106 temp
= I915_READ(reg
);
2107 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2108 temp
&= ~FDI_RX_BIT_LOCK
;
2109 I915_WRITE(reg
, temp
);
2113 /* enable CPU FDI TX and PCH FDI RX */
2114 reg
= FDI_TX_CTL(pipe
);
2115 temp
= I915_READ(reg
);
2117 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2118 temp
&= ~FDI_LINK_TRAIN_NONE
;
2119 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2120 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2122 reg
= FDI_RX_CTL(pipe
);
2123 temp
= I915_READ(reg
);
2124 temp
&= ~FDI_LINK_TRAIN_NONE
;
2125 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2126 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2131 /* Ironlake workaround, enable clock pointer after FDI enable*/
2132 if (HAS_PCH_IBX(dev
)) {
2133 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2134 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2135 FDI_RX_PHASE_SYNC_POINTER_EN
);
2138 reg
= FDI_RX_IIR(pipe
);
2139 for (tries
= 0; tries
< 5; tries
++) {
2140 temp
= I915_READ(reg
);
2141 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2143 if ((temp
& FDI_RX_BIT_LOCK
)) {
2144 DRM_DEBUG_KMS("FDI train 1 done.\n");
2145 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2150 DRM_ERROR("FDI train 1 fail!\n");
2153 reg
= FDI_TX_CTL(pipe
);
2154 temp
= I915_READ(reg
);
2155 temp
&= ~FDI_LINK_TRAIN_NONE
;
2156 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2157 I915_WRITE(reg
, temp
);
2159 reg
= FDI_RX_CTL(pipe
);
2160 temp
= I915_READ(reg
);
2161 temp
&= ~FDI_LINK_TRAIN_NONE
;
2162 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2163 I915_WRITE(reg
, temp
);
2168 reg
= FDI_RX_IIR(pipe
);
2169 for (tries
= 0; tries
< 5; tries
++) {
2170 temp
= I915_READ(reg
);
2171 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2173 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2174 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2175 DRM_DEBUG_KMS("FDI train 2 done.\n");
2180 DRM_ERROR("FDI train 2 fail!\n");
2182 DRM_DEBUG_KMS("FDI train done\n");
2186 static const int snb_b_fdi_train_param
[] = {
2187 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2188 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2189 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2190 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2193 /* The FDI link training functions for SNB/Cougarpoint. */
2194 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2196 struct drm_device
*dev
= crtc
->dev
;
2197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2198 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2199 int pipe
= intel_crtc
->pipe
;
2202 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2204 reg
= FDI_RX_IMR(pipe
);
2205 temp
= I915_READ(reg
);
2206 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2207 temp
&= ~FDI_RX_BIT_LOCK
;
2208 I915_WRITE(reg
, temp
);
2213 /* enable CPU FDI TX and PCH FDI RX */
2214 reg
= FDI_TX_CTL(pipe
);
2215 temp
= I915_READ(reg
);
2217 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2218 temp
&= ~FDI_LINK_TRAIN_NONE
;
2219 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2220 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2222 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2223 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2225 reg
= FDI_RX_CTL(pipe
);
2226 temp
= I915_READ(reg
);
2227 if (HAS_PCH_CPT(dev
)) {
2228 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2229 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2231 temp
&= ~FDI_LINK_TRAIN_NONE
;
2232 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2234 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2239 for (i
= 0; i
< 4; i
++ ) {
2240 reg
= FDI_TX_CTL(pipe
);
2241 temp
= I915_READ(reg
);
2242 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2243 temp
|= snb_b_fdi_train_param
[i
];
2244 I915_WRITE(reg
, temp
);
2249 reg
= FDI_RX_IIR(pipe
);
2250 temp
= I915_READ(reg
);
2251 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2253 if (temp
& FDI_RX_BIT_LOCK
) {
2254 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2255 DRM_DEBUG_KMS("FDI train 1 done.\n");
2260 DRM_ERROR("FDI train 1 fail!\n");
2263 reg
= FDI_TX_CTL(pipe
);
2264 temp
= I915_READ(reg
);
2265 temp
&= ~FDI_LINK_TRAIN_NONE
;
2266 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2268 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2270 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2272 I915_WRITE(reg
, temp
);
2274 reg
= FDI_RX_CTL(pipe
);
2275 temp
= I915_READ(reg
);
2276 if (HAS_PCH_CPT(dev
)) {
2277 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2278 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2280 temp
&= ~FDI_LINK_TRAIN_NONE
;
2281 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2283 I915_WRITE(reg
, temp
);
2288 for (i
= 0; i
< 4; i
++ ) {
2289 reg
= FDI_TX_CTL(pipe
);
2290 temp
= I915_READ(reg
);
2291 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2292 temp
|= snb_b_fdi_train_param
[i
];
2293 I915_WRITE(reg
, temp
);
2298 reg
= FDI_RX_IIR(pipe
);
2299 temp
= I915_READ(reg
);
2300 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2302 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2303 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2304 DRM_DEBUG_KMS("FDI train 2 done.\n");
2309 DRM_ERROR("FDI train 2 fail!\n");
2311 DRM_DEBUG_KMS("FDI train done.\n");
2314 /* Manual link training for Ivy Bridge A0 parts */
2315 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2317 struct drm_device
*dev
= crtc
->dev
;
2318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2319 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2320 int pipe
= intel_crtc
->pipe
;
2323 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2325 reg
= FDI_RX_IMR(pipe
);
2326 temp
= I915_READ(reg
);
2327 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2328 temp
&= ~FDI_RX_BIT_LOCK
;
2329 I915_WRITE(reg
, temp
);
2334 /* enable CPU FDI TX and PCH FDI RX */
2335 reg
= FDI_TX_CTL(pipe
);
2336 temp
= I915_READ(reg
);
2338 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2339 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2340 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2341 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2342 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2343 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2345 reg
= FDI_RX_CTL(pipe
);
2346 temp
= I915_READ(reg
);
2347 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2348 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2349 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2350 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2355 for (i
= 0; i
< 4; i
++ ) {
2356 reg
= FDI_TX_CTL(pipe
);
2357 temp
= I915_READ(reg
);
2358 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2359 temp
|= snb_b_fdi_train_param
[i
];
2360 I915_WRITE(reg
, temp
);
2365 reg
= FDI_RX_IIR(pipe
);
2366 temp
= I915_READ(reg
);
2367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2369 if (temp
& FDI_RX_BIT_LOCK
||
2370 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2371 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
2377 DRM_ERROR("FDI train 1 fail!\n");
2380 reg
= FDI_TX_CTL(pipe
);
2381 temp
= I915_READ(reg
);
2382 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2383 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2384 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2385 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2386 I915_WRITE(reg
, temp
);
2388 reg
= FDI_RX_CTL(pipe
);
2389 temp
= I915_READ(reg
);
2390 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2391 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2392 I915_WRITE(reg
, temp
);
2397 for (i
= 0; i
< 4; i
++ ) {
2398 reg
= FDI_TX_CTL(pipe
);
2399 temp
= I915_READ(reg
);
2400 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2401 temp
|= snb_b_fdi_train_param
[i
];
2402 I915_WRITE(reg
, temp
);
2407 reg
= FDI_RX_IIR(pipe
);
2408 temp
= I915_READ(reg
);
2409 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2411 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2412 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2413 DRM_DEBUG_KMS("FDI train 2 done.\n");
2418 DRM_ERROR("FDI train 2 fail!\n");
2420 DRM_DEBUG_KMS("FDI train done.\n");
2423 static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc
)
2425 struct drm_device
*dev
= crtc
->dev
;
2426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2427 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2428 int pipe
= intel_crtc
->pipe
;
2431 /* Write the TU size bits so error detection works */
2432 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2433 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2435 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2436 reg
= FDI_RX_CTL(pipe
);
2437 temp
= I915_READ(reg
);
2438 temp
&= ~((0x7 << 19) | (0x7 << 16));
2439 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2440 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2441 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2446 /* Switch from Rawclk to PCDclk */
2447 temp
= I915_READ(reg
);
2448 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2453 /* Enable CPU FDI TX PLL, always on for Ironlake */
2454 reg
= FDI_TX_CTL(pipe
);
2455 temp
= I915_READ(reg
);
2456 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2457 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2464 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2466 struct drm_device
*dev
= crtc
->dev
;
2467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2468 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2469 int pipe
= intel_crtc
->pipe
;
2472 /* disable CPU FDI tx and PCH FDI rx */
2473 reg
= FDI_TX_CTL(pipe
);
2474 temp
= I915_READ(reg
);
2475 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2478 reg
= FDI_RX_CTL(pipe
);
2479 temp
= I915_READ(reg
);
2480 temp
&= ~(0x7 << 16);
2481 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2482 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2487 /* Ironlake workaround, disable clock pointer after downing FDI */
2488 if (HAS_PCH_IBX(dev
)) {
2489 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2490 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2491 I915_READ(FDI_RX_CHICKEN(pipe
) &
2492 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2495 /* still set train pattern 1 */
2496 reg
= FDI_TX_CTL(pipe
);
2497 temp
= I915_READ(reg
);
2498 temp
&= ~FDI_LINK_TRAIN_NONE
;
2499 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2500 I915_WRITE(reg
, temp
);
2502 reg
= FDI_RX_CTL(pipe
);
2503 temp
= I915_READ(reg
);
2504 if (HAS_PCH_CPT(dev
)) {
2505 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2506 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2508 temp
&= ~FDI_LINK_TRAIN_NONE
;
2509 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2511 /* BPC in FDI rx is consistent with that in PIPECONF */
2512 temp
&= ~(0x07 << 16);
2513 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2514 I915_WRITE(reg
, temp
);
2521 * When we disable a pipe, we need to clear any pending scanline wait events
2522 * to avoid hanging the ring, which we assume we are waiting on.
2524 static void intel_clear_scanline_wait(struct drm_device
*dev
)
2526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2527 struct intel_ring_buffer
*ring
;
2531 /* Can't break the hang on i8xx */
2534 ring
= LP_RING(dev_priv
);
2535 tmp
= I915_READ_CTL(ring
);
2536 if (tmp
& RING_WAIT
)
2537 I915_WRITE_CTL(ring
, tmp
);
2540 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2542 struct drm_i915_gem_object
*obj
;
2543 struct drm_i915_private
*dev_priv
;
2545 if (crtc
->fb
== NULL
)
2548 obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
2549 dev_priv
= crtc
->dev
->dev_private
;
2550 wait_event(dev_priv
->pending_flip_queue
,
2551 atomic_read(&obj
->pending_flip
) == 0);
2554 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
2556 struct drm_device
*dev
= crtc
->dev
;
2557 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2558 struct intel_encoder
*encoder
;
2561 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2562 * must be driven by its own crtc; no sharing is possible.
2564 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
2565 if (encoder
->base
.crtc
!= crtc
)
2568 switch (encoder
->type
) {
2569 case INTEL_OUTPUT_EDP
:
2570 if (!intel_encoder_is_pch_edp(&encoder
->base
))
2580 * Enable PCH resources required for PCH ports:
2582 * - FDI training & RX/TX
2583 * - update transcoder timings
2584 * - DP transcoding bits
2587 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2589 struct drm_device
*dev
= crtc
->dev
;
2590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2591 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2592 int pipe
= intel_crtc
->pipe
;
2595 /* For PCH output, training FDI link */
2596 dev_priv
->display
.fdi_link_train(crtc
);
2598 intel_enable_pch_pll(dev_priv
, pipe
);
2600 if (HAS_PCH_CPT(dev
)) {
2601 /* Be sure PCH DPLL SEL is set */
2602 temp
= I915_READ(PCH_DPLL_SEL
);
2603 if (pipe
== 0 && (temp
& TRANSA_DPLL_ENABLE
) == 0)
2604 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
2605 else if (pipe
== 1 && (temp
& TRANSB_DPLL_ENABLE
) == 0)
2606 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2607 I915_WRITE(PCH_DPLL_SEL
, temp
);
2610 /* set transcoder timing, panel must allow it */
2611 assert_panel_unlocked(dev_priv
, pipe
);
2612 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
2613 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
2614 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
2616 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
2617 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
2618 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
2620 intel_fdi_normal_train(crtc
);
2622 /* For PCH DP, enable TRANS_DP_CTL */
2623 if (HAS_PCH_CPT(dev
) &&
2624 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
2625 reg
= TRANS_DP_CTL(pipe
);
2626 temp
= I915_READ(reg
);
2627 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
2628 TRANS_DP_SYNC_MASK
|
2630 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
2631 TRANS_DP_ENH_FRAMING
);
2632 temp
|= TRANS_DP_8BPC
;
2634 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
2635 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
2636 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
2637 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
2639 switch (intel_trans_dp_port_sel(crtc
)) {
2641 temp
|= TRANS_DP_PORT_SEL_B
;
2644 temp
|= TRANS_DP_PORT_SEL_C
;
2647 temp
|= TRANS_DP_PORT_SEL_D
;
2650 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2651 temp
|= TRANS_DP_PORT_SEL_B
;
2655 I915_WRITE(reg
, temp
);
2658 intel_enable_transcoder(dev_priv
, pipe
);
2661 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
2663 struct drm_device
*dev
= crtc
->dev
;
2664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2665 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2666 int pipe
= intel_crtc
->pipe
;
2667 int plane
= intel_crtc
->plane
;
2671 if (intel_crtc
->active
)
2674 intel_crtc
->active
= true;
2675 intel_update_watermarks(dev
);
2677 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2678 temp
= I915_READ(PCH_LVDS
);
2679 if ((temp
& LVDS_PORT_EN
) == 0)
2680 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
2683 is_pch_port
= intel_crtc_driving_pch(crtc
);
2686 ironlake_fdi_pll_enable(crtc
);
2688 ironlake_fdi_disable(crtc
);
2690 /* Enable panel fitting for LVDS */
2691 if (dev_priv
->pch_pf_size
&&
2692 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
2693 /* Force use of hard-coded filter coefficients
2694 * as some pre-programmed values are broken,
2697 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
2698 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
2699 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
2702 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
2703 intel_enable_plane(dev_priv
, plane
, pipe
);
2706 ironlake_pch_enable(crtc
);
2708 intel_crtc_load_lut(crtc
);
2710 mutex_lock(&dev
->struct_mutex
);
2711 intel_update_fbc(dev
);
2712 mutex_unlock(&dev
->struct_mutex
);
2714 intel_crtc_update_cursor(crtc
, true);
2717 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
2719 struct drm_device
*dev
= crtc
->dev
;
2720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2721 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2722 int pipe
= intel_crtc
->pipe
;
2723 int plane
= intel_crtc
->plane
;
2726 if (!intel_crtc
->active
)
2729 intel_crtc_wait_for_pending_flips(crtc
);
2730 drm_vblank_off(dev
, pipe
);
2731 intel_crtc_update_cursor(crtc
, false);
2733 intel_disable_plane(dev_priv
, plane
, pipe
);
2735 if (dev_priv
->cfb_plane
== plane
&&
2736 dev_priv
->display
.disable_fbc
)
2737 dev_priv
->display
.disable_fbc(dev
);
2739 intel_disable_pipe(dev_priv
, pipe
);
2742 I915_WRITE(PF_CTL(pipe
), 0);
2743 I915_WRITE(PF_WIN_SZ(pipe
), 0);
2745 ironlake_fdi_disable(crtc
);
2747 /* This is a horrible layering violation; we should be doing this in
2748 * the connector/encoder ->prepare instead, but we don't always have
2749 * enough information there about the config to know whether it will
2750 * actually be necessary or just cause undesired flicker.
2752 intel_disable_pch_ports(dev_priv
, pipe
);
2754 intel_disable_transcoder(dev_priv
, pipe
);
2756 if (HAS_PCH_CPT(dev
)) {
2757 /* disable TRANS_DP_CTL */
2758 reg
= TRANS_DP_CTL(pipe
);
2759 temp
= I915_READ(reg
);
2760 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2761 temp
|= TRANS_DP_PORT_SEL_NONE
;
2762 I915_WRITE(reg
, temp
);
2764 /* disable DPLL_SEL */
2765 temp
= I915_READ(PCH_DPLL_SEL
);
2768 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
2771 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2774 /* FIXME: manage transcoder PLLs? */
2775 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
2780 I915_WRITE(PCH_DPLL_SEL
, temp
);
2783 /* disable PCH DPLL */
2784 intel_disable_pch_pll(dev_priv
, pipe
);
2786 /* Switch from PCDclk to Rawclk */
2787 reg
= FDI_RX_CTL(pipe
);
2788 temp
= I915_READ(reg
);
2789 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2791 /* Disable CPU FDI TX PLL */
2792 reg
= FDI_TX_CTL(pipe
);
2793 temp
= I915_READ(reg
);
2794 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2799 reg
= FDI_RX_CTL(pipe
);
2800 temp
= I915_READ(reg
);
2801 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2803 /* Wait for the clocks to turn off. */
2807 intel_crtc
->active
= false;
2808 intel_update_watermarks(dev
);
2810 mutex_lock(&dev
->struct_mutex
);
2811 intel_update_fbc(dev
);
2812 intel_clear_scanline_wait(dev
);
2813 mutex_unlock(&dev
->struct_mutex
);
2816 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2818 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2819 int pipe
= intel_crtc
->pipe
;
2820 int plane
= intel_crtc
->plane
;
2822 /* XXX: When our outputs are all unaware of DPMS modes other than off
2823 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2826 case DRM_MODE_DPMS_ON
:
2827 case DRM_MODE_DPMS_STANDBY
:
2828 case DRM_MODE_DPMS_SUSPEND
:
2829 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
2830 ironlake_crtc_enable(crtc
);
2833 case DRM_MODE_DPMS_OFF
:
2834 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
2835 ironlake_crtc_disable(crtc
);
2840 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
2842 if (!enable
&& intel_crtc
->overlay
) {
2843 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2846 mutex_lock(&dev
->struct_mutex
);
2847 dev_priv
->mm
.interruptible
= false;
2848 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
2849 dev_priv
->mm
.interruptible
= true;
2850 mutex_unlock(&dev
->struct_mutex
);
2853 /* Let userspace switch the overlay on again. In most cases userspace
2854 * has to recompute where to put it anyway.
2858 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
2860 struct drm_device
*dev
= crtc
->dev
;
2861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2862 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2863 int pipe
= intel_crtc
->pipe
;
2864 int plane
= intel_crtc
->plane
;
2866 if (intel_crtc
->active
)
2869 intel_crtc
->active
= true;
2870 intel_update_watermarks(dev
);
2872 intel_enable_pll(dev_priv
, pipe
);
2873 intel_enable_pipe(dev_priv
, pipe
, false);
2874 intel_enable_plane(dev_priv
, plane
, pipe
);
2876 intel_crtc_load_lut(crtc
);
2877 intel_update_fbc(dev
);
2879 /* Give the overlay scaler a chance to enable if it's on this pipe */
2880 intel_crtc_dpms_overlay(intel_crtc
, true);
2881 intel_crtc_update_cursor(crtc
, true);
2884 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
2886 struct drm_device
*dev
= crtc
->dev
;
2887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2888 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2889 int pipe
= intel_crtc
->pipe
;
2890 int plane
= intel_crtc
->plane
;
2892 if (!intel_crtc
->active
)
2895 /* Give the overlay scaler a chance to disable if it's on this pipe */
2896 intel_crtc_wait_for_pending_flips(crtc
);
2897 drm_vblank_off(dev
, pipe
);
2898 intel_crtc_dpms_overlay(intel_crtc
, false);
2899 intel_crtc_update_cursor(crtc
, false);
2901 if (dev_priv
->cfb_plane
== plane
&&
2902 dev_priv
->display
.disable_fbc
)
2903 dev_priv
->display
.disable_fbc(dev
);
2905 intel_disable_plane(dev_priv
, plane
, pipe
);
2906 intel_disable_pipe(dev_priv
, pipe
);
2907 intel_disable_pll(dev_priv
, pipe
);
2909 intel_crtc
->active
= false;
2910 intel_update_fbc(dev
);
2911 intel_update_watermarks(dev
);
2912 intel_clear_scanline_wait(dev
);
2915 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2917 /* XXX: When our outputs are all unaware of DPMS modes other than off
2918 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2921 case DRM_MODE_DPMS_ON
:
2922 case DRM_MODE_DPMS_STANDBY
:
2923 case DRM_MODE_DPMS_SUSPEND
:
2924 i9xx_crtc_enable(crtc
);
2926 case DRM_MODE_DPMS_OFF
:
2927 i9xx_crtc_disable(crtc
);
2933 * Sets the power management mode of the pipe and plane.
2935 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2937 struct drm_device
*dev
= crtc
->dev
;
2938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2939 struct drm_i915_master_private
*master_priv
;
2940 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2941 int pipe
= intel_crtc
->pipe
;
2944 if (intel_crtc
->dpms_mode
== mode
)
2947 intel_crtc
->dpms_mode
= mode
;
2949 dev_priv
->display
.dpms(crtc
, mode
);
2951 if (!dev
->primary
->master
)
2954 master_priv
= dev
->primary
->master
->driver_priv
;
2955 if (!master_priv
->sarea_priv
)
2958 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2962 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2963 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2966 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2967 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2970 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
2975 static void intel_crtc_disable(struct drm_crtc
*crtc
)
2977 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2978 struct drm_device
*dev
= crtc
->dev
;
2980 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
2983 mutex_lock(&dev
->struct_mutex
);
2984 i915_gem_object_unpin(to_intel_framebuffer(crtc
->fb
)->obj
);
2985 mutex_unlock(&dev
->struct_mutex
);
2989 /* Prepare for a mode set.
2991 * Note we could be a lot smarter here. We need to figure out which outputs
2992 * will be enabled, which disabled (in short, how the config will changes)
2993 * and perform the minimum necessary steps to accomplish that, e.g. updating
2994 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2995 * panel fitting is in the proper state, etc.
2997 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
2999 i9xx_crtc_disable(crtc
);
3002 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
3004 i9xx_crtc_enable(crtc
);
3007 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
3009 ironlake_crtc_disable(crtc
);
3012 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
3014 ironlake_crtc_enable(crtc
);
3017 void intel_encoder_prepare (struct drm_encoder
*encoder
)
3019 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3020 /* lvds has its own version of prepare see intel_lvds_prepare */
3021 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
3024 void intel_encoder_commit (struct drm_encoder
*encoder
)
3026 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3027 /* lvds has its own version of commit see intel_lvds_commit */
3028 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3031 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3033 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3035 drm_encoder_cleanup(encoder
);
3036 kfree(intel_encoder
);
3039 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3040 struct drm_display_mode
*mode
,
3041 struct drm_display_mode
*adjusted_mode
)
3043 struct drm_device
*dev
= crtc
->dev
;
3045 if (HAS_PCH_SPLIT(dev
)) {
3046 /* FDI link clock is fixed at 2.7G */
3047 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3051 /* XXX some encoders set the crtcinfo, others don't.
3052 * Obviously we need some form of conflict resolution here...
3054 if (adjusted_mode
->crtc_htotal
== 0)
3055 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3060 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3065 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3070 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3075 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3079 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3081 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3084 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3085 case GC_DISPLAY_CLOCK_333_MHZ
:
3088 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3094 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3099 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3102 /* Assume that the hardware is in the high speed state. This
3103 * should be the default.
3105 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3106 case GC_CLOCK_133_200
:
3107 case GC_CLOCK_100_200
:
3109 case GC_CLOCK_166_250
:
3111 case GC_CLOCK_100_133
:
3115 /* Shouldn't happen */
3119 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3133 fdi_reduce_ratio(u32
*num
, u32
*den
)
3135 while (*num
> 0xffffff || *den
> 0xffffff) {
3142 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3143 int link_clock
, struct fdi_m_n
*m_n
)
3145 m_n
->tu
= 64; /* default size */
3147 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3148 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3149 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3150 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3152 m_n
->link_m
= pixel_clock
;
3153 m_n
->link_n
= link_clock
;
3154 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3158 struct intel_watermark_params
{
3159 unsigned long fifo_size
;
3160 unsigned long max_wm
;
3161 unsigned long default_wm
;
3162 unsigned long guard_size
;
3163 unsigned long cacheline_size
;
3166 /* Pineview has different values for various configs */
3167 static const struct intel_watermark_params pineview_display_wm
= {
3168 PINEVIEW_DISPLAY_FIFO
,
3172 PINEVIEW_FIFO_LINE_SIZE
3174 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
3175 PINEVIEW_DISPLAY_FIFO
,
3177 PINEVIEW_DFT_HPLLOFF_WM
,
3179 PINEVIEW_FIFO_LINE_SIZE
3181 static const struct intel_watermark_params pineview_cursor_wm
= {
3182 PINEVIEW_CURSOR_FIFO
,
3183 PINEVIEW_CURSOR_MAX_WM
,
3184 PINEVIEW_CURSOR_DFT_WM
,
3185 PINEVIEW_CURSOR_GUARD_WM
,
3186 PINEVIEW_FIFO_LINE_SIZE
,
3188 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
3189 PINEVIEW_CURSOR_FIFO
,
3190 PINEVIEW_CURSOR_MAX_WM
,
3191 PINEVIEW_CURSOR_DFT_WM
,
3192 PINEVIEW_CURSOR_GUARD_WM
,
3193 PINEVIEW_FIFO_LINE_SIZE
3195 static const struct intel_watermark_params g4x_wm_info
= {
3202 static const struct intel_watermark_params g4x_cursor_wm_info
= {
3209 static const struct intel_watermark_params i965_cursor_wm_info
= {
3214 I915_FIFO_LINE_SIZE
,
3216 static const struct intel_watermark_params i945_wm_info
= {
3223 static const struct intel_watermark_params i915_wm_info
= {
3230 static const struct intel_watermark_params i855_wm_info
= {
3237 static const struct intel_watermark_params i830_wm_info
= {
3245 static const struct intel_watermark_params ironlake_display_wm_info
= {
3252 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
3259 static const struct intel_watermark_params ironlake_display_srwm_info
= {
3260 ILK_DISPLAY_SR_FIFO
,
3261 ILK_DISPLAY_MAX_SRWM
,
3262 ILK_DISPLAY_DFT_SRWM
,
3266 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
3268 ILK_CURSOR_MAX_SRWM
,
3269 ILK_CURSOR_DFT_SRWM
,
3274 static const struct intel_watermark_params sandybridge_display_wm_info
= {
3281 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
3288 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
3289 SNB_DISPLAY_SR_FIFO
,
3290 SNB_DISPLAY_MAX_SRWM
,
3291 SNB_DISPLAY_DFT_SRWM
,
3295 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
3297 SNB_CURSOR_MAX_SRWM
,
3298 SNB_CURSOR_DFT_SRWM
,
3305 * intel_calculate_wm - calculate watermark level
3306 * @clock_in_khz: pixel clock
3307 * @wm: chip FIFO params
3308 * @pixel_size: display pixel size
3309 * @latency_ns: memory latency for the platform
3311 * Calculate the watermark level (the level at which the display plane will
3312 * start fetching from memory again). Each chip has a different display
3313 * FIFO size and allocation, so the caller needs to figure that out and pass
3314 * in the correct intel_watermark_params structure.
3316 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3317 * on the pixel size. When it reaches the watermark level, it'll start
3318 * fetching FIFO line sized based chunks from memory until the FIFO fills
3319 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3320 * will occur, and a display engine hang could result.
3322 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
3323 const struct intel_watermark_params
*wm
,
3326 unsigned long latency_ns
)
3328 long entries_required
, wm_size
;
3331 * Note: we need to make sure we don't overflow for various clock &
3333 * clocks go from a few thousand to several hundred thousand.
3334 * latency is usually a few thousand
3336 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
3338 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
3340 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
3342 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
3344 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
3346 /* Don't promote wm_size to unsigned... */
3347 if (wm_size
> (long)wm
->max_wm
)
3348 wm_size
= wm
->max_wm
;
3350 wm_size
= wm
->default_wm
;
3354 struct cxsr_latency
{
3357 unsigned long fsb_freq
;
3358 unsigned long mem_freq
;
3359 unsigned long display_sr
;
3360 unsigned long display_hpll_disable
;
3361 unsigned long cursor_sr
;
3362 unsigned long cursor_hpll_disable
;
3365 static const struct cxsr_latency cxsr_latency_table
[] = {
3366 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3367 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3368 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3369 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3370 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3372 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3373 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3374 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3375 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3376 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3378 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3379 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3380 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3381 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3382 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3384 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3385 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3386 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3387 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3388 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3390 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3391 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3392 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3393 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3394 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3396 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3397 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3398 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3399 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3400 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3403 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
3408 const struct cxsr_latency
*latency
;
3411 if (fsb
== 0 || mem
== 0)
3414 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
3415 latency
= &cxsr_latency_table
[i
];
3416 if (is_desktop
== latency
->is_desktop
&&
3417 is_ddr3
== latency
->is_ddr3
&&
3418 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
3422 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3427 static void pineview_disable_cxsr(struct drm_device
*dev
)
3429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3431 /* deactivate cxsr */
3432 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
3436 * Latency for FIFO fetches is dependent on several factors:
3437 * - memory configuration (speed, channels)
3439 * - current MCH state
3440 * It can be fairly high in some situations, so here we assume a fairly
3441 * pessimal value. It's a tradeoff between extra memory fetches (if we
3442 * set this value too high, the FIFO will fetch frequently to stay full)
3443 * and power consumption (set it too low to save power and we might see
3444 * FIFO underruns and display "flicker").
3446 * A value of 5us seems to be a good balance; safe for very low end
3447 * platforms but not overly aggressive on lower latency configs.
3449 static const int latency_ns
= 5000;
3451 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
3453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3454 uint32_t dsparb
= I915_READ(DSPARB
);
3457 size
= dsparb
& 0x7f;
3459 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
3461 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3462 plane
? "B" : "A", size
);
3467 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
3469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3470 uint32_t dsparb
= I915_READ(DSPARB
);
3473 size
= dsparb
& 0x1ff;
3475 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
3476 size
>>= 1; /* Convert to cachelines */
3478 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3479 plane
? "B" : "A", size
);
3484 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
3486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3487 uint32_t dsparb
= I915_READ(DSPARB
);
3490 size
= dsparb
& 0x7f;
3491 size
>>= 2; /* Convert to cachelines */
3493 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3500 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
3502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3503 uint32_t dsparb
= I915_READ(DSPARB
);
3506 size
= dsparb
& 0x7f;
3507 size
>>= 1; /* Convert to cachelines */
3509 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3510 plane
? "B" : "A", size
);
3515 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
3517 struct drm_crtc
*crtc
, *enabled
= NULL
;
3519 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3520 if (crtc
->enabled
&& crtc
->fb
) {
3530 static void pineview_update_wm(struct drm_device
*dev
)
3532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3533 struct drm_crtc
*crtc
;
3534 const struct cxsr_latency
*latency
;
3538 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
3539 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
3541 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3542 pineview_disable_cxsr(dev
);
3546 crtc
= single_enabled_crtc(dev
);
3548 int clock
= crtc
->mode
.clock
;
3549 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3552 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
3553 pineview_display_wm
.fifo_size
,
3554 pixel_size
, latency
->display_sr
);
3555 reg
= I915_READ(DSPFW1
);
3556 reg
&= ~DSPFW_SR_MASK
;
3557 reg
|= wm
<< DSPFW_SR_SHIFT
;
3558 I915_WRITE(DSPFW1
, reg
);
3559 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
3562 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
3563 pineview_display_wm
.fifo_size
,
3564 pixel_size
, latency
->cursor_sr
);
3565 reg
= I915_READ(DSPFW3
);
3566 reg
&= ~DSPFW_CURSOR_SR_MASK
;
3567 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
3568 I915_WRITE(DSPFW3
, reg
);
3570 /* Display HPLL off SR */
3571 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
3572 pineview_display_hplloff_wm
.fifo_size
,
3573 pixel_size
, latency
->display_hpll_disable
);
3574 reg
= I915_READ(DSPFW3
);
3575 reg
&= ~DSPFW_HPLL_SR_MASK
;
3576 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
3577 I915_WRITE(DSPFW3
, reg
);
3579 /* cursor HPLL off SR */
3580 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
3581 pineview_display_hplloff_wm
.fifo_size
,
3582 pixel_size
, latency
->cursor_hpll_disable
);
3583 reg
= I915_READ(DSPFW3
);
3584 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
3585 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
3586 I915_WRITE(DSPFW3
, reg
);
3587 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
3591 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
3592 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3594 pineview_disable_cxsr(dev
);
3595 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3599 static bool g4x_compute_wm0(struct drm_device
*dev
,
3601 const struct intel_watermark_params
*display
,
3602 int display_latency_ns
,
3603 const struct intel_watermark_params
*cursor
,
3604 int cursor_latency_ns
,
3608 struct drm_crtc
*crtc
;
3609 int htotal
, hdisplay
, clock
, pixel_size
;
3610 int line_time_us
, line_count
;
3611 int entries
, tlb_miss
;
3613 crtc
= intel_get_crtc_for_plane(dev
, plane
);
3614 if (crtc
->fb
== NULL
|| !crtc
->enabled
) {
3615 *cursor_wm
= cursor
->guard_size
;
3616 *plane_wm
= display
->guard_size
;
3620 htotal
= crtc
->mode
.htotal
;
3621 hdisplay
= crtc
->mode
.hdisplay
;
3622 clock
= crtc
->mode
.clock
;
3623 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3625 /* Use the small buffer method to calculate plane watermark */
3626 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
3627 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
3629 entries
+= tlb_miss
;
3630 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
3631 *plane_wm
= entries
+ display
->guard_size
;
3632 if (*plane_wm
> (int)display
->max_wm
)
3633 *plane_wm
= display
->max_wm
;
3635 /* Use the large buffer method to calculate cursor watermark */
3636 line_time_us
= ((htotal
* 1000) / clock
);
3637 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
3638 entries
= line_count
* 64 * pixel_size
;
3639 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
3641 entries
+= tlb_miss
;
3642 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
3643 *cursor_wm
= entries
+ cursor
->guard_size
;
3644 if (*cursor_wm
> (int)cursor
->max_wm
)
3645 *cursor_wm
= (int)cursor
->max_wm
;
3651 * Check the wm result.
3653 * If any calculated watermark values is larger than the maximum value that
3654 * can be programmed into the associated watermark register, that watermark
3657 static bool g4x_check_srwm(struct drm_device
*dev
,
3658 int display_wm
, int cursor_wm
,
3659 const struct intel_watermark_params
*display
,
3660 const struct intel_watermark_params
*cursor
)
3662 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3663 display_wm
, cursor_wm
);
3665 if (display_wm
> display
->max_wm
) {
3666 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3667 display_wm
, display
->max_wm
);
3671 if (cursor_wm
> cursor
->max_wm
) {
3672 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3673 cursor_wm
, cursor
->max_wm
);
3677 if (!(display_wm
|| cursor_wm
)) {
3678 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3685 static bool g4x_compute_srwm(struct drm_device
*dev
,
3688 const struct intel_watermark_params
*display
,
3689 const struct intel_watermark_params
*cursor
,
3690 int *display_wm
, int *cursor_wm
)
3692 struct drm_crtc
*crtc
;
3693 int hdisplay
, htotal
, pixel_size
, clock
;
3694 unsigned long line_time_us
;
3695 int line_count
, line_size
;
3700 *display_wm
= *cursor_wm
= 0;
3704 crtc
= intel_get_crtc_for_plane(dev
, plane
);
3705 hdisplay
= crtc
->mode
.hdisplay
;
3706 htotal
= crtc
->mode
.htotal
;
3707 clock
= crtc
->mode
.clock
;
3708 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3710 line_time_us
= (htotal
* 1000) / clock
;
3711 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
3712 line_size
= hdisplay
* pixel_size
;
3714 /* Use the minimum of the small and large buffer method for primary */
3715 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
3716 large
= line_count
* line_size
;
3718 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
3719 *display_wm
= entries
+ display
->guard_size
;
3721 /* calculate the self-refresh watermark for display cursor */
3722 entries
= line_count
* pixel_size
* 64;
3723 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
3724 *cursor_wm
= entries
+ cursor
->guard_size
;
3726 return g4x_check_srwm(dev
,
3727 *display_wm
, *cursor_wm
,
3731 #define single_plane_enabled(mask) is_power_of_2(mask)
3733 static void g4x_update_wm(struct drm_device
*dev
)
3735 static const int sr_latency_ns
= 12000;
3736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3737 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
3738 int plane_sr
, cursor_sr
;
3739 unsigned int enabled
= 0;
3741 if (g4x_compute_wm0(dev
, 0,
3742 &g4x_wm_info
, latency_ns
,
3743 &g4x_cursor_wm_info
, latency_ns
,
3744 &planea_wm
, &cursora_wm
))
3747 if (g4x_compute_wm0(dev
, 1,
3748 &g4x_wm_info
, latency_ns
,
3749 &g4x_cursor_wm_info
, latency_ns
,
3750 &planeb_wm
, &cursorb_wm
))
3753 plane_sr
= cursor_sr
= 0;
3754 if (single_plane_enabled(enabled
) &&
3755 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
3758 &g4x_cursor_wm_info
,
3759 &plane_sr
, &cursor_sr
))
3760 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3762 I915_WRITE(FW_BLC_SELF
,
3763 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
3765 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3766 planea_wm
, cursora_wm
,
3767 planeb_wm
, cursorb_wm
,
3768 plane_sr
, cursor_sr
);
3771 (plane_sr
<< DSPFW_SR_SHIFT
) |
3772 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
3773 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
3776 (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
3777 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
3778 /* HPLL off in SR has some issues on G4x... disable it */
3780 (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
3781 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3784 static void i965_update_wm(struct drm_device
*dev
)
3786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3787 struct drm_crtc
*crtc
;
3791 /* Calc sr entries for one plane configs */
3792 crtc
= single_enabled_crtc(dev
);
3794 /* self-refresh has much higher latency */
3795 static const int sr_latency_ns
= 12000;
3796 int clock
= crtc
->mode
.clock
;
3797 int htotal
= crtc
->mode
.htotal
;
3798 int hdisplay
= crtc
->mode
.hdisplay
;
3799 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3800 unsigned long line_time_us
;
3803 line_time_us
= ((htotal
* 1000) / clock
);
3805 /* Use ns/us then divide to preserve precision */
3806 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3807 pixel_size
* hdisplay
;
3808 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
3809 srwm
= I965_FIFO_SIZE
- entries
;
3813 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3816 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3818 entries
= DIV_ROUND_UP(entries
,
3819 i965_cursor_wm_info
.cacheline_size
);
3820 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
3821 (entries
+ i965_cursor_wm_info
.guard_size
);
3823 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
3824 cursor_sr
= i965_cursor_wm_info
.max_wm
;
3826 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3827 "cursor %d\n", srwm
, cursor_sr
);
3829 if (IS_CRESTLINE(dev
))
3830 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3832 /* Turn off self refresh if both pipes are enabled */
3833 if (IS_CRESTLINE(dev
))
3834 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3838 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3841 /* 965 has limitations... */
3842 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
3843 (8 << 16) | (8 << 8) | (8 << 0));
3844 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
3845 /* update cursor SR watermark */
3846 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3849 static void i9xx_update_wm(struct drm_device
*dev
)
3851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3852 const struct intel_watermark_params
*wm_info
;
3857 int planea_wm
, planeb_wm
;
3858 struct drm_crtc
*crtc
, *enabled
= NULL
;
3861 wm_info
= &i945_wm_info
;
3862 else if (!IS_GEN2(dev
))
3863 wm_info
= &i915_wm_info
;
3865 wm_info
= &i855_wm_info
;
3867 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3868 crtc
= intel_get_crtc_for_plane(dev
, 0);
3869 if (crtc
->enabled
&& crtc
->fb
) {
3870 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
,
3872 crtc
->fb
->bits_per_pixel
/ 8,
3876 planea_wm
= fifo_size
- wm_info
->guard_size
;
3878 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
3879 crtc
= intel_get_crtc_for_plane(dev
, 1);
3880 if (crtc
->enabled
&& crtc
->fb
) {
3881 planeb_wm
= intel_calculate_wm(crtc
->mode
.clock
,
3883 crtc
->fb
->bits_per_pixel
/ 8,
3885 if (enabled
== NULL
)
3890 planeb_wm
= fifo_size
- wm_info
->guard_size
;
3892 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3895 * Overlay gets an aggressive default since video jitter is bad.
3899 /* Play safe and disable self-refresh before adjusting watermarks. */
3900 if (IS_I945G(dev
) || IS_I945GM(dev
))
3901 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
3902 else if (IS_I915GM(dev
))
3903 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
3905 /* Calc sr entries for one plane configs */
3906 if (HAS_FW_BLC(dev
) && enabled
) {
3907 /* self-refresh has much higher latency */
3908 static const int sr_latency_ns
= 6000;
3909 int clock
= enabled
->mode
.clock
;
3910 int htotal
= enabled
->mode
.htotal
;
3911 int hdisplay
= enabled
->mode
.hdisplay
;
3912 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
3913 unsigned long line_time_us
;
3916 line_time_us
= (htotal
* 1000) / clock
;
3918 /* Use ns/us then divide to preserve precision */
3919 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3920 pixel_size
* hdisplay
;
3921 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
3922 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
3923 srwm
= wm_info
->fifo_size
- entries
;
3927 if (IS_I945G(dev
) || IS_I945GM(dev
))
3928 I915_WRITE(FW_BLC_SELF
,
3929 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
3930 else if (IS_I915GM(dev
))
3931 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
3934 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3935 planea_wm
, planeb_wm
, cwm
, srwm
);
3937 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
3938 fwater_hi
= (cwm
& 0x1f);
3940 /* Set request length to 8 cachelines per fetch */
3941 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
3942 fwater_hi
= fwater_hi
| (1 << 8);
3944 I915_WRITE(FW_BLC
, fwater_lo
);
3945 I915_WRITE(FW_BLC2
, fwater_hi
);
3947 if (HAS_FW_BLC(dev
)) {
3949 if (IS_I945G(dev
) || IS_I945GM(dev
))
3950 I915_WRITE(FW_BLC_SELF
,
3951 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
3952 else if (IS_I915GM(dev
))
3953 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
3954 DRM_DEBUG_KMS("memory self refresh enabled\n");
3956 DRM_DEBUG_KMS("memory self refresh disabled\n");
3960 static void i830_update_wm(struct drm_device
*dev
)
3962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3963 struct drm_crtc
*crtc
;
3967 crtc
= single_enabled_crtc(dev
);
3971 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
, &i830_wm_info
,
3972 dev_priv
->display
.get_fifo_size(dev
, 0),
3973 crtc
->fb
->bits_per_pixel
/ 8,
3975 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
3976 fwater_lo
|= (3<<8) | planea_wm
;
3978 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
3980 I915_WRITE(FW_BLC
, fwater_lo
);
3983 #define ILK_LP0_PLANE_LATENCY 700
3984 #define ILK_LP0_CURSOR_LATENCY 1300
3986 static bool ironlake_compute_wm0(struct drm_device
*dev
,
3988 const struct intel_watermark_params
*display
,
3989 int display_latency_ns
,
3990 const struct intel_watermark_params
*cursor
,
3991 int cursor_latency_ns
,
3995 struct drm_crtc
*crtc
;
3996 int htotal
, hdisplay
, clock
, pixel_size
;
3997 int line_time_us
, line_count
;
3998 int entries
, tlb_miss
;
4000 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
4001 if (crtc
->fb
== NULL
|| !crtc
->enabled
)
4004 htotal
= crtc
->mode
.htotal
;
4005 hdisplay
= crtc
->mode
.hdisplay
;
4006 clock
= crtc
->mode
.clock
;
4007 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4009 /* Use the small buffer method to calculate plane watermark */
4010 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
4011 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
4013 entries
+= tlb_miss
;
4014 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
4015 *plane_wm
= entries
+ display
->guard_size
;
4016 if (*plane_wm
> (int)display
->max_wm
)
4017 *plane_wm
= display
->max_wm
;
4019 /* Use the large buffer method to calculate cursor watermark */
4020 line_time_us
= ((htotal
* 1000) / clock
);
4021 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
4022 entries
= line_count
* 64 * pixel_size
;
4023 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
4025 entries
+= tlb_miss
;
4026 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4027 *cursor_wm
= entries
+ cursor
->guard_size
;
4028 if (*cursor_wm
> (int)cursor
->max_wm
)
4029 *cursor_wm
= (int)cursor
->max_wm
;
4035 * Check the wm result.
4037 * If any calculated watermark values is larger than the maximum value that
4038 * can be programmed into the associated watermark register, that watermark
4041 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
4042 int fbc_wm
, int display_wm
, int cursor_wm
,
4043 const struct intel_watermark_params
*display
,
4044 const struct intel_watermark_params
*cursor
)
4046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4048 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4049 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
4051 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
4052 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4053 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
4055 /* fbc has it's own way to disable FBC WM */
4056 I915_WRITE(DISP_ARB_CTL
,
4057 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
4061 if (display_wm
> display
->max_wm
) {
4062 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4063 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
4067 if (cursor_wm
> cursor
->max_wm
) {
4068 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4069 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
4073 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
4074 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
4082 * Compute watermark values of WM[1-3],
4084 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
4086 const struct intel_watermark_params
*display
,
4087 const struct intel_watermark_params
*cursor
,
4088 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
4090 struct drm_crtc
*crtc
;
4091 unsigned long line_time_us
;
4092 int hdisplay
, htotal
, pixel_size
, clock
;
4093 int line_count
, line_size
;
4098 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
4102 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4103 hdisplay
= crtc
->mode
.hdisplay
;
4104 htotal
= crtc
->mode
.htotal
;
4105 clock
= crtc
->mode
.clock
;
4106 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4108 line_time_us
= (htotal
* 1000) / clock
;
4109 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
4110 line_size
= hdisplay
* pixel_size
;
4112 /* Use the minimum of the small and large buffer method for primary */
4113 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
4114 large
= line_count
* line_size
;
4116 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
4117 *display_wm
= entries
+ display
->guard_size
;
4121 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4123 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
4125 /* calculate the self-refresh watermark for display cursor */
4126 entries
= line_count
* pixel_size
* 64;
4127 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4128 *cursor_wm
= entries
+ cursor
->guard_size
;
4130 return ironlake_check_srwm(dev
, level
,
4131 *fbc_wm
, *display_wm
, *cursor_wm
,
4135 static void ironlake_update_wm(struct drm_device
*dev
)
4137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4138 int fbc_wm
, plane_wm
, cursor_wm
;
4139 unsigned int enabled
;
4142 if (ironlake_compute_wm0(dev
, 0,
4143 &ironlake_display_wm_info
,
4144 ILK_LP0_PLANE_LATENCY
,
4145 &ironlake_cursor_wm_info
,
4146 ILK_LP0_CURSOR_LATENCY
,
4147 &plane_wm
, &cursor_wm
)) {
4148 I915_WRITE(WM0_PIPEA_ILK
,
4149 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4150 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4151 " plane %d, " "cursor: %d\n",
4152 plane_wm
, cursor_wm
);
4156 if (ironlake_compute_wm0(dev
, 1,
4157 &ironlake_display_wm_info
,
4158 ILK_LP0_PLANE_LATENCY
,
4159 &ironlake_cursor_wm_info
,
4160 ILK_LP0_CURSOR_LATENCY
,
4161 &plane_wm
, &cursor_wm
)) {
4162 I915_WRITE(WM0_PIPEB_ILK
,
4163 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4164 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4165 " plane %d, cursor: %d\n",
4166 plane_wm
, cursor_wm
);
4171 * Calculate and update the self-refresh watermark only when one
4172 * display plane is used.
4174 I915_WRITE(WM3_LP_ILK
, 0);
4175 I915_WRITE(WM2_LP_ILK
, 0);
4176 I915_WRITE(WM1_LP_ILK
, 0);
4178 if (!single_plane_enabled(enabled
))
4180 enabled
= ffs(enabled
) - 1;
4183 if (!ironlake_compute_srwm(dev
, 1, enabled
,
4184 ILK_READ_WM1_LATENCY() * 500,
4185 &ironlake_display_srwm_info
,
4186 &ironlake_cursor_srwm_info
,
4187 &fbc_wm
, &plane_wm
, &cursor_wm
))
4190 I915_WRITE(WM1_LP_ILK
,
4192 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4193 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4194 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4198 if (!ironlake_compute_srwm(dev
, 2, enabled
,
4199 ILK_READ_WM2_LATENCY() * 500,
4200 &ironlake_display_srwm_info
,
4201 &ironlake_cursor_srwm_info
,
4202 &fbc_wm
, &plane_wm
, &cursor_wm
))
4205 I915_WRITE(WM2_LP_ILK
,
4207 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4208 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4209 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4213 * WM3 is unsupported on ILK, probably because we don't have latency
4214 * data for that power state
4218 static void sandybridge_update_wm(struct drm_device
*dev
)
4220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4221 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4222 int fbc_wm
, plane_wm
, cursor_wm
;
4223 unsigned int enabled
;
4226 if (ironlake_compute_wm0(dev
, 0,
4227 &sandybridge_display_wm_info
, latency
,
4228 &sandybridge_cursor_wm_info
, latency
,
4229 &plane_wm
, &cursor_wm
)) {
4230 I915_WRITE(WM0_PIPEA_ILK
,
4231 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4232 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4233 " plane %d, " "cursor: %d\n",
4234 plane_wm
, cursor_wm
);
4238 if (ironlake_compute_wm0(dev
, 1,
4239 &sandybridge_display_wm_info
, latency
,
4240 &sandybridge_cursor_wm_info
, latency
,
4241 &plane_wm
, &cursor_wm
)) {
4242 I915_WRITE(WM0_PIPEB_ILK
,
4243 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4244 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4245 " plane %d, cursor: %d\n",
4246 plane_wm
, cursor_wm
);
4251 * Calculate and update the self-refresh watermark only when one
4252 * display plane is used.
4254 * SNB support 3 levels of watermark.
4256 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4257 * and disabled in the descending order
4260 I915_WRITE(WM3_LP_ILK
, 0);
4261 I915_WRITE(WM2_LP_ILK
, 0);
4262 I915_WRITE(WM1_LP_ILK
, 0);
4264 if (!single_plane_enabled(enabled
))
4266 enabled
= ffs(enabled
) - 1;
4269 if (!ironlake_compute_srwm(dev
, 1, enabled
,
4270 SNB_READ_WM1_LATENCY() * 500,
4271 &sandybridge_display_srwm_info
,
4272 &sandybridge_cursor_srwm_info
,
4273 &fbc_wm
, &plane_wm
, &cursor_wm
))
4276 I915_WRITE(WM1_LP_ILK
,
4278 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4279 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4280 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4284 if (!ironlake_compute_srwm(dev
, 2, enabled
,
4285 SNB_READ_WM2_LATENCY() * 500,
4286 &sandybridge_display_srwm_info
,
4287 &sandybridge_cursor_srwm_info
,
4288 &fbc_wm
, &plane_wm
, &cursor_wm
))
4291 I915_WRITE(WM2_LP_ILK
,
4293 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4294 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4295 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4299 if (!ironlake_compute_srwm(dev
, 3, enabled
,
4300 SNB_READ_WM3_LATENCY() * 500,
4301 &sandybridge_display_srwm_info
,
4302 &sandybridge_cursor_srwm_info
,
4303 &fbc_wm
, &plane_wm
, &cursor_wm
))
4306 I915_WRITE(WM3_LP_ILK
,
4308 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4309 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4310 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4315 * intel_update_watermarks - update FIFO watermark values based on current modes
4317 * Calculate watermark values for the various WM regs based on current mode
4318 * and plane configuration.
4320 * There are several cases to deal with here:
4321 * - normal (i.e. non-self-refresh)
4322 * - self-refresh (SR) mode
4323 * - lines are large relative to FIFO size (buffer can hold up to 2)
4324 * - lines are small relative to FIFO size (buffer can hold more than 2
4325 * lines), so need to account for TLB latency
4327 * The normal calculation is:
4328 * watermark = dotclock * bytes per pixel * latency
4329 * where latency is platform & configuration dependent (we assume pessimal
4332 * The SR calculation is:
4333 * watermark = (trunc(latency/line time)+1) * surface width *
4336 * line time = htotal / dotclock
4337 * surface width = hdisplay for normal plane and 64 for cursor
4338 * and latency is assumed to be high, as above.
4340 * The final value programmed to the register should always be rounded up,
4341 * and include an extra 2 entries to account for clock crossings.
4343 * We don't use the sprite, so we can ignore that. And on Crestline we have
4344 * to set the non-SR watermarks to 8.
4346 static void intel_update_watermarks(struct drm_device
*dev
)
4348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4350 if (dev_priv
->display
.update_wm
)
4351 dev_priv
->display
.update_wm(dev
);
4354 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4356 return dev_priv
->lvds_use_ssc
&& i915_panel_use_ssc
;
4359 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4360 struct drm_display_mode
*mode
,
4361 struct drm_display_mode
*adjusted_mode
,
4363 struct drm_framebuffer
*old_fb
)
4365 struct drm_device
*dev
= crtc
->dev
;
4366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4368 int pipe
= intel_crtc
->pipe
;
4369 int plane
= intel_crtc
->plane
;
4370 int refclk
, num_connectors
= 0;
4371 intel_clock_t clock
, reduced_clock
;
4372 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
4373 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
4374 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
4375 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4376 struct intel_encoder
*encoder
;
4377 const intel_limit_t
*limit
;
4382 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4383 if (encoder
->base
.crtc
!= crtc
)
4386 switch (encoder
->type
) {
4387 case INTEL_OUTPUT_LVDS
:
4390 case INTEL_OUTPUT_SDVO
:
4391 case INTEL_OUTPUT_HDMI
:
4393 if (encoder
->needs_tv_clock
)
4396 case INTEL_OUTPUT_DVO
:
4399 case INTEL_OUTPUT_TVOUT
:
4402 case INTEL_OUTPUT_ANALOG
:
4405 case INTEL_OUTPUT_DISPLAYPORT
:
4413 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4414 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4415 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4417 } else if (!IS_GEN2(dev
)) {
4424 * Returns a set of divisors for the desired target clock with the given
4425 * refclk, or FALSE. The returned values represent the clock equation:
4426 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4428 limit
= intel_limit(crtc
, refclk
);
4429 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
4431 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4435 /* Ensure that the cursor is valid for the new mode before changing... */
4436 intel_crtc_update_cursor(crtc
, true);
4438 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4439 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4440 dev_priv
->lvds_downclock
,
4443 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
4445 * If the different P is found, it means that we can't
4446 * switch the display clock by using the FP0/FP1.
4447 * In such case we will disable the LVDS downclock
4450 DRM_DEBUG_KMS("Different P is found for "
4451 "LVDS clock/downclock\n");
4452 has_reduced_clock
= 0;
4455 /* SDVO TV has fixed PLL values depend on its clock range,
4456 this mirrors vbios setting. */
4457 if (is_sdvo
&& is_tv
) {
4458 if (adjusted_mode
->clock
>= 100000
4459 && adjusted_mode
->clock
< 140500) {
4465 } else if (adjusted_mode
->clock
>= 140500
4466 && adjusted_mode
->clock
<= 200000) {
4475 if (IS_PINEVIEW(dev
)) {
4476 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
4477 if (has_reduced_clock
)
4478 fp2
= (1 << reduced_clock
.n
) << 16 |
4479 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
4481 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
4482 if (has_reduced_clock
)
4483 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
4487 dpll
= DPLL_VGA_MODE_DIS
;
4489 if (!IS_GEN2(dev
)) {
4491 dpll
|= DPLLB_MODE_LVDS
;
4493 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4495 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4496 if (pixel_multiplier
> 1) {
4497 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4498 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4500 dpll
|= DPLL_DVO_HIGH_SPEED
;
4503 dpll
|= DPLL_DVO_HIGH_SPEED
;
4505 /* compute bitmask from p1 value */
4506 if (IS_PINEVIEW(dev
))
4507 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4509 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4510 if (IS_G4X(dev
) && has_reduced_clock
)
4511 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4515 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4518 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4521 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4524 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4527 if (INTEL_INFO(dev
)->gen
>= 4)
4528 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4531 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4534 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4536 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4538 dpll
|= PLL_P2_DIVIDE_BY_4
;
4542 if (is_sdvo
&& is_tv
)
4543 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4545 /* XXX: just matching BIOS for now */
4546 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4548 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4549 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4551 dpll
|= PLL_REF_INPUT_DREFCLK
;
4553 /* setup pipeconf */
4554 pipeconf
= I915_READ(PIPECONF(pipe
));
4556 /* Set up the display plane register */
4557 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4559 /* Ironlake's plane is forced to pipe, bit 24 is to
4560 enable color space conversion */
4562 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4564 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4566 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4567 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4570 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4574 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4575 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4577 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4580 dpll
|= DPLL_VCO_ENABLE
;
4582 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4583 drm_mode_debug_printmodeline(mode
);
4585 I915_WRITE(FP0(pipe
), fp
);
4586 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4588 POSTING_READ(DPLL(pipe
));
4591 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4592 * This is an exception to the general rule that mode_set doesn't turn
4596 temp
= I915_READ(LVDS
);
4597 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4599 temp
|= LVDS_PIPEB_SELECT
;
4601 temp
&= ~LVDS_PIPEB_SELECT
;
4603 /* set the corresponsding LVDS_BORDER bit */
4604 temp
|= dev_priv
->lvds_border_bits
;
4605 /* Set the B0-B3 data pairs corresponding to whether we're going to
4606 * set the DPLLs for dual-channel mode or not.
4609 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4611 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4613 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4614 * appropriately here, but we need to look more thoroughly into how
4615 * panels behave in the two modes.
4617 /* set the dithering flag on LVDS as needed */
4618 if (INTEL_INFO(dev
)->gen
>= 4) {
4619 if (dev_priv
->lvds_dither
)
4620 temp
|= LVDS_ENABLE_DITHER
;
4622 temp
&= ~LVDS_ENABLE_DITHER
;
4624 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4625 lvds_sync
|= LVDS_HSYNC_POLARITY
;
4626 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4627 lvds_sync
|= LVDS_VSYNC_POLARITY
;
4628 if ((temp
& (LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
))
4630 char flags
[2] = "-+";
4631 DRM_INFO("Changing LVDS panel from "
4632 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4633 flags
[!(temp
& LVDS_HSYNC_POLARITY
)],
4634 flags
[!(temp
& LVDS_VSYNC_POLARITY
)],
4635 flags
[!(lvds_sync
& LVDS_HSYNC_POLARITY
)],
4636 flags
[!(lvds_sync
& LVDS_VSYNC_POLARITY
)]);
4637 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4640 I915_WRITE(LVDS
, temp
);
4644 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4647 I915_WRITE(DPLL(pipe
), dpll
);
4649 /* Wait for the clocks to stabilize. */
4650 POSTING_READ(DPLL(pipe
));
4653 if (INTEL_INFO(dev
)->gen
>= 4) {
4656 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4658 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4662 I915_WRITE(DPLL_MD(pipe
), temp
);
4664 /* The pixel multiplier can only be updated once the
4665 * DPLL is enabled and the clocks are stable.
4667 * So write it again.
4669 I915_WRITE(DPLL(pipe
), dpll
);
4672 intel_crtc
->lowfreq_avail
= false;
4673 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4674 I915_WRITE(FP1(pipe
), fp2
);
4675 intel_crtc
->lowfreq_avail
= true;
4676 if (HAS_PIPE_CXSR(dev
)) {
4677 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4678 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4681 I915_WRITE(FP1(pipe
), fp
);
4682 if (HAS_PIPE_CXSR(dev
)) {
4683 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4684 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4688 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4689 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4690 /* the chip adds 2 halflines automatically */
4691 adjusted_mode
->crtc_vdisplay
-= 1;
4692 adjusted_mode
->crtc_vtotal
-= 1;
4693 adjusted_mode
->crtc_vblank_start
-= 1;
4694 adjusted_mode
->crtc_vblank_end
-= 1;
4695 adjusted_mode
->crtc_vsync_end
-= 1;
4696 adjusted_mode
->crtc_vsync_start
-= 1;
4698 pipeconf
&= ~PIPECONF_INTERLACE_W_FIELD_INDICATION
; /* progressive */
4700 I915_WRITE(HTOTAL(pipe
),
4701 (adjusted_mode
->crtc_hdisplay
- 1) |
4702 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4703 I915_WRITE(HBLANK(pipe
),
4704 (adjusted_mode
->crtc_hblank_start
- 1) |
4705 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4706 I915_WRITE(HSYNC(pipe
),
4707 (adjusted_mode
->crtc_hsync_start
- 1) |
4708 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4710 I915_WRITE(VTOTAL(pipe
),
4711 (adjusted_mode
->crtc_vdisplay
- 1) |
4712 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4713 I915_WRITE(VBLANK(pipe
),
4714 (adjusted_mode
->crtc_vblank_start
- 1) |
4715 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4716 I915_WRITE(VSYNC(pipe
),
4717 (adjusted_mode
->crtc_vsync_start
- 1) |
4718 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4720 /* pipesrc and dspsize control the size that is scaled from,
4721 * which should always be the user's requested size.
4723 I915_WRITE(DSPSIZE(plane
),
4724 ((mode
->vdisplay
- 1) << 16) |
4725 (mode
->hdisplay
- 1));
4726 I915_WRITE(DSPPOS(plane
), 0);
4727 I915_WRITE(PIPESRC(pipe
),
4728 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4730 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4731 POSTING_READ(PIPECONF(pipe
));
4732 intel_enable_pipe(dev_priv
, pipe
, false);
4734 intel_wait_for_vblank(dev
, pipe
);
4736 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4737 POSTING_READ(DSPCNTR(plane
));
4739 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4741 intel_update_watermarks(dev
);
4746 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
4747 struct drm_display_mode
*mode
,
4748 struct drm_display_mode
*adjusted_mode
,
4750 struct drm_framebuffer
*old_fb
)
4752 struct drm_device
*dev
= crtc
->dev
;
4753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4754 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4755 int pipe
= intel_crtc
->pipe
;
4756 int plane
= intel_crtc
->plane
;
4757 int refclk
, num_connectors
= 0;
4758 intel_clock_t clock
, reduced_clock
;
4759 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
4760 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4761 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
4762 struct intel_encoder
*has_edp_encoder
= NULL
;
4763 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4764 struct intel_encoder
*encoder
;
4765 const intel_limit_t
*limit
;
4767 struct fdi_m_n m_n
= {0};
4770 int target_clock
, pixel_multiplier
, lane
, link_bw
, bpp
, factor
;
4772 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4773 if (encoder
->base
.crtc
!= crtc
)
4776 switch (encoder
->type
) {
4777 case INTEL_OUTPUT_LVDS
:
4780 case INTEL_OUTPUT_SDVO
:
4781 case INTEL_OUTPUT_HDMI
:
4783 if (encoder
->needs_tv_clock
)
4786 case INTEL_OUTPUT_TVOUT
:
4789 case INTEL_OUTPUT_ANALOG
:
4792 case INTEL_OUTPUT_DISPLAYPORT
:
4795 case INTEL_OUTPUT_EDP
:
4796 has_edp_encoder
= encoder
;
4803 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4804 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4805 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4809 if (!has_edp_encoder
||
4810 intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
4811 refclk
= 120000; /* 120Mhz refclk */
4815 * Returns a set of divisors for the desired target clock with the given
4816 * refclk, or FALSE. The returned values represent the clock equation:
4817 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4819 limit
= intel_limit(crtc
, refclk
);
4820 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
4822 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4826 /* Ensure that the cursor is valid for the new mode before changing... */
4827 intel_crtc_update_cursor(crtc
, true);
4829 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4830 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4831 dev_priv
->lvds_downclock
,
4834 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
4836 * If the different P is found, it means that we can't
4837 * switch the display clock by using the FP0/FP1.
4838 * In such case we will disable the LVDS downclock
4841 DRM_DEBUG_KMS("Different P is found for "
4842 "LVDS clock/downclock\n");
4843 has_reduced_clock
= 0;
4846 /* SDVO TV has fixed PLL values depend on its clock range,
4847 this mirrors vbios setting. */
4848 if (is_sdvo
&& is_tv
) {
4849 if (adjusted_mode
->clock
>= 100000
4850 && adjusted_mode
->clock
< 140500) {
4856 } else if (adjusted_mode
->clock
>= 140500
4857 && adjusted_mode
->clock
<= 200000) {
4867 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4869 /* CPU eDP doesn't require FDI link, so just set DP M/N
4870 according to current link config */
4871 if (has_edp_encoder
&&
4872 !intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4873 target_clock
= mode
->clock
;
4874 intel_edp_link_config(has_edp_encoder
,
4877 /* [e]DP over FDI requires target mode clock
4878 instead of link clock */
4879 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
4880 target_clock
= mode
->clock
;
4882 target_clock
= adjusted_mode
->clock
;
4884 /* FDI is a binary signal running at ~2.7GHz, encoding
4885 * each output octet as 10 bits. The actual frequency
4886 * is stored as a divider into a 100MHz clock, and the
4887 * mode pixel clock is stored in units of 1KHz.
4888 * Hence the bw of each lane in terms of the mode signal
4891 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4894 /* determine panel color depth */
4895 temp
= I915_READ(PIPECONF(pipe
));
4896 temp
&= ~PIPE_BPC_MASK
;
4898 /* the BPC will be 6 if it is 18-bit LVDS panel */
4899 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
4903 } else if (has_edp_encoder
) {
4904 switch (dev_priv
->edp
.bpp
/3) {
4920 I915_WRITE(PIPECONF(pipe
), temp
);
4922 switch (temp
& PIPE_BPC_MASK
) {
4936 DRM_ERROR("unknown pipe bpc value\n");
4942 * Account for spread spectrum to avoid
4943 * oversubscribing the link. Max center spread
4944 * is 2.5%; use 5% for safety's sake.
4946 u32 bps
= target_clock
* bpp
* 21 / 20;
4947 lane
= bps
/ (link_bw
* 8) + 1;
4950 intel_crtc
->fdi_lanes
= lane
;
4952 if (pixel_multiplier
> 1)
4953 link_bw
*= pixel_multiplier
;
4954 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
4956 /* Ironlake: try to setup display ref clock before DPLL
4957 * enabling. This is only under driver's control after
4958 * PCH B stepping, previous chipset stepping should be
4959 * ignoring this setting.
4961 temp
= I915_READ(PCH_DREF_CONTROL
);
4962 /* Always enable nonspread source */
4963 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4964 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4965 temp
&= ~DREF_SSC_SOURCE_MASK
;
4966 temp
|= DREF_SSC_SOURCE_ENABLE
;
4967 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4969 POSTING_READ(PCH_DREF_CONTROL
);
4972 if (has_edp_encoder
) {
4973 if (intel_panel_use_ssc(dev_priv
)) {
4974 temp
|= DREF_SSC1_ENABLE
;
4975 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4977 POSTING_READ(PCH_DREF_CONTROL
);
4980 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4982 /* Enable CPU source on CPU attached eDP */
4983 if (!intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
4984 if (intel_panel_use_ssc(dev_priv
))
4985 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4987 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4989 /* Enable SSC on PCH eDP if needed */
4990 if (intel_panel_use_ssc(dev_priv
)) {
4991 DRM_ERROR("enabling SSC on PCH\n");
4992 temp
|= DREF_SUPERSPREAD_SOURCE_ENABLE
;
4995 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4996 POSTING_READ(PCH_DREF_CONTROL
);
5000 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5001 if (has_reduced_clock
)
5002 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5005 /* Enable autotuning of the PLL clock (if permissible) */
5008 if ((intel_panel_use_ssc(dev_priv
) &&
5009 dev_priv
->lvds_ssc_freq
== 100) ||
5010 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
5012 } else if (is_sdvo
&& is_tv
)
5015 if (clock
.m1
< factor
* clock
.n
)
5021 dpll
|= DPLLB_MODE_LVDS
;
5023 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5025 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5026 if (pixel_multiplier
> 1) {
5027 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5029 dpll
|= DPLL_DVO_HIGH_SPEED
;
5031 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
5032 dpll
|= DPLL_DVO_HIGH_SPEED
;
5034 /* compute bitmask from p1 value */
5035 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5037 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5041 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5044 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5047 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5050 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5054 if (is_sdvo
&& is_tv
)
5055 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5057 /* XXX: just matching BIOS for now */
5058 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5060 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5061 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5063 dpll
|= PLL_REF_INPUT_DREFCLK
;
5065 /* setup pipeconf */
5066 pipeconf
= I915_READ(PIPECONF(pipe
));
5068 /* Set up the display plane register */
5069 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5071 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
5072 drm_mode_debug_printmodeline(mode
);
5074 /* PCH eDP needs FDI, but CPU eDP does not */
5075 if (!has_edp_encoder
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
5076 I915_WRITE(PCH_FP0(pipe
), fp
);
5077 I915_WRITE(PCH_DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
5079 POSTING_READ(PCH_DPLL(pipe
));
5083 /* enable transcoder DPLL */
5084 if (HAS_PCH_CPT(dev
)) {
5085 temp
= I915_READ(PCH_DPLL_SEL
);
5088 temp
|= TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
;
5091 temp
|= TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
;
5094 /* FIXME: manage transcoder PLLs? */
5095 temp
|= TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
;
5100 I915_WRITE(PCH_DPLL_SEL
, temp
);
5102 POSTING_READ(PCH_DPLL_SEL
);
5106 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5107 * This is an exception to the general rule that mode_set doesn't turn
5111 temp
= I915_READ(PCH_LVDS
);
5112 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5114 if (HAS_PCH_CPT(dev
))
5115 temp
|= PORT_TRANS_B_SEL_CPT
;
5117 temp
|= LVDS_PIPEB_SELECT
;
5119 if (HAS_PCH_CPT(dev
))
5120 temp
&= ~PORT_TRANS_SEL_MASK
;
5122 temp
&= ~LVDS_PIPEB_SELECT
;
5124 /* set the corresponsding LVDS_BORDER bit */
5125 temp
|= dev_priv
->lvds_border_bits
;
5126 /* Set the B0-B3 data pairs corresponding to whether we're going to
5127 * set the DPLLs for dual-channel mode or not.
5130 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5132 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
5134 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5135 * appropriately here, but we need to look more thoroughly into how
5136 * panels behave in the two modes.
5138 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5139 lvds_sync
|= LVDS_HSYNC_POLARITY
;
5140 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5141 lvds_sync
|= LVDS_VSYNC_POLARITY
;
5142 if ((temp
& (LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
))
5144 char flags
[2] = "-+";
5145 DRM_INFO("Changing LVDS panel from "
5146 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5147 flags
[!(temp
& LVDS_HSYNC_POLARITY
)],
5148 flags
[!(temp
& LVDS_VSYNC_POLARITY
)],
5149 flags
[!(lvds_sync
& LVDS_HSYNC_POLARITY
)],
5150 flags
[!(lvds_sync
& LVDS_VSYNC_POLARITY
)]);
5151 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5154 I915_WRITE(PCH_LVDS
, temp
);
5157 /* set the dithering flag and clear for anything other than a panel. */
5158 pipeconf
&= ~PIPECONF_DITHER_EN
;
5159 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
5160 if (dev_priv
->lvds_dither
&& (is_lvds
|| has_edp_encoder
)) {
5161 pipeconf
|= PIPECONF_DITHER_EN
;
5162 pipeconf
|= PIPECONF_DITHER_TYPE_ST1
;
5165 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
5166 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5168 /* For non-DP output, clear any trans DP clock recovery setting.*/
5169 I915_WRITE(TRANSDATA_M1(pipe
), 0);
5170 I915_WRITE(TRANSDATA_N1(pipe
), 0);
5171 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
5172 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
5175 if (!has_edp_encoder
||
5176 intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
5177 I915_WRITE(PCH_DPLL(pipe
), dpll
);
5179 /* Wait for the clocks to stabilize. */
5180 POSTING_READ(PCH_DPLL(pipe
));
5183 /* The pixel multiplier can only be updated once the
5184 * DPLL is enabled and the clocks are stable.
5186 * So write it again.
5188 I915_WRITE(PCH_DPLL(pipe
), dpll
);
5191 intel_crtc
->lowfreq_avail
= false;
5192 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5193 I915_WRITE(PCH_FP1(pipe
), fp2
);
5194 intel_crtc
->lowfreq_avail
= true;
5195 if (HAS_PIPE_CXSR(dev
)) {
5196 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5197 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5200 I915_WRITE(PCH_FP1(pipe
), fp
);
5201 if (HAS_PIPE_CXSR(dev
)) {
5202 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5203 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
5207 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5208 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5209 /* the chip adds 2 halflines automatically */
5210 adjusted_mode
->crtc_vdisplay
-= 1;
5211 adjusted_mode
->crtc_vtotal
-= 1;
5212 adjusted_mode
->crtc_vblank_start
-= 1;
5213 adjusted_mode
->crtc_vblank_end
-= 1;
5214 adjusted_mode
->crtc_vsync_end
-= 1;
5215 adjusted_mode
->crtc_vsync_start
-= 1;
5217 pipeconf
&= ~PIPECONF_INTERLACE_W_FIELD_INDICATION
; /* progressive */
5219 I915_WRITE(HTOTAL(pipe
),
5220 (adjusted_mode
->crtc_hdisplay
- 1) |
5221 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5222 I915_WRITE(HBLANK(pipe
),
5223 (adjusted_mode
->crtc_hblank_start
- 1) |
5224 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5225 I915_WRITE(HSYNC(pipe
),
5226 (adjusted_mode
->crtc_hsync_start
- 1) |
5227 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5229 I915_WRITE(VTOTAL(pipe
),
5230 (adjusted_mode
->crtc_vdisplay
- 1) |
5231 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
5232 I915_WRITE(VBLANK(pipe
),
5233 (adjusted_mode
->crtc_vblank_start
- 1) |
5234 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
5235 I915_WRITE(VSYNC(pipe
),
5236 (adjusted_mode
->crtc_vsync_start
- 1) |
5237 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5239 /* pipesrc controls the size that is scaled from, which should
5240 * always be the user's requested size.
5242 I915_WRITE(PIPESRC(pipe
),
5243 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
5245 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
5246 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
5247 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
5248 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
5250 if (has_edp_encoder
&&
5251 !intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
5252 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
5255 I915_WRITE(PIPECONF(pipe
), pipeconf
);
5256 POSTING_READ(PIPECONF(pipe
));
5258 intel_wait_for_vblank(dev
, pipe
);
5261 /* enable address swizzle for tiling buffer */
5262 temp
= I915_READ(DISP_ARB_CTL
);
5263 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
5266 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5267 POSTING_READ(DSPCNTR(plane
));
5269 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
5271 intel_update_watermarks(dev
);
5276 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5277 struct drm_display_mode
*mode
,
5278 struct drm_display_mode
*adjusted_mode
,
5280 struct drm_framebuffer
*old_fb
)
5282 struct drm_device
*dev
= crtc
->dev
;
5283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5284 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5285 int pipe
= intel_crtc
->pipe
;
5288 drm_vblank_pre_modeset(dev
, pipe
);
5290 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
5293 drm_vblank_post_modeset(dev
, pipe
);
5298 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5299 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
5301 struct drm_device
*dev
= crtc
->dev
;
5302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5303 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5304 int palreg
= PALETTE(intel_crtc
->pipe
);
5307 /* The clocks have to be on to load the palette. */
5311 /* use legacy palette for Ironlake */
5312 if (HAS_PCH_SPLIT(dev
))
5313 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
5315 for (i
= 0; i
< 256; i
++) {
5316 I915_WRITE(palreg
+ 4 * i
,
5317 (intel_crtc
->lut_r
[i
] << 16) |
5318 (intel_crtc
->lut_g
[i
] << 8) |
5319 intel_crtc
->lut_b
[i
]);
5323 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5325 struct drm_device
*dev
= crtc
->dev
;
5326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5327 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5328 bool visible
= base
!= 0;
5331 if (intel_crtc
->cursor_visible
== visible
)
5334 cntl
= I915_READ(_CURACNTR
);
5336 /* On these chipsets we can only modify the base whilst
5337 * the cursor is disabled.
5339 I915_WRITE(_CURABASE
, base
);
5341 cntl
&= ~(CURSOR_FORMAT_MASK
);
5342 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5343 cntl
|= CURSOR_ENABLE
|
5344 CURSOR_GAMMA_ENABLE
|
5347 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
5348 I915_WRITE(_CURACNTR
, cntl
);
5350 intel_crtc
->cursor_visible
= visible
;
5353 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5355 struct drm_device
*dev
= crtc
->dev
;
5356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5357 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5358 int pipe
= intel_crtc
->pipe
;
5359 bool visible
= base
!= 0;
5361 if (intel_crtc
->cursor_visible
!= visible
) {
5362 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
5364 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
5365 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5366 cntl
|= pipe
<< 28; /* Connect to correct pipe */
5368 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5369 cntl
|= CURSOR_MODE_DISABLE
;
5371 I915_WRITE(CURCNTR(pipe
), cntl
);
5373 intel_crtc
->cursor_visible
= visible
;
5375 /* and commit changes on next vblank */
5376 I915_WRITE(CURBASE(pipe
), base
);
5379 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5380 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
5383 struct drm_device
*dev
= crtc
->dev
;
5384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5385 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5386 int pipe
= intel_crtc
->pipe
;
5387 int x
= intel_crtc
->cursor_x
;
5388 int y
= intel_crtc
->cursor_y
;
5394 if (on
&& crtc
->enabled
&& crtc
->fb
) {
5395 base
= intel_crtc
->cursor_addr
;
5396 if (x
> (int) crtc
->fb
->width
)
5399 if (y
> (int) crtc
->fb
->height
)
5405 if (x
+ intel_crtc
->cursor_width
< 0)
5408 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
5411 pos
|= x
<< CURSOR_X_SHIFT
;
5414 if (y
+ intel_crtc
->cursor_height
< 0)
5417 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
5420 pos
|= y
<< CURSOR_Y_SHIFT
;
5422 visible
= base
!= 0;
5423 if (!visible
&& !intel_crtc
->cursor_visible
)
5426 I915_WRITE(CURPOS(pipe
), pos
);
5427 if (IS_845G(dev
) || IS_I865G(dev
))
5428 i845_update_cursor(crtc
, base
);
5430 i9xx_update_cursor(crtc
, base
);
5433 intel_mark_busy(dev
, to_intel_framebuffer(crtc
->fb
)->obj
);
5436 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
5437 struct drm_file
*file
,
5439 uint32_t width
, uint32_t height
)
5441 struct drm_device
*dev
= crtc
->dev
;
5442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5443 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5444 struct drm_i915_gem_object
*obj
;
5448 DRM_DEBUG_KMS("\n");
5450 /* if we want to turn off the cursor ignore width and height */
5452 DRM_DEBUG_KMS("cursor off\n");
5455 mutex_lock(&dev
->struct_mutex
);
5459 /* Currently we only support 64x64 cursors */
5460 if (width
!= 64 || height
!= 64) {
5461 DRM_ERROR("we currently only support 64x64 cursors\n");
5465 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
5466 if (&obj
->base
== NULL
)
5469 if (obj
->base
.size
< width
* height
* 4) {
5470 DRM_ERROR("buffer is to small\n");
5475 /* we only need to pin inside GTT if cursor is non-phy */
5476 mutex_lock(&dev
->struct_mutex
);
5477 if (!dev_priv
->info
->cursor_needs_physical
) {
5478 if (obj
->tiling_mode
) {
5479 DRM_ERROR("cursor cannot be tiled\n");
5484 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true);
5486 DRM_ERROR("failed to pin cursor bo\n");
5490 ret
= i915_gem_object_set_to_gtt_domain(obj
, 0);
5492 DRM_ERROR("failed to move cursor bo into the GTT\n");
5496 ret
= i915_gem_object_put_fence(obj
);
5498 DRM_ERROR("failed to move cursor bo into the GTT\n");
5502 addr
= obj
->gtt_offset
;
5504 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
5505 ret
= i915_gem_attach_phys_object(dev
, obj
,
5506 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
5509 DRM_ERROR("failed to attach phys object\n");
5512 addr
= obj
->phys_obj
->handle
->busaddr
;
5516 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
5519 if (intel_crtc
->cursor_bo
) {
5520 if (dev_priv
->info
->cursor_needs_physical
) {
5521 if (intel_crtc
->cursor_bo
!= obj
)
5522 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
5524 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
5525 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
5528 mutex_unlock(&dev
->struct_mutex
);
5530 intel_crtc
->cursor_addr
= addr
;
5531 intel_crtc
->cursor_bo
= obj
;
5532 intel_crtc
->cursor_width
= width
;
5533 intel_crtc
->cursor_height
= height
;
5535 intel_crtc_update_cursor(crtc
, true);
5539 i915_gem_object_unpin(obj
);
5541 mutex_unlock(&dev
->struct_mutex
);
5543 drm_gem_object_unreference_unlocked(&obj
->base
);
5547 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
5549 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5551 intel_crtc
->cursor_x
= x
;
5552 intel_crtc
->cursor_y
= y
;
5554 intel_crtc_update_cursor(crtc
, true);
5559 /** Sets the color ramps on behalf of RandR */
5560 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
5561 u16 blue
, int regno
)
5563 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5565 intel_crtc
->lut_r
[regno
] = red
>> 8;
5566 intel_crtc
->lut_g
[regno
] = green
>> 8;
5567 intel_crtc
->lut_b
[regno
] = blue
>> 8;
5570 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5571 u16
*blue
, int regno
)
5573 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5575 *red
= intel_crtc
->lut_r
[regno
] << 8;
5576 *green
= intel_crtc
->lut_g
[regno
] << 8;
5577 *blue
= intel_crtc
->lut_b
[regno
] << 8;
5580 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5581 u16
*blue
, uint32_t start
, uint32_t size
)
5583 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
5584 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5586 for (i
= start
; i
< end
; i
++) {
5587 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
5588 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
5589 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
5592 intel_crtc_load_lut(crtc
);
5596 * Get a pipe with a simple mode set on it for doing load-based monitor
5599 * It will be up to the load-detect code to adjust the pipe as appropriate for
5600 * its requirements. The pipe will be connected to no other encoders.
5602 * Currently this code will only succeed if there is a pipe with no encoders
5603 * configured for it. In the future, it could choose to temporarily disable
5604 * some outputs to free up a pipe for its use.
5606 * \return crtc, or NULL if no pipes are available.
5609 /* VESA 640x480x72Hz mode to set on the pipe */
5610 static struct drm_display_mode load_detect_mode
= {
5611 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
5612 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
5615 static struct drm_framebuffer
*
5616 intel_framebuffer_create(struct drm_device
*dev
,
5617 struct drm_mode_fb_cmd
*mode_cmd
,
5618 struct drm_i915_gem_object
*obj
)
5620 struct intel_framebuffer
*intel_fb
;
5623 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5625 drm_gem_object_unreference_unlocked(&obj
->base
);
5626 return ERR_PTR(-ENOMEM
);
5629 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
5631 drm_gem_object_unreference_unlocked(&obj
->base
);
5633 return ERR_PTR(ret
);
5636 return &intel_fb
->base
;
5640 intel_framebuffer_pitch_for_width(int width
, int bpp
)
5642 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
5643 return ALIGN(pitch
, 64);
5647 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
5649 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
5650 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
5653 static struct drm_framebuffer
*
5654 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
5655 struct drm_display_mode
*mode
,
5658 struct drm_i915_gem_object
*obj
;
5659 struct drm_mode_fb_cmd mode_cmd
;
5661 obj
= i915_gem_alloc_object(dev
,
5662 intel_framebuffer_size_for_mode(mode
, bpp
));
5664 return ERR_PTR(-ENOMEM
);
5666 mode_cmd
.width
= mode
->hdisplay
;
5667 mode_cmd
.height
= mode
->vdisplay
;
5668 mode_cmd
.depth
= depth
;
5670 mode_cmd
.pitch
= intel_framebuffer_pitch_for_width(mode_cmd
.width
, bpp
);
5672 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
5675 static struct drm_framebuffer
*
5676 mode_fits_in_fbdev(struct drm_device
*dev
,
5677 struct drm_display_mode
*mode
)
5679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5680 struct drm_i915_gem_object
*obj
;
5681 struct drm_framebuffer
*fb
;
5683 if (dev_priv
->fbdev
== NULL
)
5686 obj
= dev_priv
->fbdev
->ifb
.obj
;
5690 fb
= &dev_priv
->fbdev
->ifb
.base
;
5691 if (fb
->pitch
< intel_framebuffer_pitch_for_width(mode
->hdisplay
,
5692 fb
->bits_per_pixel
))
5695 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitch
)
5701 bool intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5702 struct drm_connector
*connector
,
5703 struct drm_display_mode
*mode
,
5704 struct intel_load_detect_pipe
*old
)
5706 struct intel_crtc
*intel_crtc
;
5707 struct drm_crtc
*possible_crtc
;
5708 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5709 struct drm_crtc
*crtc
= NULL
;
5710 struct drm_device
*dev
= encoder
->dev
;
5711 struct drm_framebuffer
*old_fb
;
5714 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5715 connector
->base
.id
, drm_get_connector_name(connector
),
5716 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5719 * Algorithm gets a little messy:
5721 * - if the connector already has an assigned crtc, use it (but make
5722 * sure it's on first)
5724 * - try to find the first unused crtc that can drive this connector,
5725 * and use that if we find one
5728 /* See if we already have a CRTC for this connector */
5729 if (encoder
->crtc
) {
5730 crtc
= encoder
->crtc
;
5732 intel_crtc
= to_intel_crtc(crtc
);
5733 old
->dpms_mode
= intel_crtc
->dpms_mode
;
5734 old
->load_detect_temp
= false;
5736 /* Make sure the crtc and connector are running */
5737 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5738 struct drm_encoder_helper_funcs
*encoder_funcs
;
5739 struct drm_crtc_helper_funcs
*crtc_funcs
;
5741 crtc_funcs
= crtc
->helper_private
;
5742 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
5744 encoder_funcs
= encoder
->helper_private
;
5745 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
5751 /* Find an unused one (if possible) */
5752 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
5754 if (!(encoder
->possible_crtcs
& (1 << i
)))
5756 if (!possible_crtc
->enabled
) {
5757 crtc
= possible_crtc
;
5763 * If we didn't find an unused CRTC, don't use any.
5766 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5770 encoder
->crtc
= crtc
;
5771 connector
->encoder
= encoder
;
5773 intel_crtc
= to_intel_crtc(crtc
);
5774 old
->dpms_mode
= intel_crtc
->dpms_mode
;
5775 old
->load_detect_temp
= true;
5776 old
->release_fb
= NULL
;
5779 mode
= &load_detect_mode
;
5783 /* We need a framebuffer large enough to accommodate all accesses
5784 * that the plane may generate whilst we perform load detection.
5785 * We can not rely on the fbcon either being present (we get called
5786 * during its initialisation to detect all boot displays, or it may
5787 * not even exist) or that it is large enough to satisfy the
5790 crtc
->fb
= mode_fits_in_fbdev(dev
, mode
);
5791 if (crtc
->fb
== NULL
) {
5792 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5793 crtc
->fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
5794 old
->release_fb
= crtc
->fb
;
5796 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5797 if (IS_ERR(crtc
->fb
)) {
5798 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5803 if (!drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, old_fb
)) {
5804 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5805 if (old
->release_fb
)
5806 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5811 /* let the connector get through one full cycle before testing */
5812 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
5817 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5818 struct drm_connector
*connector
,
5819 struct intel_load_detect_pipe
*old
)
5821 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5822 struct drm_device
*dev
= encoder
->dev
;
5823 struct drm_crtc
*crtc
= encoder
->crtc
;
5824 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
5825 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
5827 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5828 connector
->base
.id
, drm_get_connector_name(connector
),
5829 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5831 if (old
->load_detect_temp
) {
5832 connector
->encoder
= NULL
;
5833 drm_helper_disable_unused_functions(dev
);
5835 if (old
->release_fb
)
5836 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5841 /* Switch crtc and encoder back off if necessary */
5842 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5843 encoder_funcs
->dpms(encoder
, old
->dpms_mode
);
5844 crtc_funcs
->dpms(crtc
, old
->dpms_mode
);
5848 /* Returns the clock of the currently programmed mode of the given pipe. */
5849 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
5851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5852 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5853 int pipe
= intel_crtc
->pipe
;
5854 u32 dpll
= I915_READ(DPLL(pipe
));
5856 intel_clock_t clock
;
5858 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
5859 fp
= I915_READ(FP0(pipe
));
5861 fp
= I915_READ(FP1(pipe
));
5863 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
5864 if (IS_PINEVIEW(dev
)) {
5865 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
5866 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5868 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
5869 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5872 if (!IS_GEN2(dev
)) {
5873 if (IS_PINEVIEW(dev
))
5874 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
5875 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
5877 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
5878 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5880 switch (dpll
& DPLL_MODE_MASK
) {
5881 case DPLLB_MODE_DAC_SERIAL
:
5882 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
5885 case DPLLB_MODE_LVDS
:
5886 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
5890 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5891 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
5895 /* XXX: Handle the 100Mhz refclk */
5896 intel_clock(dev
, 96000, &clock
);
5898 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
5901 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
5902 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5905 if ((dpll
& PLL_REF_INPUT_MASK
) ==
5906 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
5907 /* XXX: might not be 66MHz */
5908 intel_clock(dev
, 66000, &clock
);
5910 intel_clock(dev
, 48000, &clock
);
5912 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
5915 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
5916 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
5918 if (dpll
& PLL_P2_DIVIDE_BY_4
)
5923 intel_clock(dev
, 48000, &clock
);
5927 /* XXX: It would be nice to validate the clocks, but we can't reuse
5928 * i830PllIsValid() because it relies on the xf86_config connector
5929 * configuration being accurate, which it isn't necessarily.
5935 /** Returns the currently programmed mode of the given pipe. */
5936 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
5937 struct drm_crtc
*crtc
)
5939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5940 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5941 int pipe
= intel_crtc
->pipe
;
5942 struct drm_display_mode
*mode
;
5943 int htot
= I915_READ(HTOTAL(pipe
));
5944 int hsync
= I915_READ(HSYNC(pipe
));
5945 int vtot
= I915_READ(VTOTAL(pipe
));
5946 int vsync
= I915_READ(VSYNC(pipe
));
5948 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
5952 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
5953 mode
->hdisplay
= (htot
& 0xffff) + 1;
5954 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
5955 mode
->hsync_start
= (hsync
& 0xffff) + 1;
5956 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
5957 mode
->vdisplay
= (vtot
& 0xffff) + 1;
5958 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
5959 mode
->vsync_start
= (vsync
& 0xffff) + 1;
5960 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
5962 drm_mode_set_name(mode
);
5963 drm_mode_set_crtcinfo(mode
, 0);
5968 #define GPU_IDLE_TIMEOUT 500 /* ms */
5970 /* When this timer fires, we've been idle for awhile */
5971 static void intel_gpu_idle_timer(unsigned long arg
)
5973 struct drm_device
*dev
= (struct drm_device
*)arg
;
5974 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5976 if (!list_empty(&dev_priv
->mm
.active_list
)) {
5977 /* Still processing requests, so just re-arm the timer. */
5978 mod_timer(&dev_priv
->idle_timer
, jiffies
+
5979 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
5983 dev_priv
->busy
= false;
5984 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5987 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5989 static void intel_crtc_idle_timer(unsigned long arg
)
5991 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
5992 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5993 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
5994 struct intel_framebuffer
*intel_fb
;
5996 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5997 if (intel_fb
&& intel_fb
->obj
->active
) {
5998 /* The framebuffer is still being accessed by the GPU. */
5999 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
6000 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
6004 intel_crtc
->busy
= false;
6005 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
6008 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6010 struct drm_device
*dev
= crtc
->dev
;
6011 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6012 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6013 int pipe
= intel_crtc
->pipe
;
6014 int dpll_reg
= DPLL(pipe
);
6017 if (HAS_PCH_SPLIT(dev
))
6020 if (!dev_priv
->lvds_downclock_avail
)
6023 dpll
= I915_READ(dpll_reg
);
6024 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6025 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6027 /* Unlock panel regs */
6028 I915_WRITE(PP_CONTROL
,
6029 I915_READ(PP_CONTROL
) | PANEL_UNLOCK_REGS
);
6031 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6032 I915_WRITE(dpll_reg
, dpll
);
6033 intel_wait_for_vblank(dev
, pipe
);
6035 dpll
= I915_READ(dpll_reg
);
6036 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6037 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6039 /* ...and lock them again */
6040 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
6043 /* Schedule downclock */
6044 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
6045 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
6048 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6050 struct drm_device
*dev
= crtc
->dev
;
6051 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6052 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6053 int pipe
= intel_crtc
->pipe
;
6054 int dpll_reg
= DPLL(pipe
);
6055 int dpll
= I915_READ(dpll_reg
);
6057 if (HAS_PCH_SPLIT(dev
))
6060 if (!dev_priv
->lvds_downclock_avail
)
6064 * Since this is called by a timer, we should never get here in
6067 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6068 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6070 /* Unlock panel regs */
6071 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
6074 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6075 I915_WRITE(dpll_reg
, dpll
);
6076 intel_wait_for_vblank(dev
, pipe
);
6077 dpll
= I915_READ(dpll_reg
);
6078 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6079 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6081 /* ...and lock them again */
6082 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
6088 * intel_idle_update - adjust clocks for idleness
6089 * @work: work struct
6091 * Either the GPU or display (or both) went idle. Check the busy status
6092 * here and adjust the CRTC and GPU clocks as necessary.
6094 static void intel_idle_update(struct work_struct
*work
)
6096 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
6098 struct drm_device
*dev
= dev_priv
->dev
;
6099 struct drm_crtc
*crtc
;
6100 struct intel_crtc
*intel_crtc
;
6102 if (!i915_powersave
)
6105 mutex_lock(&dev
->struct_mutex
);
6107 i915_update_gfx_val(dev_priv
);
6109 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6110 /* Skip inactive CRTCs */
6114 intel_crtc
= to_intel_crtc(crtc
);
6115 if (!intel_crtc
->busy
)
6116 intel_decrease_pllclock(crtc
);
6120 mutex_unlock(&dev
->struct_mutex
);
6124 * intel_mark_busy - mark the GPU and possibly the display busy
6126 * @obj: object we're operating on
6128 * Callers can use this function to indicate that the GPU is busy processing
6129 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6130 * buffer), we'll also mark the display as busy, so we know to increase its
6133 void intel_mark_busy(struct drm_device
*dev
, struct drm_i915_gem_object
*obj
)
6135 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6136 struct drm_crtc
*crtc
= NULL
;
6137 struct intel_framebuffer
*intel_fb
;
6138 struct intel_crtc
*intel_crtc
;
6140 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
6143 if (!dev_priv
->busy
)
6144 dev_priv
->busy
= true;
6146 mod_timer(&dev_priv
->idle_timer
, jiffies
+
6147 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
6149 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6153 intel_crtc
= to_intel_crtc(crtc
);
6154 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6155 if (intel_fb
->obj
== obj
) {
6156 if (!intel_crtc
->busy
) {
6157 /* Non-busy -> busy, upclock */
6158 intel_increase_pllclock(crtc
);
6159 intel_crtc
->busy
= true;
6161 /* Busy -> busy, put off timer */
6162 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
6163 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
6169 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6172 struct drm_device
*dev
= crtc
->dev
;
6173 struct intel_unpin_work
*work
;
6174 unsigned long flags
;
6176 spin_lock_irqsave(&dev
->event_lock
, flags
);
6177 work
= intel_crtc
->unpin_work
;
6178 intel_crtc
->unpin_work
= NULL
;
6179 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6182 cancel_work_sync(&work
->work
);
6186 drm_crtc_cleanup(crtc
);
6191 static void intel_unpin_work_fn(struct work_struct
*__work
)
6193 struct intel_unpin_work
*work
=
6194 container_of(__work
, struct intel_unpin_work
, work
);
6196 mutex_lock(&work
->dev
->struct_mutex
);
6197 i915_gem_object_unpin(work
->old_fb_obj
);
6198 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6199 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6201 mutex_unlock(&work
->dev
->struct_mutex
);
6205 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6206 struct drm_crtc
*crtc
)
6208 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6209 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6210 struct intel_unpin_work
*work
;
6211 struct drm_i915_gem_object
*obj
;
6212 struct drm_pending_vblank_event
*e
;
6213 struct timeval tnow
, tvbl
;
6214 unsigned long flags
;
6216 /* Ignore early vblank irqs */
6217 if (intel_crtc
== NULL
)
6220 do_gettimeofday(&tnow
);
6222 spin_lock_irqsave(&dev
->event_lock
, flags
);
6223 work
= intel_crtc
->unpin_work
;
6224 if (work
== NULL
|| !work
->pending
) {
6225 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6229 intel_crtc
->unpin_work
= NULL
;
6233 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
6235 /* Called before vblank count and timestamps have
6236 * been updated for the vblank interval of flip
6237 * completion? Need to increment vblank count and
6238 * add one videorefresh duration to returned timestamp
6239 * to account for this. We assume this happened if we
6240 * get called over 0.9 frame durations after the last
6241 * timestamped vblank.
6243 * This calculation can not be used with vrefresh rates
6244 * below 5Hz (10Hz to be on the safe side) without
6245 * promoting to 64 integers.
6247 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
6248 9 * crtc
->framedur_ns
) {
6249 e
->event
.sequence
++;
6250 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
6254 e
->event
.tv_sec
= tvbl
.tv_sec
;
6255 e
->event
.tv_usec
= tvbl
.tv_usec
;
6257 list_add_tail(&e
->base
.link
,
6258 &e
->base
.file_priv
->event_list
);
6259 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
6262 drm_vblank_put(dev
, intel_crtc
->pipe
);
6264 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6266 obj
= work
->old_fb_obj
;
6268 atomic_clear_mask(1 << intel_crtc
->plane
,
6269 &obj
->pending_flip
.counter
);
6270 if (atomic_read(&obj
->pending_flip
) == 0)
6271 wake_up(&dev_priv
->pending_flip_queue
);
6273 schedule_work(&work
->work
);
6275 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6278 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6280 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6281 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6283 do_intel_finish_page_flip(dev
, crtc
);
6286 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6288 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6289 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6291 do_intel_finish_page_flip(dev
, crtc
);
6294 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6296 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6297 struct intel_crtc
*intel_crtc
=
6298 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6299 unsigned long flags
;
6301 spin_lock_irqsave(&dev
->event_lock
, flags
);
6302 if (intel_crtc
->unpin_work
) {
6303 if ((++intel_crtc
->unpin_work
->pending
) > 1)
6304 DRM_ERROR("Prepared flip multiple times\n");
6306 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6308 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6311 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
6312 struct drm_framebuffer
*fb
,
6313 struct drm_pending_vblank_event
*event
)
6315 struct drm_device
*dev
= crtc
->dev
;
6316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6317 struct intel_framebuffer
*intel_fb
;
6318 struct drm_i915_gem_object
*obj
;
6319 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6320 struct intel_unpin_work
*work
;
6321 unsigned long flags
, offset
;
6322 int pipe
= intel_crtc
->pipe
;
6326 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
6330 work
->event
= event
;
6331 work
->dev
= crtc
->dev
;
6332 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6333 work
->old_fb_obj
= intel_fb
->obj
;
6334 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
6336 /* We borrow the event spin lock for protecting unpin_work */
6337 spin_lock_irqsave(&dev
->event_lock
, flags
);
6338 if (intel_crtc
->unpin_work
) {
6339 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6342 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6345 intel_crtc
->unpin_work
= work
;
6346 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6348 intel_fb
= to_intel_framebuffer(fb
);
6349 obj
= intel_fb
->obj
;
6351 mutex_lock(&dev
->struct_mutex
);
6352 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
6356 /* Reference the objects for the scheduled work. */
6357 drm_gem_object_reference(&work
->old_fb_obj
->base
);
6358 drm_gem_object_reference(&obj
->base
);
6362 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
6366 if (IS_GEN3(dev
) || IS_GEN2(dev
)) {
6369 /* Can't queue multiple flips, so wait for the previous
6370 * one to finish before executing the next.
6372 ret
= BEGIN_LP_RING(2);
6376 if (intel_crtc
->plane
)
6377 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6379 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6380 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
6385 work
->pending_flip_obj
= obj
;
6387 work
->enable_stall_check
= true;
6389 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6390 offset
= crtc
->y
* fb
->pitch
+ crtc
->x
* fb
->bits_per_pixel
/8;
6392 ret
= BEGIN_LP_RING(4);
6396 /* Block clients from rendering to the new back buffer until
6397 * the flip occurs and the object is no longer visible.
6399 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6401 switch (INTEL_INFO(dev
)->gen
) {
6403 OUT_RING(MI_DISPLAY_FLIP
|
6404 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6405 OUT_RING(fb
->pitch
);
6406 OUT_RING(obj
->gtt_offset
+ offset
);
6411 OUT_RING(MI_DISPLAY_FLIP_I915
|
6412 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6413 OUT_RING(fb
->pitch
);
6414 OUT_RING(obj
->gtt_offset
+ offset
);
6420 /* i965+ uses the linear or tiled offsets from the
6421 * Display Registers (which do not change across a page-flip)
6422 * so we need only reprogram the base address.
6424 OUT_RING(MI_DISPLAY_FLIP
|
6425 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6426 OUT_RING(fb
->pitch
);
6427 OUT_RING(obj
->gtt_offset
| obj
->tiling_mode
);
6429 /* XXX Enabling the panel-fitter across page-flip is so far
6430 * untested on non-native modes, so ignore it for now.
6431 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6434 pipesrc
= I915_READ(PIPESRC(pipe
)) & 0x0fff0fff;
6435 OUT_RING(pf
| pipesrc
);
6440 OUT_RING(MI_DISPLAY_FLIP
|
6441 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6442 OUT_RING(fb
->pitch
| obj
->tiling_mode
);
6443 OUT_RING(obj
->gtt_offset
);
6445 pf
= I915_READ(PF_CTL(pipe
)) & PF_ENABLE
;
6446 pipesrc
= I915_READ(PIPESRC(pipe
)) & 0x0fff0fff;
6447 OUT_RING(pf
| pipesrc
);
6452 mutex_unlock(&dev
->struct_mutex
);
6454 trace_i915_flip_request(intel_crtc
->plane
, obj
);
6459 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6460 drm_gem_object_unreference(&obj
->base
);
6462 mutex_unlock(&dev
->struct_mutex
);
6464 spin_lock_irqsave(&dev
->event_lock
, flags
);
6465 intel_crtc
->unpin_work
= NULL
;
6466 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6473 static void intel_sanitize_modesetting(struct drm_device
*dev
,
6474 int pipe
, int plane
)
6476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6479 if (HAS_PCH_SPLIT(dev
))
6482 /* Who knows what state these registers were left in by the BIOS or
6485 * If we leave the registers in a conflicting state (e.g. with the
6486 * display plane reading from the other pipe than the one we intend
6487 * to use) then when we attempt to teardown the active mode, we will
6488 * not disable the pipes and planes in the correct order -- leaving
6489 * a plane reading from a disabled pipe and possibly leading to
6490 * undefined behaviour.
6493 reg
= DSPCNTR(plane
);
6494 val
= I915_READ(reg
);
6496 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
6498 if (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == pipe
)
6501 /* This display plane is active and attached to the other CPU pipe. */
6504 /* Disable the plane and wait for it to stop reading from the pipe. */
6505 intel_disable_plane(dev_priv
, plane
, pipe
);
6506 intel_disable_pipe(dev_priv
, pipe
);
6509 static void intel_crtc_reset(struct drm_crtc
*crtc
)
6511 struct drm_device
*dev
= crtc
->dev
;
6512 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6514 /* Reset flags back to the 'unknown' status so that they
6515 * will be correctly set on the initial modeset.
6517 intel_crtc
->dpms_mode
= -1;
6519 /* We need to fix up any BIOS configuration that conflicts with
6522 intel_sanitize_modesetting(dev
, intel_crtc
->pipe
, intel_crtc
->plane
);
6525 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
6526 .dpms
= intel_crtc_dpms
,
6527 .mode_fixup
= intel_crtc_mode_fixup
,
6528 .mode_set
= intel_crtc_mode_set
,
6529 .mode_set_base
= intel_pipe_set_base
,
6530 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
6531 .load_lut
= intel_crtc_load_lut
,
6532 .disable
= intel_crtc_disable
,
6535 static const struct drm_crtc_funcs intel_crtc_funcs
= {
6536 .reset
= intel_crtc_reset
,
6537 .cursor_set
= intel_crtc_cursor_set
,
6538 .cursor_move
= intel_crtc_cursor_move
,
6539 .gamma_set
= intel_crtc_gamma_set
,
6540 .set_config
= drm_crtc_helper_set_config
,
6541 .destroy
= intel_crtc_destroy
,
6542 .page_flip
= intel_crtc_page_flip
,
6545 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
6547 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6548 struct intel_crtc
*intel_crtc
;
6551 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
6552 if (intel_crtc
== NULL
)
6555 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
6557 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
6558 for (i
= 0; i
< 256; i
++) {
6559 intel_crtc
->lut_r
[i
] = i
;
6560 intel_crtc
->lut_g
[i
] = i
;
6561 intel_crtc
->lut_b
[i
] = i
;
6564 /* Swap pipes & planes for FBC on pre-965 */
6565 intel_crtc
->pipe
= pipe
;
6566 intel_crtc
->plane
= pipe
;
6567 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
6568 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6569 intel_crtc
->plane
= !pipe
;
6572 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
6573 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
6574 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
6575 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
6577 intel_crtc_reset(&intel_crtc
->base
);
6578 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
6580 if (HAS_PCH_SPLIT(dev
)) {
6581 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
6582 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
6584 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
6585 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
6588 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
6590 intel_crtc
->busy
= false;
6592 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
6593 (unsigned long)intel_crtc
);
6596 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
6597 struct drm_file
*file
)
6599 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6600 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
6601 struct drm_mode_object
*drmmode_obj
;
6602 struct intel_crtc
*crtc
;
6605 DRM_ERROR("called with no initialization\n");
6609 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
6610 DRM_MODE_OBJECT_CRTC
);
6613 DRM_ERROR("no such CRTC id\n");
6617 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
6618 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
6623 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
6625 struct intel_encoder
*encoder
;
6629 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6630 if (type_mask
& encoder
->clone_mask
)
6631 index_mask
|= (1 << entry
);
6638 static bool has_edp_a(struct drm_device
*dev
)
6640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6642 if (!IS_MOBILE(dev
))
6645 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
6649 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
6655 static void intel_setup_outputs(struct drm_device
*dev
)
6657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6658 struct intel_encoder
*encoder
;
6659 bool dpd_is_edp
= false;
6660 bool has_lvds
= false;
6662 if (IS_MOBILE(dev
) && !IS_I830(dev
))
6663 has_lvds
= intel_lvds_init(dev
);
6664 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
6665 /* disable the panel fitter on everything but LVDS */
6666 I915_WRITE(PFIT_CONTROL
, 0);
6669 if (HAS_PCH_SPLIT(dev
)) {
6670 dpd_is_edp
= intel_dpd_is_edp(dev
);
6673 intel_dp_init(dev
, DP_A
);
6675 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6676 intel_dp_init(dev
, PCH_DP_D
);
6679 intel_crt_init(dev
);
6681 if (HAS_PCH_SPLIT(dev
)) {
6684 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
6685 /* PCH SDVOB multiplex with HDMIB */
6686 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
6688 intel_hdmi_init(dev
, HDMIB
);
6689 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
6690 intel_dp_init(dev
, PCH_DP_B
);
6693 if (I915_READ(HDMIC
) & PORT_DETECTED
)
6694 intel_hdmi_init(dev
, HDMIC
);
6696 if (I915_READ(HDMID
) & PORT_DETECTED
)
6697 intel_hdmi_init(dev
, HDMID
);
6699 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
6700 intel_dp_init(dev
, PCH_DP_C
);
6702 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6703 intel_dp_init(dev
, PCH_DP_D
);
6705 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
6708 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6709 DRM_DEBUG_KMS("probing SDVOB\n");
6710 found
= intel_sdvo_init(dev
, SDVOB
);
6711 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
6712 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6713 intel_hdmi_init(dev
, SDVOB
);
6716 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
6717 DRM_DEBUG_KMS("probing DP_B\n");
6718 intel_dp_init(dev
, DP_B
);
6722 /* Before G4X SDVOC doesn't have its own detect register */
6724 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6725 DRM_DEBUG_KMS("probing SDVOC\n");
6726 found
= intel_sdvo_init(dev
, SDVOC
);
6729 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
6731 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
6732 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6733 intel_hdmi_init(dev
, SDVOC
);
6735 if (SUPPORTS_INTEGRATED_DP(dev
)) {
6736 DRM_DEBUG_KMS("probing DP_C\n");
6737 intel_dp_init(dev
, DP_C
);
6741 if (SUPPORTS_INTEGRATED_DP(dev
) &&
6742 (I915_READ(DP_D
) & DP_DETECTED
)) {
6743 DRM_DEBUG_KMS("probing DP_D\n");
6744 intel_dp_init(dev
, DP_D
);
6746 } else if (IS_GEN2(dev
))
6747 intel_dvo_init(dev
);
6749 if (SUPPORTS_TV(dev
))
6752 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6753 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
6754 encoder
->base
.possible_clones
=
6755 intel_encoder_clones(dev
, encoder
->clone_mask
);
6758 intel_panel_setup_backlight(dev
);
6760 /* disable all the possible outputs/crtcs before entering KMS mode */
6761 drm_helper_disable_unused_functions(dev
);
6764 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
6766 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6768 drm_framebuffer_cleanup(fb
);
6769 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
6774 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
6775 struct drm_file
*file
,
6776 unsigned int *handle
)
6778 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6779 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
6781 return drm_gem_handle_create(file
, &obj
->base
, handle
);
6784 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
6785 .destroy
= intel_user_framebuffer_destroy
,
6786 .create_handle
= intel_user_framebuffer_create_handle
,
6789 int intel_framebuffer_init(struct drm_device
*dev
,
6790 struct intel_framebuffer
*intel_fb
,
6791 struct drm_mode_fb_cmd
*mode_cmd
,
6792 struct drm_i915_gem_object
*obj
)
6796 if (obj
->tiling_mode
== I915_TILING_Y
)
6799 if (mode_cmd
->pitch
& 63)
6802 switch (mode_cmd
->bpp
) {
6812 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
6814 DRM_ERROR("framebuffer init failed %d\n", ret
);
6818 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
6819 intel_fb
->obj
= obj
;
6823 static struct drm_framebuffer
*
6824 intel_user_framebuffer_create(struct drm_device
*dev
,
6825 struct drm_file
*filp
,
6826 struct drm_mode_fb_cmd
*mode_cmd
)
6828 struct drm_i915_gem_object
*obj
;
6830 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
));
6831 if (&obj
->base
== NULL
)
6832 return ERR_PTR(-ENOENT
);
6834 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
6837 static const struct drm_mode_config_funcs intel_mode_funcs
= {
6838 .fb_create
= intel_user_framebuffer_create
,
6839 .output_poll_changed
= intel_fb_output_poll_changed
,
6842 static struct drm_i915_gem_object
*
6843 intel_alloc_context_page(struct drm_device
*dev
)
6845 struct drm_i915_gem_object
*ctx
;
6848 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
6850 ctx
= i915_gem_alloc_object(dev
, 4096);
6852 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6856 ret
= i915_gem_object_pin(ctx
, 4096, true);
6858 DRM_ERROR("failed to pin power context: %d\n", ret
);
6862 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
6864 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
6871 i915_gem_object_unpin(ctx
);
6873 drm_gem_object_unreference(&ctx
->base
);
6874 mutex_unlock(&dev
->struct_mutex
);
6878 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
6880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6883 rgvswctl
= I915_READ16(MEMSWCTL
);
6884 if (rgvswctl
& MEMCTL_CMD_STS
) {
6885 DRM_DEBUG("gpu busy, RCS change rejected\n");
6886 return false; /* still busy with another command */
6889 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
6890 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
6891 I915_WRITE16(MEMSWCTL
, rgvswctl
);
6892 POSTING_READ16(MEMSWCTL
);
6894 rgvswctl
|= MEMCTL_CMD_STS
;
6895 I915_WRITE16(MEMSWCTL
, rgvswctl
);
6900 void ironlake_enable_drps(struct drm_device
*dev
)
6902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6903 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
6904 u8 fmax
, fmin
, fstart
, vstart
;
6906 /* Enable temp reporting */
6907 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
6908 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
6910 /* 100ms RC evaluation intervals */
6911 I915_WRITE(RCUPEI
, 100000);
6912 I915_WRITE(RCDNEI
, 100000);
6914 /* Set max/min thresholds to 90ms and 80ms respectively */
6915 I915_WRITE(RCBMAXAVG
, 90000);
6916 I915_WRITE(RCBMINAVG
, 80000);
6918 I915_WRITE(MEMIHYST
, 1);
6920 /* Set up min, max, and cur for interrupt handling */
6921 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
6922 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
6923 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
6924 MEMMODE_FSTART_SHIFT
;
6926 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
6929 dev_priv
->fmax
= fmax
; /* IPS callback will increase this */
6930 dev_priv
->fstart
= fstart
;
6932 dev_priv
->max_delay
= fstart
;
6933 dev_priv
->min_delay
= fmin
;
6934 dev_priv
->cur_delay
= fstart
;
6936 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6937 fmax
, fmin
, fstart
);
6939 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
6942 * Interrupts will be enabled in ironlake_irq_postinstall
6945 I915_WRITE(VIDSTART
, vstart
);
6946 POSTING_READ(VIDSTART
);
6948 rgvmodectl
|= MEMMODE_SWMODE_EN
;
6949 I915_WRITE(MEMMODECTL
, rgvmodectl
);
6951 if (wait_for((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
6952 DRM_ERROR("stuck trying to change perf mode\n");
6955 ironlake_set_drps(dev
, fstart
);
6957 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
6959 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
6960 dev_priv
->last_count2
= I915_READ(0x112f4);
6961 getrawmonotonic(&dev_priv
->last_time2
);
6964 void ironlake_disable_drps(struct drm_device
*dev
)
6966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6967 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
6969 /* Ack interrupts, disable EFC interrupt */
6970 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
6971 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
6972 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
6973 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
6974 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
6976 /* Go back to the starting frequency */
6977 ironlake_set_drps(dev
, dev_priv
->fstart
);
6979 rgvswctl
|= MEMCTL_CMD_STS
;
6980 I915_WRITE(MEMSWCTL
, rgvswctl
);
6985 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
6987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6990 swreq
= (val
& 0x3ff) << 25;
6991 I915_WRITE(GEN6_RPNSWREQ
, swreq
);
6994 void gen6_disable_rps(struct drm_device
*dev
)
6996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6998 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
6999 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
7000 I915_WRITE(GEN6_PMIER
, 0);
7002 spin_lock_irq(&dev_priv
->rps_lock
);
7003 dev_priv
->pm_iir
= 0;
7004 spin_unlock_irq(&dev_priv
->rps_lock
);
7006 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
7009 static unsigned long intel_pxfreq(u32 vidfreq
)
7012 int div
= (vidfreq
& 0x3f0000) >> 16;
7013 int post
= (vidfreq
& 0x3000) >> 12;
7014 int pre
= (vidfreq
& 0x7);
7019 freq
= ((div
* 133333) / ((1<<post
) * pre
));
7024 void intel_init_emon(struct drm_device
*dev
)
7026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7031 /* Disable to program */
7035 /* Program energy weights for various events */
7036 I915_WRITE(SDEW
, 0x15040d00);
7037 I915_WRITE(CSIEW0
, 0x007f0000);
7038 I915_WRITE(CSIEW1
, 0x1e220004);
7039 I915_WRITE(CSIEW2
, 0x04000004);
7041 for (i
= 0; i
< 5; i
++)
7042 I915_WRITE(PEW
+ (i
* 4), 0);
7043 for (i
= 0; i
< 3; i
++)
7044 I915_WRITE(DEW
+ (i
* 4), 0);
7046 /* Program P-state weights to account for frequency power adjustment */
7047 for (i
= 0; i
< 16; i
++) {
7048 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
7049 unsigned long freq
= intel_pxfreq(pxvidfreq
);
7050 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
7055 val
*= (freq
/ 1000);
7057 val
/= (127*127*900);
7059 DRM_ERROR("bad pxval: %ld\n", val
);
7062 /* Render standby states get 0 weight */
7066 for (i
= 0; i
< 4; i
++) {
7067 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
7068 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
7069 I915_WRITE(PXW
+ (i
* 4), val
);
7072 /* Adjust magic regs to magic values (more experimental results) */
7073 I915_WRITE(OGW0
, 0);
7074 I915_WRITE(OGW1
, 0);
7075 I915_WRITE(EG0
, 0x00007f00);
7076 I915_WRITE(EG1
, 0x0000000e);
7077 I915_WRITE(EG2
, 0x000e0000);
7078 I915_WRITE(EG3
, 0x68000300);
7079 I915_WRITE(EG4
, 0x42000000);
7080 I915_WRITE(EG5
, 0x00140031);
7084 for (i
= 0; i
< 8; i
++)
7085 I915_WRITE(PXWL
+ (i
* 4), 0);
7087 /* Enable PMON + select events */
7088 I915_WRITE(ECR
, 0x80000019);
7090 lcfuse
= I915_READ(LCFUSE02
);
7092 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
7095 void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
7097 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
7098 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
7099 u32 pcu_mbox
, rc6_mask
= 0;
7100 int cur_freq
, min_freq
, max_freq
;
7103 /* Here begins a magic sequence of register writes to enable
7104 * auto-downclocking.
7106 * Perhaps there might be some value in exposing these to
7109 I915_WRITE(GEN6_RC_STATE
, 0);
7110 mutex_lock(&dev_priv
->dev
->struct_mutex
);
7111 gen6_gt_force_wake_get(dev_priv
);
7113 /* disable the counters and set deterministic thresholds */
7114 I915_WRITE(GEN6_RC_CONTROL
, 0);
7116 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
7117 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
7118 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
7119 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
7120 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
7122 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
7123 I915_WRITE(RING_MAX_IDLE(dev_priv
->ring
[i
].mmio_base
), 10);
7125 I915_WRITE(GEN6_RC_SLEEP
, 0);
7126 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
7127 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
7128 I915_WRITE(GEN6_RC6p_THRESHOLD
, 100000);
7129 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
7131 if (i915_enable_rc6
)
7132 rc6_mask
= GEN6_RC_CTL_RC6p_ENABLE
|
7133 GEN6_RC_CTL_RC6_ENABLE
;
7135 I915_WRITE(GEN6_RC_CONTROL
,
7137 GEN6_RC_CTL_EI_MODE(1) |
7138 GEN6_RC_CTL_HW_ENABLE
);
7140 I915_WRITE(GEN6_RPNSWREQ
,
7141 GEN6_FREQUENCY(10) |
7143 GEN6_AGGRESSIVE_TURBO
);
7144 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
7145 GEN6_FREQUENCY(12));
7147 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
7148 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
7151 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 10000);
7152 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 1000000);
7153 I915_WRITE(GEN6_RP_UP_EI
, 100000);
7154 I915_WRITE(GEN6_RP_DOWN_EI
, 5000000);
7155 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
7156 I915_WRITE(GEN6_RP_CONTROL
,
7157 GEN6_RP_MEDIA_TURBO
|
7158 GEN6_RP_USE_NORMAL_FREQ
|
7159 GEN6_RP_MEDIA_IS_GFX
|
7161 GEN6_RP_UP_BUSY_AVG
|
7162 GEN6_RP_DOWN_IDLE_CONT
);
7164 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7166 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7168 I915_WRITE(GEN6_PCODE_DATA
, 0);
7169 I915_WRITE(GEN6_PCODE_MAILBOX
,
7171 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
);
7172 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7174 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7176 min_freq
= (rp_state_cap
& 0xff0000) >> 16;
7177 max_freq
= rp_state_cap
& 0xff;
7178 cur_freq
= (gt_perf_status
& 0xff00) >> 8;
7180 /* Check for overclock support */
7181 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7183 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7184 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_READ_OC_PARAMS
);
7185 pcu_mbox
= I915_READ(GEN6_PCODE_DATA
);
7186 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7188 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7189 if (pcu_mbox
& (1<<31)) { /* OC supported */
7190 max_freq
= pcu_mbox
& 0xff;
7191 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox
* 50);
7194 /* In units of 100MHz */
7195 dev_priv
->max_delay
= max_freq
;
7196 dev_priv
->min_delay
= min_freq
;
7197 dev_priv
->cur_delay
= cur_freq
;
7199 /* requires MSI enabled */
7200 I915_WRITE(GEN6_PMIER
,
7201 GEN6_PM_MBOX_EVENT
|
7202 GEN6_PM_THERMAL_EVENT
|
7203 GEN6_PM_RP_DOWN_TIMEOUT
|
7204 GEN6_PM_RP_UP_THRESHOLD
|
7205 GEN6_PM_RP_DOWN_THRESHOLD
|
7206 GEN6_PM_RP_UP_EI_EXPIRED
|
7207 GEN6_PM_RP_DOWN_EI_EXPIRED
);
7208 spin_lock_irq(&dev_priv
->rps_lock
);
7209 WARN_ON(dev_priv
->pm_iir
!= 0);
7210 I915_WRITE(GEN6_PMIMR
, 0);
7211 spin_unlock_irq(&dev_priv
->rps_lock
);
7212 /* enable all PM interrupts */
7213 I915_WRITE(GEN6_PMINTRMSK
, 0);
7215 gen6_gt_force_wake_put(dev_priv
);
7216 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
7219 static void ironlake_init_clock_gating(struct drm_device
*dev
)
7221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7222 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
7224 /* Required for FBC */
7225 dspclk_gate
|= DPFCUNIT_CLOCK_GATE_DISABLE
|
7226 DPFCRUNIT_CLOCK_GATE_DISABLE
|
7227 DPFDUNIT_CLOCK_GATE_DISABLE
;
7228 /* Required for CxSR */
7229 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
7231 I915_WRITE(PCH_3DCGDIS0
,
7232 MARIUNIT_CLOCK_GATE_DISABLE
|
7233 SVSMUNIT_CLOCK_GATE_DISABLE
);
7234 I915_WRITE(PCH_3DCGDIS1
,
7235 VFMUNIT_CLOCK_GATE_DISABLE
);
7237 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
7240 * According to the spec the following bits should be set in
7241 * order to enable memory self-refresh
7242 * The bit 22/21 of 0x42004
7243 * The bit 5 of 0x42020
7244 * The bit 15 of 0x45000
7246 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7247 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
7248 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
7249 I915_WRITE(ILK_DSPCLK_GATE
,
7250 (I915_READ(ILK_DSPCLK_GATE
) |
7251 ILK_DPARB_CLK_GATE
));
7252 I915_WRITE(DISP_ARB_CTL
,
7253 (I915_READ(DISP_ARB_CTL
) |
7255 I915_WRITE(WM3_LP_ILK
, 0);
7256 I915_WRITE(WM2_LP_ILK
, 0);
7257 I915_WRITE(WM1_LP_ILK
, 0);
7260 * Based on the document from hardware guys the following bits
7261 * should be set unconditionally in order to enable FBC.
7262 * The bit 22 of 0x42000
7263 * The bit 22 of 0x42004
7264 * The bit 7,8,9 of 0x42020.
7266 if (IS_IRONLAKE_M(dev
)) {
7267 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
7268 I915_READ(ILK_DISPLAY_CHICKEN1
) |
7270 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7271 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7273 I915_WRITE(ILK_DSPCLK_GATE
,
7274 I915_READ(ILK_DSPCLK_GATE
) |
7280 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7281 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7282 ILK_ELPIN_409_SELECT
);
7283 I915_WRITE(_3D_CHICKEN2
,
7284 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
7285 _3D_CHICKEN2_WM_READ_PIPELINED
);
7288 static void gen6_init_clock_gating(struct drm_device
*dev
)
7290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7292 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
7294 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
7296 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7297 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7298 ILK_ELPIN_409_SELECT
);
7300 I915_WRITE(WM3_LP_ILK
, 0);
7301 I915_WRITE(WM2_LP_ILK
, 0);
7302 I915_WRITE(WM1_LP_ILK
, 0);
7305 * According to the spec the following bits should be
7306 * set in order to enable memory self-refresh and fbc:
7307 * The bit21 and bit22 of 0x42000
7308 * The bit21 and bit22 of 0x42004
7309 * The bit5 and bit7 of 0x42020
7310 * The bit14 of 0x70180
7311 * The bit14 of 0x71180
7313 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
7314 I915_READ(ILK_DISPLAY_CHICKEN1
) |
7315 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
7316 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7317 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7318 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
7319 I915_WRITE(ILK_DSPCLK_GATE
,
7320 I915_READ(ILK_DSPCLK_GATE
) |
7321 ILK_DPARB_CLK_GATE
|
7325 I915_WRITE(DSPCNTR(pipe
),
7326 I915_READ(DSPCNTR(pipe
)) |
7327 DISPPLANE_TRICKLE_FEED_DISABLE
);
7330 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
7332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7334 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
7336 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
7338 I915_WRITE(WM3_LP_ILK
, 0);
7339 I915_WRITE(WM2_LP_ILK
, 0);
7340 I915_WRITE(WM1_LP_ILK
, 0);
7342 I915_WRITE(ILK_DSPCLK_GATE
, IVB_VRHUNIT_CLK_GATE
);
7345 I915_WRITE(DSPCNTR(pipe
),
7346 I915_READ(DSPCNTR(pipe
)) |
7347 DISPPLANE_TRICKLE_FEED_DISABLE
);
7350 static void g4x_init_clock_gating(struct drm_device
*dev
)
7352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7353 uint32_t dspclk_gate
;
7355 I915_WRITE(RENCLK_GATE_D1
, 0);
7356 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
7357 GS_UNIT_CLOCK_GATE_DISABLE
|
7358 CL_UNIT_CLOCK_GATE_DISABLE
);
7359 I915_WRITE(RAMCLK_GATE_D
, 0);
7360 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
7361 OVRUNIT_CLOCK_GATE_DISABLE
|
7362 OVCUNIT_CLOCK_GATE_DISABLE
;
7364 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
7365 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
7368 static void crestline_init_clock_gating(struct drm_device
*dev
)
7370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7372 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
7373 I915_WRITE(RENCLK_GATE_D2
, 0);
7374 I915_WRITE(DSPCLK_GATE_D
, 0);
7375 I915_WRITE(RAMCLK_GATE_D
, 0);
7376 I915_WRITE16(DEUC
, 0);
7379 static void broadwater_init_clock_gating(struct drm_device
*dev
)
7381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7383 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
7384 I965_RCC_CLOCK_GATE_DISABLE
|
7385 I965_RCPB_CLOCK_GATE_DISABLE
|
7386 I965_ISC_CLOCK_GATE_DISABLE
|
7387 I965_FBC_CLOCK_GATE_DISABLE
);
7388 I915_WRITE(RENCLK_GATE_D2
, 0);
7391 static void gen3_init_clock_gating(struct drm_device
*dev
)
7393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7394 u32 dstate
= I915_READ(D_STATE
);
7396 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
7397 DSTATE_DOT_CLOCK_GATING
;
7398 I915_WRITE(D_STATE
, dstate
);
7401 static void i85x_init_clock_gating(struct drm_device
*dev
)
7403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7405 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
7408 static void i830_init_clock_gating(struct drm_device
*dev
)
7410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7412 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
7415 static void ibx_init_clock_gating(struct drm_device
*dev
)
7417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7420 * On Ibex Peak and Cougar Point, we need to disable clock
7421 * gating for the panel power sequencer or it will fail to
7422 * start up when no ports are active.
7424 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
7427 static void cpt_init_clock_gating(struct drm_device
*dev
)
7429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7432 * On Ibex Peak and Cougar Point, we need to disable clock
7433 * gating for the panel power sequencer or it will fail to
7434 * start up when no ports are active.
7436 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
7437 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
7438 DPLS_EDP_PPS_FIX_DIS
);
7441 static void ironlake_teardown_rc6(struct drm_device
*dev
)
7443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7445 if (dev_priv
->renderctx
) {
7446 i915_gem_object_unpin(dev_priv
->renderctx
);
7447 drm_gem_object_unreference(&dev_priv
->renderctx
->base
);
7448 dev_priv
->renderctx
= NULL
;
7451 if (dev_priv
->pwrctx
) {
7452 i915_gem_object_unpin(dev_priv
->pwrctx
);
7453 drm_gem_object_unreference(&dev_priv
->pwrctx
->base
);
7454 dev_priv
->pwrctx
= NULL
;
7458 static void ironlake_disable_rc6(struct drm_device
*dev
)
7460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7462 if (I915_READ(PWRCTXA
)) {
7463 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7464 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
7465 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
7468 I915_WRITE(PWRCTXA
, 0);
7469 POSTING_READ(PWRCTXA
);
7471 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
7472 POSTING_READ(RSTDBYCTL
);
7475 ironlake_teardown_rc6(dev
);
7478 static int ironlake_setup_rc6(struct drm_device
*dev
)
7480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7482 if (dev_priv
->renderctx
== NULL
)
7483 dev_priv
->renderctx
= intel_alloc_context_page(dev
);
7484 if (!dev_priv
->renderctx
)
7487 if (dev_priv
->pwrctx
== NULL
)
7488 dev_priv
->pwrctx
= intel_alloc_context_page(dev
);
7489 if (!dev_priv
->pwrctx
) {
7490 ironlake_teardown_rc6(dev
);
7497 void ironlake_enable_rc6(struct drm_device
*dev
)
7499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7502 /* rc6 disabled by default due to repeated reports of hanging during
7505 if (!i915_enable_rc6
)
7508 mutex_lock(&dev
->struct_mutex
);
7509 ret
= ironlake_setup_rc6(dev
);
7511 mutex_unlock(&dev
->struct_mutex
);
7516 * GPU can automatically power down the render unit if given a page
7519 ret
= BEGIN_LP_RING(6);
7521 ironlake_teardown_rc6(dev
);
7522 mutex_unlock(&dev
->struct_mutex
);
7526 OUT_RING(MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
7527 OUT_RING(MI_SET_CONTEXT
);
7528 OUT_RING(dev_priv
->renderctx
->gtt_offset
|
7530 MI_SAVE_EXT_STATE_EN
|
7531 MI_RESTORE_EXT_STATE_EN
|
7532 MI_RESTORE_INHIBIT
);
7533 OUT_RING(MI_SUSPEND_FLUSH
);
7539 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7540 * does an implicit flush, combined with MI_FLUSH above, it should be
7541 * safe to assume that renderctx is valid
7543 ret
= intel_wait_ring_idle(LP_RING(dev_priv
));
7545 DRM_ERROR("failed to enable ironlake power power savings\n");
7546 ironlake_teardown_rc6(dev
);
7547 mutex_unlock(&dev
->struct_mutex
);
7551 I915_WRITE(PWRCTXA
, dev_priv
->pwrctx
->gtt_offset
| PWRCTX_EN
);
7552 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
7553 mutex_unlock(&dev
->struct_mutex
);
7556 void intel_init_clock_gating(struct drm_device
*dev
)
7558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7560 dev_priv
->display
.init_clock_gating(dev
);
7562 if (dev_priv
->display
.init_pch_clock_gating
)
7563 dev_priv
->display
.init_pch_clock_gating(dev
);
7566 /* Set up chip specific display functions */
7567 static void intel_init_display(struct drm_device
*dev
)
7569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7571 /* We always want a DPMS function */
7572 if (HAS_PCH_SPLIT(dev
)) {
7573 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
7574 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
7576 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
7577 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
7580 if (I915_HAS_FBC(dev
)) {
7581 if (HAS_PCH_SPLIT(dev
)) {
7582 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
7583 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
7584 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
7585 } else if (IS_GM45(dev
)) {
7586 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
7587 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
7588 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
7589 } else if (IS_CRESTLINE(dev
)) {
7590 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
7591 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
7592 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
7594 /* 855GM needs testing */
7597 /* Returns the core display clock speed */
7598 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
7599 dev_priv
->display
.get_display_clock_speed
=
7600 i945_get_display_clock_speed
;
7601 else if (IS_I915G(dev
))
7602 dev_priv
->display
.get_display_clock_speed
=
7603 i915_get_display_clock_speed
;
7604 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
7605 dev_priv
->display
.get_display_clock_speed
=
7606 i9xx_misc_get_display_clock_speed
;
7607 else if (IS_I915GM(dev
))
7608 dev_priv
->display
.get_display_clock_speed
=
7609 i915gm_get_display_clock_speed
;
7610 else if (IS_I865G(dev
))
7611 dev_priv
->display
.get_display_clock_speed
=
7612 i865_get_display_clock_speed
;
7613 else if (IS_I85X(dev
))
7614 dev_priv
->display
.get_display_clock_speed
=
7615 i855_get_display_clock_speed
;
7617 dev_priv
->display
.get_display_clock_speed
=
7618 i830_get_display_clock_speed
;
7620 /* For FIFO watermark updates */
7621 if (HAS_PCH_SPLIT(dev
)) {
7622 if (HAS_PCH_IBX(dev
))
7623 dev_priv
->display
.init_pch_clock_gating
= ibx_init_clock_gating
;
7624 else if (HAS_PCH_CPT(dev
))
7625 dev_priv
->display
.init_pch_clock_gating
= cpt_init_clock_gating
;
7628 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
7629 dev_priv
->display
.update_wm
= ironlake_update_wm
;
7631 DRM_DEBUG_KMS("Failed to get proper latency. "
7633 dev_priv
->display
.update_wm
= NULL
;
7635 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
7636 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
7637 } else if (IS_GEN6(dev
)) {
7638 if (SNB_READ_WM0_LATENCY()) {
7639 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
7641 DRM_DEBUG_KMS("Failed to read display plane latency. "
7643 dev_priv
->display
.update_wm
= NULL
;
7645 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
7646 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7647 } else if (IS_IVYBRIDGE(dev
)) {
7648 /* FIXME: detect B0+ stepping and use auto training */
7649 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
7650 if (SNB_READ_WM0_LATENCY()) {
7651 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
7653 DRM_DEBUG_KMS("Failed to read display plane latency. "
7655 dev_priv
->display
.update_wm
= NULL
;
7657 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7660 dev_priv
->display
.update_wm
= NULL
;
7661 } else if (IS_PINEVIEW(dev
)) {
7662 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
7665 dev_priv
->mem_freq
)) {
7666 DRM_INFO("failed to find known CxSR latency "
7667 "(found ddr%s fsb freq %d, mem freq %d), "
7669 (dev_priv
->is_ddr3
== 1) ? "3": "2",
7670 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7671 /* Disable CxSR and never update its watermark again */
7672 pineview_disable_cxsr(dev
);
7673 dev_priv
->display
.update_wm
= NULL
;
7675 dev_priv
->display
.update_wm
= pineview_update_wm
;
7676 } else if (IS_G4X(dev
)) {
7677 dev_priv
->display
.update_wm
= g4x_update_wm
;
7678 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
7679 } else if (IS_GEN4(dev
)) {
7680 dev_priv
->display
.update_wm
= i965_update_wm
;
7681 if (IS_CRESTLINE(dev
))
7682 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7683 else if (IS_BROADWATER(dev
))
7684 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7685 } else if (IS_GEN3(dev
)) {
7686 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7687 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7688 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7689 } else if (IS_I865G(dev
)) {
7690 dev_priv
->display
.update_wm
= i830_update_wm
;
7691 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7692 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7693 } else if (IS_I85X(dev
)) {
7694 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7695 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
7696 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7698 dev_priv
->display
.update_wm
= i830_update_wm
;
7699 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7701 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7703 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7708 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7709 * resume, or other times. This quirk makes sure that's the case for
7712 static void quirk_pipea_force (struct drm_device
*dev
)
7714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7716 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
7717 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7720 struct intel_quirk
{
7722 int subsystem_vendor
;
7723 int subsystem_device
;
7724 void (*hook
)(struct drm_device
*dev
);
7727 struct intel_quirk intel_quirks
[] = {
7728 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7729 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force
},
7730 /* HP Mini needs pipe A force quirk (LP: #322104) */
7731 { 0x27ae,0x103c, 0x361a, quirk_pipea_force
},
7733 /* Thinkpad R31 needs pipe A force quirk */
7734 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
7735 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7736 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
7738 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7739 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
7740 /* ThinkPad X40 needs pipe A force quirk */
7742 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7743 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
7745 /* 855 & before need to leave pipe A & dpll A up */
7746 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7747 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7750 static void intel_init_quirks(struct drm_device
*dev
)
7752 struct pci_dev
*d
= dev
->pdev
;
7755 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
7756 struct intel_quirk
*q
= &intel_quirks
[i
];
7758 if (d
->device
== q
->device
&&
7759 (d
->subsystem_vendor
== q
->subsystem_vendor
||
7760 q
->subsystem_vendor
== PCI_ANY_ID
) &&
7761 (d
->subsystem_device
== q
->subsystem_device
||
7762 q
->subsystem_device
== PCI_ANY_ID
))
7767 /* Disable the VGA plane that we never use */
7768 static void i915_disable_vga(struct drm_device
*dev
)
7770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7774 if (HAS_PCH_SPLIT(dev
))
7775 vga_reg
= CPU_VGACNTRL
;
7779 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7780 outb(1, VGA_SR_INDEX
);
7781 sr1
= inb(VGA_SR_DATA
);
7782 outb(sr1
| 1<<5, VGA_SR_DATA
);
7783 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7786 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
7787 POSTING_READ(vga_reg
);
7790 void intel_modeset_init(struct drm_device
*dev
)
7792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7795 drm_mode_config_init(dev
);
7797 dev
->mode_config
.min_width
= 0;
7798 dev
->mode_config
.min_height
= 0;
7800 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
7802 intel_init_quirks(dev
);
7804 intel_init_display(dev
);
7807 dev
->mode_config
.max_width
= 2048;
7808 dev
->mode_config
.max_height
= 2048;
7809 } else if (IS_GEN3(dev
)) {
7810 dev
->mode_config
.max_width
= 4096;
7811 dev
->mode_config
.max_height
= 4096;
7813 dev
->mode_config
.max_width
= 8192;
7814 dev
->mode_config
.max_height
= 8192;
7816 dev
->mode_config
.fb_base
= dev
->agp
->base
;
7818 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7819 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
7821 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
7822 intel_crtc_init(dev
, i
);
7825 /* Just disable it once at startup */
7826 i915_disable_vga(dev
);
7827 intel_setup_outputs(dev
);
7829 intel_init_clock_gating(dev
);
7831 if (IS_IRONLAKE_M(dev
)) {
7832 ironlake_enable_drps(dev
);
7833 intel_init_emon(dev
);
7837 gen6_enable_rps(dev_priv
);
7839 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
7840 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
7841 (unsigned long)dev
);
7844 void intel_modeset_gem_init(struct drm_device
*dev
)
7846 if (IS_IRONLAKE_M(dev
))
7847 ironlake_enable_rc6(dev
);
7849 intel_setup_overlay(dev
);
7852 void intel_modeset_cleanup(struct drm_device
*dev
)
7854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7855 struct drm_crtc
*crtc
;
7856 struct intel_crtc
*intel_crtc
;
7858 drm_kms_helper_poll_fini(dev
);
7859 mutex_lock(&dev
->struct_mutex
);
7861 intel_unregister_dsm_handler();
7864 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7865 /* Skip inactive CRTCs */
7869 intel_crtc
= to_intel_crtc(crtc
);
7870 intel_increase_pllclock(crtc
);
7873 if (dev_priv
->display
.disable_fbc
)
7874 dev_priv
->display
.disable_fbc(dev
);
7876 if (IS_IRONLAKE_M(dev
))
7877 ironlake_disable_drps(dev
);
7879 gen6_disable_rps(dev
);
7881 if (IS_IRONLAKE_M(dev
))
7882 ironlake_disable_rc6(dev
);
7884 mutex_unlock(&dev
->struct_mutex
);
7886 /* Disable the irq before mode object teardown, for the irq might
7887 * enqueue unpin/hotplug work. */
7888 drm_irq_uninstall(dev
);
7889 cancel_work_sync(&dev_priv
->hotplug_work
);
7891 /* Shut off idle work before the crtcs get freed. */
7892 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7893 intel_crtc
= to_intel_crtc(crtc
);
7894 del_timer_sync(&intel_crtc
->idle_timer
);
7896 del_timer_sync(&dev_priv
->idle_timer
);
7897 cancel_work_sync(&dev_priv
->idle_work
);
7899 drm_mode_config_cleanup(dev
);
7903 * Return which encoder is currently attached for connector.
7905 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
7907 return &intel_attached_encoder(connector
)->base
;
7910 void intel_connector_attach_encoder(struct intel_connector
*connector
,
7911 struct intel_encoder
*encoder
)
7913 connector
->encoder
= encoder
;
7914 drm_mode_connector_attach_encoder(&connector
->base
,
7919 * set vga decode state - true == enable VGA decode
7921 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
7923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7926 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
7928 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
7930 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
7931 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
7935 #ifdef CONFIG_DEBUG_FS
7936 #include <linux/seq_file.h>
7938 struct intel_display_error_state
{
7939 struct intel_cursor_error_state
{
7946 struct intel_pipe_error_state
{
7958 struct intel_plane_error_state
{
7969 struct intel_display_error_state
*
7970 intel_display_capture_error_state(struct drm_device
*dev
)
7972 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7973 struct intel_display_error_state
*error
;
7976 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
7980 for (i
= 0; i
< 2; i
++) {
7981 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
7982 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
7983 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
7985 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
7986 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
7987 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
7988 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
7989 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
7990 if (INTEL_INFO(dev
)->gen
>= 4) {
7991 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
7992 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
7995 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
7996 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
7997 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
7998 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
7999 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
8000 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
8001 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
8002 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
8009 intel_display_print_error_state(struct seq_file
*m
,
8010 struct drm_device
*dev
,
8011 struct intel_display_error_state
*error
)
8015 for (i
= 0; i
< 2; i
++) {
8016 seq_printf(m
, "Pipe [%d]:\n", i
);
8017 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
8018 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
8019 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
8020 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
8021 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
8022 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
8023 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
8024 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
8026 seq_printf(m
, "Plane [%d]:\n", i
);
8027 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
8028 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
8029 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
8030 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
8031 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
8032 if (INTEL_INFO(dev
)->gen
>= 4) {
8033 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
8034 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
8037 seq_printf(m
, "Cursor [%d]:\n", i
);
8038 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
8039 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
8040 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);