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[PATCH] dvb: remove version.h dependencies
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / media / dvb / frontends / dib3000mc.c
blob441de665fec32aa28850d6b680fdc6a6ea638080
1 /*
2 * Frontend driver for mobile DVB-T demodulator DiBcom 3000P/M-C
3 * DiBcom (http://www.dibcom.fr/)
4 *
5 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
6 *
7 * based on GPL code from DiBCom, which has
8 *
9 * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation, version 2.
14 *
15 * Acknowledgements
16 *
17 * Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
18 * sources, on which this driver (and the dvb-dibusb) are based.
19 *
20 * see Documentation/dvb/README.dibusb for more information
21 *
22 */
23 #include <linux/config.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29
30 #include "dib3000-common.h"
31 #include "dib3000mc_priv.h"
32 #include "dib3000.h"
33
34 /* Version information */
35 #define DRIVER_VERSION "0.1"
36 #define DRIVER_DESC "DiBcom 3000M-C DVB-T demodulator"
37 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
38
39 #ifdef CONFIG_DVB_DIBCOM_DEBUG
40 static int debug;
41 module_param(debug, int, 0644);
42 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe,16=stat (|-able)).");
43 #endif
44 #define deb_info(args...) dprintk(0x01,args)
45 #define deb_xfer(args...) dprintk(0x02,args)
46 #define deb_setf(args...) dprintk(0x04,args)
47 #define deb_getf(args...) dprintk(0x08,args)
48 #define deb_stat(args...) dprintk(0x10,args)
49
50 static int dib3000mc_set_impulse_noise(struct dib3000_state * state, int mode,
51 fe_transmit_mode_t transmission_mode, fe_bandwidth_t bandwidth)
52 {
53 switch (transmission_mode) {
54 case TRANSMISSION_MODE_2K:
55 wr_foreach(dib3000mc_reg_fft,dib3000mc_fft_modes[0]);
56 break;
57 case TRANSMISSION_MODE_8K:
58 wr_foreach(dib3000mc_reg_fft,dib3000mc_fft_modes[1]);
59 break;
60 default:
61 break;
62 }
63
64 switch (bandwidth) {
65 /* case BANDWIDTH_5_MHZ:
66 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[0]);
67 break; */
68 case BANDWIDTH_6_MHZ:
69 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[1]);
70 break;
71 case BANDWIDTH_7_MHZ:
72 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[2]);
73 break;
74 case BANDWIDTH_8_MHZ:
75 wr_foreach(dib3000mc_reg_impulse_noise,dib3000mc_impluse_noise[3]);
76 break;
77 default:
78 break;
79 }
80
81 switch (mode) {
82 case 0: /* no impulse */ /* fall through */
83 wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[0]);
84 break;
85 case 1: /* new algo */
86 wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[1]);
87 set_or(DIB3000MC_REG_IMP_NOISE_55,DIB3000MC_IMP_NEW_ALGO(0)); /* gives 1<<10 */
88 break;
89 default: /* old algo */
90 wr_foreach(dib3000mc_reg_imp_noise_ctl,dib3000mc_imp_noise_ctl[3]);
91 break;
92 }
93 return 0;
94 }
95
96 static int dib3000mc_set_timing(struct dib3000_state *state, int upd_offset,
97 fe_transmit_mode_t fft, fe_bandwidth_t bw)
98 {
99 u16 timf_msb,timf_lsb;
100 s32 tim_offset,tim_sgn;
101 u64 comp1,comp2,comp=0;
102
103 switch (bw) {
104 case BANDWIDTH_8_MHZ: comp = DIB3000MC_CLOCK_REF*8; break;
105 case BANDWIDTH_7_MHZ: comp = DIB3000MC_CLOCK_REF*7; break;
106 case BANDWIDTH_6_MHZ: comp = DIB3000MC_CLOCK_REF*6; break;
107 default: err("unknown bandwidth (%d)",bw); break;
108 }
109 timf_msb = (comp >> 16) & 0xff;
110 timf_lsb = (comp & 0xffff);
111
112 // Update the timing offset ;
113 if (upd_offset > 0) {
114 if (!state->timing_offset_comp_done) {
115 msleep(200);
116 state->timing_offset_comp_done = 1;
117 }
118 tim_offset = rd(DIB3000MC_REG_TIMING_OFFS_MSB);
119 if ((tim_offset & 0x2000) == 0x2000)
120 tim_offset |= 0xC000;
121 if (fft == TRANSMISSION_MODE_2K)
122 tim_offset <<= 2;
123 state->timing_offset += tim_offset;
124 }
125
126 tim_offset = state->timing_offset;
127 if (tim_offset < 0) {
128 tim_sgn = 1;
129 tim_offset = -tim_offset;
130 } else
131 tim_sgn = 0;
132
133 comp1 = (u32)tim_offset * (u32)timf_lsb ;
134 comp2 = (u32)tim_offset * (u32)timf_msb ;
135 comp = ((comp1 >> 16) + comp2) >> 7;
136
137 if (tim_sgn == 0)
138 comp = (u32)(timf_msb << 16) + (u32) timf_lsb + comp;
139 else
140 comp = (u32)(timf_msb << 16) + (u32) timf_lsb - comp ;
141
142 timf_msb = (comp >> 16) & 0xff;
143 timf_lsb = comp & 0xffff;
144
145 wr(DIB3000MC_REG_TIMING_FREQ_MSB,timf_msb);
146 wr(DIB3000MC_REG_TIMING_FREQ_LSB,timf_lsb);
147 return 0;
148 }
149
150 static int dib3000mc_init_auto_scan(struct dib3000_state *state, fe_bandwidth_t bw, int boost)
151 {
152 if (boost) {
153 wr(DIB3000MC_REG_SCAN_BOOST,DIB3000MC_SCAN_BOOST_ON);
154 } else {
155 wr(DIB3000MC_REG_SCAN_BOOST,DIB3000MC_SCAN_BOOST_OFF);
156 }
157 switch (bw) {
158 case BANDWIDTH_8_MHZ:
159 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);
160 break;
161 case BANDWIDTH_7_MHZ:
162 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_7mhz);
163 break;
164 case BANDWIDTH_6_MHZ:
165 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_6mhz);
166 break;
167 /* case BANDWIDTH_5_MHZ:
168 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_5mhz);
169 break;*/
170 case BANDWIDTH_AUTO:
171 return -EOPNOTSUPP;
172 default:
173 err("unknown bandwidth value (%d).",bw);
174 return -EINVAL;
175 }
176 if (boost) {
177 u32 timeout = (rd(DIB3000MC_REG_BW_TIMOUT_MSB) << 16) +
178 rd(DIB3000MC_REG_BW_TIMOUT_LSB);
179 timeout *= 85; timeout >>= 7;
180 wr(DIB3000MC_REG_BW_TIMOUT_MSB,(timeout >> 16) & 0xffff);
181 wr(DIB3000MC_REG_BW_TIMOUT_LSB,timeout & 0xffff);
182 }
183 return 0;
184 }
185
186 static int dib3000mc_set_adp_cfg(struct dib3000_state *state, fe_modulation_t con)
187 {
188 switch (con) {
189 case QAM_64:
190 wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[2]);
191 break;
192 case QAM_16:
193 wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[1]);
194 break;
195 case QPSK:
196 wr_foreach(dib3000mc_reg_adp_cfg,dib3000mc_adp_cfg[0]);
197 break;
198 case QAM_AUTO:
199 break;
200 default:
201 warn("unkown constellation.");
202 break;
203 }
204 return 0;
205 }
206
207 static int dib3000mc_set_general_cfg(struct dib3000_state *state, struct dvb_frontend_parameters *fep, int *auto_val)
208 {
209 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
210 fe_code_rate_t fe_cr = FEC_NONE;
211 u8 fft=0, guard=0, qam=0, alpha=0, sel_hp=0, cr=0, hrch=0;
212 int seq;
213
214 switch (ofdm->transmission_mode) {
215 case TRANSMISSION_MODE_2K: fft = DIB3000_TRANSMISSION_MODE_2K; break;
216 case TRANSMISSION_MODE_8K: fft = DIB3000_TRANSMISSION_MODE_8K; break;
217 case TRANSMISSION_MODE_AUTO: break;
218 default: return -EINVAL;
219 }
220 switch (ofdm->guard_interval) {
221 case GUARD_INTERVAL_1_32: guard = DIB3000_GUARD_TIME_1_32; break;
222 case GUARD_INTERVAL_1_16: guard = DIB3000_GUARD_TIME_1_16; break;
223 case GUARD_INTERVAL_1_8: guard = DIB3000_GUARD_TIME_1_8; break;
224 case GUARD_INTERVAL_1_4: guard = DIB3000_GUARD_TIME_1_4; break;
225 case GUARD_INTERVAL_AUTO: break;
226 default: return -EINVAL;
227 }
228 switch (ofdm->constellation) {
229 case QPSK: qam = DIB3000_CONSTELLATION_QPSK; break;
230 case QAM_16: qam = DIB3000_CONSTELLATION_16QAM; break;
231 case QAM_64: qam = DIB3000_CONSTELLATION_64QAM; break;
232 case QAM_AUTO: break;
233 default: return -EINVAL;
234 }
235 switch (ofdm->hierarchy_information) {
236 case HIERARCHY_NONE: /* fall through */
237 case HIERARCHY_1: alpha = DIB3000_ALPHA_1; break;
238 case HIERARCHY_2: alpha = DIB3000_ALPHA_2; break;
239 case HIERARCHY_4: alpha = DIB3000_ALPHA_4; break;
240 case HIERARCHY_AUTO: break;
241 default: return -EINVAL;
242 }
243 if (ofdm->hierarchy_information == HIERARCHY_NONE) {
244 hrch = DIB3000_HRCH_OFF;
245 sel_hp = DIB3000_SELECT_HP;
246 fe_cr = ofdm->code_rate_HP;
247 } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
248 hrch = DIB3000_HRCH_ON;
249 sel_hp = DIB3000_SELECT_LP;
250 fe_cr = ofdm->code_rate_LP;
251 }
252 switch (fe_cr) {
253 case FEC_1_2: cr = DIB3000_FEC_1_2; break;
254 case FEC_2_3: cr = DIB3000_FEC_2_3; break;
255 case FEC_3_4: cr = DIB3000_FEC_3_4; break;
256 case FEC_5_6: cr = DIB3000_FEC_5_6; break;
257 case FEC_7_8: cr = DIB3000_FEC_7_8; break;
258 case FEC_NONE: break;
259 case FEC_AUTO: break;
260 default: return -EINVAL;
261 }
262
263 wr(DIB3000MC_REG_DEMOD_PARM,DIB3000MC_DEMOD_PARM(alpha,qam,guard,fft));
264 wr(DIB3000MC_REG_HRCH_PARM,DIB3000MC_HRCH_PARM(sel_hp,cr,hrch));
265
266 switch (fep->inversion) {
267 case INVERSION_OFF:
268 wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);
269 break;
270 case INVERSION_AUTO: /* fall through */
271 case INVERSION_ON:
272 wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_ON);
273 break;
274 default:
275 return -EINVAL;
276 }
277
278 seq = dib3000_seq
279 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
280 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
281 [fep->inversion == INVERSION_AUTO];
282
283 deb_setf("seq? %d\n", seq);
284 wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS(seq,1));
285 *auto_val = ofdm->constellation == QAM_AUTO ||
286 ofdm->hierarchy_information == HIERARCHY_AUTO ||
287 ofdm->guard_interval == GUARD_INTERVAL_AUTO ||
288 ofdm->transmission_mode == TRANSMISSION_MODE_AUTO ||
289 fe_cr == FEC_AUTO ||
290 fep->inversion == INVERSION_AUTO;
291 return 0;
292 }
293
294 static int dib3000mc_get_frontend(struct dvb_frontend* fe,
295 struct dvb_frontend_parameters *fep)
296 {
297 struct dib3000_state* state = fe->demodulator_priv;
298 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
299 fe_code_rate_t *cr;
300 u16 tps_val,cr_val;
301 int inv_test1,inv_test2;
302 u32 dds_val, threshold = 0x1000000;
303
304 if (!(rd(DIB3000MC_REG_LOCK_507) & DIB3000MC_LOCK_507))
305 return 0;
306
307 dds_val = (rd(DIB3000MC_REG_DDS_FREQ_MSB) << 16) + rd(DIB3000MC_REG_DDS_FREQ_LSB);
308 deb_getf("DDS_FREQ: %6x\n",dds_val);
309 if (dds_val < threshold)
310 inv_test1 = 0;
311 else if (dds_val == threshold)
312 inv_test1 = 1;
313 else
314 inv_test1 = 2;
315
316 dds_val = (rd(DIB3000MC_REG_SET_DDS_FREQ_MSB) << 16) + rd(DIB3000MC_REG_SET_DDS_FREQ_LSB);
317 deb_getf("DDS_SET_FREQ: %6x\n",dds_val);
318 if (dds_val < threshold)
319 inv_test2 = 0;
320 else if (dds_val == threshold)
321 inv_test2 = 1;
322 else
323 inv_test2 = 2;
324
325 fep->inversion =
326 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
327 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
328 INVERSION_ON : INVERSION_OFF;
329
330 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
331
332 fep->frequency = state->last_tuned_freq;
333 fep->u.ofdm.bandwidth= state->last_tuned_bw;
334
335 tps_val = rd(DIB3000MC_REG_TUNING_PARM);
336
337 switch (DIB3000MC_TP_QAM(tps_val)) {
338 case DIB3000_CONSTELLATION_QPSK:
339 deb_getf("QPSK ");
340 ofdm->constellation = QPSK;
341 break;
342 case DIB3000_CONSTELLATION_16QAM:
343 deb_getf("QAM16 ");
344 ofdm->constellation = QAM_16;
345 break;
346 case DIB3000_CONSTELLATION_64QAM:
347 deb_getf("QAM64 ");
348 ofdm->constellation = QAM_64;
349 break;
350 default:
351 err("Unexpected constellation returned by TPS (%d)", tps_val);
352 break;
353 }
354
355 if (DIB3000MC_TP_HRCH(tps_val)) {
356 deb_getf("HRCH ON ");
357 cr = &ofdm->code_rate_LP;
358 ofdm->code_rate_HP = FEC_NONE;
359 switch (DIB3000MC_TP_ALPHA(tps_val)) {
360 case DIB3000_ALPHA_0:
361 deb_getf("HIERARCHY_NONE ");
362 ofdm->hierarchy_information = HIERARCHY_NONE;
363 break;
364 case DIB3000_ALPHA_1:
365 deb_getf("HIERARCHY_1 ");
366 ofdm->hierarchy_information = HIERARCHY_1;
367 break;
368 case DIB3000_ALPHA_2:
369 deb_getf("HIERARCHY_2 ");
370 ofdm->hierarchy_information = HIERARCHY_2;
371 break;
372 case DIB3000_ALPHA_4:
373 deb_getf("HIERARCHY_4 ");
374 ofdm->hierarchy_information = HIERARCHY_4;
375 break;
376 default:
377 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
378 break;
379 }
380 cr_val = DIB3000MC_TP_FEC_CR_LP(tps_val);
381 } else {
382 deb_getf("HRCH OFF ");
383 cr = &ofdm->code_rate_HP;
384 ofdm->code_rate_LP = FEC_NONE;
385 ofdm->hierarchy_information = HIERARCHY_NONE;
386 cr_val = DIB3000MC_TP_FEC_CR_HP(tps_val);
387 }
388
389 switch (cr_val) {
390 case DIB3000_FEC_1_2:
391 deb_getf("FEC_1_2 ");
392 *cr = FEC_1_2;
393 break;
394 case DIB3000_FEC_2_3:
395 deb_getf("FEC_2_3 ");
396 *cr = FEC_2_3;
397 break;
398 case DIB3000_FEC_3_4:
399 deb_getf("FEC_3_4 ");
400 *cr = FEC_3_4;
401 break;
402 case DIB3000_FEC_5_6:
403 deb_getf("FEC_5_6 ");
404 *cr = FEC_4_5;
405 break;
406 case DIB3000_FEC_7_8:
407 deb_getf("FEC_7_8 ");
408 *cr = FEC_7_8;
409 break;
410 default:
411 err("Unexpected FEC returned by TPS (%d)", tps_val);
412 break;
413 }
414
415 switch (DIB3000MC_TP_GUARD(tps_val)) {
416 case DIB3000_GUARD_TIME_1_32:
417 deb_getf("GUARD_INTERVAL_1_32 ");
418 ofdm->guard_interval = GUARD_INTERVAL_1_32;
419 break;
420 case DIB3000_GUARD_TIME_1_16:
421 deb_getf("GUARD_INTERVAL_1_16 ");
422 ofdm->guard_interval = GUARD_INTERVAL_1_16;
423 break;
424 case DIB3000_GUARD_TIME_1_8:
425 deb_getf("GUARD_INTERVAL_1_8 ");
426 ofdm->guard_interval = GUARD_INTERVAL_1_8;
427 break;
428 case DIB3000_GUARD_TIME_1_4:
429 deb_getf("GUARD_INTERVAL_1_4 ");
430 ofdm->guard_interval = GUARD_INTERVAL_1_4;
431 break;
432 default:
433 err("Unexpected Guard Time returned by TPS (%d)", tps_val);
434 break;
435 }
436
437 switch (DIB3000MC_TP_FFT(tps_val)) {
438 case DIB3000_TRANSMISSION_MODE_2K:
439 deb_getf("TRANSMISSION_MODE_2K ");
440 ofdm->transmission_mode = TRANSMISSION_MODE_2K;
441 break;
442 case DIB3000_TRANSMISSION_MODE_8K:
443 deb_getf("TRANSMISSION_MODE_8K ");
444 ofdm->transmission_mode = TRANSMISSION_MODE_8K;
445 break;
446 default:
447 err("unexpected transmission mode return by TPS (%d)", tps_val);
448 break;
449 }
450 deb_getf("\n");
451
452 return 0;
453 }
454
455 static int dib3000mc_set_frontend(struct dvb_frontend* fe,
456 struct dvb_frontend_parameters *fep, int tuner)
457 {
458 struct dib3000_state* state = fe->demodulator_priv;
459 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
460 int search_state,auto_val;
461 u16 val;
462
463 if (tuner && state->config.pll_set) { /* initial call from dvb */
464 state->config.pll_set(fe,fep);
465
466 state->last_tuned_freq = fep->frequency;
467 // if (!scanboost) {
468 dib3000mc_set_timing(state,0,ofdm->transmission_mode,ofdm->bandwidth);
469 dib3000mc_init_auto_scan(state, ofdm->bandwidth, 0);
470 state->last_tuned_bw = ofdm->bandwidth;
471
472 wr_foreach(dib3000mc_reg_agc_bandwidth,dib3000mc_agc_bandwidth);
473 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_AGC);
474 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);
475
476 /* Default cfg isi offset adp */
477 wr_foreach(dib3000mc_reg_offset,dib3000mc_offset[0]);
478
479 wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT | DIB3000MC_ISI_INHIBIT);
480 dib3000mc_set_adp_cfg(state,ofdm->constellation);
481 wr(DIB3000MC_REG_UNK_133,DIB3000MC_UNK_133);
482
483 wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);
484 /* power smoothing */
485 if (ofdm->bandwidth != BANDWIDTH_8_MHZ) {
486 wr_foreach(dib3000mc_reg_bw,dib3000mc_bw[0]);
487 } else {
488 wr_foreach(dib3000mc_reg_bw,dib3000mc_bw[3]);
489 }
490 auto_val = 0;
491 dib3000mc_set_general_cfg(state,fep,&auto_val);
492 dib3000mc_set_impulse_noise(state,0,ofdm->constellation,ofdm->bandwidth);
493
494 val = rd(DIB3000MC_REG_DEMOD_PARM);
495 wr(DIB3000MC_REG_DEMOD_PARM,val|DIB3000MC_DEMOD_RST_DEMOD_ON);
496 wr(DIB3000MC_REG_DEMOD_PARM,val);
497 // }
498 msleep(70);
499
500 /* something has to be auto searched */
501 if (auto_val) {
502 int as_count=0;
503
504 deb_setf("autosearch enabled.\n");
505
506 val = rd(DIB3000MC_REG_DEMOD_PARM);
507 wr(DIB3000MC_REG_DEMOD_PARM,val | DIB3000MC_DEMOD_RST_AUTO_SRCH_ON);
508 wr(DIB3000MC_REG_DEMOD_PARM,val);
509
510 while ((search_state = dib3000_search_status(
511 rd(DIB3000MC_REG_AS_IRQ),1)) < 0 && as_count++ < 100)
512 msleep(10);
513
514 deb_info("search_state after autosearch %d after %d checks\n",search_state,as_count);
515
516 if (search_state == 1) {
517 struct dvb_frontend_parameters feps;
518 if (dib3000mc_get_frontend(fe, &feps) == 0) {
519 deb_setf("reading tuning data from frontend succeeded.\n");
520 return dib3000mc_set_frontend(fe, &feps, 0);
521 }
522 }
523 } else {
524 dib3000mc_set_impulse_noise(state,0,ofdm->transmission_mode,ofdm->bandwidth);
525 wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT|DIB3000MC_ISI_ACTIVATE);
526 dib3000mc_set_adp_cfg(state,ofdm->constellation);
527
528 /* set_offset_cfg */
529 wr_foreach(dib3000mc_reg_offset,
530 dib3000mc_offset[(ofdm->transmission_mode == TRANSMISSION_MODE_8K)+1]);
531 }
532 } else { /* second call, after autosearch (fka: set_WithKnownParams) */
533 // dib3000mc_set_timing(state,1,ofdm->transmission_mode,ofdm->bandwidth);
534
535 auto_val = 0;
536 dib3000mc_set_general_cfg(state,fep,&auto_val);
537 if (auto_val)
538 deb_info("auto_val is true, even though an auto search was already performed.\n");
539
540 dib3000mc_set_impulse_noise(state,0,ofdm->constellation,ofdm->bandwidth);
541
542 val = rd(DIB3000MC_REG_DEMOD_PARM);
543 wr(DIB3000MC_REG_DEMOD_PARM,val | DIB3000MC_DEMOD_RST_AUTO_SRCH_ON);
544 wr(DIB3000MC_REG_DEMOD_PARM,val);
545
546 msleep(30);
547
548 wr(DIB3000MC_REG_ISI,DIB3000MC_ISI_DEFAULT|DIB3000MC_ISI_ACTIVATE);
549 dib3000mc_set_adp_cfg(state,ofdm->constellation);
550 wr_foreach(dib3000mc_reg_offset,
551 dib3000mc_offset[(ofdm->transmission_mode == TRANSMISSION_MODE_8K)+1]);
552 }
553 return 0;
554 }
555
556 static int dib3000mc_fe_init(struct dvb_frontend* fe, int mobile_mode)
557 {
558 struct dib3000_state *state = fe->demodulator_priv;
559 deb_info("init start\n");
560
561 state->timing_offset = 0;
562 state->timing_offset_comp_done = 0;
563
564 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_CONFIG);
565 wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);
566 wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_UP);
567 wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_PUP_MOBILE);
568 wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_UP);
569 wr(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_INIT);
570
571 wr(DIB3000MC_REG_RST_UNC,DIB3000MC_RST_UNC_OFF);
572 wr(DIB3000MC_REG_UNK_19,DIB3000MC_UNK_19);
573
574 wr(33,5);
575 wr(36,81);
576 wr(DIB3000MC_REG_UNK_88,DIB3000MC_UNK_88);
577
578 wr(DIB3000MC_REG_UNK_99,DIB3000MC_UNK_99);
579 wr(DIB3000MC_REG_UNK_111,DIB3000MC_UNK_111_PH_N_MODE_0); /* phase noise algo off */
580
581 /* mobile mode - portable reception */
582 wr_foreach(dib3000mc_reg_mobile_mode,dib3000mc_mobile_mode[1]);
583
584 /* TUNER_PANASONIC_ENV57H12D5: */
585 wr_foreach(dib3000mc_reg_agc_bandwidth,dib3000mc_agc_bandwidth);
586 wr_foreach(dib3000mc_reg_agc_bandwidth_general,dib3000mc_agc_bandwidth_general);
587 wr_foreach(dib3000mc_reg_agc,dib3000mc_agc_tuner[1]);
588
589 wr(DIB3000MC_REG_UNK_110,DIB3000MC_UNK_110);
590 wr(26,0x6680);
591 wr(DIB3000MC_REG_UNK_1,DIB3000MC_UNK_1);
592 wr(DIB3000MC_REG_UNK_2,DIB3000MC_UNK_2);
593 wr(DIB3000MC_REG_UNK_3,DIB3000MC_UNK_3);
594 wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS_DEFAULT);
595
596 wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);
597 wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);
598
599 wr(DIB3000MC_REG_UNK_4,DIB3000MC_UNK_4);
600
601 wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);
602 wr(DIB3000MC_REG_SET_DDS_FREQ_LSB,DIB3000MC_DDS_FREQ_LSB);
603
604 dib3000mc_set_timing(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);
605 // wr_foreach(dib3000mc_reg_timing_freq,dib3000mc_timing_freq[3]);
606
607 wr(DIB3000MC_REG_UNK_120,DIB3000MC_UNK_120);
608 wr(DIB3000MC_REG_UNK_134,DIB3000MC_UNK_134);
609 wr(DIB3000MC_REG_FEC_CFG,DIB3000MC_FEC_CFG);
610
611 wr(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);
612
613 dib3000mc_set_impulse_noise(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);
614
615 /* output mode control, just the MPEG2_SLAVE */
616 // set_or(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);
617 wr(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);
618 wr(DIB3000MC_REG_SMO_MODE,DIB3000MC_SMO_MODE_SLAVE);
619 wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_SLAVE);
620 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_SLAVE);
621
622 /* MPEG2_PARALLEL_CONTINUOUS_CLOCK
623 wr(DIB3000MC_REG_OUTMODE,
624 DIB3000MC_SET_OUTMODE(DIB3000MC_OM_PAR_CONT_CLK,
625 rd(DIB3000MC_REG_OUTMODE)));
626
627 wr(DIB3000MC_REG_SMO_MODE,
628 DIB3000MC_SMO_MODE_DEFAULT |
629 DIB3000MC_SMO_MODE_188);
630
631 wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_DEFAULT);
632 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);
633 */
634
635 /* diversity */
636 wr(DIB3000MC_REG_DIVERSITY1,DIB3000MC_DIVERSITY1_DEFAULT);
637 wr(DIB3000MC_REG_DIVERSITY2,DIB3000MC_DIVERSITY2_DEFAULT);
638
639 set_and(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);
640
641 set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_DIV_IN_OFF);
642
643 if (state->config.pll_init)
644 state->config.pll_init(fe);
645
646 deb_info("init end\n");
647 return 0;
648 }
649 static int dib3000mc_read_status(struct dvb_frontend* fe, fe_status_t *stat)
650 {
651 struct dib3000_state* state = fe->demodulator_priv;
652 u16 lock = rd(DIB3000MC_REG_LOCKING);
653
654 *stat = 0;
655 if (DIB3000MC_AGC_LOCK(lock))
656 *stat |= FE_HAS_SIGNAL;
657 if (DIB3000MC_CARRIER_LOCK(lock))
658 *stat |= FE_HAS_CARRIER;
659 if (DIB3000MC_TPS_LOCK(lock))
660 *stat |= FE_HAS_VITERBI;
661 if (DIB3000MC_MPEG_SYNC_LOCK(lock))
662 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
663
664 deb_stat("actual status is %2x fifo_level: %x,244: %x, 206: %x, 207: %x, 1040: %x\n",*stat,rd(510),rd(244),rd(206),rd(207),rd(1040));
665
666 return 0;
667 }
668
669 static int dib3000mc_read_ber(struct dvb_frontend* fe, u32 *ber)
670 {
671 struct dib3000_state* state = fe->demodulator_priv;
672 *ber = ((rd(DIB3000MC_REG_BER_MSB) << 16) | rd(DIB3000MC_REG_BER_LSB));
673 return 0;
674 }
675
676 static int dib3000mc_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
677 {
678 struct dib3000_state* state = fe->demodulator_priv;
679
680 *unc = rd(DIB3000MC_REG_PACKET_ERRORS);
681 return 0;
682 }
683
684 /* see dib3000mb.c for calculation comments */
685 static int dib3000mc_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
686 {
687 struct dib3000_state* state = fe->demodulator_priv;
688 u16 val = rd(DIB3000MC_REG_SIGNAL_NOISE_LSB);
689 *strength = (((val >> 6) & 0xff) << 8) + (val & 0x3f);
690
691 deb_stat("signal: mantisse = %d, exponent = %d\n",(*strength >> 8) & 0xff, *strength & 0xff);
692 return 0;
693 }
694
695 /* see dib3000mb.c for calculation comments */
696 static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr)
697 {
698 struct dib3000_state* state = fe->demodulator_priv;
699 u16 val = rd(DIB3000MC_REG_SIGNAL_NOISE_LSB),
700 val2 = rd(DIB3000MC_REG_SIGNAL_NOISE_MSB);
701 u16 sig,noise;
702
703 sig = (((val >> 6) & 0xff) << 8) + (val & 0x3f);
704 noise = (((val >> 4) & 0xff) << 8) + ((val & 0xf) << 2) + ((val2 >> 14) & 0x3);
705 if (noise == 0)
706 *snr = 0xffff;
707 else
708 *snr = (u16) sig/noise;
709
710 deb_stat("signal: mantisse = %d, exponent = %d\n",(sig >> 8) & 0xff, sig & 0xff);
711 deb_stat("noise: mantisse = %d, exponent = %d\n",(noise >> 8) & 0xff, noise & 0xff);
712 deb_stat("snr: %d\n",*snr);
713 return 0;
714 }
715
716 static int dib3000mc_sleep(struct dvb_frontend* fe)
717 {
718 struct dib3000_state* state = fe->demodulator_priv;
719
720 set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_PWR_DOWN);
721 wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_DOWN);
722 wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_POWER_DOWN);
723 wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_DOWN);
724 return 0;
725 }
726
727 static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
728 {
729 tune->min_delay_ms = 1000;
730 return 0;
731 }
732
733 static int dib3000mc_fe_init_nonmobile(struct dvb_frontend* fe)
734 {
735 return dib3000mc_fe_init(fe, 0);
736 }
737
738 static int dib3000mc_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
739 {
740 return dib3000mc_set_frontend(fe, fep, 1);
741 }
742
743 static void dib3000mc_release(struct dvb_frontend* fe)
744 {
745 struct dib3000_state *state = fe->demodulator_priv;
746 kfree(state);
747 }
748
749 /* pid filter and transfer stuff */
750 static int dib3000mc_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
751 {
752 struct dib3000_state *state = fe->demodulator_priv;
753 pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
754 wr(index+DIB3000MC_REG_FIRST_PID,pid);
755 return 0;
756 }
757
758 static int dib3000mc_fifo_control(struct dvb_frontend *fe, int onoff)
759 {
760 struct dib3000_state *state = fe->demodulator_priv;
761 u16 tmp = rd(DIB3000MC_REG_SMO_MODE);
762
763 deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
764
765 if (onoff) {
766 deb_xfer("%d %x\n",tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH,tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH);
767 wr(DIB3000MC_REG_SMO_MODE,tmp & DIB3000MC_SMO_MODE_FIFO_UNFLUSH);
768 } else {
769 deb_xfer("%d %x\n",tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH,tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH);
770 wr(DIB3000MC_REG_SMO_MODE,tmp | DIB3000MC_SMO_MODE_FIFO_FLUSH);
771 }
772 return 0;
773 }
774
775 static int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff)
776 {
777 struct dib3000_state *state = fe->demodulator_priv;
778 u16 tmp = rd(DIB3000MC_REG_SMO_MODE);
779
780 deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
781
782 if (onoff) {
783 wr(DIB3000MC_REG_SMO_MODE,tmp | DIB3000MC_SMO_MODE_PID_PARSE);
784 } else {
785 wr(DIB3000MC_REG_SMO_MODE,tmp & DIB3000MC_SMO_MODE_NO_PID_PARSE);
786 }
787 return 0;
788 }
789
790 static int dib3000mc_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
791 {
792 struct dib3000_state *state = fe->demodulator_priv;
793 if (onoff) {
794 wr(DIB3000MC_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
795 } else {
796 wr(DIB3000MC_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
797 }
798 return 0;
799 }
800
801 static int dib3000mc_demod_init(struct dib3000_state *state)
802 {
803 u16 default_addr = 0x0a;
804 /* first init */
805 if (state->config.demod_address != default_addr) {
806 deb_info("initializing the demod the first time. Setting demod addr to 0x%x\n",default_addr);
807 wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);
808 wr(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_PAR_CONT_CLK);
809
810 wr(DIB3000MC_REG_RST_I2C_ADDR,
811 DIB3000MC_DEMOD_ADDR(default_addr) |
812 DIB3000MC_DEMOD_ADDR_ON);
813
814 state->config.demod_address = default_addr;
815
816 wr(DIB3000MC_REG_RST_I2C_ADDR,
817 DIB3000MC_DEMOD_ADDR(default_addr));
818 } else
819 deb_info("demod is already initialized. Demod addr: 0x%x\n",state->config.demod_address);
820 return 0;
821 }
822
823
824 static struct dvb_frontend_ops dib3000mc_ops;
825
826 struct dvb_frontend* dib3000mc_attach(const struct dib3000_config* config,
827 struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
828 {
829 struct dib3000_state* state = NULL;
830 u16 devid;
831
832 /* allocate memory for the internal state */
833 state = kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
834 if (state == NULL)
835 goto error;
836 memset(state,0,sizeof(struct dib3000_state));
837
838 /* setup the state */
839 state->i2c = i2c;
840 memcpy(&state->config,config,sizeof(struct dib3000_config));
841 memcpy(&state->ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops));
842
843 /* check for the correct demod */
844 if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
845 goto error;
846
847 devid = rd(DIB3000_REG_DEVICE_ID);
848 if (devid != DIB3000MC_DEVICE_ID && devid != DIB3000P_DEVICE_ID)
849 goto error;
850
851 switch (devid) {
852 case DIB3000MC_DEVICE_ID:
853 info("Found a DiBcom 3000M-C, interesting...");
854 break;
855 case DIB3000P_DEVICE_ID:
856 info("Found a DiBcom 3000P.");
857 break;
858 }
859
860 /* create dvb_frontend */
861 state->frontend.ops = &state->ops;
862 state->frontend.demodulator_priv = state;
863
864 /* set the xfer operations */
865 xfer_ops->pid_parse = dib3000mc_pid_parse;
866 xfer_ops->fifo_ctrl = dib3000mc_fifo_control;
867 xfer_ops->pid_ctrl = dib3000mc_pid_control;
868 xfer_ops->tuner_pass_ctrl = dib3000mc_tuner_pass_ctrl;
869
870 dib3000mc_demod_init(state);
871
872 return &state->frontend;
873
874 error:
875 kfree(state);
876 return NULL;
877 }
878
879 static struct dvb_frontend_ops dib3000mc_ops = {
880
881 .info = {
882 .name = "DiBcom 3000P/M-C DVB-T",
883 .type = FE_OFDM,
884 .frequency_min = 44250000,
885 .frequency_max = 867250000,
886 .frequency_stepsize = 62500,
887 .caps = FE_CAN_INVERSION_AUTO |
888 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
889 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
890 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
891 FE_CAN_TRANSMISSION_MODE_AUTO |
892 FE_CAN_GUARD_INTERVAL_AUTO |
893 FE_CAN_RECOVER |
894 FE_CAN_HIERARCHY_AUTO,
895 },
896
897 .release = dib3000mc_release,
898
899 .init = dib3000mc_fe_init_nonmobile,
900 .sleep = dib3000mc_sleep,
901
902 .set_frontend = dib3000mc_set_frontend_and_tuner,
903 .get_frontend = dib3000mc_get_frontend,
904 .get_tune_settings = dib3000mc_fe_get_tune_settings,
905
906 .read_status = dib3000mc_read_status,
907 .read_ber = dib3000mc_read_ber,
908 .read_signal_strength = dib3000mc_read_signal_strength,
909 .read_snr = dib3000mc_read_snr,
910 .read_ucblocks = dib3000mc_read_unc_blocks,
911 };
912
913 MODULE_AUTHOR(DRIVER_AUTHOR);
914 MODULE_DESCRIPTION(DRIVER_DESC);
915 MODULE_LICENSE("GPL");
916
917 EXPORT_SYMBOL(dib3000mc_attach);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree