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dca: redesign locks to fix deadlocks
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / sata_promise.c
blobb26885fb8511588e5c5f4f881857a09a836dc031
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "2.12"
50
51 enum {
52 PDC_MAX_PORTS = 4,
53 PDC_MMIO_BAR = 3,
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55
56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_FLASH_CTL = 0x44, /* Flash control register */
59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
60 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
61 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
63
64 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
65 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
66 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
67 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
68 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
69 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
70 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
71 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
72 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
73 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
74 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
75 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
76
77 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
78 PDC_PHYMODE4 = 0x14,
79
80 /* PDC_GLOBAL_CTL bit definitions */
81 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
82 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
83 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
84 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
85 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
86 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
87 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
88 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
89 PDC_DRIVE_ERR = (1 << 21), /* drive error */
90 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
91 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
92 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
93 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
94 PDC2_ATA_DMA_CNT_ERR,
95 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
96 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
97 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
98 PDC1_ERR_MASK | PDC2_ERR_MASK,
99
100 board_2037x = 0, /* FastTrak S150 TX2plus */
101 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
102 board_20319 = 2, /* FastTrak S150 TX4 */
103 board_20619 = 3, /* FastTrak TX4000 */
104 board_2057x = 4, /* SATAII150 Tx2plus */
105 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
106 board_40518 = 6, /* SATAII150 Tx4 */
107
108 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
109
110 /* Sequence counter control registers bit definitions */
111 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
112
113 /* Feature register values */
114 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
115 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
116
117 /* Device/Head register values */
118 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
119
120 /* PDC_CTLSTAT bit definitions */
121 PDC_DMA_ENABLE = (1 << 7),
122 PDC_IRQ_DISABLE = (1 << 10),
123 PDC_RESET = (1 << 11), /* HDMA reset */
124
125 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
126 ATA_FLAG_MMIO |
127 ATA_FLAG_PIO_POLLING,
128
129 /* ap->flags bits */
130 PDC_FLAG_GEN_II = (1 << 24),
131 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
132 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
133 };
134
135 struct pdc_port_priv {
136 u8 *pkt;
137 dma_addr_t pkt_dma;
138 };
139
140 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
141 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
142 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
143 static int pdc_common_port_start(struct ata_port *ap);
144 static int pdc_sata_port_start(struct ata_port *ap);
145 static void pdc_qc_prep(struct ata_queued_cmd *qc);
146 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
147 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
148 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
149 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
150 static void pdc_irq_clear(struct ata_port *ap);
151 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
152 static void pdc_freeze(struct ata_port *ap);
153 static void pdc_sata_freeze(struct ata_port *ap);
154 static void pdc_thaw(struct ata_port *ap);
155 static void pdc_sata_thaw(struct ata_port *ap);
156 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
157 unsigned long deadline);
158 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
159 unsigned long deadline);
160 static void pdc_error_handler(struct ata_port *ap);
161 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
162 static int pdc_pata_cable_detect(struct ata_port *ap);
163 static int pdc_sata_cable_detect(struct ata_port *ap);
164
165 static struct scsi_host_template pdc_ata_sht = {
166 ATA_BASE_SHT(DRV_NAME),
167 .sg_tablesize = PDC_MAX_PRD,
168 .dma_boundary = ATA_DMA_BOUNDARY,
169 };
170
171 static const struct ata_port_operations pdc_common_ops = {
172 .inherits = &ata_sff_port_ops,
173
174 .sff_tf_load = pdc_tf_load_mmio,
175 .sff_exec_command = pdc_exec_command_mmio,
176 .check_atapi_dma = pdc_check_atapi_dma,
177 .qc_prep = pdc_qc_prep,
178 .qc_issue = pdc_qc_issue,
179 .sff_irq_clear = pdc_irq_clear,
180
181 .post_internal_cmd = pdc_post_internal_cmd,
182 .error_handler = pdc_error_handler,
183 };
184
185 static struct ata_port_operations pdc_sata_ops = {
186 .inherits = &pdc_common_ops,
187 .cable_detect = pdc_sata_cable_detect,
188 .freeze = pdc_sata_freeze,
189 .thaw = pdc_sata_thaw,
190 .scr_read = pdc_sata_scr_read,
191 .scr_write = pdc_sata_scr_write,
192 .port_start = pdc_sata_port_start,
193 .hardreset = pdc_sata_hardreset,
194 };
195
196 /* First-generation chips need a more restrictive ->check_atapi_dma op */
197 static struct ata_port_operations pdc_old_sata_ops = {
198 .inherits = &pdc_sata_ops,
199 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
200 };
201
202 static struct ata_port_operations pdc_pata_ops = {
203 .inherits = &pdc_common_ops,
204 .cable_detect = pdc_pata_cable_detect,
205 .freeze = pdc_freeze,
206 .thaw = pdc_thaw,
207 .port_start = pdc_common_port_start,
208 .softreset = pdc_pata_softreset,
209 };
210
211 static const struct ata_port_info pdc_port_info[] = {
212 [board_2037x] =
213 {
214 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
215 PDC_FLAG_SATA_PATA,
216 .pio_mask = 0x1f, /* pio0-4 */
217 .mwdma_mask = 0x07, /* mwdma0-2 */
218 .udma_mask = ATA_UDMA6,
219 .port_ops = &pdc_old_sata_ops,
220 },
221
222 [board_2037x_pata] =
223 {
224 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
225 .pio_mask = 0x1f, /* pio0-4 */
226 .mwdma_mask = 0x07, /* mwdma0-2 */
227 .udma_mask = ATA_UDMA6,
228 .port_ops = &pdc_pata_ops,
229 },
230
231 [board_20319] =
232 {
233 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
234 PDC_FLAG_4_PORTS,
235 .pio_mask = 0x1f, /* pio0-4 */
236 .mwdma_mask = 0x07, /* mwdma0-2 */
237 .udma_mask = ATA_UDMA6,
238 .port_ops = &pdc_old_sata_ops,
239 },
240
241 [board_20619] =
242 {
243 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
244 PDC_FLAG_4_PORTS,
245 .pio_mask = 0x1f, /* pio0-4 */
246 .mwdma_mask = 0x07, /* mwdma0-2 */
247 .udma_mask = ATA_UDMA6,
248 .port_ops = &pdc_pata_ops,
249 },
250
251 [board_2057x] =
252 {
253 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
254 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
255 .pio_mask = 0x1f, /* pio0-4 */
256 .mwdma_mask = 0x07, /* mwdma0-2 */
257 .udma_mask = ATA_UDMA6,
258 .port_ops = &pdc_sata_ops,
259 },
260
261 [board_2057x_pata] =
262 {
263 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
264 PDC_FLAG_GEN_II,
265 .pio_mask = 0x1f, /* pio0-4 */
266 .mwdma_mask = 0x07, /* mwdma0-2 */
267 .udma_mask = ATA_UDMA6,
268 .port_ops = &pdc_pata_ops,
269 },
270
271 [board_40518] =
272 {
273 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
274 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
275 .pio_mask = 0x1f, /* pio0-4 */
276 .mwdma_mask = 0x07, /* mwdma0-2 */
277 .udma_mask = ATA_UDMA6,
278 .port_ops = &pdc_sata_ops,
279 },
280 };
281
282 static const struct pci_device_id pdc_ata_pci_tbl[] = {
283 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
284 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
285 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
286 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
287 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
288 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
289 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
290 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
291 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
292 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
293
294 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
295 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
296 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
297 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
298 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
299 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
300
301 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
302
303 { } /* terminate list */
304 };
305
306 static struct pci_driver pdc_ata_pci_driver = {
307 .name = DRV_NAME,
308 .id_table = pdc_ata_pci_tbl,
309 .probe = pdc_ata_init_one,
310 .remove = ata_pci_remove_one,
311 };
312
313 static int pdc_common_port_start(struct ata_port *ap)
314 {
315 struct device *dev = ap->host->dev;
316 struct pdc_port_priv *pp;
317 int rc;
318
319 rc = ata_port_start(ap);
320 if (rc)
321 return rc;
322
323 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
324 if (!pp)
325 return -ENOMEM;
326
327 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
328 if (!pp->pkt)
329 return -ENOMEM;
330
331 ap->private_data = pp;
332
333 return 0;
334 }
335
336 static int pdc_sata_port_start(struct ata_port *ap)
337 {
338 int rc;
339
340 rc = pdc_common_port_start(ap);
341 if (rc)
342 return rc;
343
344 /* fix up PHYMODE4 align timing */
345 if (ap->flags & PDC_FLAG_GEN_II) {
346 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
347 unsigned int tmp;
348
349 tmp = readl(sata_mmio + PDC_PHYMODE4);
350 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
351 writel(tmp, sata_mmio + PDC_PHYMODE4);
352 }
353
354 return 0;
355 }
356
357 static void pdc_reset_port(struct ata_port *ap)
358 {
359 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
360 unsigned int i;
361 u32 tmp;
362
363 for (i = 11; i > 0; i--) {
364 tmp = readl(ata_ctlstat_mmio);
365 if (tmp & PDC_RESET)
366 break;
367
368 udelay(100);
369
370 tmp |= PDC_RESET;
371 writel(tmp, ata_ctlstat_mmio);
372 }
373
374 tmp &= ~PDC_RESET;
375 writel(tmp, ata_ctlstat_mmio);
376 readl(ata_ctlstat_mmio); /* flush */
377 }
378
379 static int pdc_pata_cable_detect(struct ata_port *ap)
380 {
381 u8 tmp;
382 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
383
384 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
385 if (tmp & 0x01)
386 return ATA_CBL_PATA40;
387 return ATA_CBL_PATA80;
388 }
389
390 static int pdc_sata_cable_detect(struct ata_port *ap)
391 {
392 return ATA_CBL_SATA;
393 }
394
395 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
396 {
397 if (sc_reg > SCR_CONTROL)
398 return -EINVAL;
399 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
400 return 0;
401 }
402
403 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
404 {
405 if (sc_reg > SCR_CONTROL)
406 return -EINVAL;
407 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
408 return 0;
409 }
410
411 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
412 {
413 struct ata_port *ap = qc->ap;
414 dma_addr_t sg_table = ap->prd_dma;
415 unsigned int cdb_len = qc->dev->cdb_len;
416 u8 *cdb = qc->cdb;
417 struct pdc_port_priv *pp = ap->private_data;
418 u8 *buf = pp->pkt;
419 __le32 *buf32 = (__le32 *) buf;
420 unsigned int dev_sel, feature;
421
422 /* set control bits (byte 0), zero delay seq id (byte 3),
423 * and seq id (byte 2)
424 */
425 switch (qc->tf.protocol) {
426 case ATAPI_PROT_DMA:
427 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
428 buf32[0] = cpu_to_le32(PDC_PKT_READ);
429 else
430 buf32[0] = 0;
431 break;
432 case ATAPI_PROT_NODATA:
433 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
434 break;
435 default:
436 BUG();
437 break;
438 }
439 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
440 buf32[2] = 0; /* no next-packet */
441
442 /* select drive */
443 if (sata_scr_valid(&ap->link))
444 dev_sel = PDC_DEVICE_SATA;
445 else
446 dev_sel = qc->tf.device;
447
448 buf[12] = (1 << 5) | ATA_REG_DEVICE;
449 buf[13] = dev_sel;
450 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
451 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
452
453 buf[16] = (1 << 5) | ATA_REG_NSECT;
454 buf[17] = qc->tf.nsect;
455 buf[18] = (1 << 5) | ATA_REG_LBAL;
456 buf[19] = qc->tf.lbal;
457
458 /* set feature and byte counter registers */
459 if (qc->tf.protocol != ATAPI_PROT_DMA)
460 feature = PDC_FEATURE_ATAPI_PIO;
461 else
462 feature = PDC_FEATURE_ATAPI_DMA;
463
464 buf[20] = (1 << 5) | ATA_REG_FEATURE;
465 buf[21] = feature;
466 buf[22] = (1 << 5) | ATA_REG_BYTEL;
467 buf[23] = qc->tf.lbam;
468 buf[24] = (1 << 5) | ATA_REG_BYTEH;
469 buf[25] = qc->tf.lbah;
470
471 /* send ATAPI packet command 0xA0 */
472 buf[26] = (1 << 5) | ATA_REG_CMD;
473 buf[27] = qc->tf.command;
474
475 /* select drive and check DRQ */
476 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
477 buf[29] = dev_sel;
478
479 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
480 BUG_ON(cdb_len & ~0x1E);
481
482 /* append the CDB as the final part */
483 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
484 memcpy(buf+31, cdb, cdb_len);
485 }
486
487 /**
488 * pdc_fill_sg - Fill PCI IDE PRD table
489 * @qc: Metadata associated with taskfile to be transferred
490 *
491 * Fill PCI IDE PRD (scatter-gather) table with segments
492 * associated with the current disk command.
493 * Make sure hardware does not choke on it.
494 *
495 * LOCKING:
496 * spin_lock_irqsave(host lock)
497 *
498 */
499 static void pdc_fill_sg(struct ata_queued_cmd *qc)
500 {
501 struct ata_port *ap = qc->ap;
502 struct scatterlist *sg;
503 const u32 SG_COUNT_ASIC_BUG = 41*4;
504 unsigned int si, idx;
505 u32 len;
506
507 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
508 return;
509
510 idx = 0;
511 for_each_sg(qc->sg, sg, qc->n_elem, si) {
512 u32 addr, offset;
513 u32 sg_len;
514
515 /* determine if physical DMA addr spans 64K boundary.
516 * Note h/w doesn't support 64-bit, so we unconditionally
517 * truncate dma_addr_t to u32.
518 */
519 addr = (u32) sg_dma_address(sg);
520 sg_len = sg_dma_len(sg);
521
522 while (sg_len) {
523 offset = addr & 0xffff;
524 len = sg_len;
525 if ((offset + sg_len) > 0x10000)
526 len = 0x10000 - offset;
527
528 ap->prd[idx].addr = cpu_to_le32(addr);
529 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
530 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
531
532 idx++;
533 sg_len -= len;
534 addr += len;
535 }
536 }
537
538 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
539
540 if (len > SG_COUNT_ASIC_BUG) {
541 u32 addr;
542
543 VPRINTK("Splitting last PRD.\n");
544
545 addr = le32_to_cpu(ap->prd[idx - 1].addr);
546 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
547 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
548
549 addr = addr + len - SG_COUNT_ASIC_BUG;
550 len = SG_COUNT_ASIC_BUG;
551 ap->prd[idx].addr = cpu_to_le32(addr);
552 ap->prd[idx].flags_len = cpu_to_le32(len);
553 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
554
555 idx++;
556 }
557
558 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
559 }
560
561 static void pdc_qc_prep(struct ata_queued_cmd *qc)
562 {
563 struct pdc_port_priv *pp = qc->ap->private_data;
564 unsigned int i;
565
566 VPRINTK("ENTER\n");
567
568 switch (qc->tf.protocol) {
569 case ATA_PROT_DMA:
570 pdc_fill_sg(qc);
571 /*FALLTHROUGH*/
572 case ATA_PROT_NODATA:
573 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
574 qc->dev->devno, pp->pkt);
575 if (qc->tf.flags & ATA_TFLAG_LBA48)
576 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
577 else
578 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
579 pdc_pkt_footer(&qc->tf, pp->pkt, i);
580 break;
581 case ATAPI_PROT_PIO:
582 pdc_fill_sg(qc);
583 break;
584 case ATAPI_PROT_DMA:
585 pdc_fill_sg(qc);
586 /*FALLTHROUGH*/
587 case ATAPI_PROT_NODATA:
588 pdc_atapi_pkt(qc);
589 break;
590 default:
591 break;
592 }
593 }
594
595 static int pdc_is_sataii_tx4(unsigned long flags)
596 {
597 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
598 return (flags & mask) == mask;
599 }
600
601 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
602 int is_sataii_tx4)
603 {
604 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
605 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
606 }
607
608 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
609 {
610 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
611 }
612
613 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
614 {
615 const struct ata_host *host = ap->host;
616 unsigned int nr_ports = pdc_sata_nr_ports(ap);
617 unsigned int i;
618
619 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
620 ;
621 BUG_ON(i >= nr_ports);
622 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
623 }
624
625 static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap)
626 {
627 return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR;
628 }
629
630 static void pdc_freeze(struct ata_port *ap)
631 {
632 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
633 u32 tmp;
634
635 tmp = readl(ata_mmio + PDC_CTLSTAT);
636 tmp |= PDC_IRQ_DISABLE;
637 tmp &= ~PDC_DMA_ENABLE;
638 writel(tmp, ata_mmio + PDC_CTLSTAT);
639 readl(ata_mmio + PDC_CTLSTAT); /* flush */
640 }
641
642 static void pdc_sata_freeze(struct ata_port *ap)
643 {
644 struct ata_host *host = ap->host;
645 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
646 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
647 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
648 u32 hotplug_status;
649
650 /* Disable hotplug events on this port.
651 *
652 * Locking:
653 * 1) hotplug register accesses must be serialised via host->lock
654 * 2) ap->lock == &ap->host->lock
655 * 3) ->freeze() and ->thaw() are called with ap->lock held
656 */
657 hotplug_status = readl(host_mmio + hotplug_offset);
658 hotplug_status |= 0x11 << (ata_no + 16);
659 writel(hotplug_status, host_mmio + hotplug_offset);
660 readl(host_mmio + hotplug_offset); /* flush */
661
662 pdc_freeze(ap);
663 }
664
665 static void pdc_thaw(struct ata_port *ap)
666 {
667 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
668 u32 tmp;
669
670 /* clear IRQ */
671 readl(ata_mmio + PDC_COMMAND);
672
673 /* turn IRQ back on */
674 tmp = readl(ata_mmio + PDC_CTLSTAT);
675 tmp &= ~PDC_IRQ_DISABLE;
676 writel(tmp, ata_mmio + PDC_CTLSTAT);
677 readl(ata_mmio + PDC_CTLSTAT); /* flush */
678 }
679
680 static void pdc_sata_thaw(struct ata_port *ap)
681 {
682 struct ata_host *host = ap->host;
683 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
684 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
685 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
686 u32 hotplug_status;
687
688 pdc_thaw(ap);
689
690 /* Enable hotplug events on this port.
691 * Locking: see pdc_sata_freeze().
692 */
693 hotplug_status = readl(host_mmio + hotplug_offset);
694 hotplug_status |= 0x11 << ata_no;
695 hotplug_status &= ~(0x11 << (ata_no + 16));
696 writel(hotplug_status, host_mmio + hotplug_offset);
697 readl(host_mmio + hotplug_offset); /* flush */
698 }
699
700 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
701 unsigned long deadline)
702 {
703 pdc_reset_port(link->ap);
704 return ata_sff_softreset(link, class, deadline);
705 }
706
707 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
708 unsigned long deadline)
709 {
710 pdc_reset_port(link->ap);
711 return sata_sff_hardreset(link, class, deadline);
712 }
713
714 static void pdc_error_handler(struct ata_port *ap)
715 {
716 if (!(ap->pflags & ATA_PFLAG_FROZEN))
717 pdc_reset_port(ap);
718
719 ata_std_error_handler(ap);
720 }
721
722 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
723 {
724 struct ata_port *ap = qc->ap;
725
726 /* make DMA engine forget about the failed command */
727 if (qc->flags & ATA_QCFLAG_FAILED)
728 pdc_reset_port(ap);
729 }
730
731 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
732 u32 port_status, u32 err_mask)
733 {
734 struct ata_eh_info *ehi = &ap->link.eh_info;
735 unsigned int ac_err_mask = 0;
736
737 ata_ehi_clear_desc(ehi);
738 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
739 port_status &= err_mask;
740
741 if (port_status & PDC_DRIVE_ERR)
742 ac_err_mask |= AC_ERR_DEV;
743 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
744 ac_err_mask |= AC_ERR_HSM;
745 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
746 ac_err_mask |= AC_ERR_ATA_BUS;
747 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
748 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
749 ac_err_mask |= AC_ERR_HOST_BUS;
750
751 if (sata_scr_valid(&ap->link)) {
752 u32 serror;
753
754 pdc_sata_scr_read(ap, SCR_ERROR, &serror);
755 ehi->serror |= serror;
756 }
757
758 qc->err_mask |= ac_err_mask;
759
760 pdc_reset_port(ap);
761
762 ata_port_abort(ap);
763 }
764
765 static unsigned int pdc_host_intr(struct ata_port *ap,
766 struct ata_queued_cmd *qc)
767 {
768 unsigned int handled = 0;
769 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
770 u32 port_status, err_mask;
771
772 err_mask = PDC_ERR_MASK;
773 if (ap->flags & PDC_FLAG_GEN_II)
774 err_mask &= ~PDC1_ERR_MASK;
775 else
776 err_mask &= ~PDC2_ERR_MASK;
777 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
778 if (unlikely(port_status & err_mask)) {
779 pdc_error_intr(ap, qc, port_status, err_mask);
780 return 1;
781 }
782
783 switch (qc->tf.protocol) {
784 case ATA_PROT_DMA:
785 case ATA_PROT_NODATA:
786 case ATAPI_PROT_DMA:
787 case ATAPI_PROT_NODATA:
788 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
789 ata_qc_complete(qc);
790 handled = 1;
791 break;
792 default:
793 ap->stats.idle_irq++;
794 break;
795 }
796
797 return handled;
798 }
799
800 static void pdc_irq_clear(struct ata_port *ap)
801 {
802 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
803
804 readl(ata_mmio + PDC_COMMAND);
805 }
806
807 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
808 {
809 struct ata_host *host = dev_instance;
810 struct ata_port *ap;
811 u32 mask = 0;
812 unsigned int i, tmp;
813 unsigned int handled = 0;
814 void __iomem *host_mmio;
815 unsigned int hotplug_offset, ata_no;
816 u32 hotplug_status;
817 int is_sataii_tx4;
818
819 VPRINTK("ENTER\n");
820
821 if (!host || !host->iomap[PDC_MMIO_BAR]) {
822 VPRINTK("QUICK EXIT\n");
823 return IRQ_NONE;
824 }
825
826 host_mmio = host->iomap[PDC_MMIO_BAR];
827
828 spin_lock(&host->lock);
829
830 /* read and clear hotplug flags for all ports */
831 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
832 hotplug_offset = PDC2_SATA_PLUG_CSR;
833 else
834 hotplug_offset = PDC_SATA_PLUG_CSR;
835 hotplug_status = readl(host_mmio + hotplug_offset);
836 if (hotplug_status & 0xff)
837 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
838 hotplug_status &= 0xff; /* clear uninteresting bits */
839
840 /* reading should also clear interrupts */
841 mask = readl(host_mmio + PDC_INT_SEQMASK);
842
843 if (mask == 0xffffffff && hotplug_status == 0) {
844 VPRINTK("QUICK EXIT 2\n");
845 goto done_irq;
846 }
847
848 mask &= 0xffff; /* only 16 SEQIDs possible */
849 if (mask == 0 && hotplug_status == 0) {
850 VPRINTK("QUICK EXIT 3\n");
851 goto done_irq;
852 }
853
854 writel(mask, host_mmio + PDC_INT_SEQMASK);
855
856 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
857
858 for (i = 0; i < host->n_ports; i++) {
859 VPRINTK("port %u\n", i);
860 ap = host->ports[i];
861
862 /* check for a plug or unplug event */
863 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
864 tmp = hotplug_status & (0x11 << ata_no);
865 if (tmp && ap &&
866 !(ap->flags & ATA_FLAG_DISABLED)) {
867 struct ata_eh_info *ehi = &ap->link.eh_info;
868 ata_ehi_clear_desc(ehi);
869 ata_ehi_hotplugged(ehi);
870 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
871 ata_port_freeze(ap);
872 ++handled;
873 continue;
874 }
875
876 /* check for a packet interrupt */
877 tmp = mask & (1 << (i + 1));
878 if (tmp && ap &&
879 !(ap->flags & ATA_FLAG_DISABLED)) {
880 struct ata_queued_cmd *qc;
881
882 qc = ata_qc_from_tag(ap, ap->link.active_tag);
883 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
884 handled += pdc_host_intr(ap, qc);
885 }
886 }
887
888 VPRINTK("EXIT\n");
889
890 done_irq:
891 spin_unlock(&host->lock);
892 return IRQ_RETVAL(handled);
893 }
894
895 static void pdc_packet_start(struct ata_queued_cmd *qc)
896 {
897 struct ata_port *ap = qc->ap;
898 struct pdc_port_priv *pp = ap->private_data;
899 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
900 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
901 unsigned int port_no = ap->port_no;
902 u8 seq = (u8) (port_no + 1);
903
904 VPRINTK("ENTER, ap %p\n", ap);
905
906 writel(0x00000001, host_mmio + (seq * 4));
907 readl(host_mmio + (seq * 4)); /* flush */
908
909 pp->pkt[2] = seq;
910 wmb(); /* flush PRD, pkt writes */
911 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
912 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
913 }
914
915 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
916 {
917 switch (qc->tf.protocol) {
918 case ATAPI_PROT_NODATA:
919 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
920 break;
921 /*FALLTHROUGH*/
922 case ATA_PROT_NODATA:
923 if (qc->tf.flags & ATA_TFLAG_POLLING)
924 break;
925 /*FALLTHROUGH*/
926 case ATAPI_PROT_DMA:
927 case ATA_PROT_DMA:
928 pdc_packet_start(qc);
929 return 0;
930 default:
931 break;
932 }
933 return ata_sff_qc_issue(qc);
934 }
935
936 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
937 {
938 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
939 ata_sff_tf_load(ap, tf);
940 }
941
942 static void pdc_exec_command_mmio(struct ata_port *ap,
943 const struct ata_taskfile *tf)
944 {
945 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
946 ata_sff_exec_command(ap, tf);
947 }
948
949 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
950 {
951 u8 *scsicmd = qc->scsicmd->cmnd;
952 int pio = 1; /* atapi dma off by default */
953
954 /* Whitelist commands that may use DMA. */
955 switch (scsicmd[0]) {
956 case WRITE_12:
957 case WRITE_10:
958 case WRITE_6:
959 case READ_12:
960 case READ_10:
961 case READ_6:
962 case 0xad: /* READ_DVD_STRUCTURE */
963 case 0xbe: /* READ_CD */
964 pio = 0;
965 }
966 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
967 if (scsicmd[0] == WRITE_10) {
968 unsigned int lba =
969 (scsicmd[2] << 24) |
970 (scsicmd[3] << 16) |
971 (scsicmd[4] << 8) |
972 scsicmd[5];
973 if (lba >= 0xFFFF4FA2)
974 pio = 1;
975 }
976 return pio;
977 }
978
979 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
980 {
981 /* First generation chips cannot use ATAPI DMA on SATA ports */
982 return 1;
983 }
984
985 static void pdc_ata_setup_port(struct ata_port *ap,
986 void __iomem *base, void __iomem *scr_addr)
987 {
988 ap->ioaddr.cmd_addr = base;
989 ap->ioaddr.data_addr = base;
990 ap->ioaddr.feature_addr =
991 ap->ioaddr.error_addr = base + 0x4;
992 ap->ioaddr.nsect_addr = base + 0x8;
993 ap->ioaddr.lbal_addr = base + 0xc;
994 ap->ioaddr.lbam_addr = base + 0x10;
995 ap->ioaddr.lbah_addr = base + 0x14;
996 ap->ioaddr.device_addr = base + 0x18;
997 ap->ioaddr.command_addr =
998 ap->ioaddr.status_addr = base + 0x1c;
999 ap->ioaddr.altstatus_addr =
1000 ap->ioaddr.ctl_addr = base + 0x38;
1001 ap->ioaddr.scr_addr = scr_addr;
1002 }
1003
1004 static void pdc_host_init(struct ata_host *host)
1005 {
1006 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1007 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1008 int hotplug_offset;
1009 u32 tmp;
1010
1011 if (is_gen2)
1012 hotplug_offset = PDC2_SATA_PLUG_CSR;
1013 else
1014 hotplug_offset = PDC_SATA_PLUG_CSR;
1015
1016 /*
1017 * Except for the hotplug stuff, this is voodoo from the
1018 * Promise driver. Label this entire section
1019 * "TODO: figure out why we do this"
1020 */
1021
1022 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1023 tmp = readl(host_mmio + PDC_FLASH_CTL);
1024 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1025 if (!is_gen2)
1026 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1027 writel(tmp, host_mmio + PDC_FLASH_CTL);
1028
1029 /* clear plug/unplug flags for all ports */
1030 tmp = readl(host_mmio + hotplug_offset);
1031 writel(tmp | 0xff, host_mmio + hotplug_offset);
1032
1033 /* unmask plug/unplug ints */
1034 tmp = readl(host_mmio + hotplug_offset);
1035 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1036
1037 /* don't initialise TBG or SLEW on 2nd generation chips */
1038 if (is_gen2)
1039 return;
1040
1041 /* reduce TBG clock to 133 Mhz. */
1042 tmp = readl(host_mmio + PDC_TBG_MODE);
1043 tmp &= ~0x30000; /* clear bit 17, 16*/
1044 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1045 writel(tmp, host_mmio + PDC_TBG_MODE);
1046
1047 readl(host_mmio + PDC_TBG_MODE); /* flush */
1048 msleep(10);
1049
1050 /* adjust slew rate control register. */
1051 tmp = readl(host_mmio + PDC_SLEW_CTL);
1052 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1053 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1054 writel(tmp, host_mmio + PDC_SLEW_CTL);
1055 }
1056
1057 static int pdc_ata_init_one(struct pci_dev *pdev,
1058 const struct pci_device_id *ent)
1059 {
1060 static int printed_version;
1061 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1062 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1063 struct ata_host *host;
1064 void __iomem *host_mmio;
1065 int n_ports, i, rc;
1066 int is_sataii_tx4;
1067
1068 if (!printed_version++)
1069 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1070
1071 /* enable and acquire resources */
1072 rc = pcim_enable_device(pdev);
1073 if (rc)
1074 return rc;
1075
1076 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1077 if (rc == -EBUSY)
1078 pcim_pin_device(pdev);
1079 if (rc)
1080 return rc;
1081 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1082
1083 /* determine port configuration and setup host */
1084 n_ports = 2;
1085 if (pi->flags & PDC_FLAG_4_PORTS)
1086 n_ports = 4;
1087 for (i = 0; i < n_ports; i++)
1088 ppi[i] = pi;
1089
1090 if (pi->flags & PDC_FLAG_SATA_PATA) {
1091 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1092 if (!(tmp & 0x80))
1093 ppi[n_ports++] = pi + 1;
1094 }
1095
1096 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1097 if (!host) {
1098 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1099 return -ENOMEM;
1100 }
1101 host->iomap = pcim_iomap_table(pdev);
1102
1103 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1104 for (i = 0; i < host->n_ports; i++) {
1105 struct ata_port *ap = host->ports[i];
1106 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1107 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1108 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1109
1110 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1111
1112 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1113 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1114 }
1115
1116 /* initialize adapter */
1117 pdc_host_init(host);
1118
1119 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1120 if (rc)
1121 return rc;
1122 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1123 if (rc)
1124 return rc;
1125
1126 /* start host, request IRQ and attach */
1127 pci_set_master(pdev);
1128 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1129 &pdc_ata_sht);
1130 }
1131
1132 static int __init pdc_ata_init(void)
1133 {
1134 return pci_register_driver(&pdc_ata_pci_driver);
1135 }
1136
1137 static void __exit pdc_ata_exit(void)
1138 {
1139 pci_unregister_driver(&pdc_ata_pci_driver);
1140 }
1141
1142 MODULE_AUTHOR("Jeff Garzik");
1143 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1144 MODULE_LICENSE("GPL");
1145 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1146 MODULE_VERSION(DRV_VERSION);
1147
1148 module_init(pdc_ata_init);
1149 module_exit(pdc_ata_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree