2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static __must_check
int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
,
43 static __must_check
int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object
*obj
,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object
*obj
);
47 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
49 bool map_and_fenceable
);
50 static void i915_gem_clear_fence_reg(struct drm_device
*dev
,
51 struct drm_i915_fence_reg
*reg
);
52 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
53 struct drm_i915_gem_object
*obj
,
54 struct drm_i915_gem_pwrite
*args
,
55 struct drm_file
*file
);
56 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
);
58 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
67 dev_priv
->mm
.object_count
++;
68 dev_priv
->mm
.object_memory
+= size
;
71 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
74 dev_priv
->mm
.object_count
--;
75 dev_priv
->mm
.object_memory
-= size
;
79 i915_gem_wait_for_error(struct drm_device
*dev
)
81 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
82 struct completion
*x
= &dev_priv
->error_completion
;
86 if (!atomic_read(&dev_priv
->mm
.wedged
))
89 ret
= wait_for_completion_interruptible(x
);
93 if (atomic_read(&dev_priv
->mm
.wedged
)) {
94 /* GPU is hung, bump the completion count to account for
95 * the token we just consumed so that we never hit zero and
96 * end up waiting upon a subsequent completion event that
99 spin_lock_irqsave(&x
->wait
.lock
, flags
);
101 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
106 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
110 ret
= i915_gem_wait_for_error(dev
);
114 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
118 WARN_ON(i915_verify_lists(dev
));
123 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
125 return obj
->gtt_space
&& !obj
->active
&& obj
->pin_count
== 0;
128 void i915_gem_do_init(struct drm_device
*dev
,
130 unsigned long mappable_end
,
133 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
135 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
, end
- start
);
137 dev_priv
->mm
.gtt_start
= start
;
138 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
139 dev_priv
->mm
.gtt_end
= end
;
140 dev_priv
->mm
.gtt_total
= end
- start
;
141 dev_priv
->mm
.mappable_gtt_total
= min(end
, mappable_end
) - start
;
143 /* Take over this portion of the GTT */
144 intel_gtt_clear_range(start
/ PAGE_SIZE
, (end
-start
) / PAGE_SIZE
);
148 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
149 struct drm_file
*file
)
151 struct drm_i915_gem_init
*args
= data
;
153 if (args
->gtt_start
>= args
->gtt_end
||
154 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
157 mutex_lock(&dev
->struct_mutex
);
158 i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
159 mutex_unlock(&dev
->struct_mutex
);
165 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
166 struct drm_file
*file
)
168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
169 struct drm_i915_gem_get_aperture
*args
= data
;
170 struct drm_i915_gem_object
*obj
;
173 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
177 mutex_lock(&dev
->struct_mutex
);
178 list_for_each_entry(obj
, &dev_priv
->mm
.pinned_list
, mm_list
)
179 pinned
+= obj
->gtt_space
->size
;
180 mutex_unlock(&dev
->struct_mutex
);
182 args
->aper_size
= dev_priv
->mm
.gtt_total
;
183 args
->aper_available_size
= args
->aper_size
-pinned
;
189 i915_gem_create(struct drm_file
*file
,
190 struct drm_device
*dev
,
194 struct drm_i915_gem_object
*obj
;
198 size
= roundup(size
, PAGE_SIZE
);
200 /* Allocate the new object */
201 obj
= i915_gem_alloc_object(dev
, size
);
205 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
207 drm_gem_object_release(&obj
->base
);
208 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
213 /* drop reference from allocate - handle holds it now */
214 drm_gem_object_unreference(&obj
->base
);
215 trace_i915_gem_object_create(obj
);
222 i915_gem_dumb_create(struct drm_file
*file
,
223 struct drm_device
*dev
,
224 struct drm_mode_create_dumb
*args
)
226 /* have to work out size/pitch and return them */
227 args
->pitch
= ALIGN(args
->width
& ((args
->bpp
+ 1) / 8), 64);
228 args
->size
= args
->pitch
* args
->height
;
229 return i915_gem_create(file
, dev
,
230 args
->size
, &args
->handle
);
233 int i915_gem_dumb_destroy(struct drm_file
*file
,
234 struct drm_device
*dev
,
237 return drm_gem_handle_delete(file
, handle
);
241 * Creates a new mm object and returns a handle to it.
244 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
245 struct drm_file
*file
)
247 struct drm_i915_gem_create
*args
= data
;
248 return i915_gem_create(file
, dev
,
249 args
->size
, &args
->handle
);
252 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
254 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
256 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
257 obj
->tiling_mode
!= I915_TILING_NONE
;
261 slow_shmem_copy(struct page
*dst_page
,
263 struct page
*src_page
,
267 char *dst_vaddr
, *src_vaddr
;
269 dst_vaddr
= kmap(dst_page
);
270 src_vaddr
= kmap(src_page
);
272 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
279 slow_shmem_bit17_copy(struct page
*gpu_page
,
281 struct page
*cpu_page
,
286 char *gpu_vaddr
, *cpu_vaddr
;
288 /* Use the unswizzled path if this page isn't affected. */
289 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
291 return slow_shmem_copy(cpu_page
, cpu_offset
,
292 gpu_page
, gpu_offset
, length
);
294 return slow_shmem_copy(gpu_page
, gpu_offset
,
295 cpu_page
, cpu_offset
, length
);
298 gpu_vaddr
= kmap(gpu_page
);
299 cpu_vaddr
= kmap(cpu_page
);
301 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
302 * XORing with the other bits (A9 for Y, A9 and A10 for X)
305 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
306 int this_length
= min(cacheline_end
- gpu_offset
, length
);
307 int swizzled_gpu_offset
= gpu_offset
^ 64;
310 memcpy(cpu_vaddr
+ cpu_offset
,
311 gpu_vaddr
+ swizzled_gpu_offset
,
314 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
315 cpu_vaddr
+ cpu_offset
,
318 cpu_offset
+= this_length
;
319 gpu_offset
+= this_length
;
320 length
-= this_length
;
328 * This is the fast shmem pread path, which attempts to copy_from_user directly
329 * from the backing pages of the object to the user's address space. On a
330 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
333 i915_gem_shmem_pread_fast(struct drm_device
*dev
,
334 struct drm_i915_gem_object
*obj
,
335 struct drm_i915_gem_pread
*args
,
336 struct drm_file
*file
)
338 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
341 char __user
*user_data
;
342 int page_offset
, page_length
;
344 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
347 offset
= args
->offset
;
354 /* Operation in this page
356 * page_offset = offset within page
357 * page_length = bytes to copy for this page
359 page_offset
= offset
& (PAGE_SIZE
-1);
360 page_length
= remain
;
361 if ((page_offset
+ remain
) > PAGE_SIZE
)
362 page_length
= PAGE_SIZE
- page_offset
;
364 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
365 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
367 return PTR_ERR(page
);
369 vaddr
= kmap_atomic(page
);
370 ret
= __copy_to_user_inatomic(user_data
,
373 kunmap_atomic(vaddr
);
375 mark_page_accessed(page
);
376 page_cache_release(page
);
380 remain
-= page_length
;
381 user_data
+= page_length
;
382 offset
+= page_length
;
389 * This is the fallback shmem pread path, which allocates temporary storage
390 * in kernel space to copy_to_user into outside of the struct_mutex, so we
391 * can copy out of the object's backing pages while holding the struct mutex
392 * and not take page faults.
395 i915_gem_shmem_pread_slow(struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
,
397 struct drm_i915_gem_pread
*args
,
398 struct drm_file
*file
)
400 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
401 struct mm_struct
*mm
= current
->mm
;
402 struct page
**user_pages
;
404 loff_t offset
, pinned_pages
, i
;
405 loff_t first_data_page
, last_data_page
, num_pages
;
406 int shmem_page_offset
;
407 int data_page_index
, data_page_offset
;
410 uint64_t data_ptr
= args
->data_ptr
;
411 int do_bit17_swizzling
;
415 /* Pin the user pages containing the data. We can't fault while
416 * holding the struct mutex, yet we want to hold it while
417 * dereferencing the user data.
419 first_data_page
= data_ptr
/ PAGE_SIZE
;
420 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
421 num_pages
= last_data_page
- first_data_page
+ 1;
423 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
424 if (user_pages
== NULL
)
427 mutex_unlock(&dev
->struct_mutex
);
428 down_read(&mm
->mmap_sem
);
429 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
430 num_pages
, 1, 0, user_pages
, NULL
);
431 up_read(&mm
->mmap_sem
);
432 mutex_lock(&dev
->struct_mutex
);
433 if (pinned_pages
< num_pages
) {
438 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
444 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
446 offset
= args
->offset
;
451 /* Operation in this page
453 * shmem_page_offset = offset within page in shmem file
454 * data_page_index = page number in get_user_pages return
455 * data_page_offset = offset with data_page_index page.
456 * page_length = bytes to copy for this page
458 shmem_page_offset
= offset
& ~PAGE_MASK
;
459 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
460 data_page_offset
= data_ptr
& ~PAGE_MASK
;
462 page_length
= remain
;
463 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
464 page_length
= PAGE_SIZE
- shmem_page_offset
;
465 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
466 page_length
= PAGE_SIZE
- data_page_offset
;
468 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
469 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
471 return PTR_ERR(page
);
473 if (do_bit17_swizzling
) {
474 slow_shmem_bit17_copy(page
,
476 user_pages
[data_page_index
],
481 slow_shmem_copy(user_pages
[data_page_index
],
488 mark_page_accessed(page
);
489 page_cache_release(page
);
491 remain
-= page_length
;
492 data_ptr
+= page_length
;
493 offset
+= page_length
;
497 for (i
= 0; i
< pinned_pages
; i
++) {
498 SetPageDirty(user_pages
[i
]);
499 mark_page_accessed(user_pages
[i
]);
500 page_cache_release(user_pages
[i
]);
502 drm_free_large(user_pages
);
508 * Reads data from the object referenced by handle.
510 * On error, the contents of *data are undefined.
513 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
514 struct drm_file
*file
)
516 struct drm_i915_gem_pread
*args
= data
;
517 struct drm_i915_gem_object
*obj
;
523 if (!access_ok(VERIFY_WRITE
,
524 (char __user
*)(uintptr_t)args
->data_ptr
,
528 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
533 ret
= i915_mutex_lock_interruptible(dev
);
537 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
538 if (&obj
->base
== NULL
) {
543 /* Bounds check source. */
544 if (args
->offset
> obj
->base
.size
||
545 args
->size
> obj
->base
.size
- args
->offset
) {
550 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
552 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
559 if (!i915_gem_object_needs_bit17_swizzle(obj
))
560 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file
);
562 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file
);
565 drm_gem_object_unreference(&obj
->base
);
567 mutex_unlock(&dev
->struct_mutex
);
571 /* This is the fast write path which cannot handle
572 * page faults in the source data
576 fast_user_write(struct io_mapping
*mapping
,
577 loff_t page_base
, int page_offset
,
578 char __user
*user_data
,
582 unsigned long unwritten
;
584 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
585 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
587 io_mapping_unmap_atomic(vaddr_atomic
);
591 /* Here's the write path which can sleep for
596 slow_kernel_write(struct io_mapping
*mapping
,
597 loff_t gtt_base
, int gtt_offset
,
598 struct page
*user_page
, int user_offset
,
601 char __iomem
*dst_vaddr
;
604 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
605 src_vaddr
= kmap(user_page
);
607 memcpy_toio(dst_vaddr
+ gtt_offset
,
608 src_vaddr
+ user_offset
,
612 io_mapping_unmap(dst_vaddr
);
616 * This is the fast pwrite path, where we copy the data directly from the
617 * user into the GTT, uncached.
620 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
621 struct drm_i915_gem_object
*obj
,
622 struct drm_i915_gem_pwrite
*args
,
623 struct drm_file
*file
)
625 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
627 loff_t offset
, page_base
;
628 char __user
*user_data
;
629 int page_offset
, page_length
;
631 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
634 offset
= obj
->gtt_offset
+ args
->offset
;
637 /* Operation in this page
639 * page_base = page offset within aperture
640 * page_offset = offset within page
641 * page_length = bytes to copy for this page
643 page_base
= (offset
& ~(PAGE_SIZE
-1));
644 page_offset
= offset
& (PAGE_SIZE
-1);
645 page_length
= remain
;
646 if ((page_offset
+ remain
) > PAGE_SIZE
)
647 page_length
= PAGE_SIZE
- page_offset
;
649 /* If we get a fault while copying data, then (presumably) our
650 * source page isn't available. Return the error and we'll
651 * retry in the slow path.
653 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
654 page_offset
, user_data
, page_length
))
658 remain
-= page_length
;
659 user_data
+= page_length
;
660 offset
+= page_length
;
667 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
668 * the memory and maps it using kmap_atomic for copying.
670 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
671 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
674 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
,
675 struct drm_i915_gem_object
*obj
,
676 struct drm_i915_gem_pwrite
*args
,
677 struct drm_file
*file
)
679 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
681 loff_t gtt_page_base
, offset
;
682 loff_t first_data_page
, last_data_page
, num_pages
;
683 loff_t pinned_pages
, i
;
684 struct page
**user_pages
;
685 struct mm_struct
*mm
= current
->mm
;
686 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
688 uint64_t data_ptr
= args
->data_ptr
;
692 /* Pin the user pages containing the data. We can't fault while
693 * holding the struct mutex, and all of the pwrite implementations
694 * want to hold it while dereferencing the user data.
696 first_data_page
= data_ptr
/ PAGE_SIZE
;
697 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
698 num_pages
= last_data_page
- first_data_page
+ 1;
700 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
701 if (user_pages
== NULL
)
704 mutex_unlock(&dev
->struct_mutex
);
705 down_read(&mm
->mmap_sem
);
706 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
707 num_pages
, 0, 0, user_pages
, NULL
);
708 up_read(&mm
->mmap_sem
);
709 mutex_lock(&dev
->struct_mutex
);
710 if (pinned_pages
< num_pages
) {
712 goto out_unpin_pages
;
715 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
717 goto out_unpin_pages
;
719 ret
= i915_gem_object_put_fence(obj
);
721 goto out_unpin_pages
;
723 offset
= obj
->gtt_offset
+ args
->offset
;
726 /* Operation in this page
728 * gtt_page_base = page offset within aperture
729 * gtt_page_offset = offset within page in aperture
730 * data_page_index = page number in get_user_pages return
731 * data_page_offset = offset with data_page_index page.
732 * page_length = bytes to copy for this page
734 gtt_page_base
= offset
& PAGE_MASK
;
735 gtt_page_offset
= offset
& ~PAGE_MASK
;
736 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
737 data_page_offset
= data_ptr
& ~PAGE_MASK
;
739 page_length
= remain
;
740 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
741 page_length
= PAGE_SIZE
- gtt_page_offset
;
742 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
743 page_length
= PAGE_SIZE
- data_page_offset
;
745 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
746 gtt_page_base
, gtt_page_offset
,
747 user_pages
[data_page_index
],
751 remain
-= page_length
;
752 offset
+= page_length
;
753 data_ptr
+= page_length
;
757 for (i
= 0; i
< pinned_pages
; i
++)
758 page_cache_release(user_pages
[i
]);
759 drm_free_large(user_pages
);
765 * This is the fast shmem pwrite path, which attempts to directly
766 * copy_from_user into the kmapped pages backing the object.
769 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
,
770 struct drm_i915_gem_object
*obj
,
771 struct drm_i915_gem_pwrite
*args
,
772 struct drm_file
*file
)
774 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
777 char __user
*user_data
;
778 int page_offset
, page_length
;
780 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
783 offset
= args
->offset
;
791 /* Operation in this page
793 * page_offset = offset within page
794 * page_length = bytes to copy for this page
796 page_offset
= offset
& (PAGE_SIZE
-1);
797 page_length
= remain
;
798 if ((page_offset
+ remain
) > PAGE_SIZE
)
799 page_length
= PAGE_SIZE
- page_offset
;
801 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
802 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
804 return PTR_ERR(page
);
806 vaddr
= kmap_atomic(page
, KM_USER0
);
807 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
,
810 kunmap_atomic(vaddr
, KM_USER0
);
812 set_page_dirty(page
);
813 mark_page_accessed(page
);
814 page_cache_release(page
);
816 /* If we get a fault while copying data, then (presumably) our
817 * source page isn't available. Return the error and we'll
818 * retry in the slow path.
823 remain
-= page_length
;
824 user_data
+= page_length
;
825 offset
+= page_length
;
832 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
833 * the memory and maps it using kmap_atomic for copying.
835 * This avoids taking mmap_sem for faulting on the user's address while the
836 * struct_mutex is held.
839 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
,
840 struct drm_i915_gem_object
*obj
,
841 struct drm_i915_gem_pwrite
*args
,
842 struct drm_file
*file
)
844 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
845 struct mm_struct
*mm
= current
->mm
;
846 struct page
**user_pages
;
848 loff_t offset
, pinned_pages
, i
;
849 loff_t first_data_page
, last_data_page
, num_pages
;
850 int shmem_page_offset
;
851 int data_page_index
, data_page_offset
;
854 uint64_t data_ptr
= args
->data_ptr
;
855 int do_bit17_swizzling
;
859 /* Pin the user pages containing the data. We can't fault while
860 * holding the struct mutex, and all of the pwrite implementations
861 * want to hold it while dereferencing the user data.
863 first_data_page
= data_ptr
/ PAGE_SIZE
;
864 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
865 num_pages
= last_data_page
- first_data_page
+ 1;
867 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
868 if (user_pages
== NULL
)
871 mutex_unlock(&dev
->struct_mutex
);
872 down_read(&mm
->mmap_sem
);
873 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
874 num_pages
, 0, 0, user_pages
, NULL
);
875 up_read(&mm
->mmap_sem
);
876 mutex_lock(&dev
->struct_mutex
);
877 if (pinned_pages
< num_pages
) {
882 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
886 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
888 offset
= args
->offset
;
894 /* Operation in this page
896 * shmem_page_offset = offset within page in shmem file
897 * data_page_index = page number in get_user_pages return
898 * data_page_offset = offset with data_page_index page.
899 * page_length = bytes to copy for this page
901 shmem_page_offset
= offset
& ~PAGE_MASK
;
902 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
903 data_page_offset
= data_ptr
& ~PAGE_MASK
;
905 page_length
= remain
;
906 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
907 page_length
= PAGE_SIZE
- shmem_page_offset
;
908 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
909 page_length
= PAGE_SIZE
- data_page_offset
;
911 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
912 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
918 if (do_bit17_swizzling
) {
919 slow_shmem_bit17_copy(page
,
921 user_pages
[data_page_index
],
926 slow_shmem_copy(page
,
928 user_pages
[data_page_index
],
933 set_page_dirty(page
);
934 mark_page_accessed(page
);
935 page_cache_release(page
);
937 remain
-= page_length
;
938 data_ptr
+= page_length
;
939 offset
+= page_length
;
943 for (i
= 0; i
< pinned_pages
; i
++)
944 page_cache_release(user_pages
[i
]);
945 drm_free_large(user_pages
);
951 * Writes data to the object referenced by handle.
953 * On error, the contents of the buffer that were to be modified are undefined.
956 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
957 struct drm_file
*file
)
959 struct drm_i915_gem_pwrite
*args
= data
;
960 struct drm_i915_gem_object
*obj
;
966 if (!access_ok(VERIFY_READ
,
967 (char __user
*)(uintptr_t)args
->data_ptr
,
971 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
976 ret
= i915_mutex_lock_interruptible(dev
);
980 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
981 if (&obj
->base
== NULL
) {
986 /* Bounds check destination. */
987 if (args
->offset
> obj
->base
.size
||
988 args
->size
> obj
->base
.size
- args
->offset
) {
993 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
995 /* We can only do the GTT pwrite on untiled buffers, as otherwise
996 * it would end up going through the fenced access, and we'll get
997 * different detiling behavior between reading and writing.
998 * pread/pwrite currently are reading and writing from the CPU
999 * perspective, requiring manual detiling by the client.
1002 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
1003 else if (obj
->gtt_space
&&
1004 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1005 ret
= i915_gem_object_pin(obj
, 0, true);
1009 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1013 ret
= i915_gem_object_put_fence(obj
);
1017 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1019 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
1022 i915_gem_object_unpin(obj
);
1024 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1029 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1030 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1032 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1036 drm_gem_object_unreference(&obj
->base
);
1038 mutex_unlock(&dev
->struct_mutex
);
1043 * Called when user space prepares to use an object with the CPU, either
1044 * through the mmap ioctl's mapping or a GTT mapping.
1047 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1048 struct drm_file
*file
)
1050 struct drm_i915_gem_set_domain
*args
= data
;
1051 struct drm_i915_gem_object
*obj
;
1052 uint32_t read_domains
= args
->read_domains
;
1053 uint32_t write_domain
= args
->write_domain
;
1056 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1059 /* Only handle setting domains to types used by the CPU. */
1060 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1063 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1066 /* Having something in the write domain implies it's in the read
1067 * domain, and only that read domain. Enforce that in the request.
1069 if (write_domain
!= 0 && read_domains
!= write_domain
)
1072 ret
= i915_mutex_lock_interruptible(dev
);
1076 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1077 if (&obj
->base
== NULL
) {
1082 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1083 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1085 /* Silently promote "you're not bound, there was nothing to do"
1086 * to success, since the client was just asking us to
1087 * make sure everything was done.
1092 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1095 drm_gem_object_unreference(&obj
->base
);
1097 mutex_unlock(&dev
->struct_mutex
);
1102 * Called when user space has done writes to this buffer
1105 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1106 struct drm_file
*file
)
1108 struct drm_i915_gem_sw_finish
*args
= data
;
1109 struct drm_i915_gem_object
*obj
;
1112 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1115 ret
= i915_mutex_lock_interruptible(dev
);
1119 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1120 if (&obj
->base
== NULL
) {
1125 /* Pinned buffers may be scanout, so flush the cache */
1127 i915_gem_object_flush_cpu_write_domain(obj
);
1129 drm_gem_object_unreference(&obj
->base
);
1131 mutex_unlock(&dev
->struct_mutex
);
1136 * Maps the contents of an object, returning the address it is mapped
1139 * While the mapping holds a reference on the contents of the object, it doesn't
1140 * imply a ref on the object itself.
1143 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1144 struct drm_file
*file
)
1146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1147 struct drm_i915_gem_mmap
*args
= data
;
1148 struct drm_gem_object
*obj
;
1151 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1154 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1158 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1159 drm_gem_object_unreference_unlocked(obj
);
1163 down_write(¤t
->mm
->mmap_sem
);
1164 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1165 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1167 up_write(¤t
->mm
->mmap_sem
);
1168 drm_gem_object_unreference_unlocked(obj
);
1169 if (IS_ERR((void *)addr
))
1172 args
->addr_ptr
= (uint64_t) addr
;
1178 * i915_gem_fault - fault a page into the GTT
1179 * vma: VMA in question
1182 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1183 * from userspace. The fault handler takes care of binding the object to
1184 * the GTT (if needed), allocating and programming a fence register (again,
1185 * only if needed based on whether the old reg is still valid or the object
1186 * is tiled) and inserting a new PTE into the faulting process.
1188 * Note that the faulting process may involve evicting existing objects
1189 * from the GTT and/or fence registers to make room. So performance may
1190 * suffer if the GTT working set is large or there are few fence registers
1193 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1195 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1196 struct drm_device
*dev
= obj
->base
.dev
;
1197 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1198 pgoff_t page_offset
;
1201 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1203 /* We don't use vmf->pgoff since that has the fake offset */
1204 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1207 ret
= i915_mutex_lock_interruptible(dev
);
1211 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1213 /* Now bind it into the GTT if needed */
1214 if (!obj
->map_and_fenceable
) {
1215 ret
= i915_gem_object_unbind(obj
);
1219 if (!obj
->gtt_space
) {
1220 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1225 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1229 if (obj
->tiling_mode
== I915_TILING_NONE
)
1230 ret
= i915_gem_object_put_fence(obj
);
1232 ret
= i915_gem_object_get_fence(obj
, NULL
);
1236 if (i915_gem_object_is_inactive(obj
))
1237 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1239 obj
->fault_mappable
= true;
1241 pfn
= ((dev
->agp
->base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1244 /* Finally, remap it using the new GTT offset */
1245 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1247 mutex_unlock(&dev
->struct_mutex
);
1252 /* Give the error handler a chance to run and move the
1253 * objects off the GPU active list. Next time we service the
1254 * fault, we should be able to transition the page into the
1255 * GTT without touching the GPU (and so avoid further
1256 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1257 * with coherency, just lost writes.
1263 return VM_FAULT_NOPAGE
;
1265 return VM_FAULT_OOM
;
1267 return VM_FAULT_SIGBUS
;
1272 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1273 * @obj: obj in question
1275 * GEM memory mapping works by handing back to userspace a fake mmap offset
1276 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1277 * up the object based on the offset and sets up the various memory mapping
1280 * This routine allocates and attaches a fake offset for @obj.
1283 i915_gem_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1285 struct drm_device
*dev
= obj
->base
.dev
;
1286 struct drm_gem_mm
*mm
= dev
->mm_private
;
1287 struct drm_map_list
*list
;
1288 struct drm_local_map
*map
;
1291 /* Set the object up for mmap'ing */
1292 list
= &obj
->base
.map_list
;
1293 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1298 map
->type
= _DRM_GEM
;
1299 map
->size
= obj
->base
.size
;
1302 /* Get a DRM GEM mmap offset allocated... */
1303 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1304 obj
->base
.size
/ PAGE_SIZE
,
1306 if (!list
->file_offset_node
) {
1307 DRM_ERROR("failed to allocate offset for bo %d\n",
1313 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1314 obj
->base
.size
/ PAGE_SIZE
,
1316 if (!list
->file_offset_node
) {
1321 list
->hash
.key
= list
->file_offset_node
->start
;
1322 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1324 DRM_ERROR("failed to add to map hash\n");
1331 drm_mm_put_block(list
->file_offset_node
);
1340 * i915_gem_release_mmap - remove physical page mappings
1341 * @obj: obj in question
1343 * Preserve the reservation of the mmapping with the DRM core code, but
1344 * relinquish ownership of the pages back to the system.
1346 * It is vital that we remove the page mapping if we have mapped a tiled
1347 * object through the GTT and then lose the fence register due to
1348 * resource pressure. Similarly if the object has been moved out of the
1349 * aperture, than pages mapped into userspace must be revoked. Removing the
1350 * mapping will then trigger a page fault on the next user access, allowing
1351 * fixup by i915_gem_fault().
1354 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1356 if (!obj
->fault_mappable
)
1359 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1360 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1363 obj
->fault_mappable
= false;
1367 i915_gem_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1369 struct drm_device
*dev
= obj
->base
.dev
;
1370 struct drm_gem_mm
*mm
= dev
->mm_private
;
1371 struct drm_map_list
*list
= &obj
->base
.map_list
;
1373 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1374 drm_mm_put_block(list
->file_offset_node
);
1380 i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj
)
1382 struct drm_device
*dev
= obj
->base
.dev
;
1385 if (INTEL_INFO(dev
)->gen
>= 4 ||
1386 obj
->tiling_mode
== I915_TILING_NONE
)
1387 return obj
->base
.size
;
1389 /* Previous chips need a power-of-two fence region when tiling */
1390 if (INTEL_INFO(dev
)->gen
== 3)
1395 while (size
< obj
->base
.size
)
1402 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1403 * @obj: object to check
1405 * Return the required GTT alignment for an object, taking into account
1406 * potential fence register mapping.
1409 i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj
)
1411 struct drm_device
*dev
= obj
->base
.dev
;
1414 * Minimum alignment is 4k (GTT page size), but might be greater
1415 * if a fence register is needed for the object.
1417 if (INTEL_INFO(dev
)->gen
>= 4 ||
1418 obj
->tiling_mode
== I915_TILING_NONE
)
1422 * Previous chips need to be aligned to the size of the smallest
1423 * fence register that can contain the object.
1425 return i915_gem_get_gtt_size(obj
);
1429 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1431 * @obj: object to check
1433 * Return the required GTT alignment for an object, only taking into account
1434 * unfenced tiled surface requirements.
1437 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object
*obj
)
1439 struct drm_device
*dev
= obj
->base
.dev
;
1443 * Minimum alignment is 4k (GTT page size) for sane hw.
1445 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1446 obj
->tiling_mode
== I915_TILING_NONE
)
1450 * Older chips need unfenced tiled buffers to be aligned to the left
1451 * edge of an even tile row (where tile rows are counted as if the bo is
1452 * placed in a fenced gtt region).
1455 (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
)))
1460 return tile_height
* obj
->stride
* 2;
1464 i915_gem_mmap_gtt(struct drm_file
*file
,
1465 struct drm_device
*dev
,
1469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1470 struct drm_i915_gem_object
*obj
;
1473 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1476 ret
= i915_mutex_lock_interruptible(dev
);
1480 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1481 if (&obj
->base
== NULL
) {
1486 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1491 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1492 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1497 if (!obj
->base
.map_list
.map
) {
1498 ret
= i915_gem_create_mmap_offset(obj
);
1503 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1506 drm_gem_object_unreference(&obj
->base
);
1508 mutex_unlock(&dev
->struct_mutex
);
1513 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1515 * @data: GTT mapping ioctl data
1516 * @file: GEM object info
1518 * Simply returns the fake offset to userspace so it can mmap it.
1519 * The mmap call will end up in drm_gem_mmap(), which will set things
1520 * up so we can get faults in the handler above.
1522 * The fault handler will take care of binding the object into the GTT
1523 * (since it may have been evicted to make room for something), allocating
1524 * a fence register, and mapping the appropriate aperture address into
1528 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1529 struct drm_file
*file
)
1531 struct drm_i915_gem_mmap_gtt
*args
= data
;
1533 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1536 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1541 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1545 struct address_space
*mapping
;
1546 struct inode
*inode
;
1549 /* Get the list of pages out of our struct file. They'll be pinned
1550 * at this point until we release them.
1552 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1553 BUG_ON(obj
->pages
!= NULL
);
1554 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1555 if (obj
->pages
== NULL
)
1558 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1559 mapping
= inode
->i_mapping
;
1560 for (i
= 0; i
< page_count
; i
++) {
1561 page
= read_cache_page_gfp(mapping
, i
,
1569 obj
->pages
[i
] = page
;
1572 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1573 i915_gem_object_do_bit_17_swizzle(obj
);
1579 page_cache_release(obj
->pages
[i
]);
1581 drm_free_large(obj
->pages
);
1583 return PTR_ERR(page
);
1587 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1589 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1592 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1594 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1595 i915_gem_object_save_bit_17_swizzle(obj
);
1597 if (obj
->madv
== I915_MADV_DONTNEED
)
1600 for (i
= 0; i
< page_count
; i
++) {
1602 set_page_dirty(obj
->pages
[i
]);
1604 if (obj
->madv
== I915_MADV_WILLNEED
)
1605 mark_page_accessed(obj
->pages
[i
]);
1607 page_cache_release(obj
->pages
[i
]);
1611 drm_free_large(obj
->pages
);
1616 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1617 struct intel_ring_buffer
*ring
,
1620 struct drm_device
*dev
= obj
->base
.dev
;
1621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1623 BUG_ON(ring
== NULL
);
1626 /* Add a reference if we're newly entering the active list. */
1628 drm_gem_object_reference(&obj
->base
);
1632 /* Move from whatever list we were on to the tail of execution. */
1633 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1634 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1636 obj
->last_rendering_seqno
= seqno
;
1637 if (obj
->fenced_gpu_access
) {
1638 struct drm_i915_fence_reg
*reg
;
1640 BUG_ON(obj
->fence_reg
== I915_FENCE_REG_NONE
);
1642 obj
->last_fenced_seqno
= seqno
;
1643 obj
->last_fenced_ring
= ring
;
1645 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1646 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
1651 i915_gem_object_move_off_active(struct drm_i915_gem_object
*obj
)
1653 list_del_init(&obj
->ring_list
);
1654 obj
->last_rendering_seqno
= 0;
1658 i915_gem_object_move_to_flushing(struct drm_i915_gem_object
*obj
)
1660 struct drm_device
*dev
= obj
->base
.dev
;
1661 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1663 BUG_ON(!obj
->active
);
1664 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.flushing_list
);
1666 i915_gem_object_move_off_active(obj
);
1670 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1672 struct drm_device
*dev
= obj
->base
.dev
;
1673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1675 if (obj
->pin_count
!= 0)
1676 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.pinned_list
);
1678 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1680 BUG_ON(!list_empty(&obj
->gpu_write_list
));
1681 BUG_ON(!obj
->active
);
1684 i915_gem_object_move_off_active(obj
);
1685 obj
->fenced_gpu_access
= false;
1688 obj
->pending_gpu_write
= false;
1689 drm_gem_object_unreference(&obj
->base
);
1691 WARN_ON(i915_verify_lists(dev
));
1694 /* Immediately discard the backing storage */
1696 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1698 struct inode
*inode
;
1700 /* Our goal here is to return as much of the memory as
1701 * is possible back to the system as we are called from OOM.
1702 * To do this we must instruct the shmfs to drop all of its
1703 * backing pages, *now*. Here we mirror the actions taken
1704 * when by shmem_delete_inode() to release the backing store.
1706 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1707 truncate_inode_pages(inode
->i_mapping
, 0);
1708 if (inode
->i_op
->truncate_range
)
1709 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1711 obj
->madv
= __I915_MADV_PURGED
;
1715 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1717 return obj
->madv
== I915_MADV_DONTNEED
;
1721 i915_gem_process_flushing_list(struct intel_ring_buffer
*ring
,
1722 uint32_t flush_domains
)
1724 struct drm_i915_gem_object
*obj
, *next
;
1726 list_for_each_entry_safe(obj
, next
,
1727 &ring
->gpu_write_list
,
1729 if (obj
->base
.write_domain
& flush_domains
) {
1730 uint32_t old_write_domain
= obj
->base
.write_domain
;
1732 obj
->base
.write_domain
= 0;
1733 list_del_init(&obj
->gpu_write_list
);
1734 i915_gem_object_move_to_active(obj
, ring
,
1735 i915_gem_next_request_seqno(ring
));
1737 trace_i915_gem_object_change_domain(obj
,
1738 obj
->base
.read_domains
,
1745 i915_add_request(struct intel_ring_buffer
*ring
,
1746 struct drm_file
*file
,
1747 struct drm_i915_gem_request
*request
)
1749 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1754 BUG_ON(request
== NULL
);
1756 ret
= ring
->add_request(ring
, &seqno
);
1760 trace_i915_gem_request_add(ring
, seqno
);
1762 request
->seqno
= seqno
;
1763 request
->ring
= ring
;
1764 request
->emitted_jiffies
= jiffies
;
1765 was_empty
= list_empty(&ring
->request_list
);
1766 list_add_tail(&request
->list
, &ring
->request_list
);
1769 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1771 spin_lock(&file_priv
->mm
.lock
);
1772 request
->file_priv
= file_priv
;
1773 list_add_tail(&request
->client_list
,
1774 &file_priv
->mm
.request_list
);
1775 spin_unlock(&file_priv
->mm
.lock
);
1778 ring
->outstanding_lazy_request
= false;
1780 if (!dev_priv
->mm
.suspended
) {
1781 mod_timer(&dev_priv
->hangcheck_timer
,
1782 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1784 queue_delayed_work(dev_priv
->wq
,
1785 &dev_priv
->mm
.retire_work
, HZ
);
1791 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1793 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1798 spin_lock(&file_priv
->mm
.lock
);
1799 list_del(&request
->client_list
);
1800 request
->file_priv
= NULL
;
1801 spin_unlock(&file_priv
->mm
.lock
);
1804 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1805 struct intel_ring_buffer
*ring
)
1807 while (!list_empty(&ring
->request_list
)) {
1808 struct drm_i915_gem_request
*request
;
1810 request
= list_first_entry(&ring
->request_list
,
1811 struct drm_i915_gem_request
,
1814 list_del(&request
->list
);
1815 i915_gem_request_remove_from_client(request
);
1819 while (!list_empty(&ring
->active_list
)) {
1820 struct drm_i915_gem_object
*obj
;
1822 obj
= list_first_entry(&ring
->active_list
,
1823 struct drm_i915_gem_object
,
1826 obj
->base
.write_domain
= 0;
1827 list_del_init(&obj
->gpu_write_list
);
1828 i915_gem_object_move_to_inactive(obj
);
1832 static void i915_gem_reset_fences(struct drm_device
*dev
)
1834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1837 for (i
= 0; i
< 16; i
++) {
1838 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1839 struct drm_i915_gem_object
*obj
= reg
->obj
;
1844 if (obj
->tiling_mode
)
1845 i915_gem_release_mmap(obj
);
1847 reg
->obj
->fence_reg
= I915_FENCE_REG_NONE
;
1848 reg
->obj
->fenced_gpu_access
= false;
1849 reg
->obj
->last_fenced_seqno
= 0;
1850 reg
->obj
->last_fenced_ring
= NULL
;
1851 i915_gem_clear_fence_reg(dev
, reg
);
1855 void i915_gem_reset(struct drm_device
*dev
)
1857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1858 struct drm_i915_gem_object
*obj
;
1861 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1862 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->ring
[i
]);
1864 /* Remove anything from the flushing lists. The GPU cache is likely
1865 * to be lost on reset along with the data, so simply move the
1866 * lost bo to the inactive list.
1868 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1869 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1870 struct drm_i915_gem_object
,
1873 obj
->base
.write_domain
= 0;
1874 list_del_init(&obj
->gpu_write_list
);
1875 i915_gem_object_move_to_inactive(obj
);
1878 /* Move everything out of the GPU domains to ensure we do any
1879 * necessary invalidation upon reuse.
1881 list_for_each_entry(obj
,
1882 &dev_priv
->mm
.inactive_list
,
1885 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1888 /* The fence registers are invalidated so clear them out */
1889 i915_gem_reset_fences(dev
);
1893 * This function clears the request list as sequence numbers are passed.
1896 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
1901 if (list_empty(&ring
->request_list
))
1904 WARN_ON(i915_verify_lists(ring
->dev
));
1906 seqno
= ring
->get_seqno(ring
);
1908 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
1909 if (seqno
>= ring
->sync_seqno
[i
])
1910 ring
->sync_seqno
[i
] = 0;
1912 while (!list_empty(&ring
->request_list
)) {
1913 struct drm_i915_gem_request
*request
;
1915 request
= list_first_entry(&ring
->request_list
,
1916 struct drm_i915_gem_request
,
1919 if (!i915_seqno_passed(seqno
, request
->seqno
))
1922 trace_i915_gem_request_retire(ring
, request
->seqno
);
1924 list_del(&request
->list
);
1925 i915_gem_request_remove_from_client(request
);
1929 /* Move any buffers on the active list that are no longer referenced
1930 * by the ringbuffer to the flushing/inactive lists as appropriate.
1932 while (!list_empty(&ring
->active_list
)) {
1933 struct drm_i915_gem_object
*obj
;
1935 obj
= list_first_entry(&ring
->active_list
,
1936 struct drm_i915_gem_object
,
1939 if (!i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
1942 if (obj
->base
.write_domain
!= 0)
1943 i915_gem_object_move_to_flushing(obj
);
1945 i915_gem_object_move_to_inactive(obj
);
1948 if (unlikely(ring
->trace_irq_seqno
&&
1949 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
1950 ring
->irq_put(ring
);
1951 ring
->trace_irq_seqno
= 0;
1954 WARN_ON(i915_verify_lists(ring
->dev
));
1958 i915_gem_retire_requests(struct drm_device
*dev
)
1960 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1963 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1964 struct drm_i915_gem_object
*obj
, *next
;
1966 /* We must be careful that during unbind() we do not
1967 * accidentally infinitely recurse into retire requests.
1969 * retire -> free -> unbind -> wait -> retire_ring
1971 list_for_each_entry_safe(obj
, next
,
1972 &dev_priv
->mm
.deferred_free_list
,
1974 i915_gem_free_object_tail(obj
);
1977 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1978 i915_gem_retire_requests_ring(&dev_priv
->ring
[i
]);
1982 i915_gem_retire_work_handler(struct work_struct
*work
)
1984 drm_i915_private_t
*dev_priv
;
1985 struct drm_device
*dev
;
1989 dev_priv
= container_of(work
, drm_i915_private_t
,
1990 mm
.retire_work
.work
);
1991 dev
= dev_priv
->dev
;
1993 /* Come back later if the device is busy... */
1994 if (!mutex_trylock(&dev
->struct_mutex
)) {
1995 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1999 i915_gem_retire_requests(dev
);
2001 /* Send a periodic flush down the ring so we don't hold onto GEM
2002 * objects indefinitely.
2005 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2006 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[i
];
2008 if (!list_empty(&ring
->gpu_write_list
)) {
2009 struct drm_i915_gem_request
*request
;
2012 ret
= i915_gem_flush_ring(ring
,
2013 0, I915_GEM_GPU_DOMAINS
);
2014 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2015 if (ret
|| request
== NULL
||
2016 i915_add_request(ring
, NULL
, request
))
2020 idle
&= list_empty(&ring
->request_list
);
2023 if (!dev_priv
->mm
.suspended
&& !idle
)
2024 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2026 mutex_unlock(&dev
->struct_mutex
);
2030 * Waits for a sequence number to be signaled, and cleans up the
2031 * request and object lists appropriately for that event.
2034 i915_wait_request(struct intel_ring_buffer
*ring
,
2037 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2043 if (atomic_read(&dev_priv
->mm
.wedged
)) {
2044 struct completion
*x
= &dev_priv
->error_completion
;
2045 bool recovery_complete
;
2046 unsigned long flags
;
2048 /* Give the error handler a chance to run. */
2049 spin_lock_irqsave(&x
->wait
.lock
, flags
);
2050 recovery_complete
= x
->done
> 0;
2051 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
2053 return recovery_complete
? -EIO
: -EAGAIN
;
2056 if (seqno
== ring
->outstanding_lazy_request
) {
2057 struct drm_i915_gem_request
*request
;
2059 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2060 if (request
== NULL
)
2063 ret
= i915_add_request(ring
, NULL
, request
);
2069 seqno
= request
->seqno
;
2072 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
2073 if (HAS_PCH_SPLIT(ring
->dev
))
2074 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2076 ier
= I915_READ(IER
);
2078 DRM_ERROR("something (likely vbetool) disabled "
2079 "interrupts, re-enabling\n");
2080 i915_driver_irq_preinstall(ring
->dev
);
2081 i915_driver_irq_postinstall(ring
->dev
);
2084 trace_i915_gem_request_wait_begin(ring
, seqno
);
2086 ring
->waiting_seqno
= seqno
;
2087 if (ring
->irq_get(ring
)) {
2088 if (dev_priv
->mm
.interruptible
)
2089 ret
= wait_event_interruptible(ring
->irq_queue
,
2090 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2091 || atomic_read(&dev_priv
->mm
.wedged
));
2093 wait_event(ring
->irq_queue
,
2094 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2095 || atomic_read(&dev_priv
->mm
.wedged
));
2097 ring
->irq_put(ring
);
2098 } else if (wait_for(i915_seqno_passed(ring
->get_seqno(ring
),
2100 atomic_read(&dev_priv
->mm
.wedged
), 3000))
2102 ring
->waiting_seqno
= 0;
2104 trace_i915_gem_request_wait_end(ring
, seqno
);
2106 if (atomic_read(&dev_priv
->mm
.wedged
))
2109 if (ret
&& ret
!= -ERESTARTSYS
)
2110 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2111 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2112 dev_priv
->next_seqno
);
2114 /* Directly dispatch request retiring. While we have the work queue
2115 * to handle this, the waiter on a request often wants an associated
2116 * buffer to have made it to the inactive list, and we would need
2117 * a separate wait queue to handle that.
2120 i915_gem_retire_requests_ring(ring
);
2126 * Ensures that all rendering to the object has completed and the object is
2127 * safe to unbind from the GTT or access from the CPU.
2130 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
)
2134 /* This function only exists to support waiting for existing rendering,
2135 * not for emitting required flushes.
2137 BUG_ON((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2139 /* If there is rendering queued on the buffer being evicted, wait for
2143 ret
= i915_wait_request(obj
->ring
, obj
->last_rendering_seqno
);
2152 * Unbinds an object from the GTT aperture.
2155 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2159 if (obj
->gtt_space
== NULL
)
2162 if (obj
->pin_count
!= 0) {
2163 DRM_ERROR("Attempting to unbind pinned buffer\n");
2167 /* blow away mappings if mapped through GTT */
2168 i915_gem_release_mmap(obj
);
2170 /* Move the object to the CPU domain to ensure that
2171 * any possible CPU writes while it's not in the GTT
2172 * are flushed when we go to remap it. This will
2173 * also ensure that all pending GPU writes are finished
2176 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2177 if (ret
== -ERESTARTSYS
)
2179 /* Continue on if we fail due to EIO, the GPU is hung so we
2180 * should be safe and we need to cleanup or else we might
2181 * cause memory corruption through use-after-free.
2184 i915_gem_clflush_object(obj
);
2185 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2188 /* release the fence reg _after_ flushing */
2189 ret
= i915_gem_object_put_fence(obj
);
2190 if (ret
== -ERESTARTSYS
)
2193 trace_i915_gem_object_unbind(obj
);
2195 i915_gem_gtt_unbind_object(obj
);
2196 i915_gem_object_put_pages_gtt(obj
);
2198 list_del_init(&obj
->gtt_list
);
2199 list_del_init(&obj
->mm_list
);
2200 /* Avoid an unnecessary call to unbind on rebind. */
2201 obj
->map_and_fenceable
= true;
2203 drm_mm_put_block(obj
->gtt_space
);
2204 obj
->gtt_space
= NULL
;
2205 obj
->gtt_offset
= 0;
2207 if (i915_gem_object_is_purgeable(obj
))
2208 i915_gem_object_truncate(obj
);
2214 i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
2215 uint32_t invalidate_domains
,
2216 uint32_t flush_domains
)
2220 trace_i915_gem_ring_flush(ring
, invalidate_domains
, flush_domains
);
2222 ret
= ring
->flush(ring
, invalidate_domains
, flush_domains
);
2226 i915_gem_process_flushing_list(ring
, flush_domains
);
2230 static int i915_ring_idle(struct intel_ring_buffer
*ring
)
2234 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2237 if (!list_empty(&ring
->gpu_write_list
)) {
2238 ret
= i915_gem_flush_ring(ring
,
2239 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2244 return i915_wait_request(ring
, i915_gem_next_request_seqno(ring
));
2248 i915_gpu_idle(struct drm_device
*dev
)
2250 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2254 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2255 list_empty(&dev_priv
->mm
.active_list
));
2259 /* Flush everything onto the inactive list. */
2260 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2261 ret
= i915_ring_idle(&dev_priv
->ring
[i
]);
2269 static int sandybridge_write_fence_reg(struct drm_i915_gem_object
*obj
,
2270 struct intel_ring_buffer
*pipelined
)
2272 struct drm_device
*dev
= obj
->base
.dev
;
2273 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2274 u32 size
= obj
->gtt_space
->size
;
2275 int regnum
= obj
->fence_reg
;
2278 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2280 val
|= obj
->gtt_offset
& 0xfffff000;
2281 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2282 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2284 if (obj
->tiling_mode
== I915_TILING_Y
)
2285 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2286 val
|= I965_FENCE_REG_VALID
;
2289 int ret
= intel_ring_begin(pipelined
, 6);
2293 intel_ring_emit(pipelined
, MI_NOOP
);
2294 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(2));
2295 intel_ring_emit(pipelined
, FENCE_REG_SANDYBRIDGE_0
+ regnum
*8);
2296 intel_ring_emit(pipelined
, (u32
)val
);
2297 intel_ring_emit(pipelined
, FENCE_REG_SANDYBRIDGE_0
+ regnum
*8 + 4);
2298 intel_ring_emit(pipelined
, (u32
)(val
>> 32));
2299 intel_ring_advance(pipelined
);
2301 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ regnum
* 8, val
);
2306 static int i965_write_fence_reg(struct drm_i915_gem_object
*obj
,
2307 struct intel_ring_buffer
*pipelined
)
2309 struct drm_device
*dev
= obj
->base
.dev
;
2310 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2311 u32 size
= obj
->gtt_space
->size
;
2312 int regnum
= obj
->fence_reg
;
2315 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2317 val
|= obj
->gtt_offset
& 0xfffff000;
2318 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2319 if (obj
->tiling_mode
== I915_TILING_Y
)
2320 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2321 val
|= I965_FENCE_REG_VALID
;
2324 int ret
= intel_ring_begin(pipelined
, 6);
2328 intel_ring_emit(pipelined
, MI_NOOP
);
2329 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(2));
2330 intel_ring_emit(pipelined
, FENCE_REG_965_0
+ regnum
*8);
2331 intel_ring_emit(pipelined
, (u32
)val
);
2332 intel_ring_emit(pipelined
, FENCE_REG_965_0
+ regnum
*8 + 4);
2333 intel_ring_emit(pipelined
, (u32
)(val
>> 32));
2334 intel_ring_advance(pipelined
);
2336 I915_WRITE64(FENCE_REG_965_0
+ regnum
* 8, val
);
2341 static int i915_write_fence_reg(struct drm_i915_gem_object
*obj
,
2342 struct intel_ring_buffer
*pipelined
)
2344 struct drm_device
*dev
= obj
->base
.dev
;
2345 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2346 u32 size
= obj
->gtt_space
->size
;
2347 u32 fence_reg
, val
, pitch_val
;
2350 if (WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2351 (size
& -size
) != size
||
2352 (obj
->gtt_offset
& (size
- 1)),
2353 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2354 obj
->gtt_offset
, obj
->map_and_fenceable
, size
))
2357 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2362 /* Note: pitch better be a power of two tile widths */
2363 pitch_val
= obj
->stride
/ tile_width
;
2364 pitch_val
= ffs(pitch_val
) - 1;
2366 val
= obj
->gtt_offset
;
2367 if (obj
->tiling_mode
== I915_TILING_Y
)
2368 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2369 val
|= I915_FENCE_SIZE_BITS(size
);
2370 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2371 val
|= I830_FENCE_REG_VALID
;
2373 fence_reg
= obj
->fence_reg
;
2375 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2377 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2380 int ret
= intel_ring_begin(pipelined
, 4);
2384 intel_ring_emit(pipelined
, MI_NOOP
);
2385 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(1));
2386 intel_ring_emit(pipelined
, fence_reg
);
2387 intel_ring_emit(pipelined
, val
);
2388 intel_ring_advance(pipelined
);
2390 I915_WRITE(fence_reg
, val
);
2395 static int i830_write_fence_reg(struct drm_i915_gem_object
*obj
,
2396 struct intel_ring_buffer
*pipelined
)
2398 struct drm_device
*dev
= obj
->base
.dev
;
2399 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2400 u32 size
= obj
->gtt_space
->size
;
2401 int regnum
= obj
->fence_reg
;
2405 if (WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2406 (size
& -size
) != size
||
2407 (obj
->gtt_offset
& (size
- 1)),
2408 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2409 obj
->gtt_offset
, size
))
2412 pitch_val
= obj
->stride
/ 128;
2413 pitch_val
= ffs(pitch_val
) - 1;
2415 val
= obj
->gtt_offset
;
2416 if (obj
->tiling_mode
== I915_TILING_Y
)
2417 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2418 val
|= I830_FENCE_SIZE_BITS(size
);
2419 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2420 val
|= I830_FENCE_REG_VALID
;
2423 int ret
= intel_ring_begin(pipelined
, 4);
2427 intel_ring_emit(pipelined
, MI_NOOP
);
2428 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(1));
2429 intel_ring_emit(pipelined
, FENCE_REG_830_0
+ regnum
*4);
2430 intel_ring_emit(pipelined
, val
);
2431 intel_ring_advance(pipelined
);
2433 I915_WRITE(FENCE_REG_830_0
+ regnum
* 4, val
);
2438 static bool ring_passed_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
2440 return i915_seqno_passed(ring
->get_seqno(ring
), seqno
);
2444 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
,
2445 struct intel_ring_buffer
*pipelined
)
2449 if (obj
->fenced_gpu_access
) {
2450 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2451 ret
= i915_gem_flush_ring(obj
->last_fenced_ring
,
2452 0, obj
->base
.write_domain
);
2457 obj
->fenced_gpu_access
= false;
2460 if (obj
->last_fenced_seqno
&& pipelined
!= obj
->last_fenced_ring
) {
2461 if (!ring_passed_seqno(obj
->last_fenced_ring
,
2462 obj
->last_fenced_seqno
)) {
2463 ret
= i915_wait_request(obj
->last_fenced_ring
,
2464 obj
->last_fenced_seqno
);
2469 obj
->last_fenced_seqno
= 0;
2470 obj
->last_fenced_ring
= NULL
;
2473 /* Ensure that all CPU reads are completed before installing a fence
2474 * and all writes before removing the fence.
2476 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2483 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2487 if (obj
->tiling_mode
)
2488 i915_gem_release_mmap(obj
);
2490 ret
= i915_gem_object_flush_fence(obj
, NULL
);
2494 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2495 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2496 i915_gem_clear_fence_reg(obj
->base
.dev
,
2497 &dev_priv
->fence_regs
[obj
->fence_reg
]);
2499 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2505 static struct drm_i915_fence_reg
*
2506 i915_find_fence_reg(struct drm_device
*dev
,
2507 struct intel_ring_buffer
*pipelined
)
2509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2510 struct drm_i915_fence_reg
*reg
, *first
, *avail
;
2513 /* First try to find a free reg */
2515 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2516 reg
= &dev_priv
->fence_regs
[i
];
2520 if (!reg
->obj
->pin_count
)
2527 /* None available, try to steal one or wait for a user to finish */
2528 avail
= first
= NULL
;
2529 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2530 if (reg
->obj
->pin_count
)
2537 !reg
->obj
->last_fenced_ring
||
2538 reg
->obj
->last_fenced_ring
== pipelined
) {
2551 * i915_gem_object_get_fence - set up a fence reg for an object
2552 * @obj: object to map through a fence reg
2553 * @pipelined: ring on which to queue the change, or NULL for CPU access
2554 * @interruptible: must we wait uninterruptibly for the register to retire?
2556 * When mapping objects through the GTT, userspace wants to be able to write
2557 * to them without having to worry about swizzling if the object is tiled.
2559 * This function walks the fence regs looking for a free one for @obj,
2560 * stealing one if it can't find any.
2562 * It then sets up the reg based on the object's properties: address, pitch
2563 * and tiling format.
2566 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
,
2567 struct intel_ring_buffer
*pipelined
)
2569 struct drm_device
*dev
= obj
->base
.dev
;
2570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2571 struct drm_i915_fence_reg
*reg
;
2574 /* XXX disable pipelining. There are bugs. Shocking. */
2577 /* Just update our place in the LRU if our fence is getting reused. */
2578 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2579 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2580 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2582 if (!obj
->fenced_gpu_access
&& !obj
->last_fenced_seqno
)
2586 if (reg
->setup_seqno
) {
2587 if (!ring_passed_seqno(obj
->last_fenced_ring
,
2588 reg
->setup_seqno
)) {
2589 ret
= i915_wait_request(obj
->last_fenced_ring
,
2595 reg
->setup_seqno
= 0;
2597 } else if (obj
->last_fenced_ring
&&
2598 obj
->last_fenced_ring
!= pipelined
) {
2599 ret
= i915_gem_object_flush_fence(obj
, pipelined
);
2602 } else if (obj
->tiling_changed
) {
2603 if (obj
->fenced_gpu_access
) {
2604 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2605 ret
= i915_gem_flush_ring(obj
->ring
,
2606 0, obj
->base
.write_domain
);
2611 obj
->fenced_gpu_access
= false;
2615 if (!obj
->fenced_gpu_access
&& !obj
->last_fenced_seqno
)
2617 BUG_ON(!pipelined
&& reg
->setup_seqno
);
2619 if (obj
->tiling_changed
) {
2622 i915_gem_next_request_seqno(pipelined
);
2623 obj
->last_fenced_seqno
= reg
->setup_seqno
;
2624 obj
->last_fenced_ring
= pipelined
;
2632 reg
= i915_find_fence_reg(dev
, pipelined
);
2636 ret
= i915_gem_object_flush_fence(obj
, pipelined
);
2641 struct drm_i915_gem_object
*old
= reg
->obj
;
2643 drm_gem_object_reference(&old
->base
);
2645 if (old
->tiling_mode
)
2646 i915_gem_release_mmap(old
);
2648 ret
= i915_gem_object_flush_fence(old
, pipelined
);
2650 drm_gem_object_unreference(&old
->base
);
2654 if (old
->last_fenced_seqno
== 0 && obj
->last_fenced_seqno
== 0)
2657 old
->fence_reg
= I915_FENCE_REG_NONE
;
2658 old
->last_fenced_ring
= pipelined
;
2659 old
->last_fenced_seqno
=
2660 pipelined
? i915_gem_next_request_seqno(pipelined
) : 0;
2662 drm_gem_object_unreference(&old
->base
);
2663 } else if (obj
->last_fenced_seqno
== 0)
2667 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2668 obj
->fence_reg
= reg
- dev_priv
->fence_regs
;
2669 obj
->last_fenced_ring
= pipelined
;
2672 pipelined
? i915_gem_next_request_seqno(pipelined
) : 0;
2673 obj
->last_fenced_seqno
= reg
->setup_seqno
;
2676 obj
->tiling_changed
= false;
2677 switch (INTEL_INFO(dev
)->gen
) {
2679 ret
= sandybridge_write_fence_reg(obj
, pipelined
);
2683 ret
= i965_write_fence_reg(obj
, pipelined
);
2686 ret
= i915_write_fence_reg(obj
, pipelined
);
2689 ret
= i830_write_fence_reg(obj
, pipelined
);
2697 * i915_gem_clear_fence_reg - clear out fence register info
2698 * @obj: object to clear
2700 * Zeroes out the fence register itself and clears out the associated
2701 * data structures in dev_priv and obj.
2704 i915_gem_clear_fence_reg(struct drm_device
*dev
,
2705 struct drm_i915_fence_reg
*reg
)
2707 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2708 uint32_t fence_reg
= reg
- dev_priv
->fence_regs
;
2710 switch (INTEL_INFO(dev
)->gen
) {
2712 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ fence_reg
*8, 0);
2716 I915_WRITE64(FENCE_REG_965_0
+ fence_reg
*8, 0);
2720 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2723 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2725 I915_WRITE(fence_reg
, 0);
2729 list_del_init(®
->lru_list
);
2731 reg
->setup_seqno
= 0;
2735 * Finds free space in the GTT aperture and binds the object there.
2738 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2740 bool map_and_fenceable
)
2742 struct drm_device
*dev
= obj
->base
.dev
;
2743 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2744 struct drm_mm_node
*free_space
;
2745 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2746 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2747 bool mappable
, fenceable
;
2750 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2751 DRM_ERROR("Attempting to bind a purgeable object\n");
2755 fence_size
= i915_gem_get_gtt_size(obj
);
2756 fence_alignment
= i915_gem_get_gtt_alignment(obj
);
2757 unfenced_alignment
= i915_gem_get_unfenced_gtt_alignment(obj
);
2760 alignment
= map_and_fenceable
? fence_alignment
:
2762 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2763 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2767 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2769 /* If the object is bigger than the entire aperture, reject it early
2770 * before evicting everything in a vain attempt to find space.
2772 if (obj
->base
.size
>
2773 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2774 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2779 if (map_and_fenceable
)
2781 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2783 dev_priv
->mm
.gtt_mappable_end
,
2786 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2787 size
, alignment
, 0);
2789 if (free_space
!= NULL
) {
2790 if (map_and_fenceable
)
2792 drm_mm_get_block_range_generic(free_space
,
2794 dev_priv
->mm
.gtt_mappable_end
,
2798 drm_mm_get_block(free_space
, size
, alignment
);
2800 if (obj
->gtt_space
== NULL
) {
2801 /* If the gtt is empty and we're still having trouble
2802 * fitting our object in, we're out of memory.
2804 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2812 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2814 drm_mm_put_block(obj
->gtt_space
);
2815 obj
->gtt_space
= NULL
;
2817 if (ret
== -ENOMEM
) {
2818 /* first try to reclaim some memory by clearing the GTT */
2819 ret
= i915_gem_evict_everything(dev
, false);
2821 /* now try to shrink everyone else */
2836 ret
= i915_gem_gtt_bind_object(obj
);
2838 i915_gem_object_put_pages_gtt(obj
);
2839 drm_mm_put_block(obj
->gtt_space
);
2840 obj
->gtt_space
= NULL
;
2842 if (i915_gem_evict_everything(dev
, false))
2848 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
2849 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2851 /* Assert that the object is not currently in any GPU domain. As it
2852 * wasn't in the GTT, there shouldn't be any way it could have been in
2855 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2856 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2858 obj
->gtt_offset
= obj
->gtt_space
->start
;
2861 obj
->gtt_space
->size
== fence_size
&&
2862 (obj
->gtt_space
->start
& (fence_alignment
-1)) == 0;
2865 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2867 obj
->map_and_fenceable
= mappable
&& fenceable
;
2869 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2874 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2876 /* If we don't have a page list set up, then we're not pinned
2877 * to GPU, and we can ignore the cache flush because it'll happen
2878 * again at bind time.
2880 if (obj
->pages
== NULL
)
2883 trace_i915_gem_object_clflush(obj
);
2885 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2888 /** Flushes any GPU write domain for the object if it's dirty. */
2890 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
)
2892 if ((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2895 /* Queue the GPU write cache flushing we need. */
2896 return i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
2899 /** Flushes the GTT write domain for the object if it's dirty. */
2901 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2903 uint32_t old_write_domain
;
2905 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2908 /* No actual flushing is required for the GTT write domain. Writes
2909 * to it immediately go to main memory as far as we know, so there's
2910 * no chipset flush. It also doesn't land in render cache.
2912 * However, we do have to enforce the order so that all writes through
2913 * the GTT land before any writes to the device, such as updates to
2918 i915_gem_release_mmap(obj
);
2920 old_write_domain
= obj
->base
.write_domain
;
2921 obj
->base
.write_domain
= 0;
2923 trace_i915_gem_object_change_domain(obj
,
2924 obj
->base
.read_domains
,
2928 /** Flushes the CPU write domain for the object if it's dirty. */
2930 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2932 uint32_t old_write_domain
;
2934 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2937 i915_gem_clflush_object(obj
);
2938 intel_gtt_chipset_flush();
2939 old_write_domain
= obj
->base
.write_domain
;
2940 obj
->base
.write_domain
= 0;
2942 trace_i915_gem_object_change_domain(obj
,
2943 obj
->base
.read_domains
,
2948 * Moves a single object to the GTT read, and possibly write domain.
2950 * This function returns when the move is complete, including waiting on
2954 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2956 uint32_t old_write_domain
, old_read_domains
;
2959 /* Not valid to be called on unbound objects. */
2960 if (obj
->gtt_space
== NULL
)
2963 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
2966 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2970 if (obj
->pending_gpu_write
|| write
) {
2971 ret
= i915_gem_object_wait_rendering(obj
);
2976 i915_gem_object_flush_cpu_write_domain(obj
);
2978 old_write_domain
= obj
->base
.write_domain
;
2979 old_read_domains
= obj
->base
.read_domains
;
2981 /* It should now be out of any other write domains, and we can update
2982 * the domain values for our changes.
2984 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2985 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2987 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2988 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2992 trace_i915_gem_object_change_domain(obj
,
3000 * Prepare buffer for display plane. Use uninterruptible for possible flush
3001 * wait, as in modesetting process we're not supposed to be interrupted.
3004 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object
*obj
,
3005 struct intel_ring_buffer
*pipelined
)
3007 uint32_t old_read_domains
;
3010 /* Not valid to be called on unbound objects. */
3011 if (obj
->gtt_space
== NULL
)
3014 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3019 /* Currently, we are always called from an non-interruptible context. */
3020 if (pipelined
!= obj
->ring
) {
3021 ret
= i915_gem_object_wait_rendering(obj
);
3026 i915_gem_object_flush_cpu_write_domain(obj
);
3028 old_read_domains
= obj
->base
.read_domains
;
3029 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3031 trace_i915_gem_object_change_domain(obj
,
3033 obj
->base
.write_domain
);
3039 i915_gem_object_flush_gpu(struct drm_i915_gem_object
*obj
)
3046 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3047 ret
= i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
3052 return i915_gem_object_wait_rendering(obj
);
3056 * Moves a single object to the CPU read, and possibly write domain.
3058 * This function returns when the move is complete, including waiting on
3062 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3064 uint32_t old_write_domain
, old_read_domains
;
3067 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3070 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3074 ret
= i915_gem_object_wait_rendering(obj
);
3078 i915_gem_object_flush_gtt_write_domain(obj
);
3080 /* If we have a partially-valid cache of the object in the CPU,
3081 * finish invalidating it and free the per-page flags.
3083 i915_gem_object_set_to_full_cpu_read_domain(obj
);
3085 old_write_domain
= obj
->base
.write_domain
;
3086 old_read_domains
= obj
->base
.read_domains
;
3088 /* Flush the CPU cache if it's still invalid. */
3089 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3090 i915_gem_clflush_object(obj
);
3092 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3095 /* It should now be out of any other write domains, and we can update
3096 * the domain values for our changes.
3098 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3100 /* If we're writing through the CPU, then the GPU read domains will
3101 * need to be invalidated at next use.
3104 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3105 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3108 trace_i915_gem_object_change_domain(obj
,
3116 * Moves the object from a partially CPU read to a full one.
3118 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3119 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3122 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object
*obj
)
3124 if (!obj
->page_cpu_valid
)
3127 /* If we're partially in the CPU read domain, finish moving it in.
3129 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3132 for (i
= 0; i
<= (obj
->base
.size
- 1) / PAGE_SIZE
; i
++) {
3133 if (obj
->page_cpu_valid
[i
])
3135 drm_clflush_pages(obj
->pages
+ i
, 1);
3139 /* Free the page_cpu_valid mappings which are now stale, whether
3140 * or not we've got I915_GEM_DOMAIN_CPU.
3142 kfree(obj
->page_cpu_valid
);
3143 obj
->page_cpu_valid
= NULL
;
3147 * Set the CPU read domain on a range of the object.
3149 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3150 * not entirely valid. The page_cpu_valid member of the object flags which
3151 * pages have been flushed, and will be respected by
3152 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3153 * of the whole object.
3155 * This function returns when the move is complete, including waiting on
3159 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object
*obj
,
3160 uint64_t offset
, uint64_t size
)
3162 uint32_t old_read_domains
;
3165 if (offset
== 0 && size
== obj
->base
.size
)
3166 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3168 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3172 ret
= i915_gem_object_wait_rendering(obj
);
3176 i915_gem_object_flush_gtt_write_domain(obj
);
3178 /* If we're already fully in the CPU read domain, we're done. */
3179 if (obj
->page_cpu_valid
== NULL
&&
3180 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3183 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3184 * newly adding I915_GEM_DOMAIN_CPU
3186 if (obj
->page_cpu_valid
== NULL
) {
3187 obj
->page_cpu_valid
= kzalloc(obj
->base
.size
/ PAGE_SIZE
,
3189 if (obj
->page_cpu_valid
== NULL
)
3191 } else if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3192 memset(obj
->page_cpu_valid
, 0, obj
->base
.size
/ PAGE_SIZE
);
3194 /* Flush the cache on any pages that are still invalid from the CPU's
3197 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3199 if (obj
->page_cpu_valid
[i
])
3202 drm_clflush_pages(obj
->pages
+ i
, 1);
3204 obj
->page_cpu_valid
[i
] = 1;
3207 /* It should now be out of any other write domains, and we can update
3208 * the domain values for our changes.
3210 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3212 old_read_domains
= obj
->base
.read_domains
;
3213 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3215 trace_i915_gem_object_change_domain(obj
,
3217 obj
->base
.write_domain
);
3222 /* Throttle our rendering by waiting until the ring has completed our requests
3223 * emitted over 20 msec ago.
3225 * Note that if we were to use the current jiffies each time around the loop,
3226 * we wouldn't escape the function with any frames outstanding if the time to
3227 * render a frame was over 20ms.
3229 * This should get us reasonable parallelism between CPU and GPU but also
3230 * relatively low latency when blocking on a particular request to finish.
3233 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3236 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3237 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3238 struct drm_i915_gem_request
*request
;
3239 struct intel_ring_buffer
*ring
= NULL
;
3243 if (atomic_read(&dev_priv
->mm
.wedged
))
3246 spin_lock(&file_priv
->mm
.lock
);
3247 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3248 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3251 ring
= request
->ring
;
3252 seqno
= request
->seqno
;
3254 spin_unlock(&file_priv
->mm
.lock
);
3260 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3261 /* And wait for the seqno passing without holding any locks and
3262 * causing extra latency for others. This is safe as the irq
3263 * generation is designed to be run atomically and so is
3266 if (ring
->irq_get(ring
)) {
3267 ret
= wait_event_interruptible(ring
->irq_queue
,
3268 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3269 || atomic_read(&dev_priv
->mm
.wedged
));
3270 ring
->irq_put(ring
);
3272 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3278 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3284 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3286 bool map_and_fenceable
)
3288 struct drm_device
*dev
= obj
->base
.dev
;
3289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3292 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3293 WARN_ON(i915_verify_lists(dev
));
3295 if (obj
->gtt_space
!= NULL
) {
3296 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3297 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3298 WARN(obj
->pin_count
,
3299 "bo is already pinned with incorrect alignment:"
3300 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3301 " obj->map_and_fenceable=%d\n",
3302 obj
->gtt_offset
, alignment
,
3304 obj
->map_and_fenceable
);
3305 ret
= i915_gem_object_unbind(obj
);
3311 if (obj
->gtt_space
== NULL
) {
3312 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3318 if (obj
->pin_count
++ == 0) {
3320 list_move_tail(&obj
->mm_list
,
3321 &dev_priv
->mm
.pinned_list
);
3323 obj
->pin_mappable
|= map_and_fenceable
;
3325 WARN_ON(i915_verify_lists(dev
));
3330 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3332 struct drm_device
*dev
= obj
->base
.dev
;
3333 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3335 WARN_ON(i915_verify_lists(dev
));
3336 BUG_ON(obj
->pin_count
== 0);
3337 BUG_ON(obj
->gtt_space
== NULL
);
3339 if (--obj
->pin_count
== 0) {
3341 list_move_tail(&obj
->mm_list
,
3342 &dev_priv
->mm
.inactive_list
);
3343 obj
->pin_mappable
= false;
3345 WARN_ON(i915_verify_lists(dev
));
3349 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3350 struct drm_file
*file
)
3352 struct drm_i915_gem_pin
*args
= data
;
3353 struct drm_i915_gem_object
*obj
;
3356 ret
= i915_mutex_lock_interruptible(dev
);
3360 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3361 if (&obj
->base
== NULL
) {
3366 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3367 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3372 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3373 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3379 obj
->user_pin_count
++;
3380 obj
->pin_filp
= file
;
3381 if (obj
->user_pin_count
== 1) {
3382 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3387 /* XXX - flush the CPU caches for pinned objects
3388 * as the X server doesn't manage domains yet
3390 i915_gem_object_flush_cpu_write_domain(obj
);
3391 args
->offset
= obj
->gtt_offset
;
3393 drm_gem_object_unreference(&obj
->base
);
3395 mutex_unlock(&dev
->struct_mutex
);
3400 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3401 struct drm_file
*file
)
3403 struct drm_i915_gem_pin
*args
= data
;
3404 struct drm_i915_gem_object
*obj
;
3407 ret
= i915_mutex_lock_interruptible(dev
);
3411 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3412 if (&obj
->base
== NULL
) {
3417 if (obj
->pin_filp
!= file
) {
3418 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3423 obj
->user_pin_count
--;
3424 if (obj
->user_pin_count
== 0) {
3425 obj
->pin_filp
= NULL
;
3426 i915_gem_object_unpin(obj
);
3430 drm_gem_object_unreference(&obj
->base
);
3432 mutex_unlock(&dev
->struct_mutex
);
3437 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3438 struct drm_file
*file
)
3440 struct drm_i915_gem_busy
*args
= data
;
3441 struct drm_i915_gem_object
*obj
;
3444 ret
= i915_mutex_lock_interruptible(dev
);
3448 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3449 if (&obj
->base
== NULL
) {
3454 /* Count all active objects as busy, even if they are currently not used
3455 * by the gpu. Users of this interface expect objects to eventually
3456 * become non-busy without any further actions, therefore emit any
3457 * necessary flushes here.
3459 args
->busy
= obj
->active
;
3461 /* Unconditionally flush objects, even when the gpu still uses this
3462 * object. Userspace calling this function indicates that it wants to
3463 * use this buffer rather sooner than later, so issuing the required
3464 * flush earlier is beneficial.
3466 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3467 ret
= i915_gem_flush_ring(obj
->ring
,
3468 0, obj
->base
.write_domain
);
3469 } else if (obj
->ring
->outstanding_lazy_request
==
3470 obj
->last_rendering_seqno
) {
3471 struct drm_i915_gem_request
*request
;
3473 /* This ring is not being cleared by active usage,
3474 * so emit a request to do so.
3476 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3478 ret
= i915_add_request(obj
->ring
, NULL
,request
);
3483 /* Update the active list for the hardware's current position.
3484 * Otherwise this only updates on a delayed timer or when irqs
3485 * are actually unmasked, and our working set ends up being
3486 * larger than required.
3488 i915_gem_retire_requests_ring(obj
->ring
);
3490 args
->busy
= obj
->active
;
3493 drm_gem_object_unreference(&obj
->base
);
3495 mutex_unlock(&dev
->struct_mutex
);
3500 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3501 struct drm_file
*file_priv
)
3503 return i915_gem_ring_throttle(dev
, file_priv
);
3507 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3508 struct drm_file
*file_priv
)
3510 struct drm_i915_gem_madvise
*args
= data
;
3511 struct drm_i915_gem_object
*obj
;
3514 switch (args
->madv
) {
3515 case I915_MADV_DONTNEED
:
3516 case I915_MADV_WILLNEED
:
3522 ret
= i915_mutex_lock_interruptible(dev
);
3526 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3527 if (&obj
->base
== NULL
) {
3532 if (obj
->pin_count
) {
3537 if (obj
->madv
!= __I915_MADV_PURGED
)
3538 obj
->madv
= args
->madv
;
3540 /* if the object is no longer bound, discard its backing storage */
3541 if (i915_gem_object_is_purgeable(obj
) &&
3542 obj
->gtt_space
== NULL
)
3543 i915_gem_object_truncate(obj
);
3545 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3548 drm_gem_object_unreference(&obj
->base
);
3550 mutex_unlock(&dev
->struct_mutex
);
3554 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3558 struct drm_i915_gem_object
*obj
;
3560 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3564 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3569 i915_gem_info_add_obj(dev_priv
, size
);
3571 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3572 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3574 obj
->agp_type
= AGP_USER_MEMORY
;
3575 obj
->base
.driver_private
= NULL
;
3576 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3577 INIT_LIST_HEAD(&obj
->mm_list
);
3578 INIT_LIST_HEAD(&obj
->gtt_list
);
3579 INIT_LIST_HEAD(&obj
->ring_list
);
3580 INIT_LIST_HEAD(&obj
->exec_list
);
3581 INIT_LIST_HEAD(&obj
->gpu_write_list
);
3582 obj
->madv
= I915_MADV_WILLNEED
;
3583 /* Avoid an unnecessary call to unbind on the first bind. */
3584 obj
->map_and_fenceable
= true;
3589 int i915_gem_init_object(struct drm_gem_object
*obj
)
3596 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
)
3598 struct drm_device
*dev
= obj
->base
.dev
;
3599 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3602 ret
= i915_gem_object_unbind(obj
);
3603 if (ret
== -ERESTARTSYS
) {
3604 list_move(&obj
->mm_list
,
3605 &dev_priv
->mm
.deferred_free_list
);
3609 if (obj
->base
.map_list
.map
)
3610 i915_gem_free_mmap_offset(obj
);
3612 drm_gem_object_release(&obj
->base
);
3613 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3615 kfree(obj
->page_cpu_valid
);
3619 trace_i915_gem_object_destroy(obj
);
3622 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3624 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3625 struct drm_device
*dev
= obj
->base
.dev
;
3627 while (obj
->pin_count
> 0)
3628 i915_gem_object_unpin(obj
);
3631 i915_gem_detach_phys_object(dev
, obj
);
3633 i915_gem_free_object_tail(obj
);
3637 i915_gem_idle(struct drm_device
*dev
)
3639 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3642 mutex_lock(&dev
->struct_mutex
);
3644 if (dev_priv
->mm
.suspended
) {
3645 mutex_unlock(&dev
->struct_mutex
);
3649 ret
= i915_gpu_idle(dev
);
3651 mutex_unlock(&dev
->struct_mutex
);
3655 /* Under UMS, be paranoid and evict. */
3656 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3657 ret
= i915_gem_evict_inactive(dev
, false);
3659 mutex_unlock(&dev
->struct_mutex
);
3664 i915_gem_reset_fences(dev
);
3666 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3667 * We need to replace this with a semaphore, or something.
3668 * And not confound mm.suspended!
3670 dev_priv
->mm
.suspended
= 1;
3671 del_timer_sync(&dev_priv
->hangcheck_timer
);
3673 i915_kernel_lost_context(dev
);
3674 i915_gem_cleanup_ringbuffer(dev
);
3676 mutex_unlock(&dev
->struct_mutex
);
3678 /* Cancel the retire work handler, which should be idle now. */
3679 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3685 i915_gem_init_ringbuffer(struct drm_device
*dev
)
3687 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3690 ret
= intel_init_render_ring_buffer(dev
);
3695 ret
= intel_init_bsd_ring_buffer(dev
);
3697 goto cleanup_render_ring
;
3701 ret
= intel_init_blt_ring_buffer(dev
);
3703 goto cleanup_bsd_ring
;
3706 dev_priv
->next_seqno
= 1;
3711 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3712 cleanup_render_ring
:
3713 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3718 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3720 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3723 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3724 intel_cleanup_ring_buffer(&dev_priv
->ring
[i
]);
3728 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3729 struct drm_file
*file_priv
)
3731 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3734 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3737 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3738 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3739 atomic_set(&dev_priv
->mm
.wedged
, 0);
3742 mutex_lock(&dev
->struct_mutex
);
3743 dev_priv
->mm
.suspended
= 0;
3745 ret
= i915_gem_init_ringbuffer(dev
);
3747 mutex_unlock(&dev
->struct_mutex
);
3751 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3752 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3753 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3754 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3755 BUG_ON(!list_empty(&dev_priv
->ring
[i
].active_list
));
3756 BUG_ON(!list_empty(&dev_priv
->ring
[i
].request_list
));
3758 mutex_unlock(&dev
->struct_mutex
);
3760 ret
= drm_irq_install(dev
);
3762 goto cleanup_ringbuffer
;
3767 mutex_lock(&dev
->struct_mutex
);
3768 i915_gem_cleanup_ringbuffer(dev
);
3769 dev_priv
->mm
.suspended
= 1;
3770 mutex_unlock(&dev
->struct_mutex
);
3776 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3777 struct drm_file
*file_priv
)
3779 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3782 drm_irq_uninstall(dev
);
3783 return i915_gem_idle(dev
);
3787 i915_gem_lastclose(struct drm_device
*dev
)
3791 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3794 ret
= i915_gem_idle(dev
);
3796 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3800 init_ring_lists(struct intel_ring_buffer
*ring
)
3802 INIT_LIST_HEAD(&ring
->active_list
);
3803 INIT_LIST_HEAD(&ring
->request_list
);
3804 INIT_LIST_HEAD(&ring
->gpu_write_list
);
3808 i915_gem_load(struct drm_device
*dev
)
3811 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3813 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3814 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3815 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3816 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
3817 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
3818 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
3819 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
3820 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3821 init_ring_lists(&dev_priv
->ring
[i
]);
3822 for (i
= 0; i
< 16; i
++)
3823 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
3824 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3825 i915_gem_retire_work_handler
);
3826 init_completion(&dev_priv
->error_completion
);
3828 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3830 u32 tmp
= I915_READ(MI_ARB_STATE
);
3831 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
3832 /* arb state is a masked write, so set bit + bit in mask */
3833 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
3834 I915_WRITE(MI_ARB_STATE
, tmp
);
3838 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
3840 /* Old X drivers will take 0-2 for front, back, depth buffers */
3841 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3842 dev_priv
->fence_reg_start
= 3;
3844 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3845 dev_priv
->num_fence_regs
= 16;
3847 dev_priv
->num_fence_regs
= 8;
3849 /* Initialize fence registers to zero */
3850 switch (INTEL_INFO(dev
)->gen
) {
3852 for (i
= 0; i
< 16; i
++)
3853 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
3857 for (i
= 0; i
< 16; i
++)
3858 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
3861 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3862 for (i
= 0; i
< 8; i
++)
3863 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
3865 for (i
= 0; i
< 8; i
++)
3866 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
3869 i915_gem_detect_bit_6_swizzle(dev
);
3870 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
3872 dev_priv
->mm
.interruptible
= true;
3874 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
3875 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
3876 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
3880 * Create a physically contiguous memory object for this object
3881 * e.g. for cursor + overlay regs
3883 static int i915_gem_init_phys_object(struct drm_device
*dev
,
3884 int id
, int size
, int align
)
3886 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3887 struct drm_i915_gem_phys_object
*phys_obj
;
3890 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3893 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
3899 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
3900 if (!phys_obj
->handle
) {
3905 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3908 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3916 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3918 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3919 struct drm_i915_gem_phys_object
*phys_obj
;
3921 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3924 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3925 if (phys_obj
->cur_obj
) {
3926 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3930 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3932 drm_pci_free(dev
, phys_obj
->handle
);
3934 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3937 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3941 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3942 i915_gem_free_phys_object(dev
, i
);
3945 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3946 struct drm_i915_gem_object
*obj
)
3948 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3955 vaddr
= obj
->phys_obj
->handle
->vaddr
;
3957 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3958 for (i
= 0; i
< page_count
; i
++) {
3959 struct page
*page
= read_cache_page_gfp(mapping
, i
,
3960 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3961 if (!IS_ERR(page
)) {
3962 char *dst
= kmap_atomic(page
);
3963 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
3966 drm_clflush_pages(&page
, 1);
3968 set_page_dirty(page
);
3969 mark_page_accessed(page
);
3970 page_cache_release(page
);
3973 intel_gtt_chipset_flush();
3975 obj
->phys_obj
->cur_obj
= NULL
;
3976 obj
->phys_obj
= NULL
;
3980 i915_gem_attach_phys_object(struct drm_device
*dev
,
3981 struct drm_i915_gem_object
*obj
,
3985 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3986 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3991 if (id
> I915_MAX_PHYS_OBJECT
)
3994 if (obj
->phys_obj
) {
3995 if (obj
->phys_obj
->id
== id
)
3997 i915_gem_detach_phys_object(dev
, obj
);
4000 /* create a new object */
4001 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4002 ret
= i915_gem_init_phys_object(dev
, id
,
4003 obj
->base
.size
, align
);
4005 DRM_ERROR("failed to init phys object %d size: %zu\n",
4006 id
, obj
->base
.size
);
4011 /* bind to the object */
4012 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4013 obj
->phys_obj
->cur_obj
= obj
;
4015 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4017 for (i
= 0; i
< page_count
; i
++) {
4021 page
= read_cache_page_gfp(mapping
, i
,
4022 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
4024 return PTR_ERR(page
);
4026 src
= kmap_atomic(page
);
4027 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4028 memcpy(dst
, src
, PAGE_SIZE
);
4031 mark_page_accessed(page
);
4032 page_cache_release(page
);
4039 i915_gem_phys_pwrite(struct drm_device
*dev
,
4040 struct drm_i915_gem_object
*obj
,
4041 struct drm_i915_gem_pwrite
*args
,
4042 struct drm_file
*file_priv
)
4044 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4045 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4047 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4048 unsigned long unwritten
;
4050 /* The physical object once assigned is fixed for the lifetime
4051 * of the obj, so we can safely drop the lock and continue
4054 mutex_unlock(&dev
->struct_mutex
);
4055 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4056 mutex_lock(&dev
->struct_mutex
);
4061 intel_gtt_chipset_flush();
4065 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4067 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4069 /* Clean up our request list when the client is going away, so that
4070 * later retire_requests won't dereference our soon-to-be-gone
4073 spin_lock(&file_priv
->mm
.lock
);
4074 while (!list_empty(&file_priv
->mm
.request_list
)) {
4075 struct drm_i915_gem_request
*request
;
4077 request
= list_first_entry(&file_priv
->mm
.request_list
,
4078 struct drm_i915_gem_request
,
4080 list_del(&request
->client_list
);
4081 request
->file_priv
= NULL
;
4083 spin_unlock(&file_priv
->mm
.lock
);
4087 i915_gpu_is_active(struct drm_device
*dev
)
4089 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4092 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4093 list_empty(&dev_priv
->mm
.active_list
);
4095 return !lists_empty
;
4099 i915_gem_inactive_shrink(struct shrinker
*shrinker
,
4103 struct drm_i915_private
*dev_priv
=
4104 container_of(shrinker
,
4105 struct drm_i915_private
,
4106 mm
.inactive_shrinker
);
4107 struct drm_device
*dev
= dev_priv
->dev
;
4108 struct drm_i915_gem_object
*obj
, *next
;
4111 if (!mutex_trylock(&dev
->struct_mutex
))
4114 /* "fast-path" to count number of available objects */
4115 if (nr_to_scan
== 0) {
4117 list_for_each_entry(obj
,
4118 &dev_priv
->mm
.inactive_list
,
4121 mutex_unlock(&dev
->struct_mutex
);
4122 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
4126 /* first scan for clean buffers */
4127 i915_gem_retire_requests(dev
);
4129 list_for_each_entry_safe(obj
, next
,
4130 &dev_priv
->mm
.inactive_list
,
4132 if (i915_gem_object_is_purgeable(obj
)) {
4133 if (i915_gem_object_unbind(obj
) == 0 &&
4139 /* second pass, evict/count anything still on the inactive list */
4141 list_for_each_entry_safe(obj
, next
,
4142 &dev_priv
->mm
.inactive_list
,
4145 i915_gem_object_unbind(obj
) == 0)
4151 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
4153 * We are desperate for pages, so as a last resort, wait
4154 * for the GPU to finish and discard whatever we can.
4155 * This has a dramatic impact to reduce the number of
4156 * OOM-killer events whilst running the GPU aggressively.
4158 if (i915_gpu_idle(dev
) == 0)
4161 mutex_unlock(&dev
->struct_mutex
);
4162 return cnt
/ 100 * sysctl_vfs_cache_pressure
;