drivers/spi/spi_mpc83xx.c

   1 /*
   2  * MPC83xx SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/completion.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/delay.h>
  20 #include <linux/irq.h>
  21 #include <linux/device.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/spi_bitbang.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/fsl_devices.h>
  26
  27 #include <asm/irq.h>
  28 #include <asm/io.h>
  29
  30 /* SPI Controller registers */
  31 struct mpc83xx_spi_reg {
  32         u8 res1[0x20];
  33         __be32 mode;
  34         __be32 event;
  35         __be32 mask;
  36         __be32 command;
  37         __be32 transmit;
  38         __be32 receive;
  39 };
  40
  41 /* SPI Controller mode register definitions */
  42 #define SPMODE_LOOP             (1 << 30)
  43 #define SPMODE_CI_INACTIVEHIGH  (1 << 29)
  44 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
  45 #define SPMODE_DIV16            (1 << 27)
  46 #define SPMODE_REV              (1 << 26)
  47 #define SPMODE_MS               (1 << 25)
  48 #define SPMODE_ENABLE           (1 << 24)
  49 #define SPMODE_LEN(x)           ((x) << 20)
  50 #define SPMODE_PM(x)            ((x) << 16)
  51 #define SPMODE_OP               (1 << 14)
  52 #define SPMODE_CG(x)            ((x) << 7)
  53
  54 /*
  55  * Default for SPI Mode:
  56  *      SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
  57  */
  58 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
  59                          SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
  60
  61 /* SPIE register values */
  62 #define SPIE_NE         0x00000200      /* Not empty */
  63 #define SPIE_NF         0x00000100      /* Not full */
  64
  65 /* SPIM register values */
  66 #define SPIM_NE         0x00000200      /* Not empty */
  67 #define SPIM_NF         0x00000100      /* Not full */
  68
  69 /* SPI Controller driver's private data. */
  70 struct mpc83xx_spi {
  71         struct mpc83xx_spi_reg __iomem *base;
  72
  73         /* rx & tx bufs from the spi_transfer */
  74         const void *tx;
  75         void *rx;
  76
  77         /* functions to deal with different sized buffers */
  78         void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
  79         u32(*get_tx) (struct mpc83xx_spi *);
  80
  81         unsigned int count;
  82         int irq;
  83
  84         unsigned nsecs;         /* (clock cycle time)/2 */
  85
  86         u32 spibrg;             /* SPIBRG input clock */
  87         u32 rx_shift;           /* RX data reg shift when in qe mode */
  88         u32 tx_shift;           /* TX data reg shift when in qe mode */
  89
  90         bool qe_mode;
  91
  92         void (*activate_cs) (u8 cs, u8 polarity);
  93         void (*deactivate_cs) (u8 cs, u8 polarity);
  94
  95         u8 busy;
  96
  97         struct workqueue_struct *workqueue;
  98         struct work_struct work;
  99
 100         struct list_head queue;
 101         spinlock_t lock;
 102
 103         struct completion done;
 104 };
 105
 106 struct spi_mpc83xx_cs {
 107         /* functions to deal with different sized buffers */
 108         void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
 109         u32 (*get_tx) (struct mpc83xx_spi *);
 110         u32 rx_shift;           /* RX data reg shift when in qe mode */
 111         u32 tx_shift;           /* TX data reg shift when in qe mode */
 112         u32 hw_mode;            /* Holds HW mode register settings */
 113 };
 114
 115 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
 116 {
 117         out_be32(reg, val);
 118 }
 119
 120 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
 121 {
 122         return in_be32(reg);
 123 }
 124
 125 #define MPC83XX_SPI_RX_BUF(type)                                          \
 126 static                                                                    \
 127 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
 128 {                                                                         \
 129         type * rx = mpc83xx_spi->rx;                                      \
 130         *rx++ = (type)(data >> mpc83xx_spi->rx_shift);                    \
 131         mpc83xx_spi->rx = rx;                                             \
 132 }
 133
 134 #define MPC83XX_SPI_TX_BUF(type)                                \
 135 static                                                          \
 136 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi)  \
 137 {                                                               \
 138         u32 data;                                               \
 139         const type * tx = mpc83xx_spi->tx;                      \
 140         if (!tx)                                                \
 141                 return 0;                                       \
 142         data = *tx++ << mpc83xx_spi->tx_shift;                  \
 143         mpc83xx_spi->tx = tx;                                   \
 144         return data;                                            \
 145 }
 146
 147 MPC83XX_SPI_RX_BUF(u8)
 148 MPC83XX_SPI_RX_BUF(u16)
 149 MPC83XX_SPI_RX_BUF(u32)
 150 MPC83XX_SPI_TX_BUF(u8)
 151 MPC83XX_SPI_TX_BUF(u16)
 152 MPC83XX_SPI_TX_BUF(u32)
 153
 154 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
 155 {
 156         struct mpc83xx_spi *mpc83xx_spi;
 157         u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
 158         struct spi_mpc83xx_cs   *cs = spi->controller_state;
 159
 160         mpc83xx_spi = spi_master_get_devdata(spi->master);
 161
 162         if (value == BITBANG_CS_INACTIVE) {
 163                 if (mpc83xx_spi->deactivate_cs)
 164                         mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
 165         }
 166
 167         if (value == BITBANG_CS_ACTIVE) {
 168                 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 169
 170                 mpc83xx_spi->rx_shift = cs->rx_shift;
 171                 mpc83xx_spi->tx_shift = cs->tx_shift;
 172                 mpc83xx_spi->get_rx = cs->get_rx;
 173                 mpc83xx_spi->get_tx = cs->get_tx;
 174
 175                 if (cs->hw_mode != regval) {
 176                         unsigned long flags;
 177                         __be32 __iomem *mode = &mpc83xx_spi->base->mode;
 178
 179                         regval = cs->hw_mode;
 180                         /* Turn off IRQs locally to minimize time that
 181                          * SPI is disabled
 182                          */
 183                         local_irq_save(flags);
 184                         /* Turn off SPI unit prior changing mode */
 185                         mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
 186                         mpc83xx_spi_write_reg(mode, regval);
 187                         local_irq_restore(flags);
 188                 }
 189                 if (mpc83xx_spi->activate_cs)
 190                         mpc83xx_spi->activate_cs(spi->chip_select, pol);
 191         }
 192 }
 193
 194 static
 195 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 196 {
 197         struct mpc83xx_spi *mpc83xx_spi;
 198         u32 regval;
 199         u8 bits_per_word, pm;
 200         u32 hz;
 201         struct spi_mpc83xx_cs   *cs = spi->controller_state;
 202
 203         mpc83xx_spi = spi_master_get_devdata(spi->master);
 204
 205         if (t) {
 206                 bits_per_word = t->bits_per_word;
 207                 hz = t->speed_hz;
 208         } else {
 209                 bits_per_word = 0;
 210                 hz = 0;
 211         }
 212
 213         /* spi_transfer level calls that work per-word */
 214         if (!bits_per_word)
 215                 bits_per_word = spi->bits_per_word;
 216
 217         /* Make sure its a bit width we support [4..16, 32] */
 218         if ((bits_per_word < 4)
 219             || ((bits_per_word > 16) && (bits_per_word != 32)))
 220                 return -EINVAL;
 221
 222         if (!hz)
 223                 hz = spi->max_speed_hz;
 224
 225         cs->rx_shift = 0;
 226         cs->tx_shift = 0;
 227         if (bits_per_word <= 8) {
 228                 cs->get_rx = mpc83xx_spi_rx_buf_u8;
 229                 cs->get_tx = mpc83xx_spi_tx_buf_u8;
 230                 if (mpc83xx_spi->qe_mode) {
 231                         cs->rx_shift = 16;
 232                         cs->tx_shift = 24;
 233                 }
 234         } else if (bits_per_word <= 16) {
 235                 cs->get_rx = mpc83xx_spi_rx_buf_u16;
 236                 cs->get_tx = mpc83xx_spi_tx_buf_u16;
 237                 if (mpc83xx_spi->qe_mode) {
 238                         cs->rx_shift = 16;
 239                         cs->tx_shift = 16;
 240                 }
 241         } else if (bits_per_word <= 32) {
 242                 cs->get_rx = mpc83xx_spi_rx_buf_u32;
 243                 cs->get_tx = mpc83xx_spi_tx_buf_u32;
 244         } else
 245                 return -EINVAL;
 246
 247         if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
 248                 cs->tx_shift = 0;
 249                 if (bits_per_word <= 8)
 250                         cs->rx_shift = 8;
 251                 else
 252                         cs->rx_shift = 0;
 253         }
 254
 255         mpc83xx_spi->rx_shift = cs->rx_shift;
 256         mpc83xx_spi->tx_shift = cs->tx_shift;
 257         mpc83xx_spi->get_rx = cs->get_rx;
 258         mpc83xx_spi->get_tx = cs->get_tx;
 259
 260         if (bits_per_word == 32)
 261                 bits_per_word = 0;
 262         else
 263                 bits_per_word = bits_per_word - 1;
 264
 265         /* mask out bits we are going to set */
 266         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 267                                   | SPMODE_PM(0xF));
 268
 269         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 270
 271         if ((mpc83xx_spi->spibrg / hz) > 64) {
 272                 cs->hw_mode |= SPMODE_DIV16;
 273                 pm = mpc83xx_spi->spibrg / (hz * 64);
 274                 if (pm > 16) {
 275                         dev_err(&spi->dev, "Requested speed is too "
 276                                 "low: %d Hz. Will use %d Hz instead.\n",
 277                                 hz, mpc83xx_spi->spibrg / 1024);
 278                         pm = 16;
 279                 }
 280         } else
 281                 pm = mpc83xx_spi->spibrg / (hz * 4);
 282         if (pm)
 283                 pm--;
 284
 285         cs->hw_mode |= SPMODE_PM(pm);
 286         regval =  mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 287         if (cs->hw_mode != regval) {
 288                 unsigned long flags;
 289                 __be32 __iomem *mode = &mpc83xx_spi->base->mode;
 290
 291                 regval = cs->hw_mode;
 292                 /* Turn off IRQs locally to minimize time
 293                  * that SPI is disabled
 294                  */
 295                 local_irq_save(flags);
 296                 /* Turn off SPI unit prior changing mode */
 297                 mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
 298                 mpc83xx_spi_write_reg(mode, regval);
 299                 local_irq_restore(flags);
 300         }
 301         return 0;
 302 }
 303
 304 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 305 {
 306         struct mpc83xx_spi *mpc83xx_spi;
 307         u32 word, len, bits_per_word;
 308
 309         mpc83xx_spi = spi_master_get_devdata(spi->master);
 310
 311         mpc83xx_spi->tx = t->tx_buf;
 312         mpc83xx_spi->rx = t->rx_buf;
 313         bits_per_word = spi->bits_per_word;
 314         if (t->bits_per_word)
 315                 bits_per_word = t->bits_per_word;
 316         len = t->len;
 317         if (bits_per_word > 8) {
 318                 /* invalid length? */
 319                 if (len & 1)
 320                         return -EINVAL;
 321                 len /= 2;
 322         }
 323         if (bits_per_word > 16) {
 324                 /* invalid length? */
 325                 if (len & 1)
 326                         return -EINVAL;
 327                 len /= 2;
 328         }
 329         mpc83xx_spi->count = len;
 330
 331         INIT_COMPLETION(mpc83xx_spi->done);
 332
 333         /* enable rx ints */
 334         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
 335
 336         /* transmit word */
 337         word = mpc83xx_spi->get_tx(mpc83xx_spi);
 338         mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
 339
 340         wait_for_completion(&mpc83xx_spi->done);
 341
 342         /* disable rx ints */
 343         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 344
 345         return mpc83xx_spi->count;
 346 }
 347
 348 static void mpc83xx_spi_work(struct work_struct *work)
 349 {
 350         struct mpc83xx_spi *mpc83xx_spi =
 351                 container_of(work, struct mpc83xx_spi, work);
 352
 353         spin_lock_irq(&mpc83xx_spi->lock);
 354         mpc83xx_spi->busy = 1;
 355         while (!list_empty(&mpc83xx_spi->queue)) {
 356                 struct spi_message *m;
 357                 struct spi_device *spi;
 358                 struct spi_transfer *t = NULL;
 359                 unsigned cs_change;
 360                 int status, nsecs = 50;
 361
 362                 m = container_of(mpc83xx_spi->queue.next,
 363                                 struct spi_message, queue);
 364                 list_del_init(&m->queue);
 365                 spin_unlock_irq(&mpc83xx_spi->lock);
 366
 367                 spi = m->spi;
 368                 cs_change = 1;
 369                 status = 0;
 370                 list_for_each_entry(t, &m->transfers, transfer_list) {
 371                         if (t->bits_per_word || t->speed_hz) {
 372                                 /* Don't allow changes if CS is active */
 373                                 status = -EINVAL;
 374
 375                                 if (cs_change)
 376                                         status = mpc83xx_spi_setup_transfer(spi, t);
 377                                 if (status < 0)
 378                                         break;
 379                         }
 380
 381                         if (cs_change)
 382                                 mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 383                         cs_change = t->cs_change;
 384                         if (t->len)
 385                                 status = mpc83xx_spi_bufs(spi, t);
 386                         if (status) {
 387                                 status = -EMSGSIZE;
 388                                 break;
 389                         }
 390                         m->actual_length += t->len;
 391
 392                         if (t->delay_usecs)
 393                                 udelay(t->delay_usecs);
 394
 395                         if (cs_change) {
 396                                 ndelay(nsecs);
 397                                 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 398                                 ndelay(nsecs);
 399                         }
 400                 }
 401
 402                 m->status = status;
 403                 m->complete(m->context);
 404
 405                 if (status || !cs_change) {
 406                         ndelay(nsecs);
 407                         mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 408                 }
 409
 410                 mpc83xx_spi_setup_transfer(spi, NULL);
 411
 412                 spin_lock_irq(&mpc83xx_spi->lock);
 413         }
 414         mpc83xx_spi->busy = 0;
 415         spin_unlock_irq(&mpc83xx_spi->lock);
 416 }
 417
 418 /* the spi->mode bits understood by this driver: */
 419 #define MODEBITS        (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
 420                         | SPI_LSB_FIRST | SPI_LOOP)
 421
 422 static int mpc83xx_spi_setup(struct spi_device *spi)
 423 {
 424         struct mpc83xx_spi *mpc83xx_spi;
 425         int retval;
 426         u32 hw_mode;
 427         struct spi_mpc83xx_cs   *cs = spi->controller_state;
 428
 429         if (spi->mode & ~MODEBITS) {
 430                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 431                         spi->mode & ~MODEBITS);
 432                 return -EINVAL;
 433         }
 434
 435         if (!spi->max_speed_hz)
 436                 return -EINVAL;
 437
 438         if (!cs) {
 439                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 440                 if (!cs)
 441                         return -ENOMEM;
 442                 spi->controller_state = cs;
 443         }
 444         mpc83xx_spi = spi_master_get_devdata(spi->master);
 445
 446         if (!spi->bits_per_word)
 447                 spi->bits_per_word = 8;
 448
 449         hw_mode = cs->hw_mode; /* Save orginal settings */
 450         cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 451         /* mask out bits we are going to set */
 452         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 453                          | SPMODE_REV | SPMODE_LOOP);
 454
 455         if (spi->mode & SPI_CPHA)
 456                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 457         if (spi->mode & SPI_CPOL)
 458                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 459         if (!(spi->mode & SPI_LSB_FIRST))
 460                 cs->hw_mode |= SPMODE_REV;
 461         if (spi->mode & SPI_LOOP)
 462                 cs->hw_mode |= SPMODE_LOOP;
 463
 464         retval = mpc83xx_spi_setup_transfer(spi, NULL);
 465         if (retval < 0) {
 466                 cs->hw_mode = hw_mode; /* Restore settings */
 467                 return retval;
 468         }
 469
 470         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
 471                 __func__, spi->mode & (SPI_CPOL | SPI_CPHA),
 472                 spi->bits_per_word, spi->max_speed_hz);
 473 #if 0 /* Don't think this is needed */
 474         /* NOTE we _need_ to call chipselect() early, ideally with adapter
 475          * setup, unless the hardware defaults cooperate to avoid confusion
 476          * between normal (active low) and inverted chipselects.
 477          */
 478
 479         /* deselect chip (low or high) */
 480         spin_lock(&mpc83xx_spi->lock);
 481         if (!mpc83xx_spi->busy)
 482                 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 483         spin_unlock(&mpc83xx_spi->lock);
 484 #endif
 485         return 0;
 486 }
 487
 488 static irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
 489 {
 490         struct mpc83xx_spi *mpc83xx_spi = context_data;
 491         u32 event;
 492         irqreturn_t ret = IRQ_NONE;
 493
 494         /* Get interrupt events(tx/rx) */
 495         event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
 496
 497         /* We need handle RX first */
 498         if (event & SPIE_NE) {
 499                 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
 500
 501                 if (mpc83xx_spi->rx)
 502                         mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
 503
 504                 ret = IRQ_HANDLED;
 505         }
 506
 507         if ((event & SPIE_NF) == 0)
 508                 /* spin until TX is done */
 509                 while (((event =
 510                          mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
 511                                                 SPIE_NF) == 0)
 512                          cpu_relax();
 513
 514         mpc83xx_spi->count -= 1;
 515         if (mpc83xx_spi->count) {
 516                 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
 517                 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
 518         } else {
 519                 complete(&mpc83xx_spi->done);
 520         }
 521
 522         /* Clear the events */
 523         mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
 524
 525         return ret;
 526 }
 527 static int mpc83xx_spi_transfer(struct spi_device *spi,
 528                                 struct spi_message *m)
 529 {
 530         struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
 531         unsigned long flags;
 532
 533         m->actual_length = 0;
 534         m->status = -EINPROGRESS;
 535
 536         spin_lock_irqsave(&mpc83xx_spi->lock, flags);
 537         list_add_tail(&m->queue, &mpc83xx_spi->queue);
 538         queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
 539         spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
 540
 541         return 0;
 542 }
 543
 544
 545 static void mpc83xx_spi_cleanup(struct spi_device *spi)
 546 {
 547         kfree(spi->controller_state);
 548 }
 549
 550 static int __init mpc83xx_spi_probe(struct platform_device *dev)
 551 {
 552         struct spi_master *master;
 553         struct mpc83xx_spi *mpc83xx_spi;
 554         struct fsl_spi_platform_data *pdata;
 555         struct resource *r;
 556         u32 regval;
 557         int ret = 0;
 558
 559         /* Get resources(memory, IRQ) associated with the device */
 560         master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
 561
 562         if (master == NULL) {
 563                 ret = -ENOMEM;
 564                 goto err;
 565         }
 566
 567         platform_set_drvdata(dev, master);
 568         pdata = dev->dev.platform_data;
 569
 570         if (pdata == NULL) {
 571                 ret = -ENODEV;
 572                 goto free_master;
 573         }
 574
 575         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
 576         if (r == NULL) {
 577                 ret = -ENODEV;
 578                 goto free_master;
 579         }
 580         master->setup = mpc83xx_spi_setup;
 581         master->transfer = mpc83xx_spi_transfer;
 582         master->cleanup = mpc83xx_spi_cleanup;
 583
 584         mpc83xx_spi = spi_master_get_devdata(master);
 585         mpc83xx_spi->activate_cs = pdata->activate_cs;
 586         mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
 587         mpc83xx_spi->qe_mode = pdata->qe_mode;
 588         mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
 589         mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
 590         mpc83xx_spi->spibrg = pdata->sysclk;
 591
 592         mpc83xx_spi->rx_shift = 0;
 593         mpc83xx_spi->tx_shift = 0;
 594         if (mpc83xx_spi->qe_mode) {
 595                 mpc83xx_spi->rx_shift = 16;
 596                 mpc83xx_spi->tx_shift = 24;
 597         }
 598
 599         init_completion(&mpc83xx_spi->done);
 600
 601         mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
 602         if (mpc83xx_spi->base == NULL) {
 603                 ret = -ENOMEM;
 604                 goto put_master;
 605         }
 606
 607         mpc83xx_spi->irq = platform_get_irq(dev, 0);
 608
 609         if (mpc83xx_spi->irq < 0) {
 610                 ret = -ENXIO;
 611                 goto unmap_io;
 612         }
 613
 614         /* Register for SPI Interrupt */
 615         ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
 616                           0, "mpc83xx_spi", mpc83xx_spi);
 617
 618         if (ret != 0)
 619                 goto unmap_io;
 620
 621         master->bus_num = pdata->bus_num;
 622         master->num_chipselect = pdata->max_chipselect;
 623
 624         /* SPI controller initializations */
 625         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
 626         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 627         mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
 628         mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
 629
 630         /* Enable SPI interface */
 631         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 632         if (pdata->qe_mode)
 633                 regval |= SPMODE_OP;
 634
 635         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 636         spin_lock_init(&mpc83xx_spi->lock);
 637         init_completion(&mpc83xx_spi->done);
 638         INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
 639         INIT_LIST_HEAD(&mpc83xx_spi->queue);
 640
 641         mpc83xx_spi->workqueue = create_singlethread_workqueue(
 642                 dev_name(master->dev.parent));
 643         if (mpc83xx_spi->workqueue == NULL) {
 644                 ret = -EBUSY;
 645                 goto free_irq;
 646         }
 647
 648         ret = spi_register_master(master);
 649         if (ret < 0)
 650                 goto unreg_master;
 651
 652         printk(KERN_INFO
 653                "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
 654                dev_name(&dev->dev), mpc83xx_spi->base, mpc83xx_spi->irq);
 655
 656         return ret;
 657
 658 unreg_master:
 659         destroy_workqueue(mpc83xx_spi->workqueue);
 660 free_irq:
 661         free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 662 unmap_io:
 663         iounmap(mpc83xx_spi->base);
 664 put_master:
 665         spi_master_put(master);
 666 free_master:
 667         kfree(master);
 668 err:
 669         return ret;
 670 }
 671
 672 static int __exit mpc83xx_spi_remove(struct platform_device *dev)
 673 {
 674         struct mpc83xx_spi *mpc83xx_spi;
 675         struct spi_master *master;
 676
 677         master = platform_get_drvdata(dev);
 678         mpc83xx_spi = spi_master_get_devdata(master);
 679
 680         flush_workqueue(mpc83xx_spi->workqueue);
 681         destroy_workqueue(mpc83xx_spi->workqueue);
 682         spi_unregister_master(master);
 683
 684         free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 685         iounmap(mpc83xx_spi->base);
 686
 687         return 0;
 688 }
 689
 690 MODULE_ALIAS("platform:mpc83xx_spi");
 691 static struct platform_driver mpc83xx_spi_driver = {
 692         .remove = __exit_p(mpc83xx_spi_remove),
 693         .driver = {
 694                 .name = "mpc83xx_spi",
 695                 .owner = THIS_MODULE,
 696         },
 697 };
 698
 699 static int __init mpc83xx_spi_init(void)
 700 {
 701         return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe);
 702 }
 703
 704 static void __exit mpc83xx_spi_exit(void)
 705 {
 706         platform_driver_unregister(&mpc83xx_spi_driver);
 707 }
 708
 709 module_init(mpc83xx_spi_init);
 710 module_exit(mpc83xx_spi_exit);
 711
 712 MODULE_AUTHOR("Kumar Gala");
 713 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
 714 MODULE_LICENSE("GPL");