1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if_vlan.h>
46 #include <linux/prefetch.h>
47 #include <scsi/fc/fc_fcoe.h>
50 #include "ixgbe_common.h"
51 #include "ixgbe_dcb_82599.h"
52 #include "ixgbe_sriov.h"
54 char ixgbe_driver_name
[] = "ixgbe";
55 static const char ixgbe_driver_string
[] =
56 "Intel(R) 10 Gigabit PCI Express Network Driver";
60 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
61 __stringify(BUILD) "-k"
62 const char ixgbe_driver_version
[] = DRV_VERSION
;
63 static const char ixgbe_copyright
[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
66 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
67 [board_82598
] = &ixgbe_82598_info
,
68 [board_82599
] = &ixgbe_82599_info
,
69 [board_X540
] = &ixgbe_X540_info
,
72 /* ixgbe_pci_tbl - PCI Device ID Table
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
80 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
113 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
115 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
117 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
119 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_BACKPLANE_FCOE
),
121 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_FCOE
),
123 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
125 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
127 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_X540T
),
129 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_SF2
),
131 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_LS
),
134 /* required last entry */
137 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
139 #ifdef CONFIG_IXGBE_DCA
140 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
142 static struct notifier_block dca_notifier
= {
143 .notifier_call
= ixgbe_notify_dca
,
149 #ifdef CONFIG_PCI_IOV
150 static unsigned int max_vfs
;
151 module_param(max_vfs
, uint
, 0);
152 MODULE_PARM_DESC(max_vfs
,
153 "Maximum number of virtual functions to allocate per physical function");
154 #endif /* CONFIG_PCI_IOV */
156 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158 MODULE_LICENSE("GPL");
159 MODULE_VERSION(DRV_VERSION
);
161 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
163 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
165 struct ixgbe_hw
*hw
= &adapter
->hw
;
170 #ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter
->pdev
);
175 /* turn off device IOV mode */
176 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
177 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
178 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
179 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
180 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
181 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
183 /* set default pool back to 0 */
184 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
185 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
186 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
188 /* take a breather then clean up driver data */
191 kfree(adapter
->vfinfo
);
192 adapter
->vfinfo
= NULL
;
194 adapter
->num_vfs
= 0;
195 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter
*adapter
)
200 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
))
202 schedule_work(&adapter
->service_task
);
205 static void ixgbe_service_event_complete(struct ixgbe_adapter
*adapter
)
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
));
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
);
214 struct ixgbe_reg_info
{
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
221 /* General Registers */
222 {IXGBE_CTRL
, "CTRL"},
223 {IXGBE_STATUS
, "STATUS"},
224 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
226 /* Interrupt Registers */
227 {IXGBE_EICR
, "EICR"},
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
247 /* List Terminator */
253 * ixgbe_regdump - register printout routine
255 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
261 switch (reginfo
->ofs
) {
262 case IXGBE_SRRCTL(0):
263 for (i
= 0; i
< 64; i
++)
264 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
266 case IXGBE_DCA_RXCTRL(0):
267 for (i
= 0; i
< 64; i
++)
268 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
271 for (i
= 0; i
< 64; i
++)
272 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
275 for (i
= 0; i
< 64; i
++)
276 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
279 for (i
= 0; i
< 64; i
++)
280 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
282 case IXGBE_RXDCTL(0):
283 for (i
= 0; i
< 64; i
++)
284 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
287 for (i
= 0; i
< 64; i
++)
288 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
291 for (i
= 0; i
< 64; i
++)
292 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
295 for (i
= 0; i
< 64; i
++)
296 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
299 for (i
= 0; i
< 64; i
++)
300 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
303 for (i
= 0; i
< 64; i
++)
304 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
307 for (i
= 0; i
< 64; i
++)
308 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
311 for (i
= 0; i
< 64; i
++)
312 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
314 case IXGBE_TXDCTL(0):
315 for (i
= 0; i
< 64; i
++)
316 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
319 pr_info("%-15s %08x\n", reginfo
->name
,
320 IXGBE_READ_REG(hw
, reginfo
->ofs
));
324 for (i
= 0; i
< 8; i
++) {
325 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
326 pr_err("%-15s", rname
);
327 for (j
= 0; j
< 8; j
++)
328 pr_cont(" %08x", regs
[i
*8+j
]);
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
337 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
339 struct net_device
*netdev
= adapter
->netdev
;
340 struct ixgbe_hw
*hw
= &adapter
->hw
;
341 struct ixgbe_reg_info
*reginfo
;
343 struct ixgbe_ring
*tx_ring
;
344 struct ixgbe_tx_buffer
*tx_buffer_info
;
345 union ixgbe_adv_tx_desc
*tx_desc
;
346 struct my_u0
{ u64 a
; u64 b
; } *u0
;
347 struct ixgbe_ring
*rx_ring
;
348 union ixgbe_adv_rx_desc
*rx_desc
;
349 struct ixgbe_rx_buffer
*rx_buffer_info
;
353 if (!netif_msg_hw(adapter
))
356 /* Print netdevice Info */
358 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
368 /* Print Registers */
369 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
372 reginfo
->name
; reginfo
++) {
373 ixgbe_regdump(hw
, reginfo
);
376 /* Print TX Ring Summary */
377 if (!netdev
|| !netif_running(netdev
))
380 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
382 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
383 tx_ring
= adapter
->tx_ring
[n
];
385 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
387 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
388 (u64
)tx_buffer_info
->dma
,
389 tx_buffer_info
->length
,
390 tx_buffer_info
->next_to_watch
,
391 (u64
)tx_buffer_info
->time_stamp
);
395 if (!netif_msg_tx_done(adapter
))
396 goto rx_ring_summary
;
398 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
400 /* Transmit Descriptor Formats
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
411 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
412 tx_ring
= adapter
->tx_ring
[n
];
413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
420 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
421 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
422 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
423 u0
= (struct my_u0
*)tx_desc
;
424 pr_info("T [0x%03X] %016llX %016llX %016llX"
425 " %04X %3X %016llX %p", i
,
428 (u64
)tx_buffer_info
->dma
,
429 tx_buffer_info
->length
,
430 tx_buffer_info
->next_to_watch
,
431 (u64
)tx_buffer_info
->time_stamp
,
432 tx_buffer_info
->skb
);
433 if (i
== tx_ring
->next_to_use
&&
434 i
== tx_ring
->next_to_clean
)
436 else if (i
== tx_ring
->next_to_use
)
438 else if (i
== tx_ring
->next_to_clean
)
443 if (netif_msg_pktdata(adapter
) &&
444 tx_buffer_info
->dma
!= 0)
445 print_hex_dump(KERN_INFO
, "",
446 DUMP_PREFIX_ADDRESS
, 16, 1,
447 phys_to_virt(tx_buffer_info
->dma
),
448 tx_buffer_info
->length
, true);
452 /* Print RX Rings Summary */
454 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
455 pr_info("Queue [NTU] [NTC]\n");
456 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
457 rx_ring
= adapter
->rx_ring
[n
];
458 pr_info("%5d %5X %5X\n",
459 n
, rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
463 if (!netif_msg_rx_status(adapter
))
466 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
468 /* Advanced Receive Descriptor (Read) Format
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
477 * Advanced Receive Descriptor (Write-Back) Format
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
488 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
489 rx_ring
= adapter
->rx_ring
[n
];
490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
500 for (i
= 0; i
< rx_ring
->count
; i
++) {
501 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
502 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
503 u0
= (struct my_u0
*)rx_desc
;
504 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
505 if (staterr
& IXGBE_RXD_STAT_DD
) {
506 /* Descriptor Done */
507 pr_info("RWB[0x%03X] %016llX "
508 "%016llX ---------------- %p", i
,
511 rx_buffer_info
->skb
);
513 pr_info("R [0x%03X] %016llX "
514 "%016llX %016llX %p", i
,
517 (u64
)rx_buffer_info
->dma
,
518 rx_buffer_info
->skb
);
520 if (netif_msg_pktdata(adapter
)) {
521 print_hex_dump(KERN_INFO
, "",
522 DUMP_PREFIX_ADDRESS
, 16, 1,
523 phys_to_virt(rx_buffer_info
->dma
),
524 rx_ring
->rx_buf_len
, true);
526 if (rx_ring
->rx_buf_len
527 < IXGBE_RXBUFFER_2048
)
528 print_hex_dump(KERN_INFO
, "",
529 DUMP_PREFIX_ADDRESS
, 16, 1,
531 rx_buffer_info
->page_dma
+
532 rx_buffer_info
->page_offset
538 if (i
== rx_ring
->next_to_use
)
540 else if (i
== rx_ring
->next_to_clean
)
552 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
556 /* Let firmware take over control of h/w */
557 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
558 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
559 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
562 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
566 /* Let firmware know the driver has taken over */
567 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
568 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
569 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
580 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
581 u8 queue
, u8 msix_vector
)
584 struct ixgbe_hw
*hw
= &adapter
->hw
;
585 switch (hw
->mac
.type
) {
586 case ixgbe_mac_82598EB
:
587 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
590 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
591 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
592 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
593 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
594 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
596 case ixgbe_mac_82599EB
:
598 if (direction
== -1) {
600 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
601 index
= ((queue
& 1) * 8);
602 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
603 ivar
&= ~(0xFF << index
);
604 ivar
|= (msix_vector
<< index
);
605 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
608 /* tx or rx causes */
609 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
610 index
= ((16 * (queue
& 1)) + (8 * direction
));
611 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
612 ivar
&= ~(0xFF << index
);
613 ivar
|= (msix_vector
<< index
);
614 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
622 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
627 switch (adapter
->hw
.mac
.type
) {
628 case ixgbe_mac_82598EB
:
629 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
630 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
632 case ixgbe_mac_82599EB
:
634 mask
= (qmask
& 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
636 mask
= (qmask
>> 32);
637 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
644 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*tx_ring
,
645 struct ixgbe_tx_buffer
*tx_buffer_info
)
647 if (tx_buffer_info
->dma
) {
648 if (tx_buffer_info
->mapped_as_page
)
649 dma_unmap_page(tx_ring
->dev
,
651 tx_buffer_info
->length
,
654 dma_unmap_single(tx_ring
->dev
,
656 tx_buffer_info
->length
,
658 tx_buffer_info
->dma
= 0;
660 if (tx_buffer_info
->skb
) {
661 dev_kfree_skb_any(tx_buffer_info
->skb
);
662 tx_buffer_info
->skb
= NULL
;
664 tx_buffer_info
->time_stamp
= 0;
665 /* tx_buffer_info must be completely set up in the transmit path */
668 static void ixgbe_update_xoff_received(struct ixgbe_adapter
*adapter
)
670 struct ixgbe_hw
*hw
= &adapter
->hw
;
671 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
676 if ((hw
->fc
.current_mode
== ixgbe_fc_full
) ||
677 (hw
->fc
.current_mode
== ixgbe_fc_rx_pause
)) {
678 switch (hw
->mac
.type
) {
679 case ixgbe_mac_82598EB
:
680 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
683 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
685 hwstats
->lxoffrxc
+= data
;
687 /* refill credits (no tx hang) if we received xoff */
691 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
692 clear_bit(__IXGBE_HANG_CHECK_ARMED
,
693 &adapter
->tx_ring
[i
]->state
);
695 } else if (!(adapter
->dcb_cfg
.pfc_mode_enable
))
698 /* update stats for each tc, only valid with PFC enabled */
699 for (i
= 0; i
< MAX_TX_PACKET_BUFFERS
; i
++) {
700 switch (hw
->mac
.type
) {
701 case ixgbe_mac_82598EB
:
702 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
705 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
707 hwstats
->pxoffrxc
[i
] += xoff
[i
];
710 /* disarm tx queues that have received xoff frames */
711 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
712 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
713 u8 tc
= tx_ring
->dcb_tc
;
716 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
720 static u64
ixgbe_get_tx_completed(struct ixgbe_ring
*ring
)
722 return ring
->tx_stats
.completed
;
725 static u64
ixgbe_get_tx_pending(struct ixgbe_ring
*ring
)
727 struct ixgbe_adapter
*adapter
= netdev_priv(ring
->netdev
);
728 struct ixgbe_hw
*hw
= &adapter
->hw
;
730 u32 head
= IXGBE_READ_REG(hw
, IXGBE_TDH(ring
->reg_idx
));
731 u32 tail
= IXGBE_READ_REG(hw
, IXGBE_TDT(ring
->reg_idx
));
734 return (head
< tail
) ?
735 tail
- head
: (tail
+ ring
->count
- head
);
740 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring
*tx_ring
)
742 u32 tx_done
= ixgbe_get_tx_completed(tx_ring
);
743 u32 tx_done_old
= tx_ring
->tx_stats
.tx_done_old
;
744 u32 tx_pending
= ixgbe_get_tx_pending(tx_ring
);
747 clear_check_for_tx_hang(tx_ring
);
750 * Check for a hung queue, but be thorough. This verifies
751 * that a transmit has been completed since the previous
752 * check AND there is at least one packet pending. The
753 * ARMED bit is set to indicate a potential hang. The
754 * bit is cleared if a pause frame is received to remove
755 * false hang detection due to PFC or 802.3x frames. By
756 * requiring this to fail twice we avoid races with
757 * pfc clearing the ARMED bit and conditions where we
758 * run the check_tx_hang logic with a transmit completion
759 * pending but without time to complete it yet.
761 if ((tx_done_old
== tx_done
) && tx_pending
) {
762 /* make sure it is true for two checks in a row */
763 ret
= test_and_set_bit(__IXGBE_HANG_CHECK_ARMED
,
766 /* update completed stats and continue */
767 tx_ring
->tx_stats
.tx_done_old
= tx_done
;
768 /* reset the countdown */
769 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
776 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
777 * @adapter: driver private struct
779 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter
*adapter
)
782 /* Do the reset outside of interrupt context */
783 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
784 adapter
->flags2
|= IXGBE_FLAG2_RESET_REQUESTED
;
785 ixgbe_service_event_schedule(adapter
);
790 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
791 * @q_vector: structure containing interrupt and ring information
792 * @tx_ring: tx ring to clean
794 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
795 struct ixgbe_ring
*tx_ring
)
797 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
798 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
799 struct ixgbe_tx_buffer
*tx_buffer_info
;
800 unsigned int total_bytes
= 0, total_packets
= 0;
801 u16 i
, eop
, count
= 0;
803 i
= tx_ring
->next_to_clean
;
804 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
805 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
807 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
808 (count
< q_vector
->tx
.work_limit
)) {
809 bool cleaned
= false;
810 rmb(); /* read buffer_info after eop_desc */
811 for ( ; !cleaned
; count
++) {
812 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
813 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
815 tx_desc
->wb
.status
= 0;
816 cleaned
= (i
== eop
);
819 if (i
== tx_ring
->count
)
822 if (cleaned
&& tx_buffer_info
->skb
) {
823 total_bytes
+= tx_buffer_info
->bytecount
;
824 total_packets
+= tx_buffer_info
->gso_segs
;
827 ixgbe_unmap_and_free_tx_resource(tx_ring
,
831 tx_ring
->tx_stats
.completed
++;
832 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
833 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
836 tx_ring
->next_to_clean
= i
;
837 tx_ring
->stats
.bytes
+= total_bytes
;
838 tx_ring
->stats
.packets
+= total_packets
;
839 u64_stats_update_begin(&tx_ring
->syncp
);
840 q_vector
->tx
.total_bytes
+= total_bytes
;
841 q_vector
->tx
.total_packets
+= total_packets
;
842 u64_stats_update_end(&tx_ring
->syncp
);
844 if (check_for_tx_hang(tx_ring
) && ixgbe_check_tx_hang(tx_ring
)) {
845 /* schedule immediate reset if we believe we hung */
846 struct ixgbe_hw
*hw
= &adapter
->hw
;
847 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
848 e_err(drv
, "Detected Tx Unit Hang\n"
850 " TDH, TDT <%x>, <%x>\n"
851 " next_to_use <%x>\n"
852 " next_to_clean <%x>\n"
853 "tx_buffer_info[next_to_clean]\n"
854 " time_stamp <%lx>\n"
856 tx_ring
->queue_index
,
857 IXGBE_READ_REG(hw
, IXGBE_TDH(tx_ring
->reg_idx
)),
858 IXGBE_READ_REG(hw
, IXGBE_TDT(tx_ring
->reg_idx
)),
859 tx_ring
->next_to_use
, eop
,
860 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
862 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
865 "tx hang %d detected on queue %d, resetting adapter\n",
866 adapter
->tx_timeout_count
+ 1, tx_ring
->queue_index
);
868 /* schedule immediate reset if we believe we hung */
869 ixgbe_tx_timeout_reset(adapter
);
871 /* the adapter is about to reset, no point in enabling stuff */
875 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
876 if (unlikely(count
&& netif_carrier_ok(tx_ring
->netdev
) &&
877 (ixgbe_desc_unused(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
878 /* Make sure that anybody stopping the queue after this
879 * sees the new next_to_clean.
882 if (__netif_subqueue_stopped(tx_ring
->netdev
, tx_ring
->queue_index
) &&
883 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
884 netif_wake_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
885 ++tx_ring
->tx_stats
.restart_queue
;
889 return count
< q_vector
->tx
.work_limit
;
892 #ifdef CONFIG_IXGBE_DCA
893 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
894 struct ixgbe_ring
*rx_ring
,
897 struct ixgbe_hw
*hw
= &adapter
->hw
;
899 u8 reg_idx
= rx_ring
->reg_idx
;
901 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
));
902 switch (hw
->mac
.type
) {
903 case ixgbe_mac_82598EB
:
904 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
905 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
907 case ixgbe_mac_82599EB
:
909 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
910 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
911 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
916 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
917 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
918 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
919 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
), rxctrl
);
922 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
923 struct ixgbe_ring
*tx_ring
,
926 struct ixgbe_hw
*hw
= &adapter
->hw
;
928 u8 reg_idx
= tx_ring
->reg_idx
;
930 switch (hw
->mac
.type
) {
931 case ixgbe_mac_82598EB
:
932 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
));
933 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
934 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
935 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
936 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
), txctrl
);
938 case ixgbe_mac_82599EB
:
940 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
));
941 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
942 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
943 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
944 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
945 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
), txctrl
);
952 static void ixgbe_update_dca(struct ixgbe_q_vector
*q_vector
)
954 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
959 if (q_vector
->cpu
== cpu
)
962 r_idx
= find_first_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
);
963 for (i
= 0; i
< q_vector
->tx
.count
; i
++) {
964 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[r_idx
], cpu
);
965 r_idx
= find_next_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
,
969 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
970 for (i
= 0; i
< q_vector
->rx
.count
; i
++) {
971 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[r_idx
], cpu
);
972 r_idx
= find_next_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
,
981 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
986 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
989 /* always use CB2 mode, difference is masked in the CB driver */
990 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
992 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
993 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
997 for (i
= 0; i
< num_q_vectors
; i
++) {
998 adapter
->q_vector
[i
]->cpu
= -1;
999 ixgbe_update_dca(adapter
->q_vector
[i
]);
1003 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
1005 struct ixgbe_adapter
*adapter
= dev_get_drvdata(dev
);
1006 unsigned long event
= *(unsigned long *)data
;
1008 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
1012 case DCA_PROVIDER_ADD
:
1013 /* if we're already enabled, don't do it again */
1014 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1016 if (dca_add_requester(dev
) == 0) {
1017 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
1018 ixgbe_setup_dca(adapter
);
1021 /* Fall Through since DCA is disabled. */
1022 case DCA_PROVIDER_REMOVE
:
1023 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
1024 dca_remove_requester(dev
);
1025 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
1026 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
1033 #endif /* CONFIG_IXGBE_DCA */
1035 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc
*rx_desc
,
1036 struct sk_buff
*skb
)
1038 skb
->rxhash
= le32_to_cpu(rx_desc
->wb
.lower
.hi_dword
.rss
);
1042 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1043 * @adapter: address of board private structure
1044 * @rx_desc: advanced rx descriptor
1046 * Returns : true if it is FCoE pkt
1048 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter
*adapter
,
1049 union ixgbe_adv_rx_desc
*rx_desc
)
1051 __le16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1053 return (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
1054 ((pkt_info
& cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK
)) ==
1055 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE
<<
1056 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT
)));
1060 * ixgbe_receive_skb - Send a completed packet up the stack
1061 * @adapter: board private structure
1062 * @skb: packet to send up
1063 * @status: hardware indication of status of receive
1064 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1065 * @rx_desc: rx descriptor
1067 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
1068 struct sk_buff
*skb
, u8 status
,
1069 struct ixgbe_ring
*ring
,
1070 union ixgbe_adv_rx_desc
*rx_desc
)
1072 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1073 struct napi_struct
*napi
= &q_vector
->napi
;
1074 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
1075 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
1077 if (is_vlan
&& (tag
& VLAN_VID_MASK
))
1078 __vlan_hwaccel_put_tag(skb
, tag
);
1080 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
))
1081 napi_gro_receive(napi
, skb
);
1087 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1088 * @adapter: address of board private structure
1089 * @status_err: hardware indication of status of receive
1090 * @skb: skb currently being received and modified
1091 * @status_err: status error value of last descriptor in packet
1093 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
1094 union ixgbe_adv_rx_desc
*rx_desc
,
1095 struct sk_buff
*skb
,
1098 skb
->ip_summed
= CHECKSUM_NONE
;
1100 /* Rx csum disabled */
1101 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
1104 /* if IP and error */
1105 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
1106 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
1107 adapter
->hw_csum_rx_error
++;
1111 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
1114 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1115 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1118 * 82599 errata, UDP frames with a 0 checksum can be marked as
1121 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1122 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1125 adapter
->hw_csum_rx_error
++;
1129 /* It must be a TCP or UDP packet with a valid checksum */
1130 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1133 static inline void ixgbe_release_rx_desc(struct ixgbe_ring
*rx_ring
, u32 val
)
1136 * Force memory writes to complete before letting h/w
1137 * know there are new descriptors to fetch. (Only
1138 * applicable for weak-ordered memory model archs,
1142 writel(val
, rx_ring
->tail
);
1146 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1147 * @rx_ring: ring to place buffers on
1148 * @cleaned_count: number of buffers to replace
1150 void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*rx_ring
, u16 cleaned_count
)
1152 union ixgbe_adv_rx_desc
*rx_desc
;
1153 struct ixgbe_rx_buffer
*bi
;
1154 struct sk_buff
*skb
;
1155 u16 i
= rx_ring
->next_to_use
;
1157 /* do nothing if no valid netdev defined */
1158 if (!rx_ring
->netdev
)
1161 while (cleaned_count
--) {
1162 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1163 bi
= &rx_ring
->rx_buffer_info
[i
];
1167 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
1168 rx_ring
->rx_buf_len
);
1170 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1173 /* initialize queue mapping */
1174 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1179 bi
->dma
= dma_map_single(rx_ring
->dev
,
1181 rx_ring
->rx_buf_len
,
1183 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
1184 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1190 if (ring_is_ps_enabled(rx_ring
)) {
1192 bi
->page
= netdev_alloc_page(rx_ring
->netdev
);
1194 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1199 if (!bi
->page_dma
) {
1200 /* use a half page if we're re-using */
1201 bi
->page_offset
^= PAGE_SIZE
/ 2;
1202 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
1207 if (dma_mapping_error(rx_ring
->dev
,
1209 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1215 /* Refresh the desc even if buffer_addrs didn't change
1216 * because each write-back erases this info. */
1217 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1218 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1220 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1221 rx_desc
->read
.hdr_addr
= 0;
1225 if (i
== rx_ring
->count
)
1230 if (rx_ring
->next_to_use
!= i
) {
1231 rx_ring
->next_to_use
= i
;
1232 ixgbe_release_rx_desc(rx_ring
, i
);
1236 static inline u16
ixgbe_get_hlen(union ixgbe_adv_rx_desc
*rx_desc
)
1238 /* HW will not DMA in data larger than the given buffer, even if it
1239 * parses the (NFS, of course) header to be larger. In that case, it
1240 * fills the header buffer and spills the rest into the page.
1242 u16 hdr_info
= le16_to_cpu(rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
);
1243 u16 hlen
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1244 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1245 if (hlen
> IXGBE_RX_HDR_SIZE
)
1246 hlen
= IXGBE_RX_HDR_SIZE
;
1251 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1252 * @skb: pointer to the last skb in the rsc queue
1254 * This function changes a queue full of hw rsc buffers into a completed
1255 * packet. It uses the ->prev pointers to find the first packet and then
1256 * turns it into the frag list owner.
1258 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
)
1260 unsigned int frag_list_size
= 0;
1261 unsigned int skb_cnt
= 1;
1264 struct sk_buff
*prev
= skb
->prev
;
1265 frag_list_size
+= skb
->len
;
1271 skb_shinfo(skb
)->frag_list
= skb
->next
;
1273 skb
->len
+= frag_list_size
;
1274 skb
->data_len
+= frag_list_size
;
1275 skb
->truesize
+= frag_list_size
;
1276 IXGBE_RSC_CB(skb
)->skb_cnt
= skb_cnt
;
1281 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc
*rx_desc
)
1283 return !!(le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1284 IXGBE_RXDADV_RSCCNT_MASK
);
1287 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1288 struct ixgbe_ring
*rx_ring
,
1289 int *work_done
, int work_to_do
)
1291 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1292 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1293 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1294 struct sk_buff
*skb
;
1295 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1296 const int current_node
= numa_node_id();
1299 #endif /* IXGBE_FCOE */
1302 u16 cleaned_count
= 0;
1303 bool pkt_is_rsc
= false;
1305 i
= rx_ring
->next_to_clean
;
1306 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1307 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1309 while (staterr
& IXGBE_RXD_STAT_DD
) {
1312 rmb(); /* read descriptor and rx_buffer_info after status DD */
1314 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1316 skb
= rx_buffer_info
->skb
;
1317 rx_buffer_info
->skb
= NULL
;
1318 prefetch(skb
->data
);
1320 if (ring_is_rsc_enabled(rx_ring
))
1321 pkt_is_rsc
= ixgbe_get_rsc_state(rx_desc
);
1323 /* if this is a skb from previous receive DMA will be 0 */
1324 if (rx_buffer_info
->dma
) {
1327 !(staterr
& IXGBE_RXD_STAT_EOP
) &&
1330 * When HWRSC is enabled, delay unmapping
1331 * of the first packet. It carries the
1332 * header information, HW may still
1333 * access the header after the writeback.
1334 * Only unmap it when EOP is reached
1336 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1337 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1339 dma_unmap_single(rx_ring
->dev
,
1340 rx_buffer_info
->dma
,
1341 rx_ring
->rx_buf_len
,
1344 rx_buffer_info
->dma
= 0;
1346 if (ring_is_ps_enabled(rx_ring
)) {
1347 hlen
= ixgbe_get_hlen(rx_desc
);
1348 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1350 hlen
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1355 /* assume packet split since header is unmapped */
1356 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1360 dma_unmap_page(rx_ring
->dev
,
1361 rx_buffer_info
->page_dma
,
1364 rx_buffer_info
->page_dma
= 0;
1365 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1366 rx_buffer_info
->page
,
1367 rx_buffer_info
->page_offset
,
1370 if ((page_count(rx_buffer_info
->page
) == 1) &&
1371 (page_to_nid(rx_buffer_info
->page
) == current_node
))
1372 get_page(rx_buffer_info
->page
);
1374 rx_buffer_info
->page
= NULL
;
1376 skb
->len
+= upper_len
;
1377 skb
->data_len
+= upper_len
;
1378 skb
->truesize
+= upper_len
;
1382 if (i
== rx_ring
->count
)
1385 next_rxd
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1390 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1391 IXGBE_RXDADV_NEXTP_SHIFT
;
1392 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1394 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1397 if (!(staterr
& IXGBE_RXD_STAT_EOP
)) {
1398 if (ring_is_ps_enabled(rx_ring
)) {
1399 rx_buffer_info
->skb
= next_buffer
->skb
;
1400 rx_buffer_info
->dma
= next_buffer
->dma
;
1401 next_buffer
->skb
= skb
;
1402 next_buffer
->dma
= 0;
1404 skb
->next
= next_buffer
->skb
;
1405 skb
->next
->prev
= skb
;
1407 rx_ring
->rx_stats
.non_eop_descs
++;
1412 skb
= ixgbe_transform_rsc_queue(skb
);
1413 /* if we got here without RSC the packet is invalid */
1415 __pskb_trim(skb
, 0);
1416 rx_buffer_info
->skb
= skb
;
1421 if (ring_is_rsc_enabled(rx_ring
)) {
1422 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1423 dma_unmap_single(rx_ring
->dev
,
1424 IXGBE_RSC_CB(skb
)->dma
,
1425 rx_ring
->rx_buf_len
,
1427 IXGBE_RSC_CB(skb
)->dma
= 0;
1428 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1432 if (ring_is_ps_enabled(rx_ring
))
1433 rx_ring
->rx_stats
.rsc_count
+=
1434 skb_shinfo(skb
)->nr_frags
;
1436 rx_ring
->rx_stats
.rsc_count
+=
1437 IXGBE_RSC_CB(skb
)->skb_cnt
;
1438 rx_ring
->rx_stats
.rsc_flush
++;
1441 /* ERR_MASK will only have valid bits if EOP set */
1442 if (unlikely(staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
)) {
1443 dev_kfree_skb_any(skb
);
1447 ixgbe_rx_checksum(adapter
, rx_desc
, skb
, staterr
);
1448 if (adapter
->netdev
->features
& NETIF_F_RXHASH
)
1449 ixgbe_rx_hash(rx_desc
, skb
);
1451 /* probably a little skewed due to removing CRC */
1452 total_rx_bytes
+= skb
->len
;
1455 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1457 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1458 if (ixgbe_rx_is_fcoe(adapter
, rx_desc
)) {
1459 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
,
1464 #endif /* IXGBE_FCOE */
1465 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1468 rx_desc
->wb
.upper
.status_error
= 0;
1471 if (*work_done
>= work_to_do
)
1474 /* return some buffers to hardware, one at a time is too slow */
1475 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1476 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1480 /* use prefetched values */
1482 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1485 rx_ring
->next_to_clean
= i
;
1486 cleaned_count
= ixgbe_desc_unused(rx_ring
);
1489 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1492 /* include DDPed FCoE data */
1493 if (ddp_bytes
> 0) {
1496 mss
= rx_ring
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1497 sizeof(struct fc_frame_header
) -
1498 sizeof(struct fcoe_crc_eof
);
1501 total_rx_bytes
+= ddp_bytes
;
1502 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1504 #endif /* IXGBE_FCOE */
1506 u64_stats_update_begin(&rx_ring
->syncp
);
1507 rx_ring
->stats
.packets
+= total_rx_packets
;
1508 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1509 u64_stats_update_end(&rx_ring
->syncp
);
1510 q_vector
->rx
.total_packets
+= total_rx_packets
;
1511 q_vector
->rx
.total_bytes
+= total_rx_bytes
;
1514 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1516 * ixgbe_configure_msix - Configure MSI-X hardware
1517 * @adapter: board private structure
1519 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1522 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1524 struct ixgbe_q_vector
*q_vector
;
1525 int i
, q_vectors
, v_idx
, r_idx
;
1528 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1531 * Populate the IVAR table and set the ITR values to the
1532 * corresponding register.
1534 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1535 q_vector
= adapter
->q_vector
[v_idx
];
1536 /* XXX for_each_set_bit(...) */
1537 r_idx
= find_first_bit(q_vector
->rx
.idx
,
1538 adapter
->num_rx_queues
);
1540 for (i
= 0; i
< q_vector
->rx
.count
; i
++) {
1541 u8 reg_idx
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1542 ixgbe_set_ivar(adapter
, 0, reg_idx
, v_idx
);
1543 r_idx
= find_next_bit(q_vector
->rx
.idx
,
1544 adapter
->num_rx_queues
,
1547 r_idx
= find_first_bit(q_vector
->tx
.idx
,
1548 adapter
->num_tx_queues
);
1550 for (i
= 0; i
< q_vector
->tx
.count
; i
++) {
1551 u8 reg_idx
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1552 ixgbe_set_ivar(adapter
, 1, reg_idx
, v_idx
);
1553 r_idx
= find_next_bit(q_vector
->tx
.idx
,
1554 adapter
->num_tx_queues
,
1558 if (q_vector
->tx
.count
&& !q_vector
->rx
.count
)
1560 q_vector
->eitr
= adapter
->tx_eitr_param
;
1561 else if (q_vector
->rx
.count
)
1563 q_vector
->eitr
= adapter
->rx_eitr_param
;
1565 ixgbe_write_eitr(q_vector
);
1566 /* If ATR is enabled, set interrupt affinity */
1567 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
1569 * Allocate the affinity_hint cpumask, assign the mask
1570 * for this vector, and set our affinity_hint for
1573 if (!alloc_cpumask_var(&q_vector
->affinity_mask
,
1576 cpumask_set_cpu(v_idx
, q_vector
->affinity_mask
);
1577 irq_set_affinity_hint(adapter
->msix_entries
[v_idx
].vector
,
1578 q_vector
->affinity_mask
);
1582 switch (adapter
->hw
.mac
.type
) {
1583 case ixgbe_mac_82598EB
:
1584 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1587 case ixgbe_mac_82599EB
:
1588 case ixgbe_mac_X540
:
1589 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1595 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1597 /* set up to autoclear timer, and the vectors */
1598 mask
= IXGBE_EIMS_ENABLE_MASK
;
1599 if (adapter
->num_vfs
)
1600 mask
&= ~(IXGBE_EIMS_OTHER
|
1601 IXGBE_EIMS_MAILBOX
|
1604 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1605 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1608 enum latency_range
{
1612 latency_invalid
= 255
1616 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1617 * @q_vector: structure containing interrupt and ring information
1618 * @ring_container: structure containing ring performance data
1620 * Stores a new ITR value based on packets and byte
1621 * counts during the last interrupt. The advantage of per interrupt
1622 * computation is faster updates and more accurate ITR for the current
1623 * traffic pattern. Constants in this function were computed
1624 * based on theoretical maximum wire speed and thresholds were set based
1625 * on testing data as well as attempting to minimize response time
1626 * while increasing bulk throughput.
1627 * this functionality is controlled by the InterruptThrottleRate module
1628 * parameter (see ixgbe_param.c)
1630 static void ixgbe_update_itr(struct ixgbe_q_vector
*q_vector
,
1631 struct ixgbe_ring_container
*ring_container
)
1634 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1635 int bytes
= ring_container
->total_bytes
;
1636 int packets
= ring_container
->total_packets
;
1638 u8 itr_setting
= ring_container
->itr
;
1643 /* simple throttlerate management
1644 * 0-20MB/s lowest (100000 ints/s)
1645 * 20-100MB/s low (20000 ints/s)
1646 * 100-1249MB/s bulk (8000 ints/s)
1648 /* what was last interrupt timeslice? */
1649 timepassed_us
= 1000000/q_vector
->eitr
;
1650 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1652 switch (itr_setting
) {
1653 case lowest_latency
:
1654 if (bytes_perint
> adapter
->eitr_low
)
1655 itr_setting
= low_latency
;
1658 if (bytes_perint
> adapter
->eitr_high
)
1659 itr_setting
= bulk_latency
;
1660 else if (bytes_perint
<= adapter
->eitr_low
)
1661 itr_setting
= lowest_latency
;
1664 if (bytes_perint
<= adapter
->eitr_high
)
1665 itr_setting
= low_latency
;
1669 /* clear work counters since we have the values we need */
1670 ring_container
->total_bytes
= 0;
1671 ring_container
->total_packets
= 0;
1673 /* write updated itr to ring container */
1674 ring_container
->itr
= itr_setting
;
1678 * ixgbe_write_eitr - write EITR register in hardware specific way
1679 * @q_vector: structure containing interrupt and ring information
1681 * This function is made to be called by ethtool and by the driver
1682 * when it needs to update EITR registers at runtime. Hardware
1683 * specific quirks/differences are taken care of here.
1685 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1687 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1688 struct ixgbe_hw
*hw
= &adapter
->hw
;
1689 int v_idx
= q_vector
->v_idx
;
1690 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1692 switch (adapter
->hw
.mac
.type
) {
1693 case ixgbe_mac_82598EB
:
1694 /* must write high and low 16 bits to reset counter */
1695 itr_reg
|= (itr_reg
<< 16);
1697 case ixgbe_mac_82599EB
:
1698 case ixgbe_mac_X540
:
1700 * 82599 and X540 can support a value of zero, so allow it for
1701 * max interrupt rate, but there is an errata where it can
1702 * not be zero with RSC
1705 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1709 * set the WDIS bit to not clear the timer bits and cause an
1710 * immediate assertion of the interrupt
1712 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1717 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1720 static void ixgbe_set_itr(struct ixgbe_q_vector
*q_vector
)
1722 u32 new_itr
= q_vector
->eitr
;
1725 ixgbe_update_itr(q_vector
, &q_vector
->tx
);
1726 ixgbe_update_itr(q_vector
, &q_vector
->rx
);
1728 current_itr
= max(q_vector
->rx
.itr
, q_vector
->tx
.itr
);
1730 switch (current_itr
) {
1731 /* counts and packets in update_itr are dependent on these numbers */
1732 case lowest_latency
:
1736 new_itr
= 20000; /* aka hwitr = ~200 */
1745 if (new_itr
!= q_vector
->eitr
) {
1746 /* do an exponential smoothing */
1747 new_itr
= ((q_vector
->eitr
* 9) + new_itr
)/10;
1749 /* save the algorithm value here */
1750 q_vector
->eitr
= new_itr
;
1752 ixgbe_write_eitr(q_vector
);
1757 * ixgbe_check_overtemp_subtask - check for over tempurature
1758 * @adapter: pointer to adapter
1760 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter
*adapter
)
1762 struct ixgbe_hw
*hw
= &adapter
->hw
;
1763 u32 eicr
= adapter
->interrupt_event
;
1765 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
1768 if (!(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1769 !(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_EVENT
))
1772 adapter
->flags2
&= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
1774 switch (hw
->device_id
) {
1775 case IXGBE_DEV_ID_82599_T3_LOM
:
1777 * Since the warning interrupt is for both ports
1778 * we don't have to check if:
1779 * - This interrupt wasn't for our port.
1780 * - We may have missed the interrupt so always have to
1781 * check if we got a LSC
1783 if (!(eicr
& IXGBE_EICR_GPI_SDP0
) &&
1784 !(eicr
& IXGBE_EICR_LSC
))
1787 if (!(eicr
& IXGBE_EICR_LSC
) && hw
->mac
.ops
.check_link
) {
1789 bool link_up
= false;
1791 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1797 /* Check if this is not due to overtemp */
1798 if (hw
->phy
.ops
.check_overtemp(hw
) != IXGBE_ERR_OVERTEMP
)
1803 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1808 "Network adapter has been stopped because it has over heated. "
1809 "Restart the computer. If the problem persists, "
1810 "power off the system and replace the adapter\n");
1812 adapter
->interrupt_event
= 0;
1815 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1817 struct ixgbe_hw
*hw
= &adapter
->hw
;
1819 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1820 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1821 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1822 /* write to clear the interrupt */
1823 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1827 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1829 struct ixgbe_hw
*hw
= &adapter
->hw
;
1831 if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1832 /* Clear the interrupt */
1833 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1834 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1835 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
1836 ixgbe_service_event_schedule(adapter
);
1840 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1841 /* Clear the interrupt */
1842 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1843 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1844 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_CONFIG
;
1845 ixgbe_service_event_schedule(adapter
);
1850 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1852 struct ixgbe_hw
*hw
= &adapter
->hw
;
1855 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1856 adapter
->link_check_timeout
= jiffies
;
1857 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1858 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1859 IXGBE_WRITE_FLUSH(hw
);
1860 ixgbe_service_event_schedule(adapter
);
1864 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1866 struct ixgbe_adapter
*adapter
= data
;
1867 struct ixgbe_hw
*hw
= &adapter
->hw
;
1871 * Workaround for Silicon errata. Use clear-by-write instead
1872 * of clear-by-read. Reading with EICS will return the
1873 * interrupt causes without clearing, which later be done
1874 * with the write to EICR.
1876 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1877 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1879 if (eicr
& IXGBE_EICR_LSC
)
1880 ixgbe_check_lsc(adapter
);
1882 if (eicr
& IXGBE_EICR_MAILBOX
)
1883 ixgbe_msg_task(adapter
);
1885 switch (hw
->mac
.type
) {
1886 case ixgbe_mac_82599EB
:
1887 case ixgbe_mac_X540
:
1888 /* Handle Flow Director Full threshold interrupt */
1889 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1890 int reinit_count
= 0;
1892 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1893 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
1894 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE
,
1899 /* no more flow director interrupts until after init */
1900 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_FLOW_DIR
);
1901 eicr
&= ~IXGBE_EICR_FLOW_DIR
;
1902 adapter
->flags2
|= IXGBE_FLAG2_FDIR_REQUIRES_REINIT
;
1903 ixgbe_service_event_schedule(adapter
);
1906 ixgbe_check_sfp_event(adapter
, eicr
);
1907 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1908 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
1909 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1910 adapter
->interrupt_event
= eicr
;
1911 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
1912 ixgbe_service_event_schedule(adapter
);
1920 ixgbe_check_fan_failure(adapter
, eicr
);
1922 /* re-enable the original interrupt state, no lsc, no queues */
1923 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1924 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, eicr
&
1925 ~(IXGBE_EIMS_LSC
| IXGBE_EIMS_RTX_QUEUE
));
1930 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1934 struct ixgbe_hw
*hw
= &adapter
->hw
;
1936 switch (hw
->mac
.type
) {
1937 case ixgbe_mac_82598EB
:
1938 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1939 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, mask
);
1941 case ixgbe_mac_82599EB
:
1942 case ixgbe_mac_X540
:
1943 mask
= (qmask
& 0xFFFFFFFF);
1945 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(0), mask
);
1946 mask
= (qmask
>> 32);
1948 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(1), mask
);
1953 /* skip the flush */
1956 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1960 struct ixgbe_hw
*hw
= &adapter
->hw
;
1962 switch (hw
->mac
.type
) {
1963 case ixgbe_mac_82598EB
:
1964 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1965 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, mask
);
1967 case ixgbe_mac_82599EB
:
1968 case ixgbe_mac_X540
:
1969 mask
= (qmask
& 0xFFFFFFFF);
1971 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(0), mask
);
1972 mask
= (qmask
>> 32);
1974 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(1), mask
);
1979 /* skip the flush */
1982 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1984 struct ixgbe_q_vector
*q_vector
= data
;
1985 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1986 struct ixgbe_ring
*tx_ring
;
1989 if (!q_vector
->tx
.count
)
1992 r_idx
= find_first_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
);
1993 for (i
= 0; i
< q_vector
->tx
.count
; i
++) {
1994 tx_ring
= adapter
->tx_ring
[r_idx
];
1995 r_idx
= find_next_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
,
1999 /* EIAM disabled interrupts (on this vector) for us */
2000 napi_schedule(&q_vector
->napi
);
2006 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2008 * @data: pointer to our q_vector struct for this interrupt vector
2010 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
2012 struct ixgbe_q_vector
*q_vector
= data
;
2013 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2014 struct ixgbe_ring
*rx_ring
;
2018 #ifdef CONFIG_IXGBE_DCA
2019 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2020 ixgbe_update_dca(q_vector
);
2023 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
2024 for (i
= 0; i
< q_vector
->rx
.count
; i
++) {
2025 rx_ring
= adapter
->rx_ring
[r_idx
];
2026 r_idx
= find_next_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
,
2030 if (!q_vector
->rx
.count
)
2033 /* EIAM disabled interrupts (on this vector) for us */
2034 napi_schedule(&q_vector
->napi
);
2039 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
2041 struct ixgbe_q_vector
*q_vector
= data
;
2042 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2043 struct ixgbe_ring
*ring
;
2047 if (!q_vector
->tx
.count
&& !q_vector
->rx
.count
)
2050 r_idx
= find_first_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
);
2051 for (i
= 0; i
< q_vector
->tx
.count
; i
++) {
2052 ring
= adapter
->tx_ring
[r_idx
];
2053 r_idx
= find_next_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
,
2057 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
2058 for (i
= 0; i
< q_vector
->rx
.count
; i
++) {
2059 ring
= adapter
->rx_ring
[r_idx
];
2060 r_idx
= find_next_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
,
2064 /* EIAM disabled interrupts (on this vector) for us */
2065 napi_schedule(&q_vector
->napi
);
2071 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2072 * @napi: napi struct with our devices info in it
2073 * @budget: amount of work driver is allowed to do this pass, in packets
2075 * This function is optimized for cleaning one queue only on a single
2078 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
2080 struct ixgbe_q_vector
*q_vector
=
2081 container_of(napi
, struct ixgbe_q_vector
, napi
);
2082 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2083 struct ixgbe_ring
*rx_ring
= NULL
;
2087 #ifdef CONFIG_IXGBE_DCA
2088 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2089 ixgbe_update_dca(q_vector
);
2092 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
2093 rx_ring
= adapter
->rx_ring
[r_idx
];
2095 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
2097 /* If all Rx work done, exit the polling mode */
2098 if (work_done
< budget
) {
2099 napi_complete(napi
);
2100 if (adapter
->rx_itr_setting
& 1)
2101 ixgbe_set_itr(q_vector
);
2102 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2103 ixgbe_irq_enable_queues(adapter
,
2104 ((u64
)1 << q_vector
->v_idx
));
2111 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2112 * @napi: napi struct with our devices info in it
2113 * @budget: amount of work driver is allowed to do this pass, in packets
2115 * This function will clean more than one rx queue associated with a
2118 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
2120 struct ixgbe_q_vector
*q_vector
=
2121 container_of(napi
, struct ixgbe_q_vector
, napi
);
2122 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2123 struct ixgbe_ring
*ring
= NULL
;
2124 int work_done
= 0, i
;
2126 bool tx_clean_complete
= true;
2128 #ifdef CONFIG_IXGBE_DCA
2129 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2130 ixgbe_update_dca(q_vector
);
2133 r_idx
= find_first_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
);
2134 for (i
= 0; i
< q_vector
->tx
.count
; i
++) {
2135 ring
= adapter
->tx_ring
[r_idx
];
2136 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
2137 r_idx
= find_next_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
,
2141 /* attempt to distribute budget to each queue fairly, but don't allow
2142 * the budget to go below 1 because we'll exit polling */
2143 budget
/= (q_vector
->rx
.count
?: 1);
2144 budget
= max(budget
, 1);
2145 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
2146 for (i
= 0; i
< q_vector
->rx
.count
; i
++) {
2147 ring
= adapter
->rx_ring
[r_idx
];
2148 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
2149 r_idx
= find_next_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
,
2153 r_idx
= find_first_bit(q_vector
->rx
.idx
, adapter
->num_rx_queues
);
2154 ring
= adapter
->rx_ring
[r_idx
];
2155 /* If all Rx work done, exit the polling mode */
2156 if (work_done
< budget
) {
2157 napi_complete(napi
);
2158 if (adapter
->rx_itr_setting
& 1)
2159 ixgbe_set_itr(q_vector
);
2160 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2161 ixgbe_irq_enable_queues(adapter
,
2162 ((u64
)1 << q_vector
->v_idx
));
2170 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2171 * @napi: napi struct with our devices info in it
2172 * @budget: amount of work driver is allowed to do this pass, in packets
2174 * This function is optimized for cleaning one queue only on a single
2177 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
2179 struct ixgbe_q_vector
*q_vector
=
2180 container_of(napi
, struct ixgbe_q_vector
, napi
);
2181 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2182 struct ixgbe_ring
*tx_ring
= NULL
;
2186 #ifdef CONFIG_IXGBE_DCA
2187 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2188 ixgbe_update_dca(q_vector
);
2191 r_idx
= find_first_bit(q_vector
->tx
.idx
, adapter
->num_tx_queues
);
2192 tx_ring
= adapter
->tx_ring
[r_idx
];
2194 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2197 /* If all Tx work done, exit the polling mode */
2198 if (work_done
< budget
) {
2199 napi_complete(napi
);
2200 if (adapter
->tx_itr_setting
& 1)
2201 ixgbe_set_itr(q_vector
);
2202 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2203 ixgbe_irq_enable_queues(adapter
,
2204 ((u64
)1 << q_vector
->v_idx
));
2210 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2213 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2214 struct ixgbe_ring
*rx_ring
= a
->rx_ring
[r_idx
];
2216 set_bit(r_idx
, q_vector
->rx
.idx
);
2217 q_vector
->rx
.count
++;
2218 rx_ring
->q_vector
= q_vector
;
2221 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2224 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2225 struct ixgbe_ring
*tx_ring
= a
->tx_ring
[t_idx
];
2227 set_bit(t_idx
, q_vector
->tx
.idx
);
2228 q_vector
->tx
.count
++;
2229 tx_ring
->q_vector
= q_vector
;
2230 q_vector
->tx
.work_limit
= a
->tx_work_limit
;
2234 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2235 * @adapter: board private structure to initialize
2237 * This function maps descriptor rings to the queue-specific vectors
2238 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2239 * one vector per ring/queue, but on a constrained vector budget, we
2240 * group the rings as "efficiently" as possible. You would add new
2241 * mapping configurations in here.
2243 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
)
2247 int rxr_idx
= 0, txr_idx
= 0;
2248 int rxr_remaining
= adapter
->num_rx_queues
;
2249 int txr_remaining
= adapter
->num_tx_queues
;
2254 /* No mapping required if MSI-X is disabled. */
2255 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2258 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2261 * The ideal configuration...
2262 * We have enough vectors to map one per queue.
2264 if (q_vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2265 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2266 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2268 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2269 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2275 * If we don't have enough vectors for a 1-to-1
2276 * mapping, we'll have to group them so there are
2277 * multiple queues per vector.
2279 /* Re-adjusting *qpv takes care of the remainder. */
2280 for (i
= v_start
; i
< q_vectors
; i
++) {
2281 rqpv
= DIV_ROUND_UP(rxr_remaining
, q_vectors
- i
);
2282 for (j
= 0; j
< rqpv
; j
++) {
2283 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2287 tqpv
= DIV_ROUND_UP(txr_remaining
, q_vectors
- i
);
2288 for (j
= 0; j
< tqpv
; j
++) {
2289 map_vector_to_txq(adapter
, i
, txr_idx
);
2299 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2300 * @adapter: board private structure
2302 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2303 * interrupts from the kernel.
2305 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2307 struct net_device
*netdev
= adapter
->netdev
;
2308 irqreturn_t (*handler
)(int, void *);
2309 int i
, vector
, q_vectors
, err
;
2312 /* Decrement for Other and TCP Timer vectors */
2313 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2315 err
= ixgbe_map_rings_to_vectors(adapter
);
2319 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count) \
2320 ? &ixgbe_msix_clean_many : \
2321 (_v)->rx.count ? &ixgbe_msix_clean_rx : \
2322 (_v)->tx.count ? &ixgbe_msix_clean_tx : \
2324 for (vector
= 0; vector
< q_vectors
; vector
++) {
2325 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[vector
];
2326 handler
= SET_HANDLER(q_vector
);
2328 if (handler
== &ixgbe_msix_clean_rx
) {
2329 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2330 "%s-%s-%d", netdev
->name
, "rx", ri
++);
2331 } else if (handler
== &ixgbe_msix_clean_tx
) {
2332 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2333 "%s-%s-%d", netdev
->name
, "tx", ti
++);
2334 } else if (handler
== &ixgbe_msix_clean_many
) {
2335 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2336 "%s-%s-%d", netdev
->name
, "TxRx", ri
++);
2339 /* skip this unused q_vector */
2342 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2343 handler
, 0, q_vector
->name
,
2346 e_err(probe
, "request_irq failed for MSIX interrupt "
2347 "Error: %d\n", err
);
2348 goto free_queue_irqs
;
2352 sprintf(adapter
->lsc_int_name
, "%s:lsc", netdev
->name
);
2353 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2354 ixgbe_msix_lsc
, 0, adapter
->lsc_int_name
, adapter
);
2356 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2357 goto free_queue_irqs
;
2363 for (i
= vector
- 1; i
>= 0; i
--)
2364 free_irq(adapter
->msix_entries
[--vector
].vector
,
2365 adapter
->q_vector
[i
]);
2366 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2367 pci_disable_msix(adapter
->pdev
);
2368 kfree(adapter
->msix_entries
);
2369 adapter
->msix_entries
= NULL
;
2374 * ixgbe_irq_enable - Enable default interrupt generation settings
2375 * @adapter: board private structure
2377 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
, bool queues
,
2382 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2383 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2384 mask
|= IXGBE_EIMS_GPI_SDP0
;
2385 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2386 mask
|= IXGBE_EIMS_GPI_SDP1
;
2387 switch (adapter
->hw
.mac
.type
) {
2388 case ixgbe_mac_82599EB
:
2389 case ixgbe_mac_X540
:
2390 mask
|= IXGBE_EIMS_ECC
;
2391 mask
|= IXGBE_EIMS_GPI_SDP1
;
2392 mask
|= IXGBE_EIMS_GPI_SDP2
;
2393 if (adapter
->num_vfs
)
2394 mask
|= IXGBE_EIMS_MAILBOX
;
2399 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)
2400 mask
|= IXGBE_EIMS_FLOW_DIR
;
2402 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2404 ixgbe_irq_enable_queues(adapter
, ~0);
2406 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2408 if (adapter
->num_vfs
> 32) {
2409 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2410 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2415 * ixgbe_intr - legacy mode Interrupt Handler
2416 * @irq: interrupt number
2417 * @data: pointer to a network interface device structure
2419 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2421 struct ixgbe_adapter
*adapter
= data
;
2422 struct ixgbe_hw
*hw
= &adapter
->hw
;
2423 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2427 * Workaround for silicon errata on 82598. Mask the interrupts
2428 * before the read of EICR.
2430 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2432 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2433 * therefore no explict interrupt disable is necessary */
2434 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2437 * shared interrupt alert!
2438 * make sure interrupts are enabled because the read will
2439 * have disabled interrupts due to EIAM
2440 * finish the workaround of silicon errata on 82598. Unmask
2441 * the interrupt that we masked before the EICR read.
2443 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2444 ixgbe_irq_enable(adapter
, true, true);
2445 return IRQ_NONE
; /* Not our interrupt */
2448 if (eicr
& IXGBE_EICR_LSC
)
2449 ixgbe_check_lsc(adapter
);
2451 switch (hw
->mac
.type
) {
2452 case ixgbe_mac_82599EB
:
2453 ixgbe_check_sfp_event(adapter
, eicr
);
2454 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2455 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
2456 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
2457 adapter
->interrupt_event
= eicr
;
2458 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
2459 ixgbe_service_event_schedule(adapter
);
2467 ixgbe_check_fan_failure(adapter
, eicr
);
2469 if (napi_schedule_prep(&(q_vector
->napi
))) {
2470 /* would disable interrupts here but EIAM disabled it */
2471 __napi_schedule(&(q_vector
->napi
));
2475 * re-enable link(maybe) and non-queue interrupts, no flush.
2476 * ixgbe_poll will re-enable the queue interrupts
2479 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2480 ixgbe_irq_enable(adapter
, false, false);
2485 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2487 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2489 for (i
= 0; i
< q_vectors
; i
++) {
2490 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2491 bitmap_zero(q_vector
->rx
.idx
, MAX_RX_QUEUES
);
2492 bitmap_zero(q_vector
->tx
.idx
, MAX_TX_QUEUES
);
2493 q_vector
->rx
.count
= 0;
2494 q_vector
->tx
.count
= 0;
2499 * ixgbe_request_irq - initialize interrupts
2500 * @adapter: board private structure
2502 * Attempts to configure interrupts using the best available
2503 * capabilities of the hardware and kernel.
2505 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2507 struct net_device
*netdev
= adapter
->netdev
;
2510 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2511 err
= ixgbe_request_msix_irqs(adapter
);
2512 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2513 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2514 netdev
->name
, adapter
);
2516 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2517 netdev
->name
, adapter
);
2521 e_err(probe
, "request_irq failed, Error %d\n", err
);
2526 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2528 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2531 q_vectors
= adapter
->num_msix_vectors
;
2534 free_irq(adapter
->msix_entries
[i
].vector
, adapter
);
2537 for (; i
>= 0; i
--) {
2538 /* free only the irqs that were actually requested */
2539 if (!adapter
->q_vector
[i
]->rx
.count
&&
2540 !adapter
->q_vector
[i
]->tx
.count
)
2543 free_irq(adapter
->msix_entries
[i
].vector
,
2544 adapter
->q_vector
[i
]);
2547 ixgbe_reset_q_vectors(adapter
);
2549 free_irq(adapter
->pdev
->irq
, adapter
);
2554 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2555 * @adapter: board private structure
2557 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2559 switch (adapter
->hw
.mac
.type
) {
2560 case ixgbe_mac_82598EB
:
2561 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2563 case ixgbe_mac_82599EB
:
2564 case ixgbe_mac_X540
:
2565 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2566 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2567 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2568 if (adapter
->num_vfs
> 32)
2569 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2574 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2575 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2577 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2578 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2580 synchronize_irq(adapter
->pdev
->irq
);
2585 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2588 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2590 struct ixgbe_hw
*hw
= &adapter
->hw
;
2592 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2593 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2595 ixgbe_set_ivar(adapter
, 0, 0, 0);
2596 ixgbe_set_ivar(adapter
, 1, 0, 0);
2598 map_vector_to_rxq(adapter
, 0, 0);
2599 map_vector_to_txq(adapter
, 0, 0);
2601 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2605 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2606 * @adapter: board private structure
2607 * @ring: structure containing ring specific data
2609 * Configure the Tx descriptor ring after a reset.
2611 void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2612 struct ixgbe_ring
*ring
)
2614 struct ixgbe_hw
*hw
= &adapter
->hw
;
2615 u64 tdba
= ring
->dma
;
2618 u8 reg_idx
= ring
->reg_idx
;
2620 /* disable queue to avoid issues while updating state */
2621 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2622 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
2623 txdctl
& ~IXGBE_TXDCTL_ENABLE
);
2624 IXGBE_WRITE_FLUSH(hw
);
2626 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2627 (tdba
& DMA_BIT_MASK(32)));
2628 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2629 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2630 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2631 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2632 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2633 ring
->tail
= hw
->hw_addr
+ IXGBE_TDT(reg_idx
);
2635 /* configure fetching thresholds */
2636 if (adapter
->rx_itr_setting
== 0) {
2637 /* cannot set wthresh when itr==0 */
2638 txdctl
&= ~0x007F0000;
2640 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2641 txdctl
|= (8 << 16);
2643 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2644 /* PThresh workaround for Tx hang with DFP enabled. */
2648 /* reinitialize flowdirector state */
2649 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) &&
2650 adapter
->atr_sample_rate
) {
2651 ring
->atr_sample_rate
= adapter
->atr_sample_rate
;
2652 ring
->atr_count
= 0;
2653 set_bit(__IXGBE_TX_FDIR_INIT_DONE
, &ring
->state
);
2655 ring
->atr_sample_rate
= 0;
2658 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &ring
->state
);
2661 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2662 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), txdctl
);
2664 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2665 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2666 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2669 /* poll to verify queue is enabled */
2671 usleep_range(1000, 2000);
2672 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2673 } while (--wait_loop
&& !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2675 e_err(drv
, "Could not enable Tx Queue %d\n", reg_idx
);
2678 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2680 struct ixgbe_hw
*hw
= &adapter
->hw
;
2683 u8 tcs
= netdev_get_num_tc(adapter
->netdev
);
2685 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2688 /* disable the arbiter while setting MTQC */
2689 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2690 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2691 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2693 /* set transmit pool layout */
2694 switch (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2695 case (IXGBE_FLAG_SRIOV_ENABLED
):
2696 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2697 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2701 reg
= IXGBE_MTQC_64Q_1PB
;
2703 reg
= IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_4TC_4TQ
;
2705 reg
= IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
;
2707 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, reg
);
2709 /* Enable Security TX Buffer IFG for multiple pb */
2711 reg
= IXGBE_READ_REG(hw
, IXGBE_SECTXMINIFG
);
2712 reg
|= IXGBE_SECTX_DCB
;
2713 IXGBE_WRITE_REG(hw
, IXGBE_SECTXMINIFG
, reg
);
2718 /* re-enable the arbiter */
2719 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2720 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2724 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2725 * @adapter: board private structure
2727 * Configure the Tx unit of the MAC after a reset.
2729 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2731 struct ixgbe_hw
*hw
= &adapter
->hw
;
2735 ixgbe_setup_mtqc(adapter
);
2737 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
2738 /* DMATXCTL.EN must be before Tx queues are enabled */
2739 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2740 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2741 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2744 /* Setup the HW Tx Head and Tail descriptor pointers */
2745 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2746 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2749 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2751 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2752 struct ixgbe_ring
*rx_ring
)
2755 u8 reg_idx
= rx_ring
->reg_idx
;
2757 switch (adapter
->hw
.mac
.type
) {
2758 case ixgbe_mac_82598EB
: {
2759 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2760 const int mask
= feature
[RING_F_RSS
].mask
;
2761 reg_idx
= reg_idx
& mask
;
2764 case ixgbe_mac_82599EB
:
2765 case ixgbe_mac_X540
:
2770 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
));
2772 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2773 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2774 if (adapter
->num_vfs
)
2775 srrctl
|= IXGBE_SRRCTL_DROP_EN
;
2777 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2778 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2780 if (ring_is_ps_enabled(rx_ring
)) {
2781 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2782 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2784 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2786 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2788 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2789 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2790 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2793 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
), srrctl
);
2796 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2798 struct ixgbe_hw
*hw
= &adapter
->hw
;
2799 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2800 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2801 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2802 u32 mrqc
= 0, reta
= 0;
2805 u8 tcs
= netdev_get_num_tc(adapter
->netdev
);
2806 int maxq
= adapter
->ring_feature
[RING_F_RSS
].indices
;
2809 maxq
= min(maxq
, adapter
->num_tx_queues
/ tcs
);
2811 /* Fill out hash function seeds */
2812 for (i
= 0; i
< 10; i
++)
2813 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2815 /* Fill out redirection table */
2816 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2819 /* reta = 4-byte sliding window of
2820 * 0x00..(indices-1)(indices-1)00..etc. */
2821 reta
= (reta
<< 8) | (j
* 0x11);
2823 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2826 /* Disable indicating checksum in descriptor, enables RSS hash */
2827 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2828 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2829 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2831 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
&&
2832 (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)) {
2833 mrqc
= IXGBE_MRQC_RSSEN
;
2835 int mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2836 | IXGBE_FLAG_SRIOV_ENABLED
);
2839 case (IXGBE_FLAG_RSS_ENABLED
):
2841 mrqc
= IXGBE_MRQC_RSSEN
;
2843 mrqc
= IXGBE_MRQC_RTRSS4TCEN
;
2845 mrqc
= IXGBE_MRQC_RTRSS8TCEN
;
2847 case (IXGBE_FLAG_SRIOV_ENABLED
):
2848 mrqc
= IXGBE_MRQC_VMDQEN
;
2855 /* Perform hash on these packet types */
2856 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2857 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2858 | IXGBE_MRQC_RSS_FIELD_IPV6
2859 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2861 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2865 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2866 * @adapter: address of board private structure
2867 * @ring: structure containing ring specific data
2869 void ixgbe_clear_rscctl(struct ixgbe_adapter
*adapter
,
2870 struct ixgbe_ring
*ring
)
2872 struct ixgbe_hw
*hw
= &adapter
->hw
;
2874 u8 reg_idx
= ring
->reg_idx
;
2876 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2877 rscctrl
&= ~IXGBE_RSCCTL_RSCEN
;
2878 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2882 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2883 * @adapter: address of board private structure
2884 * @index: index of ring to set
2886 void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
,
2887 struct ixgbe_ring
*ring
)
2889 struct ixgbe_hw
*hw
= &adapter
->hw
;
2892 u8 reg_idx
= ring
->reg_idx
;
2894 if (!ring_is_rsc_enabled(ring
))
2897 rx_buf_len
= ring
->rx_buf_len
;
2898 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2899 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2901 * we must limit the number of descriptors so that the
2902 * total size of max desc * buf_len is not greater
2905 if (ring_is_ps_enabled(ring
)) {
2906 #if (MAX_SKB_FRAGS > 16)
2907 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2908 #elif (MAX_SKB_FRAGS > 8)
2909 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2910 #elif (MAX_SKB_FRAGS > 4)
2911 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2913 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2916 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2917 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2918 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2919 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2921 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2923 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2927 * ixgbe_set_uta - Set unicast filter table address
2928 * @adapter: board private structure
2930 * The unicast table address is a register array of 32-bit registers.
2931 * The table is meant to be used in a way similar to how the MTA is used
2932 * however due to certain limitations in the hardware it is necessary to
2933 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2934 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2936 static void ixgbe_set_uta(struct ixgbe_adapter
*adapter
)
2938 struct ixgbe_hw
*hw
= &adapter
->hw
;
2941 /* The UTA table only exists on 82599 hardware and newer */
2942 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
2945 /* we only need to do this if VMDq is enabled */
2946 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2949 for (i
= 0; i
< 128; i
++)
2950 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), ~0);
2953 #define IXGBE_MAX_RX_DESC_POLL 10
2954 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2955 struct ixgbe_ring
*ring
)
2957 struct ixgbe_hw
*hw
= &adapter
->hw
;
2958 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
2960 u8 reg_idx
= ring
->reg_idx
;
2962 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2963 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2964 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2968 usleep_range(1000, 2000);
2969 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2970 } while (--wait_loop
&& !(rxdctl
& IXGBE_RXDCTL_ENABLE
));
2973 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
2974 "the polling period\n", reg_idx
);
2978 void ixgbe_disable_rx_queue(struct ixgbe_adapter
*adapter
,
2979 struct ixgbe_ring
*ring
)
2981 struct ixgbe_hw
*hw
= &adapter
->hw
;
2982 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
2984 u8 reg_idx
= ring
->reg_idx
;
2986 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2987 rxdctl
&= ~IXGBE_RXDCTL_ENABLE
;
2989 /* write value back with RXDCTL.ENABLE bit cleared */
2990 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
2992 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2993 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2996 /* the hardware may take up to 100us to really disable the rx queue */
2999 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3000 } while (--wait_loop
&& (rxdctl
& IXGBE_RXDCTL_ENABLE
));
3003 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3004 "the polling period\n", reg_idx
);
3008 void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
3009 struct ixgbe_ring
*ring
)
3011 struct ixgbe_hw
*hw
= &adapter
->hw
;
3012 u64 rdba
= ring
->dma
;
3014 u8 reg_idx
= ring
->reg_idx
;
3016 /* disable queue to avoid issues while updating state */
3017 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3018 ixgbe_disable_rx_queue(adapter
, ring
);
3020 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
3021 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
3022 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
3023 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
3024 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
3025 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
3026 ring
->tail
= hw
->hw_addr
+ IXGBE_RDT(reg_idx
);
3028 ixgbe_configure_srrctl(adapter
, ring
);
3029 ixgbe_configure_rscctl(adapter
, ring
);
3031 /* If operating in IOV mode set RLPML for X540 */
3032 if ((adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) &&
3033 hw
->mac
.type
== ixgbe_mac_X540
) {
3034 rxdctl
&= ~IXGBE_RXDCTL_RLPMLMASK
;
3035 rxdctl
|= ((ring
->netdev
->mtu
+ ETH_HLEN
+
3036 ETH_FCS_LEN
+ VLAN_HLEN
) | IXGBE_RXDCTL_RLPML_EN
);
3039 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3041 * enable cache line friendly hardware writes:
3042 * PTHRESH=32 descriptors (half the internal cache),
3043 * this also removes ugly rx_no_buffer_count increment
3044 * HTHRESH=4 descriptors (to minimize latency on fetch)
3045 * WTHRESH=8 burst writeback up to two cache lines
3047 rxdctl
&= ~0x3FFFFF;
3051 /* enable receive descriptor ring */
3052 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
3053 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
3055 ixgbe_rx_desc_queue_enable(adapter
, ring
);
3056 ixgbe_alloc_rx_buffers(ring
, ixgbe_desc_unused(ring
));
3059 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
3061 struct ixgbe_hw
*hw
= &adapter
->hw
;
3064 /* PSRTYPE must be initialized in non 82598 adapters */
3065 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
3066 IXGBE_PSRTYPE_UDPHDR
|
3067 IXGBE_PSRTYPE_IPV4HDR
|
3068 IXGBE_PSRTYPE_L2HDR
|
3069 IXGBE_PSRTYPE_IPV6HDR
;
3071 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3074 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
3075 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
3077 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
3078 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
3082 static void ixgbe_configure_virtualization(struct ixgbe_adapter
*adapter
)
3084 struct ixgbe_hw
*hw
= &adapter
->hw
;
3087 u32 reg_offset
, vf_shift
;
3090 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
3093 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
3094 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
| IXGBE_VT_CTL_REPLEN
;
3095 vt_reg_bits
|= (adapter
->num_vfs
<< IXGBE_VT_CTL_POOL_SHIFT
);
3096 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
3098 vf_shift
= adapter
->num_vfs
% 32;
3099 reg_offset
= (adapter
->num_vfs
> 32) ? 1 : 0;
3101 /* Enable only the PF's pool for Tx/Rx */
3102 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
3103 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
^ 1), 0);
3104 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
3105 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
^ 1), 0);
3106 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3108 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3109 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
3112 * Set up VF register offsets for selected VT Mode,
3113 * i.e. 32 or 64 VFs for SR-IOV
3115 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
3116 gcr_ext
|= IXGBE_GCR_EXT_MSIX_EN
;
3117 gcr_ext
|= IXGBE_GCR_EXT_VT_MODE_64
;
3118 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
3120 /* enable Tx loopback for VF/PF communication */
3121 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3122 /* Enable MAC Anti-Spoofing */
3123 hw
->mac
.ops
.set_mac_anti_spoofing(hw
,
3124 (adapter
->antispoofing_enabled
=
3125 (adapter
->num_vfs
!= 0)),
3129 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
3131 struct ixgbe_hw
*hw
= &adapter
->hw
;
3132 struct net_device
*netdev
= adapter
->netdev
;
3133 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3135 struct ixgbe_ring
*rx_ring
;
3139 /* Decide whether to use packet split mode or not */
3141 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
3143 /* Do not use packet split if we're in SR-IOV Mode */
3144 if (adapter
->num_vfs
)
3145 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
3147 /* Disable packet split due to 82599 erratum #45 */
3148 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3149 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
3151 /* Set the RX buffer length according to the mode */
3152 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
3153 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
3155 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
3156 (netdev
->mtu
<= ETH_DATA_LEN
))
3157 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
3159 rx_buf_len
= ALIGN(max_frame
+ VLAN_HLEN
, 1024);
3163 /* adjust max frame to be able to do baby jumbo for FCoE */
3164 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
3165 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
3166 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3168 #endif /* IXGBE_FCOE */
3169 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
3170 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
3171 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
3172 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
3174 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
3177 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
3178 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3179 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
3180 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
3183 * Setup the HW Rx Head and Tail Descriptor Pointers and
3184 * the Base and Length of the Rx Descriptor Ring
3186 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3187 rx_ring
= adapter
->rx_ring
[i
];
3188 rx_ring
->rx_buf_len
= rx_buf_len
;
3190 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
3191 set_ring_ps_enabled(rx_ring
);
3193 clear_ring_ps_enabled(rx_ring
);
3195 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
3196 set_ring_rsc_enabled(rx_ring
);
3198 clear_ring_rsc_enabled(rx_ring
);
3201 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
3202 struct ixgbe_ring_feature
*f
;
3203 f
= &adapter
->ring_feature
[RING_F_FCOE
];
3204 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
3205 clear_ring_ps_enabled(rx_ring
);
3206 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
3207 rx_ring
->rx_buf_len
=
3208 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3209 } else if (!ring_is_rsc_enabled(rx_ring
) &&
3210 !ring_is_ps_enabled(rx_ring
)) {
3211 rx_ring
->rx_buf_len
=
3212 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3215 #endif /* IXGBE_FCOE */
3219 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter
*adapter
)
3221 struct ixgbe_hw
*hw
= &adapter
->hw
;
3222 u32 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
3224 switch (hw
->mac
.type
) {
3225 case ixgbe_mac_82598EB
:
3227 * For VMDq support of different descriptor types or
3228 * buffer sizes through the use of multiple SRRCTL
3229 * registers, RDRXCTL.MVMEN must be set to 1
3231 * also, the manual doesn't mention it clearly but DCA hints
3232 * will only use queue 0's tags unless this bit is set. Side
3233 * effects of setting this bit are only that SRRCTL must be
3234 * fully programmed [0..15]
3236 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
3238 case ixgbe_mac_82599EB
:
3239 case ixgbe_mac_X540
:
3240 /* Disable RSC for ACK packets */
3241 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
3242 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
3243 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
3244 /* hardware requires some bits to be set by default */
3245 rdrxctl
|= (IXGBE_RDRXCTL_RSCACKC
| IXGBE_RDRXCTL_FCOE_WRFIX
);
3246 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
3249 /* We should do nothing since we don't know this hardware */
3253 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
3257 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3258 * @adapter: board private structure
3260 * Configure the Rx unit of the MAC after a reset.
3262 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
3264 struct ixgbe_hw
*hw
= &adapter
->hw
;
3268 /* disable receives while setting up the descriptors */
3269 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3270 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3272 ixgbe_setup_psrtype(adapter
);
3273 ixgbe_setup_rdrxctl(adapter
);
3275 /* Program registers for the distribution of queues */
3276 ixgbe_setup_mrqc(adapter
);
3278 ixgbe_set_uta(adapter
);
3280 /* set_rx_buffer_len must be called before ring initialization */
3281 ixgbe_set_rx_buffer_len(adapter
);
3284 * Setup the HW Rx Head and Tail Descriptor Pointers and
3285 * the Base and Length of the Rx Descriptor Ring
3287 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3288 ixgbe_configure_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3290 /* disable drop enable for 82598 parts */
3291 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3292 rxctrl
|= IXGBE_RXCTRL_DMBYPS
;
3294 /* enable all receives */
3295 rxctrl
|= IXGBE_RXCTRL_RXEN
;
3296 hw
->mac
.ops
.enable_rx_dma(hw
, rxctrl
);
3299 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
3301 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3302 struct ixgbe_hw
*hw
= &adapter
->hw
;
3303 int pool_ndx
= adapter
->num_vfs
;
3305 /* add VID to filter table */
3306 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
3307 set_bit(vid
, adapter
->active_vlans
);
3310 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
3312 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3313 struct ixgbe_hw
*hw
= &adapter
->hw
;
3314 int pool_ndx
= adapter
->num_vfs
;
3316 /* remove VID from filter table */
3317 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
3318 clear_bit(vid
, adapter
->active_vlans
);
3322 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3323 * @adapter: driver data
3325 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
3327 struct ixgbe_hw
*hw
= &adapter
->hw
;
3330 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3331 vlnctrl
&= ~(IXGBE_VLNCTRL_VFE
| IXGBE_VLNCTRL_CFIEN
);
3332 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3336 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3337 * @adapter: driver data
3339 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
3341 struct ixgbe_hw
*hw
= &adapter
->hw
;
3344 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3345 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
3346 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3347 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3351 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3352 * @adapter: driver data
3354 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter
*adapter
)
3356 struct ixgbe_hw
*hw
= &adapter
->hw
;
3360 switch (hw
->mac
.type
) {
3361 case ixgbe_mac_82598EB
:
3362 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3363 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
3364 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3366 case ixgbe_mac_82599EB
:
3367 case ixgbe_mac_X540
:
3368 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3369 j
= adapter
->rx_ring
[i
]->reg_idx
;
3370 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3371 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
3372 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3381 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3382 * @adapter: driver data
3384 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter
*adapter
)
3386 struct ixgbe_hw
*hw
= &adapter
->hw
;
3390 switch (hw
->mac
.type
) {
3391 case ixgbe_mac_82598EB
:
3392 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3393 vlnctrl
|= IXGBE_VLNCTRL_VME
;
3394 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3396 case ixgbe_mac_82599EB
:
3397 case ixgbe_mac_X540
:
3398 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3399 j
= adapter
->rx_ring
[i
]->reg_idx
;
3400 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3401 vlnctrl
|= IXGBE_RXDCTL_VME
;
3402 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3410 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3414 ixgbe_vlan_rx_add_vid(adapter
->netdev
, 0);
3416 for_each_set_bit(vid
, adapter
->active_vlans
, VLAN_N_VID
)
3417 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3421 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3422 * @netdev: network interface device structure
3424 * Writes unicast address list to the RAR table.
3425 * Returns: -ENOMEM on failure/insufficient address space
3426 * 0 on no addresses written
3427 * X on writing X addresses to the RAR table
3429 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3431 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3432 struct ixgbe_hw
*hw
= &adapter
->hw
;
3433 unsigned int vfn
= adapter
->num_vfs
;
3434 unsigned int rar_entries
= IXGBE_MAX_PF_MACVLANS
;
3437 /* return ENOMEM indicating insufficient memory for addresses */
3438 if (netdev_uc_count(netdev
) > rar_entries
)
3441 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3442 struct netdev_hw_addr
*ha
;
3443 /* return error if we do not support writing to RAR table */
3444 if (!hw
->mac
.ops
.set_rar
)
3447 netdev_for_each_uc_addr(ha
, netdev
) {
3450 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3455 /* write the addresses in reverse order to avoid write combining */
3456 for (; rar_entries
> 0 ; rar_entries
--)
3457 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3463 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3464 * @netdev: network interface device structure
3466 * The set_rx_method entry point is called whenever the unicast/multicast
3467 * address list or the network interface flags are updated. This routine is
3468 * responsible for configuring the hardware for proper unicast, multicast and
3471 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3473 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3474 struct ixgbe_hw
*hw
= &adapter
->hw
;
3475 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3478 /* Check for Promiscuous and All Multicast modes */
3480 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3482 /* set all bits that we expect to always be set */
3483 fctrl
|= IXGBE_FCTRL_BAM
;
3484 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3485 fctrl
|= IXGBE_FCTRL_PMCF
;
3487 /* clear the bits we are changing the status of */
3488 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3490 if (netdev
->flags
& IFF_PROMISC
) {
3491 hw
->addr_ctrl
.user_set_promisc
= true;
3492 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3493 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3494 /* don't hardware filter vlans in promisc mode */
3495 ixgbe_vlan_filter_disable(adapter
);
3497 if (netdev
->flags
& IFF_ALLMULTI
) {
3498 fctrl
|= IXGBE_FCTRL_MPE
;
3499 vmolr
|= IXGBE_VMOLR_MPE
;
3502 * Write addresses to the MTA, if the attempt fails
3503 * then we should just turn on promiscuous mode so
3504 * that we can at least receive multicast traffic
3506 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3507 vmolr
|= IXGBE_VMOLR_ROMPE
;
3509 ixgbe_vlan_filter_enable(adapter
);
3510 hw
->addr_ctrl
.user_set_promisc
= false;
3512 * Write addresses to available RAR registers, if there is not
3513 * sufficient space to store all the addresses then enable
3514 * unicast promiscuous mode
3516 count
= ixgbe_write_uc_addr_list(netdev
);
3518 fctrl
|= IXGBE_FCTRL_UPE
;
3519 vmolr
|= IXGBE_VMOLR_ROPE
;
3523 if (adapter
->num_vfs
) {
3524 ixgbe_restore_vf_multicasts(adapter
);
3525 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3526 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3528 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3531 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3533 if (netdev
->features
& NETIF_F_HW_VLAN_RX
)
3534 ixgbe_vlan_strip_enable(adapter
);
3536 ixgbe_vlan_strip_disable(adapter
);
3539 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3542 struct ixgbe_q_vector
*q_vector
;
3543 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3545 /* legacy and MSI only use one vector */
3546 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3549 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3550 struct napi_struct
*napi
;
3551 q_vector
= adapter
->q_vector
[q_idx
];
3552 napi
= &q_vector
->napi
;
3553 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3554 if (!q_vector
->rx
.count
|| !q_vector
->tx
.count
) {
3555 if (q_vector
->tx
.count
== 1)
3556 napi
->poll
= &ixgbe_clean_txonly
;
3557 else if (q_vector
->rx
.count
== 1)
3558 napi
->poll
= &ixgbe_clean_rxonly
;
3566 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3569 struct ixgbe_q_vector
*q_vector
;
3570 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3572 /* legacy and MSI only use one vector */
3573 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3576 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3577 q_vector
= adapter
->q_vector
[q_idx
];
3578 napi_disable(&q_vector
->napi
);
3582 #ifdef CONFIG_IXGBE_DCB
3584 * ixgbe_configure_dcb - Configure DCB hardware
3585 * @adapter: ixgbe adapter struct
3587 * This is called by the driver on open to configure the DCB hardware.
3588 * This is also called by the gennetlink interface when reconfiguring
3591 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3593 struct ixgbe_hw
*hw
= &adapter
->hw
;
3594 int max_frame
= adapter
->netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3596 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3597 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3598 netif_set_gso_max_size(adapter
->netdev
, 65536);
3602 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3603 netif_set_gso_max_size(adapter
->netdev
, 32768);
3606 /* Enable VLAN tag insert/strip */
3607 adapter
->netdev
->features
|= NETIF_F_HW_VLAN_RX
;
3609 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3611 /* reconfigure the hardware */
3612 if (adapter
->dcbx_cap
& DCB_CAP_DCBX_VER_CEE
) {
3614 if (adapter
->netdev
->features
& NETIF_F_FCOE_MTU
)
3615 max_frame
= max(max_frame
, IXGBE_FCOE_JUMBO_FRAME_SIZE
);
3617 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3619 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3621 ixgbe_dcb_hw_config(hw
, &adapter
->dcb_cfg
);
3623 struct net_device
*dev
= adapter
->netdev
;
3625 if (adapter
->ixgbe_ieee_ets
)
3626 dev
->dcbnl_ops
->ieee_setets(dev
,
3627 adapter
->ixgbe_ieee_ets
);
3628 if (adapter
->ixgbe_ieee_pfc
)
3629 dev
->dcbnl_ops
->ieee_setpfc(dev
,
3630 adapter
->ixgbe_ieee_pfc
);
3633 /* Enable RSS Hash per TC */
3634 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
3638 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
3640 u8 cnt
= adapter
->netdev
->tc_to_txq
[i
].count
;
3645 reg
|= msb
<< IXGBE_RQTC_SHIFT_TC(i
);
3647 IXGBE_WRITE_REG(hw
, IXGBE_RQTC
, reg
);
3653 static void ixgbe_configure_pb(struct ixgbe_adapter
*adapter
)
3656 int num_tc
= netdev_get_num_tc(adapter
->netdev
);
3657 struct ixgbe_hw
*hw
= &adapter
->hw
;
3659 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3660 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3661 hdrm
= 64 << adapter
->fdir_pballoc
;
3663 hw
->mac
.ops
.set_rxpba(&adapter
->hw
, num_tc
, hdrm
, PBA_STRATEGY_EQUAL
);
3666 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter
*adapter
)
3668 struct ixgbe_hw
*hw
= &adapter
->hw
;
3669 struct hlist_node
*node
, *node2
;
3670 struct ixgbe_fdir_filter
*filter
;
3672 spin_lock(&adapter
->fdir_perfect_lock
);
3674 if (!hlist_empty(&adapter
->fdir_filter_list
))
3675 ixgbe_fdir_set_input_mask_82599(hw
, &adapter
->fdir_mask
);
3677 hlist_for_each_entry_safe(filter
, node
, node2
,
3678 &adapter
->fdir_filter_list
, fdir_node
) {
3679 ixgbe_fdir_write_perfect_filter_82599(hw
,
3682 (filter
->action
== IXGBE_FDIR_DROP_QUEUE
) ?
3683 IXGBE_FDIR_DROP_QUEUE
:
3684 adapter
->rx_ring
[filter
->action
]->reg_idx
);
3687 spin_unlock(&adapter
->fdir_perfect_lock
);
3690 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3692 struct net_device
*netdev
= adapter
->netdev
;
3693 struct ixgbe_hw
*hw
= &adapter
->hw
;
3696 ixgbe_configure_pb(adapter
);
3697 #ifdef CONFIG_IXGBE_DCB
3698 ixgbe_configure_dcb(adapter
);
3701 ixgbe_set_rx_mode(netdev
);
3702 ixgbe_restore_vlan(adapter
);
3705 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3706 ixgbe_configure_fcoe(adapter
);
3708 #endif /* IXGBE_FCOE */
3709 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3710 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3711 adapter
->tx_ring
[i
]->atr_sample_rate
=
3712 adapter
->atr_sample_rate
;
3713 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3714 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3715 ixgbe_init_fdir_perfect_82599(&adapter
->hw
,
3716 adapter
->fdir_pballoc
);
3717 ixgbe_fdir_filter_restore(adapter
);
3719 ixgbe_configure_virtualization(adapter
);
3721 ixgbe_configure_tx(adapter
);
3722 ixgbe_configure_rx(adapter
);
3725 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3727 switch (hw
->phy
.type
) {
3728 case ixgbe_phy_sfp_avago
:
3729 case ixgbe_phy_sfp_ftl
:
3730 case ixgbe_phy_sfp_intel
:
3731 case ixgbe_phy_sfp_unknown
:
3732 case ixgbe_phy_sfp_passive_tyco
:
3733 case ixgbe_phy_sfp_passive_unknown
:
3734 case ixgbe_phy_sfp_active_unknown
:
3735 case ixgbe_phy_sfp_ftl_active
:
3743 * ixgbe_sfp_link_config - set up SFP+ link
3744 * @adapter: pointer to private adapter struct
3746 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3749 * We are assuming the worst case scenerio here, and that
3750 * is that an SFP was inserted/removed after the reset
3751 * but before SFP detection was enabled. As such the best
3752 * solution is to just start searching as soon as we start
3754 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
3755 adapter
->flags2
|= IXGBE_FLAG2_SEARCH_FOR_SFP
;
3757 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
3761 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3762 * @hw: pointer to private hardware struct
3764 * Returns 0 on success, negative on failure
3766 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3769 bool negotiation
, link_up
= false;
3770 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3772 if (hw
->mac
.ops
.check_link
)
3773 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3778 autoneg
= hw
->phy
.autoneg_advertised
;
3779 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
3780 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
3785 if (hw
->mac
.ops
.setup_link
)
3786 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3791 static void ixgbe_setup_gpie(struct ixgbe_adapter
*adapter
)
3793 struct ixgbe_hw
*hw
= &adapter
->hw
;
3796 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3797 gpie
= IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_PBA_SUPPORT
|
3799 gpie
|= IXGBE_GPIE_EIAME
;
3801 * use EIAM to auto-mask when MSI-X interrupt is asserted
3802 * this saves a register write for every interrupt
3804 switch (hw
->mac
.type
) {
3805 case ixgbe_mac_82598EB
:
3806 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3808 case ixgbe_mac_82599EB
:
3809 case ixgbe_mac_X540
:
3811 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3812 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3816 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3817 * specifically only auto mask tx and rx interrupts */
3818 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3821 /* XXX: to interrupt immediately for EICS writes, enable this */
3822 /* gpie |= IXGBE_GPIE_EIMEN; */
3824 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3825 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3826 gpie
|= IXGBE_GPIE_VTMODE_64
;
3829 /* Enable fan failure interrupt */
3830 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
3831 gpie
|= IXGBE_SDP1_GPIEN
;
3833 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3834 gpie
|= IXGBE_SDP1_GPIEN
;
3835 gpie
|= IXGBE_SDP2_GPIEN
;
3838 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3841 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3843 struct ixgbe_hw
*hw
= &adapter
->hw
;
3847 ixgbe_get_hw_control(adapter
);
3848 ixgbe_setup_gpie(adapter
);
3850 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3851 ixgbe_configure_msix(adapter
);
3853 ixgbe_configure_msi_and_legacy(adapter
);
3855 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3856 if (hw
->mac
.ops
.enable_tx_laser
&&
3857 ((hw
->phy
.multispeed_fiber
) ||
3858 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
3859 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
3860 hw
->mac
.ops
.enable_tx_laser(hw
);
3862 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3863 ixgbe_napi_enable_all(adapter
);
3865 if (ixgbe_is_sfp(hw
)) {
3866 ixgbe_sfp_link_config(adapter
);
3868 err
= ixgbe_non_sfp_link_config(hw
);
3870 e_err(probe
, "link_config FAILED %d\n", err
);
3873 /* clear any pending interrupts, may auto mask */
3874 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3875 ixgbe_irq_enable(adapter
, true, true);
3878 * If this adapter has a fan, check to see if we had a failure
3879 * before we enabled the interrupt.
3881 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3882 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3883 if (esdp
& IXGBE_ESDP_SDP1
)
3884 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3887 /* enable transmits */
3888 netif_tx_start_all_queues(adapter
->netdev
);
3890 /* bring the link up in the watchdog, this could race with our first
3891 * link up interrupt but shouldn't be a problem */
3892 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3893 adapter
->link_check_timeout
= jiffies
;
3894 mod_timer(&adapter
->service_timer
, jiffies
);
3896 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3897 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3898 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3899 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3904 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3906 WARN_ON(in_interrupt());
3907 /* put off any impending NetWatchDogTimeout */
3908 adapter
->netdev
->trans_start
= jiffies
;
3910 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3911 usleep_range(1000, 2000);
3912 ixgbe_down(adapter
);
3914 * If SR-IOV enabled then wait a bit before bringing the adapter
3915 * back up to give the VFs time to respond to the reset. The
3916 * two second wait is based upon the watchdog timer cycle in
3919 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3922 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3925 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3927 /* hardware has been reset, we need to reload some things */
3928 ixgbe_configure(adapter
);
3930 return ixgbe_up_complete(adapter
);
3933 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3935 struct ixgbe_hw
*hw
= &adapter
->hw
;
3938 /* lock SFP init bit to prevent race conditions with the watchdog */
3939 while (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
3940 usleep_range(1000, 2000);
3942 /* clear all SFP and link config related flags while holding SFP_INIT */
3943 adapter
->flags2
&= ~(IXGBE_FLAG2_SEARCH_FOR_SFP
|
3944 IXGBE_FLAG2_SFP_NEEDS_RESET
);
3945 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_CONFIG
;
3947 err
= hw
->mac
.ops
.init_hw(hw
);
3950 case IXGBE_ERR_SFP_NOT_PRESENT
:
3951 case IXGBE_ERR_SFP_NOT_SUPPORTED
:
3953 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3954 e_dev_err("master disable timed out\n");
3956 case IXGBE_ERR_EEPROM_VERSION
:
3957 /* We are running on a pre-production device, log a warning */
3958 e_dev_warn("This device is a pre-production adapter/LOM. "
3959 "Please be aware there may be issuesassociated with "
3960 "your hardware. If you are experiencing problems "
3961 "please contact your Intel or hardware "
3962 "representative who provided you with this "
3966 e_dev_err("Hardware Error: %d\n", err
);
3969 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
3971 /* reprogram the RAR[0] in case user changed it. */
3972 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3977 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3978 * @rx_ring: ring to free buffers from
3980 static void ixgbe_clean_rx_ring(struct ixgbe_ring
*rx_ring
)
3982 struct device
*dev
= rx_ring
->dev
;
3986 /* ring already cleared, nothing to do */
3987 if (!rx_ring
->rx_buffer_info
)
3990 /* Free all the Rx ring sk_buffs */
3991 for (i
= 0; i
< rx_ring
->count
; i
++) {
3992 struct ixgbe_rx_buffer
*rx_buffer_info
;
3994 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3995 if (rx_buffer_info
->dma
) {
3996 dma_unmap_single(rx_ring
->dev
, rx_buffer_info
->dma
,
3997 rx_ring
->rx_buf_len
,
3999 rx_buffer_info
->dma
= 0;
4001 if (rx_buffer_info
->skb
) {
4002 struct sk_buff
*skb
= rx_buffer_info
->skb
;
4003 rx_buffer_info
->skb
= NULL
;
4005 struct sk_buff
*this = skb
;
4006 if (IXGBE_RSC_CB(this)->delay_unmap
) {
4007 dma_unmap_single(dev
,
4008 IXGBE_RSC_CB(this)->dma
,
4009 rx_ring
->rx_buf_len
,
4011 IXGBE_RSC_CB(this)->dma
= 0;
4012 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
4015 dev_kfree_skb(this);
4018 if (!rx_buffer_info
->page
)
4020 if (rx_buffer_info
->page_dma
) {
4021 dma_unmap_page(dev
, rx_buffer_info
->page_dma
,
4022 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
4023 rx_buffer_info
->page_dma
= 0;
4025 put_page(rx_buffer_info
->page
);
4026 rx_buffer_info
->page
= NULL
;
4027 rx_buffer_info
->page_offset
= 0;
4030 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4031 memset(rx_ring
->rx_buffer_info
, 0, size
);
4033 /* Zero out the descriptor ring */
4034 memset(rx_ring
->desc
, 0, rx_ring
->size
);
4036 rx_ring
->next_to_clean
= 0;
4037 rx_ring
->next_to_use
= 0;
4041 * ixgbe_clean_tx_ring - Free Tx Buffers
4042 * @tx_ring: ring to be cleaned
4044 static void ixgbe_clean_tx_ring(struct ixgbe_ring
*tx_ring
)
4046 struct ixgbe_tx_buffer
*tx_buffer_info
;
4050 /* ring already cleared, nothing to do */
4051 if (!tx_ring
->tx_buffer_info
)
4054 /* Free all the Tx ring sk_buffs */
4055 for (i
= 0; i
< tx_ring
->count
; i
++) {
4056 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4057 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
4060 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4061 memset(tx_ring
->tx_buffer_info
, 0, size
);
4063 /* Zero out the descriptor ring */
4064 memset(tx_ring
->desc
, 0, tx_ring
->size
);
4066 tx_ring
->next_to_use
= 0;
4067 tx_ring
->next_to_clean
= 0;
4071 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4072 * @adapter: board private structure
4074 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
4078 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4079 ixgbe_clean_rx_ring(adapter
->rx_ring
[i
]);
4083 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4084 * @adapter: board private structure
4086 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
4090 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4091 ixgbe_clean_tx_ring(adapter
->tx_ring
[i
]);
4094 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter
*adapter
)
4096 struct hlist_node
*node
, *node2
;
4097 struct ixgbe_fdir_filter
*filter
;
4099 spin_lock(&adapter
->fdir_perfect_lock
);
4101 hlist_for_each_entry_safe(filter
, node
, node2
,
4102 &adapter
->fdir_filter_list
, fdir_node
) {
4103 hlist_del(&filter
->fdir_node
);
4106 adapter
->fdir_filter_count
= 0;
4108 spin_unlock(&adapter
->fdir_perfect_lock
);
4111 void ixgbe_down(struct ixgbe_adapter
*adapter
)
4113 struct net_device
*netdev
= adapter
->netdev
;
4114 struct ixgbe_hw
*hw
= &adapter
->hw
;
4117 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4119 /* signal that we are down to the interrupt handler */
4120 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4122 /* disable receives */
4123 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
4124 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
4126 /* disable all enabled rx queues */
4127 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4128 /* this call also flushes the previous write */
4129 ixgbe_disable_rx_queue(adapter
, adapter
->rx_ring
[i
]);
4131 usleep_range(10000, 20000);
4133 netif_tx_stop_all_queues(netdev
);
4135 /* call carrier off first to avoid false dev_watchdog timeouts */
4136 netif_carrier_off(netdev
);
4137 netif_tx_disable(netdev
);
4139 ixgbe_irq_disable(adapter
);
4141 ixgbe_napi_disable_all(adapter
);
4143 adapter
->flags2
&= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT
|
4144 IXGBE_FLAG2_RESET_REQUESTED
);
4145 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
4147 del_timer_sync(&adapter
->service_timer
);
4149 /* disable receive for all VFs and wait one second */
4150 if (adapter
->num_vfs
) {
4151 /* ping all the active vfs to let them know we are going down */
4152 ixgbe_ping_all_vfs(adapter
);
4154 /* Disable all VFTE/VFRE TX/RX */
4155 ixgbe_disable_tx_rx(adapter
);
4157 /* Mark all the VFs as inactive */
4158 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
4159 adapter
->vfinfo
[i
].clear_to_send
= 0;
4162 /* Cleanup the affinity_hint CPU mask memory and callback */
4163 for (i
= 0; i
< num_q_vectors
; i
++) {
4164 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
4165 /* clear the affinity_mask in the IRQ descriptor */
4166 irq_set_affinity_hint(adapter
->msix_entries
[i
]. vector
, NULL
);
4167 /* release the CPU mask memory */
4168 free_cpumask_var(q_vector
->affinity_mask
);
4171 /* disable transmits in the hardware now that interrupts are off */
4172 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4173 u8 reg_idx
= adapter
->tx_ring
[i
]->reg_idx
;
4174 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), IXGBE_TXDCTL_SWFLSH
);
4177 /* Disable the Tx DMA engine on 82599 and X540 */
4178 switch (hw
->mac
.type
) {
4179 case ixgbe_mac_82599EB
:
4180 case ixgbe_mac_X540
:
4181 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
4182 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
4183 ~IXGBE_DMATXCTL_TE
));
4189 if (!pci_channel_offline(adapter
->pdev
))
4190 ixgbe_reset(adapter
);
4192 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4193 if (hw
->mac
.ops
.disable_tx_laser
&&
4194 ((hw
->phy
.multispeed_fiber
) ||
4195 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
4196 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
4197 hw
->mac
.ops
.disable_tx_laser(hw
);
4199 ixgbe_clean_all_tx_rings(adapter
);
4200 ixgbe_clean_all_rx_rings(adapter
);
4202 #ifdef CONFIG_IXGBE_DCA
4203 /* since we reset the hardware DCA settings were cleared */
4204 ixgbe_setup_dca(adapter
);
4209 * ixgbe_poll - NAPI Rx polling callback
4210 * @napi: structure for representing this polling device
4211 * @budget: how many packets driver is allowed to clean
4213 * This function is used for legacy and MSI, NAPI mode
4215 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
4217 struct ixgbe_q_vector
*q_vector
=
4218 container_of(napi
, struct ixgbe_q_vector
, napi
);
4219 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
4220 int tx_clean_complete
, work_done
= 0;
4222 #ifdef CONFIG_IXGBE_DCA
4223 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
4224 ixgbe_update_dca(q_vector
);
4227 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
4228 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
4230 if (!tx_clean_complete
)
4233 /* If budget not fully consumed, exit the polling mode */
4234 if (work_done
< budget
) {
4235 napi_complete(napi
);
4236 if (adapter
->rx_itr_setting
& 1)
4237 ixgbe_set_itr(q_vector
);
4238 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
4239 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
4245 * ixgbe_tx_timeout - Respond to a Tx Hang
4246 * @netdev: network interface device structure
4248 static void ixgbe_tx_timeout(struct net_device
*netdev
)
4250 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4252 /* Do the reset outside of interrupt context */
4253 ixgbe_tx_timeout_reset(adapter
);
4257 * ixgbe_set_rss_queues: Allocate queues for RSS
4258 * @adapter: board private structure to initialize
4260 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4261 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4264 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
4267 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
4269 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4271 adapter
->num_rx_queues
= f
->indices
;
4272 adapter
->num_tx_queues
= f
->indices
;
4282 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4283 * @adapter: board private structure to initialize
4285 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4286 * to the original CPU that initiated the Tx session. This runs in addition
4287 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4288 * Rx load across CPUs using RSS.
4291 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
4294 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
4296 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
4299 /* Flow Director must have RSS enabled */
4300 if ((adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) &&
4301 (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)) {
4302 adapter
->num_tx_queues
= f_fdir
->indices
;
4303 adapter
->num_rx_queues
= f_fdir
->indices
;
4306 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4313 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4314 * @adapter: board private structure to initialize
4316 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4317 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4318 * rx queues out of the max number of rx queues, instead, it is used as the
4319 * index of the first rx queue used by FCoE.
4322 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
4324 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4326 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4329 f
->indices
= min((int)num_online_cpus(), f
->indices
);
4331 adapter
->num_rx_queues
= 1;
4332 adapter
->num_tx_queues
= 1;
4334 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4335 e_info(probe
, "FCoE enabled with RSS\n");
4336 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)
4337 ixgbe_set_fdir_queues(adapter
);
4339 ixgbe_set_rss_queues(adapter
);
4342 /* adding FCoE rx rings to the end */
4343 f
->mask
= adapter
->num_rx_queues
;
4344 adapter
->num_rx_queues
+= f
->indices
;
4345 adapter
->num_tx_queues
+= f
->indices
;
4349 #endif /* IXGBE_FCOE */
4351 /* Artificial max queue cap per traffic class in DCB mode */
4352 #define DCB_QUEUE_CAP 8
4354 #ifdef CONFIG_IXGBE_DCB
4355 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
4357 int per_tc_q
, q
, i
, offset
= 0;
4358 struct net_device
*dev
= adapter
->netdev
;
4359 int tcs
= netdev_get_num_tc(dev
);
4364 /* Map queue offset and counts onto allocated tx queues */
4365 per_tc_q
= min(dev
->num_tx_queues
/ tcs
, (unsigned int)DCB_QUEUE_CAP
);
4366 q
= min((int)num_online_cpus(), per_tc_q
);
4368 for (i
= 0; i
< tcs
; i
++) {
4369 netdev_set_prio_tc_map(dev
, i
, i
);
4370 netdev_set_tc_queue(dev
, i
, q
, offset
);
4374 adapter
->num_tx_queues
= q
* tcs
;
4375 adapter
->num_rx_queues
= q
* tcs
;
4378 /* FCoE enabled queues require special configuration indexed
4379 * by feature specific indices and mask. Here we map FCoE
4380 * indices onto the DCB queue pairs allowing FCoE to own
4381 * configuration later.
4383 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4385 struct ixgbe_ring_feature
*f
=
4386 &adapter
->ring_feature
[RING_F_FCOE
];
4388 tc
= netdev_get_prio_tc_map(dev
, adapter
->fcoe
.up
);
4389 f
->indices
= dev
->tc_to_txq
[tc
].count
;
4390 f
->mask
= dev
->tc_to_txq
[tc
].offset
;
4399 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4400 * @adapter: board private structure to initialize
4402 * IOV doesn't actually use anything, so just NAK the
4403 * request for now and let the other queue routines
4404 * figure out what to do.
4406 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4412 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4413 * @adapter: board private structure to initialize
4415 * This is the top level queue allocation routine. The order here is very
4416 * important, starting with the "most" number of features turned on at once,
4417 * and ending with the smallest set of features. This way large combinations
4418 * can be allocated if they're turned on, and smaller combinations are the
4419 * fallthrough conditions.
4422 static int ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4424 /* Start with base case */
4425 adapter
->num_rx_queues
= 1;
4426 adapter
->num_tx_queues
= 1;
4427 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4428 adapter
->num_rx_queues_per_pool
= 1;
4430 if (ixgbe_set_sriov_queues(adapter
))
4433 #ifdef CONFIG_IXGBE_DCB
4434 if (ixgbe_set_dcb_queues(adapter
))
4439 if (ixgbe_set_fcoe_queues(adapter
))
4442 #endif /* IXGBE_FCOE */
4443 if (ixgbe_set_fdir_queues(adapter
))
4446 if (ixgbe_set_rss_queues(adapter
))
4449 /* fallback to base case */
4450 adapter
->num_rx_queues
= 1;
4451 adapter
->num_tx_queues
= 1;
4454 /* Notify the stack of the (possibly) reduced queue counts. */
4455 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4456 return netif_set_real_num_rx_queues(adapter
->netdev
,
4457 adapter
->num_rx_queues
);
4460 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4463 int err
, vector_threshold
;
4465 /* We'll want at least 3 (vector_threshold):
4468 * 3) Other (Link Status Change, etc.)
4469 * 4) TCP Timer (optional)
4471 vector_threshold
= MIN_MSIX_COUNT
;
4473 /* The more we get, the more we will assign to Tx/Rx Cleanup
4474 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4475 * Right now, we simply care about how many we'll get; we'll
4476 * set them up later while requesting irq's.
4478 while (vectors
>= vector_threshold
) {
4479 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4481 if (!err
) /* Success in acquiring all requested vectors. */
4484 vectors
= 0; /* Nasty failure, quit now */
4485 else /* err == number of vectors we should try again with */
4489 if (vectors
< vector_threshold
) {
4490 /* Can't allocate enough MSI-X interrupts? Oh well.
4491 * This just means we'll go with either a single MSI
4492 * vector or fall back to legacy interrupts.
4494 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4495 "Unable to allocate MSI-X interrupts\n");
4496 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4497 kfree(adapter
->msix_entries
);
4498 adapter
->msix_entries
= NULL
;
4500 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4502 * Adjust for only the vectors we'll use, which is minimum
4503 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4504 * vectors we were allocated.
4506 adapter
->num_msix_vectors
= min(vectors
,
4507 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4512 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4513 * @adapter: board private structure to initialize
4515 * Cache the descriptor ring offsets for RSS to the assigned rings.
4518 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4522 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
4525 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4526 adapter
->rx_ring
[i
]->reg_idx
= i
;
4527 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4528 adapter
->tx_ring
[i
]->reg_idx
= i
;
4533 #ifdef CONFIG_IXGBE_DCB
4535 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4536 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter
*adapter
, u8 tc
,
4537 unsigned int *tx
, unsigned int *rx
)
4539 struct net_device
*dev
= adapter
->netdev
;
4540 struct ixgbe_hw
*hw
= &adapter
->hw
;
4541 u8 num_tcs
= netdev_get_num_tc(dev
);
4546 switch (hw
->mac
.type
) {
4547 case ixgbe_mac_82598EB
:
4551 case ixgbe_mac_82599EB
:
4552 case ixgbe_mac_X540
:
4557 } else if (tc
< 5) {
4558 *tx
= ((tc
+ 2) << 4);
4560 } else if (tc
< num_tcs
) {
4561 *tx
= ((tc
+ 8) << 3);
4564 } else if (num_tcs
== 4) {
4590 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4591 * @adapter: board private structure to initialize
4593 * Cache the descriptor ring offsets for DCB to the assigned rings.
4596 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4598 struct net_device
*dev
= adapter
->netdev
;
4600 u8 num_tcs
= netdev_get_num_tc(dev
);
4605 for (i
= 0, k
= 0; i
< num_tcs
; i
++) {
4606 unsigned int tx_s
, rx_s
;
4607 u16 count
= dev
->tc_to_txq
[i
].count
;
4609 ixgbe_get_first_reg_idx(adapter
, i
, &tx_s
, &rx_s
);
4610 for (j
= 0; j
< count
; j
++, k
++) {
4611 adapter
->tx_ring
[k
]->reg_idx
= tx_s
+ j
;
4612 adapter
->rx_ring
[k
]->reg_idx
= rx_s
+ j
;
4613 adapter
->tx_ring
[k
]->dcb_tc
= i
;
4614 adapter
->rx_ring
[k
]->dcb_tc
= i
;
4623 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4624 * @adapter: board private structure to initialize
4626 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4629 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4634 if ((adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) &&
4635 (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)) {
4636 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4637 adapter
->rx_ring
[i
]->reg_idx
= i
;
4638 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4639 adapter
->tx_ring
[i
]->reg_idx
= i
;
4648 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4649 * @adapter: board private structure to initialize
4651 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4654 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4656 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4658 u8 fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4660 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4663 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4664 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)
4665 ixgbe_cache_ring_fdir(adapter
);
4667 ixgbe_cache_ring_rss(adapter
);
4669 fcoe_rx_i
= f
->mask
;
4670 fcoe_tx_i
= f
->mask
;
4672 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4673 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4674 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4679 #endif /* IXGBE_FCOE */
4681 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4682 * @adapter: board private structure to initialize
4684 * SR-IOV doesn't use any descriptor rings but changes the default if
4685 * no other mapping is used.
4688 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4690 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4691 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4692 if (adapter
->num_vfs
)
4699 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4700 * @adapter: board private structure to initialize
4702 * Once we know the feature-set enabled for the device, we'll cache
4703 * the register offset the descriptor ring is assigned to.
4705 * Note, the order the various feature calls is important. It must start with
4706 * the "most" features enabled at the same time, then trickle down to the
4707 * least amount of features turned on at once.
4709 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4711 /* start with default case */
4712 adapter
->rx_ring
[0]->reg_idx
= 0;
4713 adapter
->tx_ring
[0]->reg_idx
= 0;
4715 if (ixgbe_cache_ring_sriov(adapter
))
4718 #ifdef CONFIG_IXGBE_DCB
4719 if (ixgbe_cache_ring_dcb(adapter
))
4724 if (ixgbe_cache_ring_fcoe(adapter
))
4726 #endif /* IXGBE_FCOE */
4728 if (ixgbe_cache_ring_fdir(adapter
))
4731 if (ixgbe_cache_ring_rss(adapter
))
4736 * ixgbe_alloc_queues - Allocate memory for all rings
4737 * @adapter: board private structure to initialize
4739 * We allocate one ring per queue at run-time since we don't know the
4740 * number of queues at compile-time. The polling_netdev array is
4741 * intended for Multiqueue, but should work fine with a single queue.
4743 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4745 int rx
= 0, tx
= 0, nid
= adapter
->node
;
4747 if (nid
< 0 || !node_online(nid
))
4748 nid
= first_online_node
;
4750 for (; tx
< adapter
->num_tx_queues
; tx
++) {
4751 struct ixgbe_ring
*ring
;
4753 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4755 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4757 goto err_allocation
;
4758 ring
->count
= adapter
->tx_ring_count
;
4759 ring
->queue_index
= tx
;
4760 ring
->numa_node
= nid
;
4761 ring
->dev
= &adapter
->pdev
->dev
;
4762 ring
->netdev
= adapter
->netdev
;
4764 adapter
->tx_ring
[tx
] = ring
;
4767 for (; rx
< adapter
->num_rx_queues
; rx
++) {
4768 struct ixgbe_ring
*ring
;
4770 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4772 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4774 goto err_allocation
;
4775 ring
->count
= adapter
->rx_ring_count
;
4776 ring
->queue_index
= rx
;
4777 ring
->numa_node
= nid
;
4778 ring
->dev
= &adapter
->pdev
->dev
;
4779 ring
->netdev
= adapter
->netdev
;
4781 adapter
->rx_ring
[rx
] = ring
;
4784 ixgbe_cache_ring_register(adapter
);
4790 kfree(adapter
->tx_ring
[--tx
]);
4793 kfree(adapter
->rx_ring
[--rx
]);
4798 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4799 * @adapter: board private structure to initialize
4801 * Attempt to configure the interrupts using the best available
4802 * capabilities of the hardware and the kernel.
4804 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4806 struct ixgbe_hw
*hw
= &adapter
->hw
;
4808 int vector
, v_budget
;
4811 * It's easy to be greedy for MSI-X vectors, but it really
4812 * doesn't do us much good if we have a lot more vectors
4813 * than CPU's. So let's be conservative and only ask for
4814 * (roughly) the same number of vectors as there are CPU's.
4816 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4817 (int)num_online_cpus()) + NON_Q_VECTORS
;
4820 * At the same time, hardware can only support a maximum of
4821 * hw.mac->max_msix_vectors vectors. With features
4822 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4823 * descriptor queues supported by our device. Thus, we cap it off in
4824 * those rare cases where the cpu count also exceeds our vector limit.
4826 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4828 /* A failure in MSI-X entry allocation isn't fatal, but it does
4829 * mean we disable MSI-X capabilities of the adapter. */
4830 adapter
->msix_entries
= kcalloc(v_budget
,
4831 sizeof(struct msix_entry
), GFP_KERNEL
);
4832 if (adapter
->msix_entries
) {
4833 for (vector
= 0; vector
< v_budget
; vector
++)
4834 adapter
->msix_entries
[vector
].entry
= vector
;
4836 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4838 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4842 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4843 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4844 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
4846 "ATR is not supported while multiple "
4847 "queues are disabled. Disabling Flow Director\n");
4849 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4850 adapter
->atr_sample_rate
= 0;
4851 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4852 ixgbe_disable_sriov(adapter
);
4854 err
= ixgbe_set_num_queues(adapter
);
4858 err
= pci_enable_msi(adapter
->pdev
);
4860 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4862 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4863 "Unable to allocate MSI interrupt, "
4864 "falling back to legacy. Error: %d\n", err
);
4874 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4875 * @adapter: board private structure to initialize
4877 * We allocate one q_vector per queue interrupt. If allocation fails we
4880 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4882 int q_idx
, num_q_vectors
;
4883 struct ixgbe_q_vector
*q_vector
;
4884 int (*poll
)(struct napi_struct
*, int);
4886 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4887 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4888 poll
= &ixgbe_clean_rxtx_many
;
4894 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4895 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4896 GFP_KERNEL
, adapter
->node
);
4898 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4902 q_vector
->adapter
= adapter
;
4903 if (q_vector
->tx
.count
&& !q_vector
->rx
.count
)
4904 q_vector
->eitr
= adapter
->tx_eitr_param
;
4906 q_vector
->eitr
= adapter
->rx_eitr_param
;
4907 q_vector
->v_idx
= q_idx
;
4908 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4909 adapter
->q_vector
[q_idx
] = q_vector
;
4917 q_vector
= adapter
->q_vector
[q_idx
];
4918 netif_napi_del(&q_vector
->napi
);
4920 adapter
->q_vector
[q_idx
] = NULL
;
4926 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4927 * @adapter: board private structure to initialize
4929 * This function frees the memory allocated to the q_vectors. In addition if
4930 * NAPI is enabled it will delete any references to the NAPI struct prior
4931 * to freeing the q_vector.
4933 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4935 int q_idx
, num_q_vectors
;
4937 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4938 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4942 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4943 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4944 adapter
->q_vector
[q_idx
] = NULL
;
4945 netif_napi_del(&q_vector
->napi
);
4950 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4952 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4953 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4954 pci_disable_msix(adapter
->pdev
);
4955 kfree(adapter
->msix_entries
);
4956 adapter
->msix_entries
= NULL
;
4957 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4958 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4959 pci_disable_msi(adapter
->pdev
);
4964 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4965 * @adapter: board private structure to initialize
4967 * We determine which interrupt scheme to use based on...
4968 * - Kernel support (MSI, MSI-X)
4969 * - which can be user-defined (via MODULE_PARAM)
4970 * - Hardware queue count (num_*_queues)
4971 * - defined by miscellaneous hardware support/features (RSS, etc.)
4973 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4977 /* Number of supported queues */
4978 err
= ixgbe_set_num_queues(adapter
);
4982 err
= ixgbe_set_interrupt_capability(adapter
);
4984 e_dev_err("Unable to setup interrupt capabilities\n");
4985 goto err_set_interrupt
;
4988 err
= ixgbe_alloc_q_vectors(adapter
);
4990 e_dev_err("Unable to allocate memory for queue vectors\n");
4991 goto err_alloc_q_vectors
;
4994 err
= ixgbe_alloc_queues(adapter
);
4996 e_dev_err("Unable to allocate memory for queues\n");
4997 goto err_alloc_queues
;
5000 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5001 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
5002 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
5004 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5009 ixgbe_free_q_vectors(adapter
);
5010 err_alloc_q_vectors
:
5011 ixgbe_reset_interrupt_capability(adapter
);
5017 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5018 * @adapter: board private structure to clear interrupt scheme on
5020 * We go through and clear interrupt specific resources and reset the structure
5021 * to pre-load conditions
5023 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
5027 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5028 kfree(adapter
->tx_ring
[i
]);
5029 adapter
->tx_ring
[i
] = NULL
;
5031 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5032 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
5034 /* ixgbe_get_stats64() might access this ring, we must wait
5035 * a grace period before freeing it.
5037 kfree_rcu(ring
, rcu
);
5038 adapter
->rx_ring
[i
] = NULL
;
5041 adapter
->num_tx_queues
= 0;
5042 adapter
->num_rx_queues
= 0;
5044 ixgbe_free_q_vectors(adapter
);
5045 ixgbe_reset_interrupt_capability(adapter
);
5049 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5050 * @adapter: board private structure to initialize
5052 * ixgbe_sw_init initializes the Adapter private data structure.
5053 * Fields are initialized based on PCI device information and
5054 * OS network device settings (MTU size).
5056 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
5058 struct ixgbe_hw
*hw
= &adapter
->hw
;
5059 struct pci_dev
*pdev
= adapter
->pdev
;
5060 struct net_device
*dev
= adapter
->netdev
;
5062 #ifdef CONFIG_IXGBE_DCB
5064 struct tc_configuration
*tc
;
5066 int max_frame
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5068 /* PCI config space info */
5070 hw
->vendor_id
= pdev
->vendor
;
5071 hw
->device_id
= pdev
->device
;
5072 hw
->revision_id
= pdev
->revision
;
5073 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
5074 hw
->subsystem_device_id
= pdev
->subsystem_device
;
5076 /* Set capability flags */
5077 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
5078 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
5079 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
5080 switch (hw
->mac
.type
) {
5081 case ixgbe_mac_82598EB
:
5082 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
5083 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
5084 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
5086 case ixgbe_mac_82599EB
:
5087 case ixgbe_mac_X540
:
5088 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
5089 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
5090 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
5091 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
5092 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
5093 /* Flow Director hash filters enabled */
5094 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
5095 adapter
->atr_sample_rate
= 20;
5096 adapter
->ring_feature
[RING_F_FDIR
].indices
=
5097 IXGBE_MAX_FDIR_INDICES
;
5098 adapter
->fdir_pballoc
= IXGBE_FDIR_PBALLOC_64K
;
5100 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
5101 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
5102 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
5103 #ifdef CONFIG_IXGBE_DCB
5104 /* Default traffic class to use for FCoE */
5105 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
5107 #endif /* IXGBE_FCOE */
5113 /* n-tuple support exists, always init our spinlock */
5114 spin_lock_init(&adapter
->fdir_perfect_lock
);
5116 #ifdef CONFIG_IXGBE_DCB
5117 /* Configure DCB traffic classes */
5118 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
5119 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
5120 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
5121 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5122 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
5123 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5124 tc
->dcb_pfc
= pfc_disabled
;
5126 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
5127 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
5128 adapter
->dcb_cfg
.pfc_mode_enable
= false;
5129 adapter
->dcb_set_bitmap
= 0x00;
5130 adapter
->dcbx_cap
= DCB_CAP_DCBX_HOST
| DCB_CAP_DCBX_VER_CEE
;
5131 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
5136 /* default flow control settings */
5137 hw
->fc
.requested_mode
= ixgbe_fc_full
;
5138 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
5140 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
5142 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5143 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5144 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
5145 hw
->fc
.send_xon
= true;
5146 hw
->fc
.disable_fc_autoneg
= false;
5148 /* enable itr by default in dynamic mode */
5149 adapter
->rx_itr_setting
= 1;
5150 adapter
->rx_eitr_param
= 20000;
5151 adapter
->tx_itr_setting
= 1;
5152 adapter
->tx_eitr_param
= 10000;
5154 /* set defaults for eitr in MegaBytes */
5155 adapter
->eitr_low
= 10;
5156 adapter
->eitr_high
= 20;
5158 /* set default ring sizes */
5159 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
5160 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
5162 /* set default work limits */
5163 adapter
->tx_work_limit
= adapter
->tx_ring_count
;
5165 /* initialize eeprom parameters */
5166 if (ixgbe_init_eeprom_params_generic(hw
)) {
5167 e_dev_err("EEPROM initialization failed\n");
5171 /* enable rx csum by default */
5172 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
5174 /* get assigned NUMA node */
5175 adapter
->node
= dev_to_node(&pdev
->dev
);
5177 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5183 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5184 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5186 * Return 0 on success, negative on failure
5188 int ixgbe_setup_tx_resources(struct ixgbe_ring
*tx_ring
)
5190 struct device
*dev
= tx_ring
->dev
;
5193 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
5194 tx_ring
->tx_buffer_info
= vzalloc_node(size
, tx_ring
->numa_node
);
5195 if (!tx_ring
->tx_buffer_info
)
5196 tx_ring
->tx_buffer_info
= vzalloc(size
);
5197 if (!tx_ring
->tx_buffer_info
)
5200 /* round up to nearest 4K */
5201 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
5202 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
5204 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
5205 &tx_ring
->dma
, GFP_KERNEL
);
5209 tx_ring
->next_to_use
= 0;
5210 tx_ring
->next_to_clean
= 0;
5214 vfree(tx_ring
->tx_buffer_info
);
5215 tx_ring
->tx_buffer_info
= NULL
;
5216 dev_err(dev
, "Unable to allocate memory for the Tx descriptor ring\n");
5221 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5222 * @adapter: board private structure
5224 * If this function returns with an error, then it's possible one or
5225 * more of the rings is populated (while the rest are not). It is the
5226 * callers duty to clean those orphaned rings.
5228 * Return 0 on success, negative on failure
5230 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
5234 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5235 err
= ixgbe_setup_tx_resources(adapter
->tx_ring
[i
]);
5238 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
5246 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5247 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5249 * Returns 0 on success, negative on failure
5251 int ixgbe_setup_rx_resources(struct ixgbe_ring
*rx_ring
)
5253 struct device
*dev
= rx_ring
->dev
;
5256 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
5257 rx_ring
->rx_buffer_info
= vzalloc_node(size
, rx_ring
->numa_node
);
5258 if (!rx_ring
->rx_buffer_info
)
5259 rx_ring
->rx_buffer_info
= vzalloc(size
);
5260 if (!rx_ring
->rx_buffer_info
)
5263 /* Round up to nearest 4K */
5264 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
5265 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
5267 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
5268 &rx_ring
->dma
, GFP_KERNEL
);
5273 rx_ring
->next_to_clean
= 0;
5274 rx_ring
->next_to_use
= 0;
5278 vfree(rx_ring
->rx_buffer_info
);
5279 rx_ring
->rx_buffer_info
= NULL
;
5280 dev_err(dev
, "Unable to allocate memory for the Rx descriptor ring\n");
5285 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5286 * @adapter: board private structure
5288 * If this function returns with an error, then it's possible one or
5289 * more of the rings is populated (while the rest are not). It is the
5290 * callers duty to clean those orphaned rings.
5292 * Return 0 on success, negative on failure
5294 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
5298 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5299 err
= ixgbe_setup_rx_resources(adapter
->rx_ring
[i
]);
5302 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5310 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5311 * @tx_ring: Tx descriptor ring for a specific queue
5313 * Free all transmit software resources
5315 void ixgbe_free_tx_resources(struct ixgbe_ring
*tx_ring
)
5317 ixgbe_clean_tx_ring(tx_ring
);
5319 vfree(tx_ring
->tx_buffer_info
);
5320 tx_ring
->tx_buffer_info
= NULL
;
5322 /* if not set, then don't free */
5326 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
5327 tx_ring
->desc
, tx_ring
->dma
);
5329 tx_ring
->desc
= NULL
;
5333 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5334 * @adapter: board private structure
5336 * Free all transmit software resources
5338 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5342 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5343 if (adapter
->tx_ring
[i
]->desc
)
5344 ixgbe_free_tx_resources(adapter
->tx_ring
[i
]);
5348 * ixgbe_free_rx_resources - Free Rx Resources
5349 * @rx_ring: ring to clean the resources from
5351 * Free all receive software resources
5353 void ixgbe_free_rx_resources(struct ixgbe_ring
*rx_ring
)
5355 ixgbe_clean_rx_ring(rx_ring
);
5357 vfree(rx_ring
->rx_buffer_info
);
5358 rx_ring
->rx_buffer_info
= NULL
;
5360 /* if not set, then don't free */
5364 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
5365 rx_ring
->desc
, rx_ring
->dma
);
5367 rx_ring
->desc
= NULL
;
5371 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5372 * @adapter: board private structure
5374 * Free all receive software resources
5376 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5380 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5381 if (adapter
->rx_ring
[i
]->desc
)
5382 ixgbe_free_rx_resources(adapter
->rx_ring
[i
]);
5386 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5387 * @netdev: network interface device structure
5388 * @new_mtu: new value for maximum frame size
5390 * Returns 0 on success, negative on failure
5392 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5394 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5395 struct ixgbe_hw
*hw
= &adapter
->hw
;
5396 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5398 /* MTU < 68 is an error and causes problems on some kernels */
5399 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
&&
5400 hw
->mac
.type
!= ixgbe_mac_X540
) {
5401 if ((new_mtu
< 68) || (max_frame
> MAXIMUM_ETHERNET_VLAN_SIZE
))
5404 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5408 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5409 /* must set new MTU before calling down or up */
5410 netdev
->mtu
= new_mtu
;
5412 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5413 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5415 if (netif_running(netdev
))
5416 ixgbe_reinit_locked(adapter
);
5422 * ixgbe_open - Called when a network interface is made active
5423 * @netdev: network interface device structure
5425 * Returns 0 on success, negative value on failure
5427 * The open entry point is called when a network interface is made
5428 * active by the system (IFF_UP). At this point all resources needed
5429 * for transmit and receive operations are allocated, the interrupt
5430 * handler is registered with the OS, the watchdog timer is started,
5431 * and the stack is notified that the interface is ready.
5433 static int ixgbe_open(struct net_device
*netdev
)
5435 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5438 /* disallow open during test */
5439 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5442 netif_carrier_off(netdev
);
5444 /* allocate transmit descriptors */
5445 err
= ixgbe_setup_all_tx_resources(adapter
);
5449 /* allocate receive descriptors */
5450 err
= ixgbe_setup_all_rx_resources(adapter
);
5454 ixgbe_configure(adapter
);
5456 err
= ixgbe_request_irq(adapter
);
5460 err
= ixgbe_up_complete(adapter
);
5464 netif_tx_start_all_queues(netdev
);
5469 ixgbe_release_hw_control(adapter
);
5470 ixgbe_free_irq(adapter
);
5473 ixgbe_free_all_rx_resources(adapter
);
5475 ixgbe_free_all_tx_resources(adapter
);
5476 ixgbe_reset(adapter
);
5482 * ixgbe_close - Disables a network interface
5483 * @netdev: network interface device structure
5485 * Returns 0, this is not allowed to fail
5487 * The close entry point is called when an interface is de-activated
5488 * by the OS. The hardware is still under the drivers control, but
5489 * needs to be disabled. A global MAC reset is issued to stop the
5490 * hardware, and all transmit and receive resources are freed.
5492 static int ixgbe_close(struct net_device
*netdev
)
5494 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5496 ixgbe_down(adapter
);
5497 ixgbe_free_irq(adapter
);
5499 ixgbe_fdir_filter_exit(adapter
);
5501 ixgbe_free_all_tx_resources(adapter
);
5502 ixgbe_free_all_rx_resources(adapter
);
5504 ixgbe_release_hw_control(adapter
);
5510 static int ixgbe_resume(struct pci_dev
*pdev
)
5512 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5513 struct net_device
*netdev
= adapter
->netdev
;
5516 pci_set_power_state(pdev
, PCI_D0
);
5517 pci_restore_state(pdev
);
5519 * pci_restore_state clears dev->state_saved so call
5520 * pci_save_state to restore it.
5522 pci_save_state(pdev
);
5524 err
= pci_enable_device_mem(pdev
);
5526 e_dev_err("Cannot enable PCI device from suspend\n");
5529 pci_set_master(pdev
);
5531 pci_wake_from_d3(pdev
, false);
5533 err
= ixgbe_init_interrupt_scheme(adapter
);
5535 e_dev_err("Cannot initialize interrupts for device\n");
5539 ixgbe_reset(adapter
);
5541 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5543 if (netif_running(netdev
)) {
5544 err
= ixgbe_open(netdev
);
5549 netif_device_attach(netdev
);
5553 #endif /* CONFIG_PM */
5555 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5557 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5558 struct net_device
*netdev
= adapter
->netdev
;
5559 struct ixgbe_hw
*hw
= &adapter
->hw
;
5561 u32 wufc
= adapter
->wol
;
5566 netif_device_detach(netdev
);
5568 if (netif_running(netdev
)) {
5569 ixgbe_down(adapter
);
5570 ixgbe_free_irq(adapter
);
5571 ixgbe_free_all_tx_resources(adapter
);
5572 ixgbe_free_all_rx_resources(adapter
);
5575 ixgbe_clear_interrupt_scheme(adapter
);
5577 kfree(adapter
->ixgbe_ieee_pfc
);
5578 kfree(adapter
->ixgbe_ieee_ets
);
5582 retval
= pci_save_state(pdev
);
5588 ixgbe_set_rx_mode(netdev
);
5590 /* turn on all-multi mode if wake on multicast is enabled */
5591 if (wufc
& IXGBE_WUFC_MC
) {
5592 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5593 fctrl
|= IXGBE_FCTRL_MPE
;
5594 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5597 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5598 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5599 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5601 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5603 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5604 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5607 switch (hw
->mac
.type
) {
5608 case ixgbe_mac_82598EB
:
5609 pci_wake_from_d3(pdev
, false);
5611 case ixgbe_mac_82599EB
:
5612 case ixgbe_mac_X540
:
5613 pci_wake_from_d3(pdev
, !!wufc
);
5619 *enable_wake
= !!wufc
;
5621 ixgbe_release_hw_control(adapter
);
5623 pci_disable_device(pdev
);
5629 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5634 retval
= __ixgbe_shutdown(pdev
, &wake
);
5639 pci_prepare_to_sleep(pdev
);
5641 pci_wake_from_d3(pdev
, false);
5642 pci_set_power_state(pdev
, PCI_D3hot
);
5647 #endif /* CONFIG_PM */
5649 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5653 __ixgbe_shutdown(pdev
, &wake
);
5655 if (system_state
== SYSTEM_POWER_OFF
) {
5656 pci_wake_from_d3(pdev
, wake
);
5657 pci_set_power_state(pdev
, PCI_D3hot
);
5662 * ixgbe_update_stats - Update the board statistics counters.
5663 * @adapter: board private structure
5665 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5667 struct net_device
*netdev
= adapter
->netdev
;
5668 struct ixgbe_hw
*hw
= &adapter
->hw
;
5669 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
5671 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5672 u64 non_eop_descs
= 0, restart_queue
= 0, tx_busy
= 0;
5673 u64 alloc_rx_page_failed
= 0, alloc_rx_buff_failed
= 0;
5674 u64 bytes
= 0, packets
= 0;
5676 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5677 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5680 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5683 for (i
= 0; i
< 16; i
++)
5684 adapter
->hw_rx_no_dma_resources
+=
5685 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5686 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5687 rsc_count
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_count
;
5688 rsc_flush
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_flush
;
5690 adapter
->rsc_total_count
= rsc_count
;
5691 adapter
->rsc_total_flush
= rsc_flush
;
5694 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5695 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[i
];
5696 non_eop_descs
+= rx_ring
->rx_stats
.non_eop_descs
;
5697 alloc_rx_page_failed
+= rx_ring
->rx_stats
.alloc_rx_page_failed
;
5698 alloc_rx_buff_failed
+= rx_ring
->rx_stats
.alloc_rx_buff_failed
;
5699 bytes
+= rx_ring
->stats
.bytes
;
5700 packets
+= rx_ring
->stats
.packets
;
5702 adapter
->non_eop_descs
= non_eop_descs
;
5703 adapter
->alloc_rx_page_failed
= alloc_rx_page_failed
;
5704 adapter
->alloc_rx_buff_failed
= alloc_rx_buff_failed
;
5705 netdev
->stats
.rx_bytes
= bytes
;
5706 netdev
->stats
.rx_packets
= packets
;
5710 /* gather some stats to the adapter struct that are per queue */
5711 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5712 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
5713 restart_queue
+= tx_ring
->tx_stats
.restart_queue
;
5714 tx_busy
+= tx_ring
->tx_stats
.tx_busy
;
5715 bytes
+= tx_ring
->stats
.bytes
;
5716 packets
+= tx_ring
->stats
.packets
;
5718 adapter
->restart_queue
= restart_queue
;
5719 adapter
->tx_busy
= tx_busy
;
5720 netdev
->stats
.tx_bytes
= bytes
;
5721 netdev
->stats
.tx_packets
= packets
;
5723 hwstats
->crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5724 for (i
= 0; i
< 8; i
++) {
5725 /* for packet buffers not used, the register should read 0 */
5726 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5728 hwstats
->mpc
[i
] += mpc
;
5729 total_mpc
+= hwstats
->mpc
[i
];
5730 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5731 hwstats
->rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5732 hwstats
->qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5733 hwstats
->qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5734 hwstats
->qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5735 hwstats
->qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5736 switch (hw
->mac
.type
) {
5737 case ixgbe_mac_82598EB
:
5738 hwstats
->pxonrxc
[i
] +=
5739 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
5741 case ixgbe_mac_82599EB
:
5742 case ixgbe_mac_X540
:
5743 hwstats
->pxonrxc
[i
] +=
5744 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
5749 hwstats
->pxontxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
5750 hwstats
->pxofftxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
5752 hwstats
->gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5753 /* work around hardware counting issue */
5754 hwstats
->gprc
-= missed_rx
;
5756 ixgbe_update_xoff_received(adapter
);
5758 /* 82598 hardware only has a 32 bit counter in the high register */
5759 switch (hw
->mac
.type
) {
5760 case ixgbe_mac_82598EB
:
5761 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5762 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5763 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5764 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5766 case ixgbe_mac_X540
:
5767 /* OS2BMC stats are X540 only*/
5768 hwstats
->o2bgptc
+= IXGBE_READ_REG(hw
, IXGBE_O2BGPTC
);
5769 hwstats
->o2bspc
+= IXGBE_READ_REG(hw
, IXGBE_O2BSPC
);
5770 hwstats
->b2ospc
+= IXGBE_READ_REG(hw
, IXGBE_B2OSPC
);
5771 hwstats
->b2ogprc
+= IXGBE_READ_REG(hw
, IXGBE_B2OGPRC
);
5772 case ixgbe_mac_82599EB
:
5773 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5774 IXGBE_READ_REG(hw
, IXGBE_GORCH
); /* to clear */
5775 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5776 IXGBE_READ_REG(hw
, IXGBE_GOTCH
); /* to clear */
5777 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5778 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5779 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5780 hwstats
->fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5781 hwstats
->fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5783 hwstats
->fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5784 hwstats
->fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5785 hwstats
->fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5786 hwstats
->fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5787 hwstats
->fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5788 hwstats
->fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5789 #endif /* IXGBE_FCOE */
5794 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5795 hwstats
->bprc
+= bprc
;
5796 hwstats
->mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5797 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5798 hwstats
->mprc
-= bprc
;
5799 hwstats
->roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5800 hwstats
->prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5801 hwstats
->prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5802 hwstats
->prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5803 hwstats
->prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5804 hwstats
->prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5805 hwstats
->prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5806 hwstats
->rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5807 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5808 hwstats
->lxontxc
+= lxon
;
5809 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5810 hwstats
->lxofftxc
+= lxoff
;
5811 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5812 hwstats
->gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5813 hwstats
->mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5815 * 82598 errata - tx of flow control packets is included in tx counters
5817 xon_off_tot
= lxon
+ lxoff
;
5818 hwstats
->gptc
-= xon_off_tot
;
5819 hwstats
->mptc
-= xon_off_tot
;
5820 hwstats
->gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5821 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5822 hwstats
->rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5823 hwstats
->rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5824 hwstats
->tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5825 hwstats
->ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5826 hwstats
->ptc64
-= xon_off_tot
;
5827 hwstats
->ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5828 hwstats
->ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5829 hwstats
->ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5830 hwstats
->ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5831 hwstats
->ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5832 hwstats
->bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5834 /* Fill out the OS statistics structure */
5835 netdev
->stats
.multicast
= hwstats
->mprc
;
5838 netdev
->stats
.rx_errors
= hwstats
->crcerrs
+ hwstats
->rlec
;
5839 netdev
->stats
.rx_dropped
= 0;
5840 netdev
->stats
.rx_length_errors
= hwstats
->rlec
;
5841 netdev
->stats
.rx_crc_errors
= hwstats
->crcerrs
;
5842 netdev
->stats
.rx_missed_errors
= total_mpc
;
5846 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5847 * @adapter - pointer to the device adapter structure
5849 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter
*adapter
)
5851 struct ixgbe_hw
*hw
= &adapter
->hw
;
5854 if (!(adapter
->flags2
& IXGBE_FLAG2_FDIR_REQUIRES_REINIT
))
5857 adapter
->flags2
&= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT
;
5859 /* if interface is down do nothing */
5860 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5863 /* do nothing if we are not using signature filters */
5864 if (!(adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
))
5867 adapter
->fdir_overflow
++;
5869 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5870 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5871 set_bit(__IXGBE_TX_FDIR_INIT_DONE
,
5872 &(adapter
->tx_ring
[i
]->state
));
5873 /* re-enable flow director interrupts */
5874 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_FLOW_DIR
);
5876 e_err(probe
, "failed to finish FDIR re-initialization, "
5877 "ignored adding FDIR ATR filters\n");
5882 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5883 * @adapter - pointer to the device adapter structure
5885 * This function serves two purposes. First it strobes the interrupt lines
5886 * in order to make certain interrupts are occuring. Secondly it sets the
5887 * bits needed to check for TX hangs. As a result we should immediately
5888 * determine if a hang has occured.
5890 static void ixgbe_check_hang_subtask(struct ixgbe_adapter
*adapter
)
5892 struct ixgbe_hw
*hw
= &adapter
->hw
;
5896 /* If we're down or resetting, just bail */
5897 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5898 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5901 /* Force detection of hung controller */
5902 if (netif_carrier_ok(adapter
->netdev
)) {
5903 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5904 set_check_for_tx_hang(adapter
->tx_ring
[i
]);
5907 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5909 * for legacy and MSI interrupts don't set any bits
5910 * that are enabled for EIAM, because this operation
5911 * would set *both* EIMS and EICS for any bit in EIAM
5913 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5914 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5916 /* get one bit for every active tx/rx interrupt vector */
5917 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5918 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5919 if (qv
->rx
.count
|| qv
->tx
.count
)
5920 eics
|= ((u64
)1 << i
);
5924 /* Cause software interrupt to ensure rings are cleaned */
5925 ixgbe_irq_rearm_queues(adapter
, eics
);
5930 * ixgbe_watchdog_update_link - update the link status
5931 * @adapter - pointer to the device adapter structure
5932 * @link_speed - pointer to a u32 to store the link_speed
5934 static void ixgbe_watchdog_update_link(struct ixgbe_adapter
*adapter
)
5936 struct ixgbe_hw
*hw
= &adapter
->hw
;
5937 u32 link_speed
= adapter
->link_speed
;
5938 bool link_up
= adapter
->link_up
;
5941 if (!(adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
))
5944 if (hw
->mac
.ops
.check_link
) {
5945 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5947 /* always assume link is up, if no check link function */
5948 link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
5952 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5953 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5954 hw
->mac
.ops
.fc_enable(hw
, i
);
5956 hw
->mac
.ops
.fc_enable(hw
, 0);
5961 time_after(jiffies
, (adapter
->link_check_timeout
+
5962 IXGBE_TRY_LINK_TIMEOUT
))) {
5963 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5964 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5965 IXGBE_WRITE_FLUSH(hw
);
5968 adapter
->link_up
= link_up
;
5969 adapter
->link_speed
= link_speed
;
5973 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5974 * print link up message
5975 * @adapter - pointer to the device adapter structure
5977 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter
*adapter
)
5979 struct net_device
*netdev
= adapter
->netdev
;
5980 struct ixgbe_hw
*hw
= &adapter
->hw
;
5981 u32 link_speed
= adapter
->link_speed
;
5982 bool flow_rx
, flow_tx
;
5984 /* only continue if link was previously down */
5985 if (netif_carrier_ok(netdev
))
5988 adapter
->flags2
&= ~IXGBE_FLAG2_SEARCH_FOR_SFP
;
5990 switch (hw
->mac
.type
) {
5991 case ixgbe_mac_82598EB
: {
5992 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5993 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5994 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5995 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5998 case ixgbe_mac_X540
:
5999 case ixgbe_mac_82599EB
: {
6000 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
6001 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
6002 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
6003 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
6011 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
6012 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
6014 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
6016 (link_speed
== IXGBE_LINK_SPEED_100_FULL
?
6019 ((flow_rx
&& flow_tx
) ? "RX/TX" :
6021 (flow_tx
? "TX" : "None"))));
6023 netif_carrier_on(netdev
);
6024 ixgbe_check_vf_rate_limit(adapter
);
6028 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6029 * print link down message
6030 * @adapter - pointer to the adapter structure
6032 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter
* adapter
)
6034 struct net_device
*netdev
= adapter
->netdev
;
6035 struct ixgbe_hw
*hw
= &adapter
->hw
;
6037 adapter
->link_up
= false;
6038 adapter
->link_speed
= 0;
6040 /* only continue if link was up previously */
6041 if (!netif_carrier_ok(netdev
))
6044 /* poll for SFP+ cable when link is down */
6045 if (ixgbe_is_sfp(hw
) && hw
->mac
.type
== ixgbe_mac_82598EB
)
6046 adapter
->flags2
|= IXGBE_FLAG2_SEARCH_FOR_SFP
;
6048 e_info(drv
, "NIC Link is Down\n");
6049 netif_carrier_off(netdev
);
6053 * ixgbe_watchdog_flush_tx - flush queues on link down
6054 * @adapter - pointer to the device adapter structure
6056 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter
*adapter
)
6059 int some_tx_pending
= 0;
6061 if (!netif_carrier_ok(adapter
->netdev
)) {
6062 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
6063 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
6064 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
6065 some_tx_pending
= 1;
6070 if (some_tx_pending
) {
6071 /* We've lost link, so the controller stops DMA,
6072 * but we've got queued Tx work that's never going
6073 * to get done, so reset controller to flush Tx.
6074 * (Do the reset outside of interrupt context).
6076 adapter
->flags2
|= IXGBE_FLAG2_RESET_REQUESTED
;
6081 static void ixgbe_spoof_check(struct ixgbe_adapter
*adapter
)
6085 /* Do not perform spoof check for 82598 */
6086 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
6089 ssvpc
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SSVPC
);
6092 * ssvpc register is cleared on read, if zero then no
6093 * spoofed packets in the last interval.
6098 e_warn(drv
, "%d Spoofed packets detected\n", ssvpc
);
6102 * ixgbe_watchdog_subtask - check and bring link up
6103 * @adapter - pointer to the device adapter structure
6105 static void ixgbe_watchdog_subtask(struct ixgbe_adapter
*adapter
)
6107 /* if interface is down do nothing */
6108 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6111 ixgbe_watchdog_update_link(adapter
);
6113 if (adapter
->link_up
)
6114 ixgbe_watchdog_link_is_up(adapter
);
6116 ixgbe_watchdog_link_is_down(adapter
);
6118 ixgbe_spoof_check(adapter
);
6119 ixgbe_update_stats(adapter
);
6121 ixgbe_watchdog_flush_tx(adapter
);
6125 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6126 * @adapter - the ixgbe adapter structure
6128 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter
*adapter
)
6130 struct ixgbe_hw
*hw
= &adapter
->hw
;
6133 /* not searching for SFP so there is nothing to do here */
6134 if (!(adapter
->flags2
& IXGBE_FLAG2_SEARCH_FOR_SFP
) &&
6135 !(adapter
->flags2
& IXGBE_FLAG2_SFP_NEEDS_RESET
))
6138 /* someone else is in init, wait until next service event */
6139 if (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
6142 err
= hw
->phy
.ops
.identify_sfp(hw
);
6143 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
6146 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
) {
6147 /* If no cable is present, then we need to reset
6148 * the next time we find a good cable. */
6149 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
6156 /* exit if reset not needed */
6157 if (!(adapter
->flags2
& IXGBE_FLAG2_SFP_NEEDS_RESET
))
6160 adapter
->flags2
&= ~IXGBE_FLAG2_SFP_NEEDS_RESET
;
6163 * A module may be identified correctly, but the EEPROM may not have
6164 * support for that module. setup_sfp() will fail in that case, so
6165 * we should not allow that module to load.
6167 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
6168 err
= hw
->phy
.ops
.reset(hw
);
6170 err
= hw
->mac
.ops
.setup_sfp(hw
);
6172 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
6175 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_CONFIG
;
6176 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
6179 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
6181 if ((err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) &&
6182 (adapter
->netdev
->reg_state
== NETREG_REGISTERED
)) {
6183 e_dev_err("failed to initialize because an unsupported "
6184 "SFP+ module type was detected.\n");
6185 e_dev_err("Reload the driver after installing a "
6186 "supported module.\n");
6187 unregister_netdev(adapter
->netdev
);
6192 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6193 * @adapter - the ixgbe adapter structure
6195 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter
*adapter
)
6197 struct ixgbe_hw
*hw
= &adapter
->hw
;
6201 if (!(adapter
->flags
& IXGBE_FLAG_NEED_LINK_CONFIG
))
6204 /* someone else is in init, wait until next service event */
6205 if (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
6208 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_CONFIG
;
6210 autoneg
= hw
->phy
.autoneg_advertised
;
6211 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
6212 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
6213 hw
->mac
.autotry_restart
= false;
6214 if (hw
->mac
.ops
.setup_link
)
6215 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
6217 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
6218 adapter
->link_check_timeout
= jiffies
;
6219 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
6223 * ixgbe_service_timer - Timer Call-back
6224 * @data: pointer to adapter cast into an unsigned long
6226 static void ixgbe_service_timer(unsigned long data
)
6228 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
6229 unsigned long next_event_offset
;
6231 /* poll faster when waiting for link */
6232 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
)
6233 next_event_offset
= HZ
/ 10;
6235 next_event_offset
= HZ
* 2;
6237 /* Reset the timer */
6238 mod_timer(&adapter
->service_timer
, next_event_offset
+ jiffies
);
6240 ixgbe_service_event_schedule(adapter
);
6243 static void ixgbe_reset_subtask(struct ixgbe_adapter
*adapter
)
6245 if (!(adapter
->flags2
& IXGBE_FLAG2_RESET_REQUESTED
))
6248 adapter
->flags2
&= ~IXGBE_FLAG2_RESET_REQUESTED
;
6250 /* If we're already down or resetting, just bail */
6251 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
6252 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
6255 ixgbe_dump(adapter
);
6256 netdev_err(adapter
->netdev
, "Reset adapter\n");
6257 adapter
->tx_timeout_count
++;
6259 ixgbe_reinit_locked(adapter
);
6263 * ixgbe_service_task - manages and runs subtasks
6264 * @work: pointer to work_struct containing our data
6266 static void ixgbe_service_task(struct work_struct
*work
)
6268 struct ixgbe_adapter
*adapter
= container_of(work
,
6269 struct ixgbe_adapter
,
6272 ixgbe_reset_subtask(adapter
);
6273 ixgbe_sfp_detection_subtask(adapter
);
6274 ixgbe_sfp_link_config_subtask(adapter
);
6275 ixgbe_check_overtemp_subtask(adapter
);
6276 ixgbe_watchdog_subtask(adapter
);
6277 ixgbe_fdir_reinit_subtask(adapter
);
6278 ixgbe_check_hang_subtask(adapter
);
6280 ixgbe_service_event_complete(adapter
);
6283 void ixgbe_tx_ctxtdesc(struct ixgbe_ring
*tx_ring
, u32 vlan_macip_lens
,
6284 u32 fcoe_sof_eof
, u32 type_tucmd
, u32 mss_l4len_idx
)
6286 struct ixgbe_adv_tx_context_desc
*context_desc
;
6287 u16 i
= tx_ring
->next_to_use
;
6289 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6292 tx_ring
->next_to_use
= (i
< tx_ring
->count
) ? i
: 0;
6294 /* set bits to identify this as an advanced context descriptor */
6295 type_tucmd
|= IXGBE_TXD_CMD_DEXT
| IXGBE_ADVTXD_DTYP_CTXT
;
6297 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6298 context_desc
->seqnum_seed
= cpu_to_le32(fcoe_sof_eof
);
6299 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd
);
6300 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
6303 static int ixgbe_tso(struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
6304 u32 tx_flags
, __be16 protocol
, u8
*hdr_len
)
6307 u32 vlan_macip_lens
, type_tucmd
;
6308 u32 mss_l4len_idx
, l4len
;
6310 if (!skb_is_gso(skb
))
6313 if (skb_header_cloned(skb
)) {
6314 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
6319 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6320 type_tucmd
= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6322 if (protocol
== __constant_htons(ETH_P_IP
)) {
6323 struct iphdr
*iph
= ip_hdr(skb
);
6326 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
6330 type_tucmd
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6331 } else if (skb_is_gso_v6(skb
)) {
6332 ipv6_hdr(skb
)->payload_len
= 0;
6333 tcp_hdr(skb
)->check
=
6334 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
6335 &ipv6_hdr(skb
)->daddr
,
6339 l4len
= tcp_hdrlen(skb
);
6340 *hdr_len
= skb_transport_offset(skb
) + l4len
;
6342 /* mss_l4len_id: use 1 as index for TSO */
6343 mss_l4len_idx
= l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
;
6344 mss_l4len_idx
|= skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
;
6345 mss_l4len_idx
|= 1 << IXGBE_ADVTXD_IDX_SHIFT
;
6347 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6348 vlan_macip_lens
= skb_network_header_len(skb
);
6349 vlan_macip_lens
|= skb_network_offset(skb
) << IXGBE_ADVTXD_MACLEN_SHIFT
;
6350 vlan_macip_lens
|= tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
;
6352 ixgbe_tx_ctxtdesc(tx_ring
, vlan_macip_lens
, 0, type_tucmd
,
6358 static bool ixgbe_tx_csum(struct ixgbe_ring
*tx_ring
,
6359 struct sk_buff
*skb
, u32 tx_flags
,
6362 u32 vlan_macip_lens
= 0;
6363 u32 mss_l4len_idx
= 0;
6366 if (skb
->ip_summed
!= CHECKSUM_PARTIAL
) {
6367 if (!(tx_flags
& IXGBE_TX_FLAGS_VLAN
))
6372 case __constant_htons(ETH_P_IP
):
6373 vlan_macip_lens
|= skb_network_header_len(skb
);
6374 type_tucmd
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6375 l4_hdr
= ip_hdr(skb
)->protocol
;
6377 case __constant_htons(ETH_P_IPV6
):
6378 vlan_macip_lens
|= skb_network_header_len(skb
);
6379 l4_hdr
= ipv6_hdr(skb
)->nexthdr
;
6382 if (unlikely(net_ratelimit())) {
6383 dev_warn(tx_ring
->dev
,
6384 "partial checksum but proto=%x!\n",
6392 type_tucmd
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6393 mss_l4len_idx
= tcp_hdrlen(skb
) <<
6394 IXGBE_ADVTXD_L4LEN_SHIFT
;
6397 type_tucmd
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6398 mss_l4len_idx
= sizeof(struct sctphdr
) <<
6399 IXGBE_ADVTXD_L4LEN_SHIFT
;
6402 mss_l4len_idx
= sizeof(struct udphdr
) <<
6403 IXGBE_ADVTXD_L4LEN_SHIFT
;
6406 if (unlikely(net_ratelimit())) {
6407 dev_warn(tx_ring
->dev
,
6408 "partial checksum but l4 proto=%x!\n",
6415 vlan_macip_lens
|= skb_network_offset(skb
) << IXGBE_ADVTXD_MACLEN_SHIFT
;
6416 vlan_macip_lens
|= tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
;
6418 ixgbe_tx_ctxtdesc(tx_ring
, vlan_macip_lens
, 0,
6419 type_tucmd
, mss_l4len_idx
);
6421 return (skb
->ip_summed
== CHECKSUM_PARTIAL
);
6424 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
6425 struct ixgbe_ring
*tx_ring
,
6426 struct sk_buff
*skb
, u32 tx_flags
,
6427 unsigned int first
, const u8 hdr_len
)
6429 struct device
*dev
= tx_ring
->dev
;
6430 struct ixgbe_tx_buffer
*tx_buffer_info
;
6432 unsigned int total
= skb
->len
;
6433 unsigned int offset
= 0, size
, count
= 0;
6434 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
6436 unsigned int bytecount
= skb
->len
;
6440 i
= tx_ring
->next_to_use
;
6442 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
6443 /* excluding fcoe_crc_eof for FCoE */
6444 total
-= sizeof(struct fcoe_crc_eof
);
6446 len
= min(skb_headlen(skb
), total
);
6448 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6449 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6451 tx_buffer_info
->length
= size
;
6452 tx_buffer_info
->mapped_as_page
= false;
6453 tx_buffer_info
->dma
= dma_map_single(dev
,
6455 size
, DMA_TO_DEVICE
);
6456 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6458 tx_buffer_info
->time_stamp
= jiffies
;
6459 tx_buffer_info
->next_to_watch
= i
;
6468 if (i
== tx_ring
->count
)
6473 for (f
= 0; f
< nr_frags
; f
++) {
6474 struct skb_frag_struct
*frag
;
6476 frag
= &skb_shinfo(skb
)->frags
[f
];
6477 len
= min((unsigned int)frag
->size
, total
);
6478 offset
= frag
->page_offset
;
6482 if (i
== tx_ring
->count
)
6485 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6486 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6488 tx_buffer_info
->length
= size
;
6489 tx_buffer_info
->dma
= dma_map_page(dev
,
6493 tx_buffer_info
->mapped_as_page
= true;
6494 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6496 tx_buffer_info
->time_stamp
= jiffies
;
6497 tx_buffer_info
->next_to_watch
= i
;
6508 if (tx_flags
& IXGBE_TX_FLAGS_TSO
)
6509 gso_segs
= skb_shinfo(skb
)->gso_segs
;
6511 /* adjust for FCoE Sequence Offload */
6512 else if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6513 gso_segs
= DIV_ROUND_UP(skb
->len
- hdr_len
,
6514 skb_shinfo(skb
)->gso_size
);
6515 #endif /* IXGBE_FCOE */
6516 bytecount
+= (gso_segs
- 1) * hdr_len
;
6518 /* multiply data chunks by size of headers */
6519 tx_ring
->tx_buffer_info
[i
].bytecount
= bytecount
;
6520 tx_ring
->tx_buffer_info
[i
].gso_segs
= gso_segs
;
6521 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
6522 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
6527 e_dev_err("TX DMA map failed\n");
6529 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6530 tx_buffer_info
->dma
= 0;
6531 tx_buffer_info
->time_stamp
= 0;
6532 tx_buffer_info
->next_to_watch
= 0;
6536 /* clear timestamp and dma mappings for remaining portion of packet */
6539 i
+= tx_ring
->count
;
6541 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6542 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
6548 static void ixgbe_tx_queue(struct ixgbe_ring
*tx_ring
,
6549 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6551 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6552 struct ixgbe_tx_buffer
*tx_buffer_info
;
6553 u32 olinfo_status
= 0, cmd_type_len
= 0;
6555 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6557 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6559 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6561 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6562 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6564 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6565 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6567 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6568 IXGBE_ADVTXD_POPTS_SHIFT
;
6570 /* use index 1 context for tso */
6571 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6572 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6573 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6574 IXGBE_ADVTXD_POPTS_SHIFT
;
6576 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6577 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6578 IXGBE_ADVTXD_POPTS_SHIFT
;
6580 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6581 olinfo_status
|= IXGBE_ADVTXD_CC
;
6582 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6583 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6584 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6587 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6589 i
= tx_ring
->next_to_use
;
6591 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6592 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
6593 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6594 tx_desc
->read
.cmd_type_len
=
6595 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6596 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6598 if (i
== tx_ring
->count
)
6602 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6605 * Force memory writes to complete before letting h/w
6606 * know there are new descriptors to fetch. (Only
6607 * applicable for weak-ordered memory model archs,
6612 tx_ring
->next_to_use
= i
;
6613 writel(i
, tx_ring
->tail
);
6616 static void ixgbe_atr(struct ixgbe_ring
*ring
, struct sk_buff
*skb
,
6617 u32 tx_flags
, __be16 protocol
)
6619 struct ixgbe_q_vector
*q_vector
= ring
->q_vector
;
6620 union ixgbe_atr_hash_dword input
= { .dword
= 0 };
6621 union ixgbe_atr_hash_dword common
= { .dword
= 0 };
6623 unsigned char *network
;
6625 struct ipv6hdr
*ipv6
;
6630 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6634 /* do nothing if sampling is disabled */
6635 if (!ring
->atr_sample_rate
)
6640 /* snag network header to get L4 type and address */
6641 hdr
.network
= skb_network_header(skb
);
6643 /* Currently only IPv4/IPv6 with TCP is supported */
6644 if ((protocol
!= __constant_htons(ETH_P_IPV6
) ||
6645 hdr
.ipv6
->nexthdr
!= IPPROTO_TCP
) &&
6646 (protocol
!= __constant_htons(ETH_P_IP
) ||
6647 hdr
.ipv4
->protocol
!= IPPROTO_TCP
))
6652 /* skip this packet since the socket is closing */
6656 /* sample on all syn packets or once every atr sample count */
6657 if (!th
->syn
&& (ring
->atr_count
< ring
->atr_sample_rate
))
6660 /* reset sample count */
6661 ring
->atr_count
= 0;
6663 vlan_id
= htons(tx_flags
>> IXGBE_TX_FLAGS_VLAN_SHIFT
);
6666 * src and dst are inverted, think how the receiver sees them
6668 * The input is broken into two sections, a non-compressed section
6669 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6670 * is XORed together and stored in the compressed dword.
6672 input
.formatted
.vlan_id
= vlan_id
;
6675 * since src port and flex bytes occupy the same word XOR them together
6676 * and write the value to source port portion of compressed dword
6679 common
.port
.src
^= th
->dest
^ __constant_htons(ETH_P_8021Q
);
6681 common
.port
.src
^= th
->dest
^ protocol
;
6682 common
.port
.dst
^= th
->source
;
6684 if (protocol
== __constant_htons(ETH_P_IP
)) {
6685 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV4
;
6686 common
.ip
^= hdr
.ipv4
->saddr
^ hdr
.ipv4
->daddr
;
6688 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV6
;
6689 common
.ip
^= hdr
.ipv6
->saddr
.s6_addr32
[0] ^
6690 hdr
.ipv6
->saddr
.s6_addr32
[1] ^
6691 hdr
.ipv6
->saddr
.s6_addr32
[2] ^
6692 hdr
.ipv6
->saddr
.s6_addr32
[3] ^
6693 hdr
.ipv6
->daddr
.s6_addr32
[0] ^
6694 hdr
.ipv6
->daddr
.s6_addr32
[1] ^
6695 hdr
.ipv6
->daddr
.s6_addr32
[2] ^
6696 hdr
.ipv6
->daddr
.s6_addr32
[3];
6699 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6700 ixgbe_fdir_add_signature_filter_82599(&q_vector
->adapter
->hw
,
6701 input
, common
, ring
->queue_index
);
6704 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, u16 size
)
6706 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6707 /* Herbert's original patch had:
6708 * smp_mb__after_netif_stop_queue();
6709 * but since that doesn't exist yet, just open code it. */
6712 /* We need to check again in a case another CPU has just
6713 * made room available. */
6714 if (likely(ixgbe_desc_unused(tx_ring
) < size
))
6717 /* A reprieve! - use start_queue because it doesn't call schedule */
6718 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6719 ++tx_ring
->tx_stats
.restart_queue
;
6723 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, u16 size
)
6725 if (likely(ixgbe_desc_unused(tx_ring
) >= size
))
6727 return __ixgbe_maybe_stop_tx(tx_ring
, size
);
6730 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6732 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6733 int txq
= skb_rx_queue_recorded(skb
) ? skb_get_rx_queue(skb
) :
6736 __be16 protocol
= vlan_get_protocol(skb
);
6738 if (((protocol
== htons(ETH_P_FCOE
)) ||
6739 (protocol
== htons(ETH_P_FIP
))) &&
6740 (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)) {
6741 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6742 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6747 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6748 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6749 txq
-= dev
->real_num_tx_queues
;
6753 return skb_tx_hash(dev
, skb
);
6756 netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*skb
,
6757 struct ixgbe_adapter
*adapter
,
6758 struct ixgbe_ring
*tx_ring
)
6762 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6766 u16 count
= TXD_USE_COUNT(skb_headlen(skb
));
6771 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6772 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6773 * + 2 desc gap to keep tail from touching head,
6774 * + 1 desc for context descriptor,
6775 * otherwise try next time
6777 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6778 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6779 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6781 count
+= skb_shinfo(skb
)->nr_frags
;
6783 if (ixgbe_maybe_stop_tx(tx_ring
, count
+ 3)) {
6784 tx_ring
->tx_stats
.tx_busy
++;
6785 return NETDEV_TX_BUSY
;
6788 protocol
= vlan_get_protocol(skb
);
6790 if (vlan_tx_tag_present(skb
)) {
6791 tx_flags
|= vlan_tx_tag_get(skb
);
6792 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6793 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6794 tx_flags
|= tx_ring
->dcb_tc
<< 13;
6796 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6797 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6798 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6799 skb
->priority
!= TC_PRIO_CONTROL
) {
6800 tx_flags
|= tx_ring
->dcb_tc
<< 13;
6801 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6802 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6806 /* for FCoE with DCB, we force the priority to what
6807 * was specified by the switch */
6808 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
&&
6809 (protocol
== htons(ETH_P_FCOE
)))
6810 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6813 /* record the location of the first descriptor for this packet */
6814 first
= tx_ring
->next_to_use
;
6816 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6818 /* setup tx offload for FCoE */
6819 tso
= ixgbe_fso(tx_ring
, skb
, tx_flags
, &hdr_len
);
6823 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6824 #endif /* IXGBE_FCOE */
6826 if (protocol
== htons(ETH_P_IP
))
6827 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6828 tso
= ixgbe_tso(tx_ring
, skb
, tx_flags
, protocol
, &hdr_len
);
6832 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6833 else if (ixgbe_tx_csum(tx_ring
, skb
, tx_flags
, protocol
))
6834 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6837 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
, hdr_len
);
6839 /* add the ATR filter if ATR is on */
6840 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE
, &tx_ring
->state
))
6841 ixgbe_atr(tx_ring
, skb
, tx_flags
, protocol
);
6842 ixgbe_tx_queue(tx_ring
, tx_flags
, count
, skb
->len
, hdr_len
);
6843 ixgbe_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
6846 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6847 tx_ring
->next_to_use
= first
;
6851 return NETDEV_TX_OK
;
6854 dev_kfree_skb_any(skb
);
6855 return NETDEV_TX_OK
;
6858 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
6860 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6861 struct ixgbe_ring
*tx_ring
;
6863 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6864 return ixgbe_xmit_frame_ring(skb
, adapter
, tx_ring
);
6868 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6869 * @netdev: network interface device structure
6870 * @p: pointer to an address structure
6872 * Returns 0 on success, negative on failure
6874 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6876 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6877 struct ixgbe_hw
*hw
= &adapter
->hw
;
6878 struct sockaddr
*addr
= p
;
6880 if (!is_valid_ether_addr(addr
->sa_data
))
6881 return -EADDRNOTAVAIL
;
6883 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6884 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6886 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6893 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6895 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6896 struct ixgbe_hw
*hw
= &adapter
->hw
;
6900 if (prtad
!= hw
->phy
.mdio
.prtad
)
6902 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6908 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6909 u16 addr
, u16 value
)
6911 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6912 struct ixgbe_hw
*hw
= &adapter
->hw
;
6914 if (prtad
!= hw
->phy
.mdio
.prtad
)
6916 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6919 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6921 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6923 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6927 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6929 * @netdev: network interface device structure
6931 * Returns non-zero on failure
6933 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6936 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6937 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6939 if (is_valid_ether_addr(mac
->san_addr
)) {
6941 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6948 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6950 * @netdev: network interface device structure
6952 * Returns non-zero on failure
6954 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6957 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6958 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6960 if (is_valid_ether_addr(mac
->san_addr
)) {
6962 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6968 #ifdef CONFIG_NET_POLL_CONTROLLER
6970 * Polling 'interrupt' - used by things like netconsole to send skbs
6971 * without having to re-enable interrupts. It's not called while
6972 * the interrupt routine is executing.
6974 static void ixgbe_netpoll(struct net_device
*netdev
)
6976 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6979 /* if interface is down do nothing */
6980 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6983 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
6984 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
6985 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
6986 for (i
= 0; i
< num_q_vectors
; i
++) {
6987 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
6988 ixgbe_msix_clean_many(0, q_vector
);
6991 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
6993 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
6997 static struct rtnl_link_stats64
*ixgbe_get_stats64(struct net_device
*netdev
,
6998 struct rtnl_link_stats64
*stats
)
7000 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7004 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
7005 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->rx_ring
[i
]);
7011 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
7012 packets
= ring
->stats
.packets
;
7013 bytes
= ring
->stats
.bytes
;
7014 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
7015 stats
->rx_packets
+= packets
;
7016 stats
->rx_bytes
+= bytes
;
7020 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
7021 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->tx_ring
[i
]);
7027 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
7028 packets
= ring
->stats
.packets
;
7029 bytes
= ring
->stats
.bytes
;
7030 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
7031 stats
->tx_packets
+= packets
;
7032 stats
->tx_bytes
+= bytes
;
7036 /* following stats updated by ixgbe_watchdog_task() */
7037 stats
->multicast
= netdev
->stats
.multicast
;
7038 stats
->rx_errors
= netdev
->stats
.rx_errors
;
7039 stats
->rx_length_errors
= netdev
->stats
.rx_length_errors
;
7040 stats
->rx_crc_errors
= netdev
->stats
.rx_crc_errors
;
7041 stats
->rx_missed_errors
= netdev
->stats
.rx_missed_errors
;
7045 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7046 * #adapter: pointer to ixgbe_adapter
7047 * @tc: number of traffic classes currently enabled
7049 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7050 * 802.1Q priority maps to a packet buffer that exists.
7052 static void ixgbe_validate_rtr(struct ixgbe_adapter
*adapter
, u8 tc
)
7054 struct ixgbe_hw
*hw
= &adapter
->hw
;
7058 /* 82598 have a static priority to TC mapping that can not
7059 * be changed so no validation is needed.
7061 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
7064 reg
= IXGBE_READ_REG(hw
, IXGBE_RTRUP2TC
);
7067 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
7068 u8 up2tc
= reg
>> (i
* IXGBE_RTRUP2TC_UP_SHIFT
);
7070 /* If up2tc is out of bounds default to zero */
7072 reg
&= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT
);
7076 IXGBE_WRITE_REG(hw
, IXGBE_RTRUP2TC
, reg
);
7082 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7085 * @netdev: net device to configure
7086 * @tc: number of traffic classes to enable
7088 int ixgbe_setup_tc(struct net_device
*dev
, u8 tc
)
7090 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
7091 struct ixgbe_hw
*hw
= &adapter
->hw
;
7093 /* If DCB is anabled do not remove traffic classes, multiple
7094 * traffic classes are required to implement DCB
7096 if (!tc
&& (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
7099 /* Hardware supports up to 8 traffic classes */
7100 if (tc
> MAX_TRAFFIC_CLASS
||
7101 (hw
->mac
.type
== ixgbe_mac_82598EB
&& tc
< MAX_TRAFFIC_CLASS
))
7104 /* Hardware has to reinitialize queues and interrupts to
7105 * match packet buffer alignment. Unfortunantly, the
7106 * hardware is not flexible enough to do this dynamically.
7108 if (netif_running(dev
))
7110 ixgbe_clear_interrupt_scheme(adapter
);
7113 netdev_set_num_tc(dev
, tc
);
7115 netdev_reset_tc(dev
);
7117 ixgbe_init_interrupt_scheme(adapter
);
7118 ixgbe_validate_rtr(adapter
, tc
);
7119 if (netif_running(dev
))
7125 static const struct net_device_ops ixgbe_netdev_ops
= {
7126 .ndo_open
= ixgbe_open
,
7127 .ndo_stop
= ixgbe_close
,
7128 .ndo_start_xmit
= ixgbe_xmit_frame
,
7129 .ndo_select_queue
= ixgbe_select_queue
,
7130 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
7131 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
7132 .ndo_validate_addr
= eth_validate_addr
,
7133 .ndo_set_mac_address
= ixgbe_set_mac
,
7134 .ndo_change_mtu
= ixgbe_change_mtu
,
7135 .ndo_tx_timeout
= ixgbe_tx_timeout
,
7136 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
7137 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
7138 .ndo_do_ioctl
= ixgbe_ioctl
,
7139 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
7140 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
7141 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
7142 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
7143 .ndo_get_stats64
= ixgbe_get_stats64
,
7144 .ndo_setup_tc
= ixgbe_setup_tc
,
7145 #ifdef CONFIG_NET_POLL_CONTROLLER
7146 .ndo_poll_controller
= ixgbe_netpoll
,
7149 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
7150 .ndo_fcoe_ddp_target
= ixgbe_fcoe_ddp_target
,
7151 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
7152 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
7153 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
7154 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
7155 #endif /* IXGBE_FCOE */
7158 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
7159 const struct ixgbe_info
*ii
)
7161 #ifdef CONFIG_PCI_IOV
7162 struct ixgbe_hw
*hw
= &adapter
->hw
;
7164 int num_vf_macvlans
, i
;
7165 struct vf_macvlans
*mv_list
;
7167 if (hw
->mac
.type
== ixgbe_mac_82598EB
|| !max_vfs
)
7170 /* The 82599 supports up to 64 VFs per physical function
7171 * but this implementation limits allocation to 63 so that
7172 * basic networking resources are still available to the
7175 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
7176 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
7177 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
7179 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
7183 num_vf_macvlans
= hw
->mac
.num_rar_entries
-
7184 (IXGBE_MAX_PF_MACVLANS
+ 1 + adapter
->num_vfs
);
7186 adapter
->mv_list
= mv_list
= kcalloc(num_vf_macvlans
,
7187 sizeof(struct vf_macvlans
),
7190 /* Initialize list of VF macvlans */
7191 INIT_LIST_HEAD(&adapter
->vf_mvs
.l
);
7192 for (i
= 0; i
< num_vf_macvlans
; i
++) {
7194 mv_list
->free
= true;
7195 mv_list
->rar_entry
= hw
->mac
.num_rar_entries
-
7196 (i
+ adapter
->num_vfs
+ 1);
7197 list_add(&mv_list
->l
, &adapter
->vf_mvs
.l
);
7202 /* If call to enable VFs succeeded then allocate memory
7203 * for per VF control structures.
7206 kcalloc(adapter
->num_vfs
,
7207 sizeof(struct vf_data_storage
), GFP_KERNEL
);
7208 if (adapter
->vfinfo
) {
7209 /* Now that we're sure SR-IOV is enabled
7210 * and memory allocated set up the mailbox parameters
7212 ixgbe_init_mbx_params_pf(hw
);
7213 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
7214 sizeof(hw
->mbx
.ops
));
7216 /* Disable RSC when in SR-IOV mode */
7217 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
7218 IXGBE_FLAG2_RSC_ENABLED
);
7223 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
7224 "SRIOV disabled\n");
7225 pci_disable_sriov(adapter
->pdev
);
7228 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
7229 adapter
->num_vfs
= 0;
7230 #endif /* CONFIG_PCI_IOV */
7234 * ixgbe_probe - Device Initialization Routine
7235 * @pdev: PCI device information struct
7236 * @ent: entry in ixgbe_pci_tbl
7238 * Returns 0 on success, negative on failure
7240 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7241 * The OS initialization, configuring of the adapter private structure,
7242 * and a hardware reset occur.
7244 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
7245 const struct pci_device_id
*ent
)
7247 struct net_device
*netdev
;
7248 struct ixgbe_adapter
*adapter
= NULL
;
7249 struct ixgbe_hw
*hw
;
7250 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
7251 static int cards_found
;
7252 int i
, err
, pci_using_dac
;
7253 u8 part_str
[IXGBE_PBANUM_LENGTH
];
7254 unsigned int indices
= num_possible_cpus();
7260 /* Catch broken hardware that put the wrong VF device ID in
7261 * the PCIe SR-IOV capability.
7263 if (pdev
->is_virtfn
) {
7264 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
7265 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
7269 err
= pci_enable_device_mem(pdev
);
7273 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
7274 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
7277 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
7279 err
= dma_set_coherent_mask(&pdev
->dev
,
7283 "No usable DMA configuration, aborting\n");
7290 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
7291 IORESOURCE_MEM
), ixgbe_driver_name
);
7294 "pci_request_selected_regions failed 0x%x\n", err
);
7298 pci_enable_pcie_error_reporting(pdev
);
7300 pci_set_master(pdev
);
7301 pci_save_state(pdev
);
7303 #ifdef CONFIG_IXGBE_DCB
7304 indices
*= MAX_TRAFFIC_CLASS
;
7307 if (ii
->mac
== ixgbe_mac_82598EB
)
7308 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
7310 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
7313 indices
+= min_t(unsigned int, num_possible_cpus(),
7314 IXGBE_MAX_FCOE_INDICES
);
7316 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
7319 goto err_alloc_etherdev
;
7322 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
7324 adapter
= netdev_priv(netdev
);
7325 pci_set_drvdata(pdev
, adapter
);
7327 adapter
->netdev
= netdev
;
7328 adapter
->pdev
= pdev
;
7331 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
7333 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
7334 pci_resource_len(pdev
, 0));
7340 for (i
= 1; i
<= 5; i
++) {
7341 if (pci_resource_len(pdev
, i
) == 0)
7345 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
7346 ixgbe_set_ethtool_ops(netdev
);
7347 netdev
->watchdog_timeo
= 5 * HZ
;
7348 strncpy(netdev
->name
, pci_name(pdev
), sizeof(netdev
->name
) - 1);
7350 adapter
->bd_number
= cards_found
;
7353 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
7354 hw
->mac
.type
= ii
->mac
;
7357 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
7358 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
7359 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7360 if (!(eec
& (1 << 8)))
7361 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
7364 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
7365 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
7366 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7367 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
7368 hw
->phy
.mdio
.mmds
= 0;
7369 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
7370 hw
->phy
.mdio
.dev
= netdev
;
7371 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
7372 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
7374 ii
->get_invariants(hw
);
7376 /* setup the private structure */
7377 err
= ixgbe_sw_init(adapter
);
7381 /* Make it possible the adapter to be woken up via WOL */
7382 switch (adapter
->hw
.mac
.type
) {
7383 case ixgbe_mac_82599EB
:
7384 case ixgbe_mac_X540
:
7385 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7392 * If there is a fan on this device and it has failed log the
7395 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
7396 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
7397 if (esdp
& IXGBE_ESDP_SDP1
)
7398 e_crit(probe
, "Fan has stopped, replace the adapter\n");
7401 /* reset_hw fills in the perm_addr as well */
7402 hw
->phy
.reset_if_overtemp
= true;
7403 err
= hw
->mac
.ops
.reset_hw(hw
);
7404 hw
->phy
.reset_if_overtemp
= false;
7405 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
7406 hw
->mac
.type
== ixgbe_mac_82598EB
) {
7408 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
7409 e_dev_err("failed to load because an unsupported SFP+ "
7410 "module type was detected.\n");
7411 e_dev_err("Reload the driver after installing a supported "
7415 e_dev_err("HW Init failed: %d\n", err
);
7419 ixgbe_probe_vf(adapter
, ii
);
7421 netdev
->features
= NETIF_F_SG
|
7423 NETIF_F_HW_VLAN_TX
|
7424 NETIF_F_HW_VLAN_RX
|
7425 NETIF_F_HW_VLAN_FILTER
;
7427 netdev
->features
|= NETIF_F_IPV6_CSUM
;
7428 netdev
->features
|= NETIF_F_TSO
;
7429 netdev
->features
|= NETIF_F_TSO6
;
7430 netdev
->features
|= NETIF_F_GRO
;
7431 netdev
->features
|= NETIF_F_RXHASH
;
7433 switch (adapter
->hw
.mac
.type
) {
7434 case ixgbe_mac_82599EB
:
7435 case ixgbe_mac_X540
:
7436 netdev
->features
|= NETIF_F_SCTP_CSUM
;
7442 netdev
->vlan_features
|= NETIF_F_TSO
;
7443 netdev
->vlan_features
|= NETIF_F_TSO6
;
7444 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
7445 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
7446 netdev
->vlan_features
|= NETIF_F_SG
;
7448 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7449 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
7450 IXGBE_FLAG_DCB_ENABLED
);
7452 #ifdef CONFIG_IXGBE_DCB
7453 netdev
->dcbnl_ops
= &dcbnl_ops
;
7457 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7458 if (hw
->mac
.ops
.get_device_caps
) {
7459 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
7460 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
7461 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
7464 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7465 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
7466 netdev
->vlan_features
|= NETIF_F_FSO
;
7467 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
7469 #endif /* IXGBE_FCOE */
7470 if (pci_using_dac
) {
7471 netdev
->features
|= NETIF_F_HIGHDMA
;
7472 netdev
->vlan_features
|= NETIF_F_HIGHDMA
;
7475 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
7476 netdev
->features
|= NETIF_F_LRO
;
7478 /* make sure the EEPROM is good */
7479 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
7480 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7485 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7486 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7488 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
7489 e_dev_err("invalid MAC address\n");
7494 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7495 if (hw
->mac
.ops
.disable_tx_laser
&&
7496 ((hw
->phy
.multispeed_fiber
) ||
7497 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
7498 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
7499 hw
->mac
.ops
.disable_tx_laser(hw
);
7501 setup_timer(&adapter
->service_timer
, &ixgbe_service_timer
,
7502 (unsigned long) adapter
);
7504 INIT_WORK(&adapter
->service_task
, ixgbe_service_task
);
7505 clear_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
);
7507 err
= ixgbe_init_interrupt_scheme(adapter
);
7511 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
7512 netdev
->features
&= ~NETIF_F_RXHASH
;
7514 switch (pdev
->device
) {
7515 case IXGBE_DEV_ID_82599_SFP
:
7516 /* Only this subdevice supports WOL */
7517 if (pdev
->subsystem_device
== IXGBE_SUBDEV_ID_82599_SFP
)
7518 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7519 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7521 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
7522 /* All except this subdevice support WOL */
7523 if (pdev
->subsystem_device
!= IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ
)
7524 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7525 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7527 case IXGBE_DEV_ID_82599_KX4
:
7528 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7529 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7535 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
7537 /* pick up the PCI bus settings for reporting later */
7538 hw
->mac
.ops
.get_bus_info(hw
);
7540 /* print bus type/speed/width info */
7541 e_dev_info("(PCI Express:%s:%s) %pM\n",
7542 (hw
->bus
.speed
== ixgbe_bus_speed_5000
? "5.0GT/s" :
7543 hw
->bus
.speed
== ixgbe_bus_speed_2500
? "2.5GT/s" :
7545 (hw
->bus
.width
== ixgbe_bus_width_pcie_x8
? "Width x8" :
7546 hw
->bus
.width
== ixgbe_bus_width_pcie_x4
? "Width x4" :
7547 hw
->bus
.width
== ixgbe_bus_width_pcie_x1
? "Width x1" :
7551 err
= ixgbe_read_pba_string_generic(hw
, part_str
, IXGBE_PBANUM_LENGTH
);
7553 strncpy(part_str
, "Unknown", IXGBE_PBANUM_LENGTH
);
7554 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
7555 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7556 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
7559 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7560 hw
->mac
.type
, hw
->phy
.type
, part_str
);
7562 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
7563 e_dev_warn("PCI-Express bandwidth available for this card is "
7564 "not sufficient for optimal performance.\n");
7565 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7569 /* save off EEPROM version number */
7570 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
7572 /* reset the hardware with the new settings */
7573 err
= hw
->mac
.ops
.start_hw(hw
);
7575 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
7576 /* We are running on a pre-production device, log a warning */
7577 e_dev_warn("This device is a pre-production adapter/LOM. "
7578 "Please be aware there may be issues associated "
7579 "with your hardware. If you are experiencing "
7580 "problems please contact your Intel or hardware "
7581 "representative who provided you with this "
7584 strcpy(netdev
->name
, "eth%d");
7585 err
= register_netdev(netdev
);
7589 /* carrier off reporting is important to ethtool even BEFORE open */
7590 netif_carrier_off(netdev
);
7592 #ifdef CONFIG_IXGBE_DCA
7593 if (dca_add_requester(&pdev
->dev
) == 0) {
7594 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
7595 ixgbe_setup_dca(adapter
);
7598 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
7599 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
7600 for (i
= 0; i
< adapter
->num_vfs
; i
++)
7601 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
7604 /* Inform firmware of driver version */
7605 if (hw
->mac
.ops
.set_fw_drv_ver
)
7606 hw
->mac
.ops
.set_fw_drv_ver(hw
, MAJ
, MIN
, BUILD
,
7609 /* add san mac addr to netdev */
7610 ixgbe_add_sanmac_netdev(netdev
);
7612 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7617 ixgbe_release_hw_control(adapter
);
7618 ixgbe_clear_interrupt_scheme(adapter
);
7621 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7622 ixgbe_disable_sriov(adapter
);
7623 adapter
->flags2
&= ~IXGBE_FLAG2_SEARCH_FOR_SFP
;
7624 iounmap(hw
->hw_addr
);
7626 free_netdev(netdev
);
7628 pci_release_selected_regions(pdev
,
7629 pci_select_bars(pdev
, IORESOURCE_MEM
));
7632 pci_disable_device(pdev
);
7637 * ixgbe_remove - Device Removal Routine
7638 * @pdev: PCI device information struct
7640 * ixgbe_remove is called by the PCI subsystem to alert the driver
7641 * that it should release a PCI device. The could be caused by a
7642 * Hot-Plug event, or because the driver is going to be removed from
7645 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
7647 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7648 struct net_device
*netdev
= adapter
->netdev
;
7650 set_bit(__IXGBE_DOWN
, &adapter
->state
);
7651 cancel_work_sync(&adapter
->service_task
);
7653 #ifdef CONFIG_IXGBE_DCA
7654 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
7655 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
7656 dca_remove_requester(&pdev
->dev
);
7657 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
7662 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
7663 ixgbe_cleanup_fcoe(adapter
);
7665 #endif /* IXGBE_FCOE */
7667 /* remove the added san mac */
7668 ixgbe_del_sanmac_netdev(netdev
);
7670 if (netdev
->reg_state
== NETREG_REGISTERED
)
7671 unregister_netdev(netdev
);
7673 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7674 ixgbe_disable_sriov(adapter
);
7676 ixgbe_clear_interrupt_scheme(adapter
);
7678 ixgbe_release_hw_control(adapter
);
7680 iounmap(adapter
->hw
.hw_addr
);
7681 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
7684 e_dev_info("complete\n");
7686 free_netdev(netdev
);
7688 pci_disable_pcie_error_reporting(pdev
);
7690 pci_disable_device(pdev
);
7694 * ixgbe_io_error_detected - called when PCI error is detected
7695 * @pdev: Pointer to PCI device
7696 * @state: The current pci connection state
7698 * This function is called after a PCI bus error affecting
7699 * this device has been detected.
7701 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7702 pci_channel_state_t state
)
7704 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7705 struct net_device
*netdev
= adapter
->netdev
;
7707 netif_device_detach(netdev
);
7709 if (state
== pci_channel_io_perm_failure
)
7710 return PCI_ERS_RESULT_DISCONNECT
;
7712 if (netif_running(netdev
))
7713 ixgbe_down(adapter
);
7714 pci_disable_device(pdev
);
7716 /* Request a slot reset. */
7717 return PCI_ERS_RESULT_NEED_RESET
;
7721 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7722 * @pdev: Pointer to PCI device
7724 * Restart the card from scratch, as if from a cold-boot.
7726 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7728 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7729 pci_ers_result_t result
;
7732 if (pci_enable_device_mem(pdev
)) {
7733 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7734 result
= PCI_ERS_RESULT_DISCONNECT
;
7736 pci_set_master(pdev
);
7737 pci_restore_state(pdev
);
7738 pci_save_state(pdev
);
7740 pci_wake_from_d3(pdev
, false);
7742 ixgbe_reset(adapter
);
7743 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7744 result
= PCI_ERS_RESULT_RECOVERED
;
7747 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7749 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7750 "failed 0x%0x\n", err
);
7751 /* non-fatal, continue */
7758 * ixgbe_io_resume - called when traffic can start flowing again.
7759 * @pdev: Pointer to PCI device
7761 * This callback is called when the error recovery driver tells us that
7762 * its OK to resume normal operation.
7764 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7766 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7767 struct net_device
*netdev
= adapter
->netdev
;
7769 if (netif_running(netdev
)) {
7770 if (ixgbe_up(adapter
)) {
7771 e_info(probe
, "ixgbe_up failed after reset\n");
7776 netif_device_attach(netdev
);
7779 static struct pci_error_handlers ixgbe_err_handler
= {
7780 .error_detected
= ixgbe_io_error_detected
,
7781 .slot_reset
= ixgbe_io_slot_reset
,
7782 .resume
= ixgbe_io_resume
,
7785 static struct pci_driver ixgbe_driver
= {
7786 .name
= ixgbe_driver_name
,
7787 .id_table
= ixgbe_pci_tbl
,
7788 .probe
= ixgbe_probe
,
7789 .remove
= __devexit_p(ixgbe_remove
),
7791 .suspend
= ixgbe_suspend
,
7792 .resume
= ixgbe_resume
,
7794 .shutdown
= ixgbe_shutdown
,
7795 .err_handler
= &ixgbe_err_handler
7799 * ixgbe_init_module - Driver Registration Routine
7801 * ixgbe_init_module is the first routine called when the driver is
7802 * loaded. All it does is register with the PCI subsystem.
7804 static int __init
ixgbe_init_module(void)
7807 pr_info("%s - version %s\n", ixgbe_driver_string
, ixgbe_driver_version
);
7808 pr_info("%s\n", ixgbe_copyright
);
7810 #ifdef CONFIG_IXGBE_DCA
7811 dca_register_notify(&dca_notifier
);
7814 ret
= pci_register_driver(&ixgbe_driver
);
7818 module_init(ixgbe_init_module
);
7821 * ixgbe_exit_module - Driver Exit Cleanup Routine
7823 * ixgbe_exit_module is called just before the driver is removed
7826 static void __exit
ixgbe_exit_module(void)
7828 #ifdef CONFIG_IXGBE_DCA
7829 dca_unregister_notify(&dca_notifier
);
7831 pci_unregister_driver(&ixgbe_driver
);
7832 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7835 #ifdef CONFIG_IXGBE_DCA
7836 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7841 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7842 __ixgbe_notify_dca
);
7844 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7847 #endif /* CONFIG_IXGBE_DCA */
7849 module_exit(ixgbe_exit_module
);