3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
28 #include "zd_ieee80211.h"
33 void zd_chip_init(struct zd_chip
*chip
,
34 struct net_device
*netdev
,
35 struct usb_interface
*intf
)
37 memset(chip
, 0, sizeof(*chip
));
38 mutex_init(&chip
->mutex
);
39 zd_usb_init(&chip
->usb
, netdev
, intf
);
40 zd_rf_init(&chip
->rf
);
43 void zd_chip_clear(struct zd_chip
*chip
)
45 ZD_ASSERT(!mutex_is_locked(&chip
->mutex
));
46 zd_usb_clear(&chip
->usb
);
47 zd_rf_clear(&chip
->rf
);
48 mutex_destroy(&chip
->mutex
);
49 ZD_MEMCLEAR(chip
, sizeof(*chip
));
52 static int scnprint_mac_oui(const u8
*addr
, char *buffer
, size_t size
)
54 return scnprintf(buffer
, size
, "%02x-%02x-%02x",
55 addr
[0], addr
[1], addr
[2]);
58 /* Prints an identifier line, which will support debugging. */
59 static int scnprint_id(struct zd_chip
*chip
, char *buffer
, size_t size
)
63 i
= scnprintf(buffer
, size
, "zd1211%s chip ",
64 chip
->is_zd1211b
? "b" : "");
65 i
+= zd_usb_scnprint_id(&chip
->usb
, buffer
+i
, size
-i
);
66 i
+= scnprintf(buffer
+i
, size
-i
, " ");
67 i
+= scnprint_mac_oui(chip
->e2p_mac
, buffer
+i
, size
-i
);
68 i
+= scnprintf(buffer
+i
, size
-i
, " ");
69 i
+= zd_rf_scnprint_id(&chip
->rf
, buffer
+i
, size
-i
);
70 i
+= scnprintf(buffer
+i
, size
-i
, " pa%1x %c%c%c%c", chip
->pa_type
,
71 chip
->patch_cck_gain
? 'g' : '-',
72 chip
->patch_cr157
? '7' : '-',
73 chip
->patch_6m_band_edge
? '6' : '-',
74 chip
->new_phy_layout
? 'N' : '-');
78 static void print_id(struct zd_chip
*chip
)
82 scnprint_id(chip
, buffer
, sizeof(buffer
));
83 buffer
[sizeof(buffer
)-1] = 0;
84 dev_info(zd_chip_dev(chip
), "%s\n", buffer
);
87 /* Read a variable number of 32-bit values. Parameter count is not allowed to
88 * exceed USB_MAX_IOREAD32_COUNT.
90 int zd_ioread32v_locked(struct zd_chip
*chip
, u32
*values
, const zd_addr_t
*addr
,
95 zd_addr_t
*a16
= (zd_addr_t
*)NULL
;
99 if (count
> USB_MAX_IOREAD32_COUNT
)
102 /* Allocate a single memory block for values and addresses. */
104 a16
= kmalloc(count16
* (sizeof(zd_addr_t
) + sizeof(u16
)),
107 dev_dbg_f(zd_chip_dev(chip
),
108 "error ENOMEM in allocation of a16\n");
112 v16
= (u16
*)(a16
+ count16
);
114 for (i
= 0; i
< count
; i
++) {
116 /* We read the high word always first. */
117 a16
[j
] = zd_inc_word(addr
[i
]);
121 r
= zd_ioread16v_locked(chip
, v16
, a16
, count16
);
123 dev_dbg_f(zd_chip_dev(chip
),
124 "error: zd_ioread16v_locked. Error number %d\n", r
);
128 for (i
= 0; i
< count
; i
++) {
130 values
[i
] = (v16
[j
] << 16) | v16
[j
+1];
138 int _zd_iowrite32v_locked(struct zd_chip
*chip
, const struct zd_ioreq32
*ioreqs
,
142 struct zd_ioreq16
*ioreqs16
;
143 unsigned int count16
;
145 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
149 if (count
> USB_MAX_IOWRITE32_COUNT
)
152 /* Allocate a single memory block for values and addresses. */
154 ioreqs16
= kmalloc(count16
* sizeof(struct zd_ioreq16
), GFP_NOFS
);
157 dev_dbg_f(zd_chip_dev(chip
),
158 "error %d in ioreqs16 allocation\n", r
);
162 for (i
= 0; i
< count
; i
++) {
164 /* We write the high word always first. */
165 ioreqs16
[j
].value
= ioreqs
[i
].value
>> 16;
166 ioreqs16
[j
].addr
= zd_inc_word(ioreqs
[i
].addr
);
167 ioreqs16
[j
+1].value
= ioreqs
[i
].value
;
168 ioreqs16
[j
+1].addr
= ioreqs
[i
].addr
;
171 r
= zd_usb_iowrite16v(&chip
->usb
, ioreqs16
, count16
);
174 dev_dbg_f(zd_chip_dev(chip
),
175 "error %d in zd_usb_write16v\n", r
);
183 int zd_iowrite16a_locked(struct zd_chip
*chip
,
184 const struct zd_ioreq16
*ioreqs
, unsigned int count
)
187 unsigned int i
, j
, t
, max
;
189 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
190 for (i
= 0; i
< count
; i
+= j
+ t
) {
193 if (max
> USB_MAX_IOWRITE16_COUNT
)
194 max
= USB_MAX_IOWRITE16_COUNT
;
195 for (j
= 0; j
< max
; j
++) {
196 if (!ioreqs
[i
+j
].addr
) {
202 r
= zd_usb_iowrite16v(&chip
->usb
, &ioreqs
[i
], j
);
204 dev_dbg_f(zd_chip_dev(chip
),
205 "error zd_usb_iowrite16v. Error number %d\n",
214 /* Writes a variable number of 32 bit registers. The functions will split
215 * that in several USB requests. A split can be forced by inserting an IO
216 * request with an zero address field.
218 int zd_iowrite32a_locked(struct zd_chip
*chip
,
219 const struct zd_ioreq32
*ioreqs
, unsigned int count
)
222 unsigned int i
, j
, t
, max
;
224 for (i
= 0; i
< count
; i
+= j
+ t
) {
227 if (max
> USB_MAX_IOWRITE32_COUNT
)
228 max
= USB_MAX_IOWRITE32_COUNT
;
229 for (j
= 0; j
< max
; j
++) {
230 if (!ioreqs
[i
+j
].addr
) {
236 r
= _zd_iowrite32v_locked(chip
, &ioreqs
[i
], j
);
238 dev_dbg_f(zd_chip_dev(chip
),
239 "error _zd_iowrite32v_locked."
240 " Error number %d\n", r
);
248 int zd_ioread16(struct zd_chip
*chip
, zd_addr_t addr
, u16
*value
)
252 mutex_lock(&chip
->mutex
);
253 r
= zd_ioread16_locked(chip
, value
, addr
);
254 mutex_unlock(&chip
->mutex
);
258 int zd_ioread32(struct zd_chip
*chip
, zd_addr_t addr
, u32
*value
)
262 mutex_lock(&chip
->mutex
);
263 r
= zd_ioread32_locked(chip
, value
, addr
);
264 mutex_unlock(&chip
->mutex
);
268 int zd_iowrite16(struct zd_chip
*chip
, zd_addr_t addr
, u16 value
)
272 mutex_lock(&chip
->mutex
);
273 r
= zd_iowrite16_locked(chip
, value
, addr
);
274 mutex_unlock(&chip
->mutex
);
278 int zd_iowrite32(struct zd_chip
*chip
, zd_addr_t addr
, u32 value
)
282 mutex_lock(&chip
->mutex
);
283 r
= zd_iowrite32_locked(chip
, value
, addr
);
284 mutex_unlock(&chip
->mutex
);
288 int zd_ioread32v(struct zd_chip
*chip
, const zd_addr_t
*addresses
,
289 u32
*values
, unsigned int count
)
293 mutex_lock(&chip
->mutex
);
294 r
= zd_ioread32v_locked(chip
, values
, addresses
, count
);
295 mutex_unlock(&chip
->mutex
);
299 int zd_iowrite32a(struct zd_chip
*chip
, const struct zd_ioreq32
*ioreqs
,
304 mutex_lock(&chip
->mutex
);
305 r
= zd_iowrite32a_locked(chip
, ioreqs
, count
);
306 mutex_unlock(&chip
->mutex
);
310 static int read_pod(struct zd_chip
*chip
, u8
*rf_type
)
315 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
316 r
= zd_ioread32_locked(chip
, &value
, E2P_POD
);
319 dev_dbg_f(zd_chip_dev(chip
), "E2P_POD %#010x\n", value
);
321 /* FIXME: AL2230 handling (Bit 7 in POD) */
322 *rf_type
= value
& 0x0f;
323 chip
->pa_type
= (value
>> 16) & 0x0f;
324 chip
->patch_cck_gain
= (value
>> 8) & 0x1;
325 chip
->patch_cr157
= (value
>> 13) & 0x1;
326 chip
->patch_6m_band_edge
= (value
>> 21) & 0x1;
327 chip
->new_phy_layout
= (value
>> 31) & 0x1;
328 chip
->link_led
= ((value
>> 4) & 1) ? LED1
: LED2
;
329 chip
->supports_tx_led
= 1;
330 if (value
& (1 << 24)) { /* LED scenario */
331 if (value
& (1 << 29))
332 chip
->supports_tx_led
= 0;
335 dev_dbg_f(zd_chip_dev(chip
),
336 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
337 "patch 6M %d new PHY %d link LED%d tx led %d\n",
338 zd_rf_name(*rf_type
), *rf_type
,
339 chip
->pa_type
, chip
->patch_cck_gain
,
340 chip
->patch_cr157
, chip
->patch_6m_band_edge
,
341 chip
->new_phy_layout
,
342 chip
->link_led
== LED1
? 1 : 2,
343 chip
->supports_tx_led
);
348 chip
->patch_cck_gain
= 0;
349 chip
->patch_cr157
= 0;
350 chip
->patch_6m_band_edge
= 0;
351 chip
->new_phy_layout
= 0;
355 static int _read_mac_addr(struct zd_chip
*chip
, u8
*mac_addr
,
356 const zd_addr_t
*addr
)
361 r
= zd_ioread32v_locked(chip
, parts
, (const zd_addr_t
*)addr
, 2);
363 dev_dbg_f(zd_chip_dev(chip
),
364 "error: couldn't read e2p macs. Error number %d\n", r
);
368 mac_addr
[0] = parts
[0];
369 mac_addr
[1] = parts
[0] >> 8;
370 mac_addr
[2] = parts
[0] >> 16;
371 mac_addr
[3] = parts
[0] >> 24;
372 mac_addr
[4] = parts
[1];
373 mac_addr
[5] = parts
[1] >> 8;
378 static int read_e2p_mac_addr(struct zd_chip
*chip
)
380 static const zd_addr_t addr
[2] = { E2P_MAC_ADDR_P1
, E2P_MAC_ADDR_P2
};
382 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
383 return _read_mac_addr(chip
, chip
->e2p_mac
, (const zd_addr_t
*)addr
);
386 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
387 * CR_MAC_ADDR_P2 must be overwritten
389 void zd_get_e2p_mac_addr(struct zd_chip
*chip
, u8
*mac_addr
)
391 mutex_lock(&chip
->mutex
);
392 memcpy(mac_addr
, chip
->e2p_mac
, ETH_ALEN
);
393 mutex_unlock(&chip
->mutex
);
396 static int read_mac_addr(struct zd_chip
*chip
, u8
*mac_addr
)
398 static const zd_addr_t addr
[2] = { CR_MAC_ADDR_P1
, CR_MAC_ADDR_P2
};
399 return _read_mac_addr(chip
, mac_addr
, (const zd_addr_t
*)addr
);
402 int zd_read_mac_addr(struct zd_chip
*chip
, u8
*mac_addr
)
406 dev_dbg_f(zd_chip_dev(chip
), "\n");
407 mutex_lock(&chip
->mutex
);
408 r
= read_mac_addr(chip
, mac_addr
);
409 mutex_unlock(&chip
->mutex
);
413 int zd_write_mac_addr(struct zd_chip
*chip
, const u8
*mac_addr
)
416 struct zd_ioreq32 reqs
[2] = {
417 [0] = { .addr
= CR_MAC_ADDR_P1
},
418 [1] = { .addr
= CR_MAC_ADDR_P2
},
421 reqs
[0].value
= (mac_addr
[3] << 24)
422 | (mac_addr
[2] << 16)
425 reqs
[1].value
= (mac_addr
[5] << 8)
428 dev_dbg_f(zd_chip_dev(chip
),
429 "mac addr " MAC_FMT
"\n", MAC_ARG(mac_addr
));
431 mutex_lock(&chip
->mutex
);
432 r
= zd_iowrite32a_locked(chip
, reqs
, ARRAY_SIZE(reqs
));
436 read_mac_addr(chip
, tmp
);
439 mutex_unlock(&chip
->mutex
);
443 int zd_read_regdomain(struct zd_chip
*chip
, u8
*regdomain
)
448 mutex_lock(&chip
->mutex
);
449 r
= zd_ioread32_locked(chip
, &value
, E2P_SUBID
);
450 mutex_unlock(&chip
->mutex
);
454 *regdomain
= value
>> 16;
455 dev_dbg_f(zd_chip_dev(chip
), "regdomain: %#04x\n", *regdomain
);
460 static int read_values(struct zd_chip
*chip
, u8
*values
, size_t count
,
461 zd_addr_t e2p_addr
, u32 guard
)
467 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
469 r
= zd_ioread32_locked(chip
, &v
, e2p_addr
+i
/2);
475 values
[i
++] = v
>> 8;
476 values
[i
++] = v
>> 16;
477 values
[i
++] = v
>> 24;
480 for (;i
< count
; i
++)
481 values
[i
] = v
>> (8*(i
%3));
486 static int read_pwr_cal_values(struct zd_chip
*chip
)
488 return read_values(chip
, chip
->pwr_cal_values
,
489 E2P_CHANNEL_COUNT
, E2P_PWR_CAL_VALUE1
,
493 static int read_pwr_int_values(struct zd_chip
*chip
)
495 return read_values(chip
, chip
->pwr_int_values
,
496 E2P_CHANNEL_COUNT
, E2P_PWR_INT_VALUE1
,
500 static int read_ofdm_cal_values(struct zd_chip
*chip
)
504 static const zd_addr_t addresses
[] = {
510 for (i
= 0; i
< 3; i
++) {
511 r
= read_values(chip
, chip
->ofdm_cal_values
[i
],
512 E2P_CHANNEL_COUNT
, addresses
[i
], 0);
519 static int read_cal_int_tables(struct zd_chip
*chip
)
523 r
= read_pwr_cal_values(chip
);
526 r
= read_pwr_int_values(chip
);
529 r
= read_ofdm_cal_values(chip
);
535 /* phy means physical registers */
536 int zd_chip_lock_phy_regs(struct zd_chip
*chip
)
541 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
542 r
= zd_ioread32_locked(chip
, &tmp
, CR_REG1
);
544 dev_err(zd_chip_dev(chip
), "error ioread32(CR_REG1): %d\n", r
);
548 dev_dbg_f(zd_chip_dev(chip
),
549 "CR_REG1: 0x%02x -> 0x%02x\n", tmp
, tmp
& ~UNLOCK_PHY_REGS
);
550 tmp
&= ~UNLOCK_PHY_REGS
;
552 r
= zd_iowrite32_locked(chip
, tmp
, CR_REG1
);
554 dev_err(zd_chip_dev(chip
), "error iowrite32(CR_REG1): %d\n", r
);
558 int zd_chip_unlock_phy_regs(struct zd_chip
*chip
)
563 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
564 r
= zd_ioread32_locked(chip
, &tmp
, CR_REG1
);
566 dev_err(zd_chip_dev(chip
),
567 "error ioread32(CR_REG1): %d\n", r
);
571 dev_dbg_f(zd_chip_dev(chip
),
572 "CR_REG1: 0x%02x -> 0x%02x\n", tmp
, tmp
| UNLOCK_PHY_REGS
);
573 tmp
|= UNLOCK_PHY_REGS
;
575 r
= zd_iowrite32_locked(chip
, tmp
, CR_REG1
);
577 dev_err(zd_chip_dev(chip
), "error iowrite32(CR_REG1): %d\n", r
);
581 /* CR157 can be optionally patched by the EEPROM */
582 static int patch_cr157(struct zd_chip
*chip
)
587 if (!chip
->patch_cr157
)
590 r
= zd_ioread32_locked(chip
, &value
, E2P_PHY_REG
);
594 dev_dbg_f(zd_chip_dev(chip
), "patching value %x\n", value
>> 8);
595 return zd_iowrite32_locked(chip
, value
>> 8, CR157
);
599 * 6M band edge can be optionally overwritten for certain RF's
600 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
601 * bit (for AL2230, AL2230S)
603 static int patch_6m_band_edge(struct zd_chip
*chip
, int channel
)
605 struct zd_ioreq16 ioreqs
[] = {
606 { CR128
, 0x14 }, { CR129
, 0x12 }, { CR130
, 0x10 },
610 if (!chip
->patch_6m_band_edge
|| !chip
->rf
.patch_6m_band_edge
)
613 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
614 if (channel
== 1 || channel
== 11)
615 ioreqs
[0].value
= 0x12;
617 dev_dbg_f(zd_chip_dev(chip
), "patching for channel %d\n", channel
);
618 return zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
621 static int zd1211_hw_reset_phy(struct zd_chip
*chip
)
623 static const struct zd_ioreq16 ioreqs
[] = {
624 { CR0
, 0x0a }, { CR1
, 0x06 }, { CR2
, 0x26 },
625 { CR3
, 0x38 }, { CR4
, 0x80 }, { CR9
, 0xa0 },
626 { CR10
, 0x81 }, { CR11
, 0x00 }, { CR12
, 0x7f },
627 { CR13
, 0x8c }, { CR14
, 0x80 }, { CR15
, 0x3d },
628 { CR16
, 0x20 }, { CR17
, 0x1e }, { CR18
, 0x0a },
629 { CR19
, 0x48 }, { CR20
, 0x0c }, { CR21
, 0x0c },
630 { CR22
, 0x23 }, { CR23
, 0x90 }, { CR24
, 0x14 },
631 { CR25
, 0x40 }, { CR26
, 0x10 }, { CR27
, 0x19 },
632 { CR28
, 0x7f }, { CR29
, 0x80 }, { CR30
, 0x4b },
633 { CR31
, 0x60 }, { CR32
, 0x43 }, { CR33
, 0x08 },
634 { CR34
, 0x06 }, { CR35
, 0x0a }, { CR36
, 0x00 },
635 { CR37
, 0x00 }, { CR38
, 0x38 }, { CR39
, 0x0c },
636 { CR40
, 0x84 }, { CR41
, 0x2a }, { CR42
, 0x80 },
637 { CR43
, 0x10 }, { CR44
, 0x12 }, { CR46
, 0xff },
638 { CR47
, 0x1E }, { CR48
, 0x26 }, { CR49
, 0x5b },
639 { CR64
, 0xd0 }, { CR65
, 0x04 }, { CR66
, 0x58 },
640 { CR67
, 0xc9 }, { CR68
, 0x88 }, { CR69
, 0x41 },
641 { CR70
, 0x23 }, { CR71
, 0x10 }, { CR72
, 0xff },
642 { CR73
, 0x32 }, { CR74
, 0x30 }, { CR75
, 0x65 },
643 { CR76
, 0x41 }, { CR77
, 0x1b }, { CR78
, 0x30 },
644 { CR79
, 0x68 }, { CR80
, 0x64 }, { CR81
, 0x64 },
645 { CR82
, 0x00 }, { CR83
, 0x00 }, { CR84
, 0x00 },
646 { CR85
, 0x02 }, { CR86
, 0x00 }, { CR87
, 0x00 },
647 { CR88
, 0xff }, { CR89
, 0xfc }, { CR90
, 0x00 },
648 { CR91
, 0x00 }, { CR92
, 0x00 }, { CR93
, 0x08 },
649 { CR94
, 0x00 }, { CR95
, 0x00 }, { CR96
, 0xff },
650 { CR97
, 0xe7 }, { CR98
, 0x00 }, { CR99
, 0x00 },
651 { CR100
, 0x00 }, { CR101
, 0xae }, { CR102
, 0x02 },
652 { CR103
, 0x00 }, { CR104
, 0x03 }, { CR105
, 0x65 },
653 { CR106
, 0x04 }, { CR107
, 0x00 }, { CR108
, 0x0a },
654 { CR109
, 0xaa }, { CR110
, 0xaa }, { CR111
, 0x25 },
655 { CR112
, 0x25 }, { CR113
, 0x00 }, { CR119
, 0x1e },
656 { CR125
, 0x90 }, { CR126
, 0x00 }, { CR127
, 0x00 },
658 { CR5
, 0x00 }, { CR6
, 0x00 }, { CR7
, 0x00 },
659 { CR8
, 0x00 }, { CR9
, 0x20 }, { CR12
, 0xf0 },
660 { CR20
, 0x0e }, { CR21
, 0x0e }, { CR27
, 0x10 },
661 { CR44
, 0x33 }, { CR47
, 0x1E }, { CR83
, 0x24 },
662 { CR84
, 0x04 }, { CR85
, 0x00 }, { CR86
, 0x0C },
663 { CR87
, 0x12 }, { CR88
, 0x0C }, { CR89
, 0x00 },
664 { CR90
, 0x10 }, { CR91
, 0x08 }, { CR93
, 0x00 },
665 { CR94
, 0x01 }, { CR95
, 0x00 }, { CR96
, 0x50 },
666 { CR97
, 0x37 }, { CR98
, 0x35 }, { CR101
, 0x13 },
667 { CR102
, 0x27 }, { CR103
, 0x27 }, { CR104
, 0x18 },
668 { CR105
, 0x12 }, { CR109
, 0x27 }, { CR110
, 0x27 },
669 { CR111
, 0x27 }, { CR112
, 0x27 }, { CR113
, 0x27 },
670 { CR114
, 0x27 }, { CR115
, 0x26 }, { CR116
, 0x24 },
671 { CR117
, 0xfc }, { CR118
, 0xfa }, { CR120
, 0x4f },
672 { CR123
, 0x27 }, { CR125
, 0xaa }, { CR127
, 0x03 },
673 { CR128
, 0x14 }, { CR129
, 0x12 }, { CR130
, 0x10 },
674 { CR131
, 0x0C }, { CR136
, 0xdf }, { CR137
, 0x40 },
675 { CR138
, 0xa0 }, { CR139
, 0xb0 }, { CR140
, 0x99 },
676 { CR141
, 0x82 }, { CR142
, 0x54 }, { CR143
, 0x1c },
677 { CR144
, 0x6c }, { CR147
, 0x07 }, { CR148
, 0x4c },
678 { CR149
, 0x50 }, { CR150
, 0x0e }, { CR151
, 0x18 },
679 { CR160
, 0xfe }, { CR161
, 0xee }, { CR162
, 0xaa },
680 { CR163
, 0xfa }, { CR164
, 0xfa }, { CR165
, 0xea },
681 { CR166
, 0xbe }, { CR167
, 0xbe }, { CR168
, 0x6a },
682 { CR169
, 0xba }, { CR170
, 0xba }, { CR171
, 0xba },
683 /* Note: CR204 must lead the CR203 */
691 dev_dbg_f(zd_chip_dev(chip
), "\n");
693 r
= zd_chip_lock_phy_regs(chip
);
697 r
= zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
701 r
= patch_cr157(chip
);
703 t
= zd_chip_unlock_phy_regs(chip
);
710 static int zd1211b_hw_reset_phy(struct zd_chip
*chip
)
712 static const struct zd_ioreq16 ioreqs
[] = {
713 { CR0
, 0x14 }, { CR1
, 0x06 }, { CR2
, 0x26 },
714 { CR3
, 0x38 }, { CR4
, 0x80 }, { CR9
, 0xe0 },
716 /* power control { { CR11, 1 << 6 }, */
718 { CR12
, 0xf0 }, { CR13
, 0x8c }, { CR14
, 0x80 },
719 { CR15
, 0x3d }, { CR16
, 0x20 }, { CR17
, 0x1e },
720 { CR18
, 0x0a }, { CR19
, 0x48 },
721 { CR20
, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
722 { CR21
, 0x0e }, { CR22
, 0x23 }, { CR23
, 0x90 },
723 { CR24
, 0x14 }, { CR25
, 0x40 }, { CR26
, 0x10 },
724 { CR27
, 0x10 }, { CR28
, 0x7f }, { CR29
, 0x80 },
725 { CR30
, 0x4b }, /* ASIC/FWT, no jointly decoder */
726 { CR31
, 0x60 }, { CR32
, 0x43 }, { CR33
, 0x08 },
727 { CR34
, 0x06 }, { CR35
, 0x0a }, { CR36
, 0x00 },
728 { CR37
, 0x00 }, { CR38
, 0x38 }, { CR39
, 0x0c },
729 { CR40
, 0x84 }, { CR41
, 0x2a }, { CR42
, 0x80 },
730 { CR43
, 0x10 }, { CR44
, 0x33 }, { CR46
, 0xff },
731 { CR47
, 0x1E }, { CR48
, 0x26 }, { CR49
, 0x5b },
732 { CR64
, 0xd0 }, { CR65
, 0x04 }, { CR66
, 0x58 },
733 { CR67
, 0xc9 }, { CR68
, 0x88 }, { CR69
, 0x41 },
734 { CR70
, 0x23 }, { CR71
, 0x10 }, { CR72
, 0xff },
735 { CR73
, 0x32 }, { CR74
, 0x30 }, { CR75
, 0x65 },
736 { CR76
, 0x41 }, { CR77
, 0x1b }, { CR78
, 0x30 },
737 { CR79
, 0xf0 }, { CR80
, 0x64 }, { CR81
, 0x64 },
738 { CR82
, 0x00 }, { CR83
, 0x24 }, { CR84
, 0x04 },
739 { CR85
, 0x00 }, { CR86
, 0x0c }, { CR87
, 0x12 },
740 { CR88
, 0x0c }, { CR89
, 0x00 }, { CR90
, 0x58 },
741 { CR91
, 0x04 }, { CR92
, 0x00 }, { CR93
, 0x00 },
743 { CR95
, 0x20 }, /* ZD1211B */
744 { CR96
, 0x50 }, { CR97
, 0x37 }, { CR98
, 0x35 },
745 { CR99
, 0x00 }, { CR100
, 0x01 }, { CR101
, 0x13 },
746 { CR102
, 0x27 }, { CR103
, 0x27 }, { CR104
, 0x18 },
747 { CR105
, 0x12 }, { CR106
, 0x04 }, { CR107
, 0x00 },
748 { CR108
, 0x0a }, { CR109
, 0x27 }, { CR110
, 0x27 },
749 { CR111
, 0x27 }, { CR112
, 0x27 }, { CR113
, 0x27 },
750 { CR114
, 0x27 }, { CR115
, 0x26 }, { CR116
, 0x24 },
751 { CR117
, 0xfc }, { CR118
, 0xfa }, { CR119
, 0x1e },
752 { CR125
, 0x90 }, { CR126
, 0x00 }, { CR127
, 0x00 },
753 { CR128
, 0x14 }, { CR129
, 0x12 }, { CR130
, 0x10 },
754 { CR131
, 0x0c }, { CR136
, 0xdf }, { CR137
, 0xa0 },
755 { CR138
, 0xa8 }, { CR139
, 0xb4 }, { CR140
, 0x98 },
756 { CR141
, 0x82 }, { CR142
, 0x53 }, { CR143
, 0x1c },
757 { CR144
, 0x6c }, { CR147
, 0x07 }, { CR148
, 0x40 },
758 { CR149
, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
759 { CR150
, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
760 { CR151
, 0x18 }, { CR159
, 0x70 }, { CR160
, 0xfe },
761 { CR161
, 0xee }, { CR162
, 0xaa }, { CR163
, 0xfa },
762 { CR164
, 0xfa }, { CR165
, 0xea }, { CR166
, 0xbe },
763 { CR167
, 0xbe }, { CR168
, 0x6a }, { CR169
, 0xba },
764 { CR170
, 0xba }, { CR171
, 0xba },
765 /* Note: CR204 must lead the CR203 */
773 dev_dbg_f(zd_chip_dev(chip
), "\n");
775 r
= zd_chip_lock_phy_regs(chip
);
779 r
= zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
783 r
= patch_cr157(chip
);
785 t
= zd_chip_unlock_phy_regs(chip
);
792 static int hw_reset_phy(struct zd_chip
*chip
)
794 return chip
->is_zd1211b
? zd1211b_hw_reset_phy(chip
) :
795 zd1211_hw_reset_phy(chip
);
798 static int zd1211_hw_init_hmac(struct zd_chip
*chip
)
800 static const struct zd_ioreq32 ioreqs
[] = {
801 { CR_ZD1211_RETRY_MAX
, 0x2 },
802 { CR_RX_THRESHOLD
, 0x000c0640 },
805 dev_dbg_f(zd_chip_dev(chip
), "\n");
806 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
807 return zd_iowrite32a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
810 static int zd1211b_hw_init_hmac(struct zd_chip
*chip
)
812 static const struct zd_ioreq32 ioreqs
[] = {
813 { CR_ZD1211B_RETRY_MAX
, 0x02020202 },
814 { CR_ZD1211B_TX_PWR_CTL4
, 0x007f003f },
815 { CR_ZD1211B_TX_PWR_CTL3
, 0x007f003f },
816 { CR_ZD1211B_TX_PWR_CTL2
, 0x003f001f },
817 { CR_ZD1211B_TX_PWR_CTL1
, 0x001f000f },
818 { CR_ZD1211B_AIFS_CTL1
, 0x00280028 },
819 { CR_ZD1211B_AIFS_CTL2
, 0x008C003C },
820 { CR_ZD1211B_TXOP
, 0x01800824 },
821 { CR_RX_THRESHOLD
, 0x000c0eff, },
824 dev_dbg_f(zd_chip_dev(chip
), "\n");
825 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
826 return zd_iowrite32a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
829 static int hw_init_hmac(struct zd_chip
*chip
)
832 static const struct zd_ioreq32 ioreqs
[] = {
833 { CR_ACK_TIMEOUT_EXT
, 0x20 },
834 { CR_ADDA_MBIAS_WARMTIME
, 0x30000808 },
835 { CR_SNIFFER_ON
, 0 },
836 { CR_RX_FILTER
, STA_RX_FILTER
},
837 { CR_GROUP_HASH_P1
, 0x00 },
838 { CR_GROUP_HASH_P2
, 0x80000000 },
840 { CR_ADDA_PWR_DWN
, 0x7f },
841 { CR_BCN_PLCP_CFG
, 0x00f00401 },
842 { CR_PHY_DELAY
, 0x00 },
843 { CR_ACK_TIMEOUT_EXT
, 0x80 },
844 { CR_ADDA_PWR_DWN
, 0x00 },
845 { CR_ACK_TIME_80211
, 0x100 },
846 { CR_RX_PE_DELAY
, 0x70 },
847 { CR_PS_CTRL
, 0x10000000 },
848 { CR_RTS_CTS_RATE
, 0x02030203 },
849 { CR_AFTER_PNP
, 0x1 },
850 { CR_WEP_PROTECT
, 0x114 },
851 { CR_IFS_VALUE
, IFS_VALUE_DEFAULT
},
854 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
855 r
= zd_iowrite32a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
859 return chip
->is_zd1211b
?
860 zd1211b_hw_init_hmac(chip
) : zd1211_hw_init_hmac(chip
);
869 static int get_aw_pt_bi(struct zd_chip
*chip
, struct aw_pt_bi
*s
)
872 static const zd_addr_t aw_pt_bi_addr
[] =
873 { CR_ATIM_WND_PERIOD
, CR_PRE_TBTT
, CR_BCN_INTERVAL
};
876 r
= zd_ioread32v_locked(chip
, values
, (const zd_addr_t
*)aw_pt_bi_addr
,
877 ARRAY_SIZE(aw_pt_bi_addr
));
879 memset(s
, 0, sizeof(*s
));
883 s
->atim_wnd_period
= values
[0];
884 s
->pre_tbtt
= values
[1];
885 s
->beacon_interval
= values
[2];
886 dev_dbg_f(zd_chip_dev(chip
), "aw %u pt %u bi %u\n",
887 s
->atim_wnd_period
, s
->pre_tbtt
, s
->beacon_interval
);
891 static int set_aw_pt_bi(struct zd_chip
*chip
, struct aw_pt_bi
*s
)
893 struct zd_ioreq32 reqs
[3];
895 if (s
->beacon_interval
<= 5)
896 s
->beacon_interval
= 5;
897 if (s
->pre_tbtt
< 4 || s
->pre_tbtt
>= s
->beacon_interval
)
898 s
->pre_tbtt
= s
->beacon_interval
- 1;
899 if (s
->atim_wnd_period
>= s
->pre_tbtt
)
900 s
->atim_wnd_period
= s
->pre_tbtt
- 1;
902 reqs
[0].addr
= CR_ATIM_WND_PERIOD
;
903 reqs
[0].value
= s
->atim_wnd_period
;
904 reqs
[1].addr
= CR_PRE_TBTT
;
905 reqs
[1].value
= s
->pre_tbtt
;
906 reqs
[2].addr
= CR_BCN_INTERVAL
;
907 reqs
[2].value
= s
->beacon_interval
;
909 dev_dbg_f(zd_chip_dev(chip
),
910 "aw %u pt %u bi %u\n", s
->atim_wnd_period
, s
->pre_tbtt
,
912 return zd_iowrite32a_locked(chip
, reqs
, ARRAY_SIZE(reqs
));
916 static int set_beacon_interval(struct zd_chip
*chip
, u32 interval
)
921 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
922 r
= get_aw_pt_bi(chip
, &s
);
925 s
.beacon_interval
= interval
;
926 return set_aw_pt_bi(chip
, &s
);
929 int zd_set_beacon_interval(struct zd_chip
*chip
, u32 interval
)
933 mutex_lock(&chip
->mutex
);
934 r
= set_beacon_interval(chip
, interval
);
935 mutex_unlock(&chip
->mutex
);
939 static int hw_init(struct zd_chip
*chip
)
943 dev_dbg_f(zd_chip_dev(chip
), "\n");
944 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
945 r
= hw_reset_phy(chip
);
949 r
= hw_init_hmac(chip
);
953 return set_beacon_interval(chip
, 100);
957 static int dump_cr(struct zd_chip
*chip
, const zd_addr_t addr
,
958 const char *addr_string
)
963 r
= zd_ioread32_locked(chip
, &value
, addr
);
965 dev_dbg_f(zd_chip_dev(chip
),
966 "error reading %s. Error number %d\n", addr_string
, r
);
970 dev_dbg_f(zd_chip_dev(chip
), "%s %#010x\n",
971 addr_string
, (unsigned int)value
);
975 static int test_init(struct zd_chip
*chip
)
979 r
= dump_cr(chip
, CR_AFTER_PNP
, "CR_AFTER_PNP");
982 r
= dump_cr(chip
, CR_GPI_EN
, "CR_GPI_EN");
985 return dump_cr(chip
, CR_INTERRUPT
, "CR_INTERRUPT");
988 static void dump_fw_registers(struct zd_chip
*chip
)
990 static const zd_addr_t addr
[4] = {
991 FW_FIRMWARE_VER
, FW_USB_SPEED
, FW_FIX_TX_RATE
,
998 r
= zd_ioread16v_locked(chip
, values
, (const zd_addr_t
*)addr
,
1001 dev_dbg_f(zd_chip_dev(chip
), "error %d zd_ioread16v_locked\n",
1006 dev_dbg_f(zd_chip_dev(chip
), "FW_FIRMWARE_VER %#06hx\n", values
[0]);
1007 dev_dbg_f(zd_chip_dev(chip
), "FW_USB_SPEED %#06hx\n", values
[1]);
1008 dev_dbg_f(zd_chip_dev(chip
), "FW_FIX_TX_RATE %#06hx\n", values
[2]);
1009 dev_dbg_f(zd_chip_dev(chip
), "FW_LINK_STATUS %#06hx\n", values
[3]);
1013 static int print_fw_version(struct zd_chip
*chip
)
1018 r
= zd_ioread16_locked(chip
, &version
, FW_FIRMWARE_VER
);
1022 dev_info(zd_chip_dev(chip
),"firmware version %04hx\n", version
);
1026 static int set_mandatory_rates(struct zd_chip
*chip
, enum ieee80211_std std
)
1029 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
1030 /* This sets the mandatory rates, which only depend from the standard
1031 * that the device is supporting. Until further notice we should try
1032 * to support 802.11g also for full speed USB.
1036 rates
= CR_RATE_1M
|CR_RATE_2M
|CR_RATE_5_5M
|CR_RATE_11M
;
1039 rates
= CR_RATE_1M
|CR_RATE_2M
|CR_RATE_5_5M
|CR_RATE_11M
|
1040 CR_RATE_6M
|CR_RATE_12M
|CR_RATE_24M
;
1045 return zd_iowrite32_locked(chip
, rates
, CR_MANDATORY_RATE_TBL
);
1048 int zd_chip_set_rts_cts_rate_locked(struct zd_chip
*chip
,
1049 u8 rts_rate
, int preamble
)
1051 int rts_mod
= ZD_RX_CCK
;
1054 /* Modulation bit */
1055 if (ZD_CS_TYPE(rts_rate
) == ZD_CS_OFDM
)
1056 rts_mod
= ZD_RX_OFDM
;
1058 dev_dbg_f(zd_chip_dev(chip
), "rts_rate=%x preamble=%x\n",
1059 rts_rate
, preamble
);
1061 value
|= rts_rate
<< RTSCTS_SH_RTS_RATE
;
1062 value
|= rts_mod
<< RTSCTS_SH_RTS_MOD_TYPE
;
1063 value
|= preamble
<< RTSCTS_SH_RTS_PMB_TYPE
;
1064 value
|= preamble
<< RTSCTS_SH_CTS_PMB_TYPE
;
1066 /* We always send 11M self-CTS messages, like the vendor driver. */
1067 value
|= ZD_CCK_RATE_11M
<< RTSCTS_SH_CTS_RATE
;
1068 value
|= ZD_RX_CCK
<< RTSCTS_SH_CTS_MOD_TYPE
;
1070 return zd_iowrite32_locked(chip
, value
, CR_RTS_CTS_RATE
);
1073 int zd_chip_enable_hwint(struct zd_chip
*chip
)
1077 mutex_lock(&chip
->mutex
);
1078 r
= zd_iowrite32_locked(chip
, HWINT_ENABLED
, CR_INTERRUPT
);
1079 mutex_unlock(&chip
->mutex
);
1083 static int disable_hwint(struct zd_chip
*chip
)
1085 return zd_iowrite32_locked(chip
, HWINT_DISABLED
, CR_INTERRUPT
);
1088 int zd_chip_disable_hwint(struct zd_chip
*chip
)
1092 mutex_lock(&chip
->mutex
);
1093 r
= disable_hwint(chip
);
1094 mutex_unlock(&chip
->mutex
);
1098 int zd_chip_init_hw(struct zd_chip
*chip
, u8 device_type
)
1103 dev_dbg_f(zd_chip_dev(chip
), "\n");
1105 mutex_lock(&chip
->mutex
);
1106 chip
->is_zd1211b
= (device_type
== DEVICE_ZD1211B
) != 0;
1109 r
= test_init(chip
);
1113 r
= zd_iowrite32_locked(chip
, 1, CR_AFTER_PNP
);
1117 r
= zd_usb_init_hw(&chip
->usb
);
1121 /* GPI is always disabled, also in the other driver.
1123 r
= zd_iowrite32_locked(chip
, 0, CR_GPI_EN
);
1126 r
= zd_iowrite32_locked(chip
, CWIN_SIZE
, CR_CWMIN_CWMAX
);
1129 /* Currently we support IEEE 802.11g for full and high speed USB.
1130 * It might be discussed, whether we should suppport pure b mode for
1133 r
= set_mandatory_rates(chip
, IEEE80211G
);
1136 /* Disabling interrupts is certainly a smart thing here.
1138 r
= disable_hwint(chip
);
1141 r
= read_pod(chip
, &rf_type
);
1147 r
= zd_rf_init_hw(&chip
->rf
, rf_type
);
1151 r
= print_fw_version(chip
);
1156 dump_fw_registers(chip
);
1157 r
= test_init(chip
);
1162 r
= read_e2p_mac_addr(chip
);
1166 r
= read_cal_int_tables(chip
);
1172 mutex_unlock(&chip
->mutex
);
1176 static int update_pwr_int(struct zd_chip
*chip
, u8 channel
)
1178 u8 value
= chip
->pwr_int_values
[channel
- 1];
1179 dev_dbg_f(zd_chip_dev(chip
), "channel %d pwr_int %#04x\n",
1181 return zd_iowrite16_locked(chip
, value
, CR31
);
1184 static int update_pwr_cal(struct zd_chip
*chip
, u8 channel
)
1186 u8 value
= chip
->pwr_cal_values
[channel
-1];
1187 dev_dbg_f(zd_chip_dev(chip
), "channel %d pwr_cal %#04x\n",
1189 return zd_iowrite16_locked(chip
, value
, CR68
);
1192 static int update_ofdm_cal(struct zd_chip
*chip
, u8 channel
)
1194 struct zd_ioreq16 ioreqs
[3];
1196 ioreqs
[0].addr
= CR67
;
1197 ioreqs
[0].value
= chip
->ofdm_cal_values
[OFDM_36M_INDEX
][channel
-1];
1198 ioreqs
[1].addr
= CR66
;
1199 ioreqs
[1].value
= chip
->ofdm_cal_values
[OFDM_48M_INDEX
][channel
-1];
1200 ioreqs
[2].addr
= CR65
;
1201 ioreqs
[2].value
= chip
->ofdm_cal_values
[OFDM_54M_INDEX
][channel
-1];
1203 dev_dbg_f(zd_chip_dev(chip
),
1204 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1205 channel
, ioreqs
[0].value
, ioreqs
[1].value
, ioreqs
[2].value
);
1206 return zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
1209 static int update_channel_integration_and_calibration(struct zd_chip
*chip
,
1214 r
= update_pwr_int(chip
, channel
);
1217 if (chip
->is_zd1211b
) {
1218 static const struct zd_ioreq16 ioreqs
[] = {
1224 r
= update_ofdm_cal(chip
, channel
);
1227 r
= update_pwr_cal(chip
, channel
);
1230 r
= zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
1238 /* The CCK baseband gain can be optionally patched by the EEPROM */
1239 static int patch_cck_gain(struct zd_chip
*chip
)
1244 if (!chip
->patch_cck_gain
)
1247 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
1248 r
= zd_ioread32_locked(chip
, &value
, E2P_PHY_REG
);
1251 dev_dbg_f(zd_chip_dev(chip
), "patching value %x\n", value
& 0xff);
1252 return zd_iowrite16_locked(chip
, value
& 0xff, CR47
);
1255 int zd_chip_set_channel(struct zd_chip
*chip
, u8 channel
)
1259 mutex_lock(&chip
->mutex
);
1260 r
= zd_chip_lock_phy_regs(chip
);
1263 r
= zd_rf_set_channel(&chip
->rf
, channel
);
1266 r
= update_channel_integration_and_calibration(chip
, channel
);
1269 r
= patch_cck_gain(chip
);
1272 r
= patch_6m_band_edge(chip
, channel
);
1275 r
= zd_iowrite32_locked(chip
, 0, CR_CONFIG_PHILIPS
);
1277 t
= zd_chip_unlock_phy_regs(chip
);
1281 mutex_unlock(&chip
->mutex
);
1285 u8
zd_chip_get_channel(struct zd_chip
*chip
)
1289 mutex_lock(&chip
->mutex
);
1290 channel
= chip
->rf
.channel
;
1291 mutex_unlock(&chip
->mutex
);
1295 int zd_chip_control_leds(struct zd_chip
*chip
, enum led_status status
)
1297 static const zd_addr_t a
[] = {
1303 u16 v
[ARRAY_SIZE(a
)];
1304 struct zd_ioreq16 ioreqs
[ARRAY_SIZE(a
)] = {
1305 [0] = { FW_LINK_STATUS
},
1310 mutex_lock(&chip
->mutex
);
1311 r
= zd_ioread16v_locked(chip
, v
, (const zd_addr_t
*)a
, ARRAY_SIZE(a
));
1315 other_led
= chip
->link_led
== LED1
? LED2
: LED1
;
1319 ioreqs
[0].value
= FW_LINK_OFF
;
1320 ioreqs
[1].value
= v
[1] & ~(LED1
|LED2
);
1323 ioreqs
[0].value
= FW_LINK_OFF
;
1324 ioreqs
[1].value
= v
[1] & ~other_led
;
1325 if (get_seconds() % 3 == 0) {
1326 ioreqs
[1].value
&= ~chip
->link_led
;
1328 ioreqs
[1].value
|= chip
->link_led
;
1331 case LED_ASSOCIATED
:
1332 ioreqs
[0].value
= FW_LINK_TX
;
1333 ioreqs
[1].value
= v
[1] & ~other_led
;
1334 ioreqs
[1].value
|= chip
->link_led
;
1341 if (v
[0] != ioreqs
[0].value
|| v
[1] != ioreqs
[1].value
) {
1342 r
= zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
1348 mutex_unlock(&chip
->mutex
);
1352 int zd_chip_set_basic_rates_locked(struct zd_chip
*chip
, u16 cr_rates
)
1354 ZD_ASSERT((cr_rates
& ~(CR_RATES_80211B
| CR_RATES_80211G
)) == 0);
1355 dev_dbg_f(zd_chip_dev(chip
), "%x\n", cr_rates
);
1357 return zd_iowrite32_locked(chip
, cr_rates
, CR_BASIC_RATE_TBL
);
1360 static int ofdm_qual_db(u8 status_quality
, u8 rate
, unsigned int size
)
1362 static const u16 constants
[] = {
1363 715, 655, 585, 540, 470, 410, 360, 315,
1364 270, 235, 205, 175, 150, 125, 105, 85,
1371 /* It seems that their quality parameter is somehow per signal
1372 * and is now transferred per bit.
1375 case ZD_OFDM_RATE_6M
:
1376 case ZD_OFDM_RATE_12M
:
1377 case ZD_OFDM_RATE_24M
:
1380 case ZD_OFDM_RATE_9M
:
1381 case ZD_OFDM_RATE_18M
:
1382 case ZD_OFDM_RATE_36M
:
1383 case ZD_OFDM_RATE_54M
:
1387 case ZD_OFDM_RATE_48M
:
1395 x
= (10000 * status_quality
)/size
;
1396 for (i
= 0; i
< ARRAY_SIZE(constants
); i
++) {
1397 if (x
> constants
[i
])
1402 case ZD_OFDM_RATE_6M
:
1403 case ZD_OFDM_RATE_9M
:
1406 case ZD_OFDM_RATE_12M
:
1407 case ZD_OFDM_RATE_18M
:
1410 case ZD_OFDM_RATE_24M
:
1411 case ZD_OFDM_RATE_36M
:
1414 case ZD_OFDM_RATE_48M
:
1415 case ZD_OFDM_RATE_54M
:
1425 static int ofdm_qual_percent(u8 status_quality
, u8 rate
, unsigned int size
)
1429 r
= ofdm_qual_db(status_quality
, rate
, size
);
1435 return r
<= 100 ? r
: 100;
1438 static unsigned int log10times100(unsigned int x
)
1440 static const u8 log10
[] = {
1442 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1443 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1444 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1445 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1446 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1447 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1448 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1449 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1450 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1451 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1452 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1453 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1454 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1455 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1456 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1457 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1458 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1459 223, 223, 223, 224, 224, 224, 224,
1462 return x
< ARRAY_SIZE(log10
) ? log10
[x
] : 225;
1466 MAX_CCK_EVM_DB
= 45,
1469 static int cck_evm_db(u8 status_quality
)
1471 return (20 * log10times100(status_quality
)) / 100;
1474 static int cck_snr_db(u8 status_quality
)
1476 int r
= MAX_CCK_EVM_DB
- cck_evm_db(status_quality
);
1481 static int cck_qual_percent(u8 status_quality
)
1485 r
= cck_snr_db(status_quality
);
1487 return r
<= 100 ? r
: 100;
1490 u8
zd_rx_qual_percent(const void *rx_frame
, unsigned int size
,
1491 const struct rx_status
*status
)
1493 return (status
->frame_status
&ZD_RX_OFDM
) ?
1494 ofdm_qual_percent(status
->signal_quality_ofdm
,
1495 zd_ofdm_plcp_header_rate(rx_frame
),
1497 cck_qual_percent(status
->signal_quality_cck
);
1500 u8
zd_rx_strength_percent(u8 rssi
)
1502 int r
= (rssi
*100) / 41;
1508 u16
zd_rx_rate(const void *rx_frame
, const struct rx_status
*status
)
1510 static const u16 ofdm_rates
[] = {
1511 [ZD_OFDM_RATE_6M
] = 60,
1512 [ZD_OFDM_RATE_9M
] = 90,
1513 [ZD_OFDM_RATE_12M
] = 120,
1514 [ZD_OFDM_RATE_18M
] = 180,
1515 [ZD_OFDM_RATE_24M
] = 240,
1516 [ZD_OFDM_RATE_36M
] = 360,
1517 [ZD_OFDM_RATE_48M
] = 480,
1518 [ZD_OFDM_RATE_54M
] = 540,
1521 if (status
->frame_status
& ZD_RX_OFDM
) {
1522 u8 ofdm_rate
= zd_ofdm_plcp_header_rate(rx_frame
);
1523 rate
= ofdm_rates
[ofdm_rate
& 0xf];
1525 u8 cck_rate
= zd_cck_plcp_header_rate(rx_frame
);
1527 case ZD_CCK_SIGNAL_1M
:
1530 case ZD_CCK_SIGNAL_2M
:
1533 case ZD_CCK_SIGNAL_5M5
:
1536 case ZD_CCK_SIGNAL_11M
:
1547 int zd_chip_switch_radio_on(struct zd_chip
*chip
)
1551 mutex_lock(&chip
->mutex
);
1552 r
= zd_switch_radio_on(&chip
->rf
);
1553 mutex_unlock(&chip
->mutex
);
1557 int zd_chip_switch_radio_off(struct zd_chip
*chip
)
1561 mutex_lock(&chip
->mutex
);
1562 r
= zd_switch_radio_off(&chip
->rf
);
1563 mutex_unlock(&chip
->mutex
);
1567 int zd_chip_enable_int(struct zd_chip
*chip
)
1571 mutex_lock(&chip
->mutex
);
1572 r
= zd_usb_enable_int(&chip
->usb
);
1573 mutex_unlock(&chip
->mutex
);
1577 void zd_chip_disable_int(struct zd_chip
*chip
)
1579 mutex_lock(&chip
->mutex
);
1580 zd_usb_disable_int(&chip
->usb
);
1581 mutex_unlock(&chip
->mutex
);
1584 int zd_chip_enable_rx(struct zd_chip
*chip
)
1588 mutex_lock(&chip
->mutex
);
1589 r
= zd_usb_enable_rx(&chip
->usb
);
1590 mutex_unlock(&chip
->mutex
);
1594 void zd_chip_disable_rx(struct zd_chip
*chip
)
1596 mutex_lock(&chip
->mutex
);
1597 zd_usb_disable_rx(&chip
->usb
);
1598 mutex_unlock(&chip
->mutex
);
1601 int zd_rfwritev_locked(struct zd_chip
*chip
,
1602 const u32
* values
, unsigned int count
, u8 bits
)
1607 for (i
= 0; i
< count
; i
++) {
1608 r
= zd_rfwrite_locked(chip
, values
[i
], bits
);
1617 * We can optionally program the RF directly through CR regs, if supported by
1618 * the hardware. This is much faster than the older method.
1620 int zd_rfwrite_cr_locked(struct zd_chip
*chip
, u32 value
)
1622 struct zd_ioreq16 ioreqs
[] = {
1623 { CR244
, (value
>> 16) & 0xff },
1624 { CR243
, (value
>> 8) & 0xff },
1625 { CR242
, value
& 0xff },
1627 ZD_ASSERT(mutex_is_locked(&chip
->mutex
));
1628 return zd_iowrite16a_locked(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));
1631 int zd_rfwritev_cr_locked(struct zd_chip
*chip
,
1632 const u32
*values
, unsigned int count
)
1637 for (i
= 0; i
< count
; i
++) {
1638 r
= zd_rfwrite_cr_locked(chip
, values
[i
]);
1646 int zd_chip_set_multicast_hash(struct zd_chip
*chip
,
1647 struct zd_mc_hash
*hash
)
1649 struct zd_ioreq32 ioreqs
[] = {
1650 { CR_GROUP_HASH_P1
, hash
->low
},
1651 { CR_GROUP_HASH_P2
, hash
->high
},
1654 dev_dbg_f(zd_chip_dev(chip
), "hash l 0x%08x h 0x%08x\n",
1655 ioreqs
[0].value
, ioreqs
[1].value
);
1656 return zd_iowrite32a(chip
, ioreqs
, ARRAY_SIZE(ioreqs
));