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KVM: Don't spam kernel log when injecting exceptions due to bad cr writes
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / x86.c
blob1b880f8720d2cdf1b66b6a67050a396e01534ca9
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 #include <linux/kvm_host.h>
22 #include "irq.h"
23 #include "mmu.h"
24 #include "i8254.h"
25 #include "tss.h"
26 #include "kvm_cache_regs.h"
27 #include "x86.h"
28
29 #include <linux/clocksource.h>
30 #include <linux/interrupt.h>
31 #include <linux/kvm.h>
32 #include <linux/fs.h>
33 #include <linux/vmalloc.h>
34 #include <linux/module.h>
35 #include <linux/mman.h>
36 #include <linux/highmem.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/cpufreq.h>
40 #include <linux/user-return-notifier.h>
41 #include <trace/events/kvm.h>
42 #undef TRACE_INCLUDE_FILE
43 #define CREATE_TRACE_POINTS
44 #include "trace.h"
45
46 #include <asm/debugreg.h>
47 #include <asm/uaccess.h>
48 #include <asm/msr.h>
49 #include <asm/desc.h>
50 #include <asm/mtrr.h>
51 #include <asm/mce.h>
52
53 #define MAX_IO_MSRS 256
54 #define CR0_RESERVED_BITS \
55 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
56 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
57 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
58 #define CR4_RESERVED_BITS \
59 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
60 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
61 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
62 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
63
64 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
65
66 #define KVM_MAX_MCE_BANKS 32
67 #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
68
69 /* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73 #ifdef CONFIG_X86_64
74 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
75 #else
76 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
77 #endif
78
79 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
80 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
81
82 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
83 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
84 struct kvm_cpuid_entry2 __user *entries);
85
86 struct kvm_x86_ops *kvm_x86_ops;
87 EXPORT_SYMBOL_GPL(kvm_x86_ops);
88
89 int ignore_msrs = 0;
90 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
91
92 #define KVM_NR_SHARED_MSRS 16
93
94 struct kvm_shared_msrs_global {
95 int nr;
96 struct kvm_shared_msr {
97 u32 msr;
98 u64 value;
99 } msrs[KVM_NR_SHARED_MSRS];
100 };
101
102 struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
105 u64 current_value[KVM_NR_SHARED_MSRS];
106 };
107
108 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
109 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
110
111 struct kvm_stats_debugfs_item debugfs_entries[] = {
112 { "pf_fixed", VCPU_STAT(pf_fixed) },
113 { "pf_guest", VCPU_STAT(pf_guest) },
114 { "tlb_flush", VCPU_STAT(tlb_flush) },
115 { "invlpg", VCPU_STAT(invlpg) },
116 { "exits", VCPU_STAT(exits) },
117 { "io_exits", VCPU_STAT(io_exits) },
118 { "mmio_exits", VCPU_STAT(mmio_exits) },
119 { "signal_exits", VCPU_STAT(signal_exits) },
120 { "irq_window", VCPU_STAT(irq_window_exits) },
121 { "nmi_window", VCPU_STAT(nmi_window_exits) },
122 { "halt_exits", VCPU_STAT(halt_exits) },
123 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
124 { "hypercalls", VCPU_STAT(hypercalls) },
125 { "request_irq", VCPU_STAT(request_irq_exits) },
126 { "irq_exits", VCPU_STAT(irq_exits) },
127 { "host_state_reload", VCPU_STAT(host_state_reload) },
128 { "efer_reload", VCPU_STAT(efer_reload) },
129 { "fpu_reload", VCPU_STAT(fpu_reload) },
130 { "insn_emulation", VCPU_STAT(insn_emulation) },
131 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
132 { "irq_injections", VCPU_STAT(irq_injections) },
133 { "nmi_injections", VCPU_STAT(nmi_injections) },
134 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
135 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
136 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
137 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
138 { "mmu_flooded", VM_STAT(mmu_flooded) },
139 { "mmu_recycled", VM_STAT(mmu_recycled) },
140 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
141 { "mmu_unsync", VM_STAT(mmu_unsync) },
142 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
143 { "largepages", VM_STAT(lpages) },
144 { NULL }
145 };
146
147 static void kvm_on_user_return(struct user_return_notifier *urn)
148 {
149 unsigned slot;
150 struct kvm_shared_msr *global;
151 struct kvm_shared_msrs *locals
152 = container_of(urn, struct kvm_shared_msrs, urn);
153
154 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
155 global = &shared_msrs_global.msrs[slot];
156 if (global->value != locals->current_value[slot]) {
157 wrmsrl(global->msr, global->value);
158 locals->current_value[slot] = global->value;
159 }
160 }
161 locals->registered = false;
162 user_return_notifier_unregister(urn);
163 }
164
165 void kvm_define_shared_msr(unsigned slot, u32 msr)
166 {
167 int cpu;
168 u64 value;
169
170 if (slot >= shared_msrs_global.nr)
171 shared_msrs_global.nr = slot + 1;
172 shared_msrs_global.msrs[slot].msr = msr;
173 rdmsrl_safe(msr, &value);
174 shared_msrs_global.msrs[slot].value = value;
175 for_each_online_cpu(cpu)
176 per_cpu(shared_msrs, cpu).current_value[slot] = value;
177 }
178 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
179
180 static void kvm_shared_msr_cpu_online(void)
181 {
182 unsigned i;
183 struct kvm_shared_msrs *locals = &__get_cpu_var(shared_msrs);
184
185 for (i = 0; i < shared_msrs_global.nr; ++i)
186 locals->current_value[i] = shared_msrs_global.msrs[i].value;
187 }
188
189 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
190 {
191 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
192
193 if (((value ^ smsr->current_value[slot]) & mask) == 0)
194 return;
195 smsr->current_value[slot] = value;
196 wrmsrl(shared_msrs_global.msrs[slot].msr, value);
197 if (!smsr->registered) {
198 smsr->urn.on_user_return = kvm_on_user_return;
199 user_return_notifier_register(&smsr->urn);
200 smsr->registered = true;
201 }
202 }
203 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
204
205 static void drop_user_return_notifiers(void *ignore)
206 {
207 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
208
209 if (smsr->registered)
210 kvm_on_user_return(&smsr->urn);
211 }
212
213 unsigned long segment_base(u16 selector)
214 {
215 struct descriptor_table gdt;
216 struct desc_struct *d;
217 unsigned long table_base;
218 unsigned long v;
219
220 if (selector == 0)
221 return 0;
222
223 kvm_get_gdt(&gdt);
224 table_base = gdt.base;
225
226 if (selector & 4) { /* from ldt */
227 u16 ldt_selector = kvm_read_ldt();
228
229 table_base = segment_base(ldt_selector);
230 }
231 d = (struct desc_struct *)(table_base + (selector & ~7));
232 v = get_desc_base(d);
233 #ifdef CONFIG_X86_64
234 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
235 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
236 #endif
237 return v;
238 }
239 EXPORT_SYMBOL_GPL(segment_base);
240
241 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
242 {
243 if (irqchip_in_kernel(vcpu->kvm))
244 return vcpu->arch.apic_base;
245 else
246 return vcpu->arch.apic_base;
247 }
248 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
249
250 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
251 {
252 /* TODO: reserve bits check */
253 if (irqchip_in_kernel(vcpu->kvm))
254 kvm_lapic_set_base(vcpu, data);
255 else
256 vcpu->arch.apic_base = data;
257 }
258 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
260 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
261 {
262 WARN_ON(vcpu->arch.exception.pending);
263 vcpu->arch.exception.pending = true;
264 vcpu->arch.exception.has_error_code = false;
265 vcpu->arch.exception.nr = nr;
266 }
267 EXPORT_SYMBOL_GPL(kvm_queue_exception);
268
269 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
270 u32 error_code)
271 {
272 ++vcpu->stat.pf_guest;
273
274 if (vcpu->arch.exception.pending) {
275 switch(vcpu->arch.exception.nr) {
276 case DF_VECTOR:
277 /* triple fault -> shutdown */
278 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
279 return;
280 case PF_VECTOR:
281 vcpu->arch.exception.nr = DF_VECTOR;
282 vcpu->arch.exception.error_code = 0;
283 return;
284 default:
285 /* replace previous exception with a new one in a hope
286 that instruction re-execution will regenerate lost
287 exception */
288 vcpu->arch.exception.pending = false;
289 break;
290 }
291 }
292 vcpu->arch.cr2 = addr;
293 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
294 }
295
296 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
297 {
298 vcpu->arch.nmi_pending = 1;
299 }
300 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
301
302 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
303 {
304 WARN_ON(vcpu->arch.exception.pending);
305 vcpu->arch.exception.pending = true;
306 vcpu->arch.exception.has_error_code = true;
307 vcpu->arch.exception.nr = nr;
308 vcpu->arch.exception.error_code = error_code;
309 }
310 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
311
312 /*
313 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
314 * a #GP and return false.
315 */
316 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
317 {
318 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
319 return true;
320 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
321 return false;
322 }
323 EXPORT_SYMBOL_GPL(kvm_require_cpl);
324
325 /*
326 * Load the pae pdptrs. Return true is they are all valid.
327 */
328 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
329 {
330 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
331 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
332 int i;
333 int ret;
334 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
335
336 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
337 offset * sizeof(u64), sizeof(pdpte));
338 if (ret < 0) {
339 ret = 0;
340 goto out;
341 }
342 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
343 if (is_present_gpte(pdpte[i]) &&
344 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
345 ret = 0;
346 goto out;
347 }
348 }
349 ret = 1;
350
351 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
352 __set_bit(VCPU_EXREG_PDPTR,
353 (unsigned long *)&vcpu->arch.regs_avail);
354 __set_bit(VCPU_EXREG_PDPTR,
355 (unsigned long *)&vcpu->arch.regs_dirty);
356 out:
357
358 return ret;
359 }
360 EXPORT_SYMBOL_GPL(load_pdptrs);
361
362 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
363 {
364 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
365 bool changed = true;
366 int r;
367
368 if (is_long_mode(vcpu) || !is_pae(vcpu))
369 return false;
370
371 if (!test_bit(VCPU_EXREG_PDPTR,
372 (unsigned long *)&vcpu->arch.regs_avail))
373 return true;
374
375 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
376 if (r < 0)
377 goto out;
378 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
379 out:
380
381 return changed;
382 }
383
384 void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
385 {
386 if (cr0 & CR0_RESERVED_BITS) {
387 kvm_inject_gp(vcpu, 0);
388 return;
389 }
390
391 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
392 kvm_inject_gp(vcpu, 0);
393 return;
394 }
395
396 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
397 kvm_inject_gp(vcpu, 0);
398 return;
399 }
400
401 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
402 #ifdef CONFIG_X86_64
403 if ((vcpu->arch.shadow_efer & EFER_LME)) {
404 int cs_db, cs_l;
405
406 if (!is_pae(vcpu)) {
407 kvm_inject_gp(vcpu, 0);
408 return;
409 }
410 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
411 if (cs_l) {
412 kvm_inject_gp(vcpu, 0);
413 return;
414
415 }
416 } else
417 #endif
418 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
419 kvm_inject_gp(vcpu, 0);
420 return;
421 }
422
423 }
424
425 kvm_x86_ops->set_cr0(vcpu, cr0);
426 vcpu->arch.cr0 = cr0;
427
428 kvm_mmu_reset_context(vcpu);
429 return;
430 }
431 EXPORT_SYMBOL_GPL(kvm_set_cr0);
432
433 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
434 {
435 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
436 }
437 EXPORT_SYMBOL_GPL(kvm_lmsw);
438
439 void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
440 {
441 unsigned long old_cr4 = vcpu->arch.cr4;
442 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
443
444 if (cr4 & CR4_RESERVED_BITS) {
445 kvm_inject_gp(vcpu, 0);
446 return;
447 }
448
449 if (is_long_mode(vcpu)) {
450 if (!(cr4 & X86_CR4_PAE)) {
451 kvm_inject_gp(vcpu, 0);
452 return;
453 }
454 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
455 && ((cr4 ^ old_cr4) & pdptr_bits)
456 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
457 kvm_inject_gp(vcpu, 0);
458 return;
459 }
460
461 if (cr4 & X86_CR4_VMXE) {
462 kvm_inject_gp(vcpu, 0);
463 return;
464 }
465 kvm_x86_ops->set_cr4(vcpu, cr4);
466 vcpu->arch.cr4 = cr4;
467 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
468 kvm_mmu_reset_context(vcpu);
469 }
470 EXPORT_SYMBOL_GPL(kvm_set_cr4);
471
472 void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
473 {
474 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
475 kvm_mmu_sync_roots(vcpu);
476 kvm_mmu_flush_tlb(vcpu);
477 return;
478 }
479
480 if (is_long_mode(vcpu)) {
481 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
482 kvm_inject_gp(vcpu, 0);
483 return;
484 }
485 } else {
486 if (is_pae(vcpu)) {
487 if (cr3 & CR3_PAE_RESERVED_BITS) {
488 kvm_inject_gp(vcpu, 0);
489 return;
490 }
491 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
492 kvm_inject_gp(vcpu, 0);
493 return;
494 }
495 }
496 /*
497 * We don't check reserved bits in nonpae mode, because
498 * this isn't enforced, and VMware depends on this.
499 */
500 }
501
502 /*
503 * Does the new cr3 value map to physical memory? (Note, we
504 * catch an invalid cr3 even in real-mode, because it would
505 * cause trouble later on when we turn on paging anyway.)
506 *
507 * A real CPU would silently accept an invalid cr3 and would
508 * attempt to use it - with largely undefined (and often hard
509 * to debug) behavior on the guest side.
510 */
511 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
512 kvm_inject_gp(vcpu, 0);
513 else {
514 vcpu->arch.cr3 = cr3;
515 vcpu->arch.mmu.new_cr3(vcpu);
516 }
517 }
518 EXPORT_SYMBOL_GPL(kvm_set_cr3);
519
520 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
521 {
522 if (cr8 & CR8_RESERVED_BITS) {
523 kvm_inject_gp(vcpu, 0);
524 return;
525 }
526 if (irqchip_in_kernel(vcpu->kvm))
527 kvm_lapic_set_tpr(vcpu, cr8);
528 else
529 vcpu->arch.cr8 = cr8;
530 }
531 EXPORT_SYMBOL_GPL(kvm_set_cr8);
532
533 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
534 {
535 if (irqchip_in_kernel(vcpu->kvm))
536 return kvm_lapic_get_cr8(vcpu);
537 else
538 return vcpu->arch.cr8;
539 }
540 EXPORT_SYMBOL_GPL(kvm_get_cr8);
541
542 static inline u32 bit(int bitno)
543 {
544 return 1 << (bitno & 31);
545 }
546
547 /*
548 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
549 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
550 *
551 * This list is modified at module load time to reflect the
552 * capabilities of the host cpu. This capabilities test skips MSRs that are
553 * kvm-specific. Those are put in the beginning of the list.
554 */
555
556 #define KVM_SAVE_MSRS_BEGIN 2
557 static u32 msrs_to_save[] = {
558 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
559 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
560 MSR_K6_STAR,
561 #ifdef CONFIG_X86_64
562 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
563 #endif
564 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
565 };
566
567 static unsigned num_msrs_to_save;
568
569 static u32 emulated_msrs[] = {
570 MSR_IA32_MISC_ENABLE,
571 };
572
573 static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
574 {
575 if (efer & efer_reserved_bits) {
576 kvm_inject_gp(vcpu, 0);
577 return;
578 }
579
580 if (is_paging(vcpu)
581 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
582 kvm_inject_gp(vcpu, 0);
583 return;
584 }
585
586 if (efer & EFER_FFXSR) {
587 struct kvm_cpuid_entry2 *feat;
588
589 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
590 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
591 kvm_inject_gp(vcpu, 0);
592 return;
593 }
594 }
595
596 if (efer & EFER_SVME) {
597 struct kvm_cpuid_entry2 *feat;
598
599 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
600 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
601 kvm_inject_gp(vcpu, 0);
602 return;
603 }
604 }
605
606 kvm_x86_ops->set_efer(vcpu, efer);
607
608 efer &= ~EFER_LMA;
609 efer |= vcpu->arch.shadow_efer & EFER_LMA;
610
611 vcpu->arch.shadow_efer = efer;
612
613 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
614 kvm_mmu_reset_context(vcpu);
615 }
616
617 void kvm_enable_efer_bits(u64 mask)
618 {
619 efer_reserved_bits &= ~mask;
620 }
621 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
622
623
624 /*
625 * Writes msr value into into the appropriate "register".
626 * Returns 0 on success, non-0 otherwise.
627 * Assumes vcpu_load() was already called.
628 */
629 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
630 {
631 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
632 }
633
634 /*
635 * Adapt set_msr() to msr_io()'s calling convention
636 */
637 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
638 {
639 return kvm_set_msr(vcpu, index, *data);
640 }
641
642 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
643 {
644 static int version;
645 struct pvclock_wall_clock wc;
646 struct timespec boot;
647
648 if (!wall_clock)
649 return;
650
651 version++;
652
653 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
654
655 /*
656 * The guest calculates current wall clock time by adding
657 * system time (updated by kvm_write_guest_time below) to the
658 * wall clock specified here. guest system time equals host
659 * system time for us, thus we must fill in host boot time here.
660 */
661 getboottime(&boot);
662
663 wc.sec = boot.tv_sec;
664 wc.nsec = boot.tv_nsec;
665 wc.version = version;
666
667 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
668
669 version++;
670 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
671 }
672
673 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
674 {
675 uint32_t quotient, remainder;
676
677 /* Don't try to replace with do_div(), this one calculates
678 * "(dividend << 32) / divisor" */
679 __asm__ ( "divl %4"
680 : "=a" (quotient), "=d" (remainder)
681 : "0" (0), "1" (dividend), "r" (divisor) );
682 return quotient;
683 }
684
685 static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
686 {
687 uint64_t nsecs = 1000000000LL;
688 int32_t shift = 0;
689 uint64_t tps64;
690 uint32_t tps32;
691
692 tps64 = tsc_khz * 1000LL;
693 while (tps64 > nsecs*2) {
694 tps64 >>= 1;
695 shift--;
696 }
697
698 tps32 = (uint32_t)tps64;
699 while (tps32 <= (uint32_t)nsecs) {
700 tps32 <<= 1;
701 shift++;
702 }
703
704 hv_clock->tsc_shift = shift;
705 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
706
707 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
708 __func__, tsc_khz, hv_clock->tsc_shift,
709 hv_clock->tsc_to_system_mul);
710 }
711
712 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
713
714 static void kvm_write_guest_time(struct kvm_vcpu *v)
715 {
716 struct timespec ts;
717 unsigned long flags;
718 struct kvm_vcpu_arch *vcpu = &v->arch;
719 void *shared_kaddr;
720 unsigned long this_tsc_khz;
721
722 if ((!vcpu->time_page))
723 return;
724
725 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
726 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
727 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
728 vcpu->hv_clock_tsc_khz = this_tsc_khz;
729 }
730 put_cpu_var(cpu_tsc_khz);
731
732 /* Keep irq disabled to prevent changes to the clock */
733 local_irq_save(flags);
734 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
735 ktime_get_ts(&ts);
736 monotonic_to_bootbased(&ts);
737 local_irq_restore(flags);
738
739 /* With all the info we got, fill in the values */
740
741 vcpu->hv_clock.system_time = ts.tv_nsec +
742 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
743
744 /*
745 * The interface expects us to write an even number signaling that the
746 * update is finished. Since the guest won't see the intermediate
747 * state, we just increase by 2 at the end.
748 */
749 vcpu->hv_clock.version += 2;
750
751 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
752
753 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
754 sizeof(vcpu->hv_clock));
755
756 kunmap_atomic(shared_kaddr, KM_USER0);
757
758 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
759 }
760
761 static int kvm_request_guest_time_update(struct kvm_vcpu *v)
762 {
763 struct kvm_vcpu_arch *vcpu = &v->arch;
764
765 if (!vcpu->time_page)
766 return 0;
767 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
768 return 1;
769 }
770
771 static bool msr_mtrr_valid(unsigned msr)
772 {
773 switch (msr) {
774 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
775 case MSR_MTRRfix64K_00000:
776 case MSR_MTRRfix16K_80000:
777 case MSR_MTRRfix16K_A0000:
778 case MSR_MTRRfix4K_C0000:
779 case MSR_MTRRfix4K_C8000:
780 case MSR_MTRRfix4K_D0000:
781 case MSR_MTRRfix4K_D8000:
782 case MSR_MTRRfix4K_E0000:
783 case MSR_MTRRfix4K_E8000:
784 case MSR_MTRRfix4K_F0000:
785 case MSR_MTRRfix4K_F8000:
786 case MSR_MTRRdefType:
787 case MSR_IA32_CR_PAT:
788 return true;
789 case 0x2f8:
790 return true;
791 }
792 return false;
793 }
794
795 static bool valid_pat_type(unsigned t)
796 {
797 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
798 }
799
800 static bool valid_mtrr_type(unsigned t)
801 {
802 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
803 }
804
805 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
806 {
807 int i;
808
809 if (!msr_mtrr_valid(msr))
810 return false;
811
812 if (msr == MSR_IA32_CR_PAT) {
813 for (i = 0; i < 8; i++)
814 if (!valid_pat_type((data >> (i * 8)) & 0xff))
815 return false;
816 return true;
817 } else if (msr == MSR_MTRRdefType) {
818 if (data & ~0xcff)
819 return false;
820 return valid_mtrr_type(data & 0xff);
821 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
822 for (i = 0; i < 8 ; i++)
823 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
824 return false;
825 return true;
826 }
827
828 /* variable MTRRs */
829 return valid_mtrr_type(data & 0xff);
830 }
831
832 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
833 {
834 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
835
836 if (!mtrr_valid(vcpu, msr, data))
837 return 1;
838
839 if (msr == MSR_MTRRdefType) {
840 vcpu->arch.mtrr_state.def_type = data;
841 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
842 } else if (msr == MSR_MTRRfix64K_00000)
843 p[0] = data;
844 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
845 p[1 + msr - MSR_MTRRfix16K_80000] = data;
846 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
847 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
848 else if (msr == MSR_IA32_CR_PAT)
849 vcpu->arch.pat = data;
850 else { /* Variable MTRRs */
851 int idx, is_mtrr_mask;
852 u64 *pt;
853
854 idx = (msr - 0x200) / 2;
855 is_mtrr_mask = msr - 0x200 - 2 * idx;
856 if (!is_mtrr_mask)
857 pt =
858 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
859 else
860 pt =
861 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
862 *pt = data;
863 }
864
865 kvm_mmu_reset_context(vcpu);
866 return 0;
867 }
868
869 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
870 {
871 u64 mcg_cap = vcpu->arch.mcg_cap;
872 unsigned bank_num = mcg_cap & 0xff;
873
874 switch (msr) {
875 case MSR_IA32_MCG_STATUS:
876 vcpu->arch.mcg_status = data;
877 break;
878 case MSR_IA32_MCG_CTL:
879 if (!(mcg_cap & MCG_CTL_P))
880 return 1;
881 if (data != 0 && data != ~(u64)0)
882 return -1;
883 vcpu->arch.mcg_ctl = data;
884 break;
885 default:
886 if (msr >= MSR_IA32_MC0_CTL &&
887 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
888 u32 offset = msr - MSR_IA32_MC0_CTL;
889 /* only 0 or all 1s can be written to IA32_MCi_CTL */
890 if ((offset & 0x3) == 0 &&
891 data != 0 && data != ~(u64)0)
892 return -1;
893 vcpu->arch.mce_banks[offset] = data;
894 break;
895 }
896 return 1;
897 }
898 return 0;
899 }
900
901 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
902 {
903 struct kvm *kvm = vcpu->kvm;
904 int lm = is_long_mode(vcpu);
905 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
906 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
907 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
908 : kvm->arch.xen_hvm_config.blob_size_32;
909 u32 page_num = data & ~PAGE_MASK;
910 u64 page_addr = data & PAGE_MASK;
911 u8 *page;
912 int r;
913
914 r = -E2BIG;
915 if (page_num >= blob_size)
916 goto out;
917 r = -ENOMEM;
918 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
919 if (!page)
920 goto out;
921 r = -EFAULT;
922 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
923 goto out_free;
924 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
925 goto out_free;
926 r = 0;
927 out_free:
928 kfree(page);
929 out:
930 return r;
931 }
932
933 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
934 {
935 switch (msr) {
936 case MSR_EFER:
937 set_efer(vcpu, data);
938 break;
939 case MSR_K7_HWCR:
940 data &= ~(u64)0x40; /* ignore flush filter disable */
941 if (data != 0) {
942 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
943 data);
944 return 1;
945 }
946 break;
947 case MSR_FAM10H_MMIO_CONF_BASE:
948 if (data != 0) {
949 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
950 "0x%llx\n", data);
951 return 1;
952 }
953 break;
954 case MSR_AMD64_NB_CFG:
955 break;
956 case MSR_IA32_DEBUGCTLMSR:
957 if (!data) {
958 /* We support the non-activated case already */
959 break;
960 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
961 /* Values other than LBR and BTF are vendor-specific,
962 thus reserved and should throw a #GP */
963 return 1;
964 }
965 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
966 __func__, data);
967 break;
968 case MSR_IA32_UCODE_REV:
969 case MSR_IA32_UCODE_WRITE:
970 case MSR_VM_HSAVE_PA:
971 case MSR_AMD64_PATCH_LOADER:
972 break;
973 case 0x200 ... 0x2ff:
974 return set_msr_mtrr(vcpu, msr, data);
975 case MSR_IA32_APICBASE:
976 kvm_set_apic_base(vcpu, data);
977 break;
978 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
979 return kvm_x2apic_msr_write(vcpu, msr, data);
980 case MSR_IA32_MISC_ENABLE:
981 vcpu->arch.ia32_misc_enable_msr = data;
982 break;
983 case MSR_KVM_WALL_CLOCK:
984 vcpu->kvm->arch.wall_clock = data;
985 kvm_write_wall_clock(vcpu->kvm, data);
986 break;
987 case MSR_KVM_SYSTEM_TIME: {
988 if (vcpu->arch.time_page) {
989 kvm_release_page_dirty(vcpu->arch.time_page);
990 vcpu->arch.time_page = NULL;
991 }
992
993 vcpu->arch.time = data;
994
995 /* we verify if the enable bit is set... */
996 if (!(data & 1))
997 break;
998
999 /* ...but clean it before doing the actual write */
1000 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1001
1002 vcpu->arch.time_page =
1003 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1004
1005 if (is_error_page(vcpu->arch.time_page)) {
1006 kvm_release_page_clean(vcpu->arch.time_page);
1007 vcpu->arch.time_page = NULL;
1008 }
1009
1010 kvm_request_guest_time_update(vcpu);
1011 break;
1012 }
1013 case MSR_IA32_MCG_CTL:
1014 case MSR_IA32_MCG_STATUS:
1015 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1016 return set_msr_mce(vcpu, msr, data);
1017
1018 /* Performance counters are not protected by a CPUID bit,
1019 * so we should check all of them in the generic path for the sake of
1020 * cross vendor migration.
1021 * Writing a zero into the event select MSRs disables them,
1022 * which we perfectly emulate ;-). Any other value should be at least
1023 * reported, some guests depend on them.
1024 */
1025 case MSR_P6_EVNTSEL0:
1026 case MSR_P6_EVNTSEL1:
1027 case MSR_K7_EVNTSEL0:
1028 case MSR_K7_EVNTSEL1:
1029 case MSR_K7_EVNTSEL2:
1030 case MSR_K7_EVNTSEL3:
1031 if (data != 0)
1032 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1033 "0x%x data 0x%llx\n", msr, data);
1034 break;
1035 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1036 * so we ignore writes to make it happy.
1037 */
1038 case MSR_P6_PERFCTR0:
1039 case MSR_P6_PERFCTR1:
1040 case MSR_K7_PERFCTR0:
1041 case MSR_K7_PERFCTR1:
1042 case MSR_K7_PERFCTR2:
1043 case MSR_K7_PERFCTR3:
1044 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1045 "0x%x data 0x%llx\n", msr, data);
1046 break;
1047 default:
1048 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1049 return xen_hvm_config(vcpu, data);
1050 if (!ignore_msrs) {
1051 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1052 msr, data);
1053 return 1;
1054 } else {
1055 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1056 msr, data);
1057 break;
1058 }
1059 }
1060 return 0;
1061 }
1062 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1063
1064
1065 /*
1066 * Reads an msr value (of 'msr_index') into 'pdata'.
1067 * Returns 0 on success, non-0 otherwise.
1068 * Assumes vcpu_load() was already called.
1069 */
1070 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1071 {
1072 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1073 }
1074
1075 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1076 {
1077 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1078
1079 if (!msr_mtrr_valid(msr))
1080 return 1;
1081
1082 if (msr == MSR_MTRRdefType)
1083 *pdata = vcpu->arch.mtrr_state.def_type +
1084 (vcpu->arch.mtrr_state.enabled << 10);
1085 else if (msr == MSR_MTRRfix64K_00000)
1086 *pdata = p[0];
1087 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1088 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1089 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1090 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1091 else if (msr == MSR_IA32_CR_PAT)
1092 *pdata = vcpu->arch.pat;
1093 else { /* Variable MTRRs */
1094 int idx, is_mtrr_mask;
1095 u64 *pt;
1096
1097 idx = (msr - 0x200) / 2;
1098 is_mtrr_mask = msr - 0x200 - 2 * idx;
1099 if (!is_mtrr_mask)
1100 pt =
1101 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1102 else
1103 pt =
1104 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1105 *pdata = *pt;
1106 }
1107
1108 return 0;
1109 }
1110
1111 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1112 {
1113 u64 data;
1114 u64 mcg_cap = vcpu->arch.mcg_cap;
1115 unsigned bank_num = mcg_cap & 0xff;
1116
1117 switch (msr) {
1118 case MSR_IA32_P5_MC_ADDR:
1119 case MSR_IA32_P5_MC_TYPE:
1120 data = 0;
1121 break;
1122 case MSR_IA32_MCG_CAP:
1123 data = vcpu->arch.mcg_cap;
1124 break;
1125 case MSR_IA32_MCG_CTL:
1126 if (!(mcg_cap & MCG_CTL_P))
1127 return 1;
1128 data = vcpu->arch.mcg_ctl;
1129 break;
1130 case MSR_IA32_MCG_STATUS:
1131 data = vcpu->arch.mcg_status;
1132 break;
1133 default:
1134 if (msr >= MSR_IA32_MC0_CTL &&
1135 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1136 u32 offset = msr - MSR_IA32_MC0_CTL;
1137 data = vcpu->arch.mce_banks[offset];
1138 break;
1139 }
1140 return 1;
1141 }
1142 *pdata = data;
1143 return 0;
1144 }
1145
1146 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1147 {
1148 u64 data;
1149
1150 switch (msr) {
1151 case MSR_IA32_PLATFORM_ID:
1152 case MSR_IA32_UCODE_REV:
1153 case MSR_IA32_EBL_CR_POWERON:
1154 case MSR_IA32_DEBUGCTLMSR:
1155 case MSR_IA32_LASTBRANCHFROMIP:
1156 case MSR_IA32_LASTBRANCHTOIP:
1157 case MSR_IA32_LASTINTFROMIP:
1158 case MSR_IA32_LASTINTTOIP:
1159 case MSR_K8_SYSCFG:
1160 case MSR_K7_HWCR:
1161 case MSR_VM_HSAVE_PA:
1162 case MSR_P6_PERFCTR0:
1163 case MSR_P6_PERFCTR1:
1164 case MSR_P6_EVNTSEL0:
1165 case MSR_P6_EVNTSEL1:
1166 case MSR_K7_EVNTSEL0:
1167 case MSR_K7_PERFCTR0:
1168 case MSR_K8_INT_PENDING_MSG:
1169 case MSR_AMD64_NB_CFG:
1170 case MSR_FAM10H_MMIO_CONF_BASE:
1171 data = 0;
1172 break;
1173 case MSR_MTRRcap:
1174 data = 0x500 | KVM_NR_VAR_MTRR;
1175 break;
1176 case 0x200 ... 0x2ff:
1177 return get_msr_mtrr(vcpu, msr, pdata);
1178 case 0xcd: /* fsb frequency */
1179 data = 3;
1180 break;
1181 case MSR_IA32_APICBASE:
1182 data = kvm_get_apic_base(vcpu);
1183 break;
1184 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1185 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1186 break;
1187 case MSR_IA32_MISC_ENABLE:
1188 data = vcpu->arch.ia32_misc_enable_msr;
1189 break;
1190 case MSR_IA32_PERF_STATUS:
1191 /* TSC increment by tick */
1192 data = 1000ULL;
1193 /* CPU multiplier */
1194 data |= (((uint64_t)4ULL) << 40);
1195 break;
1196 case MSR_EFER:
1197 data = vcpu->arch.shadow_efer;
1198 break;
1199 case MSR_KVM_WALL_CLOCK:
1200 data = vcpu->kvm->arch.wall_clock;
1201 break;
1202 case MSR_KVM_SYSTEM_TIME:
1203 data = vcpu->arch.time;
1204 break;
1205 case MSR_IA32_P5_MC_ADDR:
1206 case MSR_IA32_P5_MC_TYPE:
1207 case MSR_IA32_MCG_CAP:
1208 case MSR_IA32_MCG_CTL:
1209 case MSR_IA32_MCG_STATUS:
1210 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1211 return get_msr_mce(vcpu, msr, pdata);
1212 default:
1213 if (!ignore_msrs) {
1214 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1215 return 1;
1216 } else {
1217 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1218 data = 0;
1219 }
1220 break;
1221 }
1222 *pdata = data;
1223 return 0;
1224 }
1225 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1226
1227 /*
1228 * Read or write a bunch of msrs. All parameters are kernel addresses.
1229 *
1230 * @return number of msrs set successfully.
1231 */
1232 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1233 struct kvm_msr_entry *entries,
1234 int (*do_msr)(struct kvm_vcpu *vcpu,
1235 unsigned index, u64 *data))
1236 {
1237 int i;
1238
1239 vcpu_load(vcpu);
1240
1241 down_read(&vcpu->kvm->slots_lock);
1242 for (i = 0; i < msrs->nmsrs; ++i)
1243 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1244 break;
1245 up_read(&vcpu->kvm->slots_lock);
1246
1247 vcpu_put(vcpu);
1248
1249 return i;
1250 }
1251
1252 /*
1253 * Read or write a bunch of msrs. Parameters are user addresses.
1254 *
1255 * @return number of msrs set successfully.
1256 */
1257 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1258 int (*do_msr)(struct kvm_vcpu *vcpu,
1259 unsigned index, u64 *data),
1260 int writeback)
1261 {
1262 struct kvm_msrs msrs;
1263 struct kvm_msr_entry *entries;
1264 int r, n;
1265 unsigned size;
1266
1267 r = -EFAULT;
1268 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1269 goto out;
1270
1271 r = -E2BIG;
1272 if (msrs.nmsrs >= MAX_IO_MSRS)
1273 goto out;
1274
1275 r = -ENOMEM;
1276 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1277 entries = vmalloc(size);
1278 if (!entries)
1279 goto out;
1280
1281 r = -EFAULT;
1282 if (copy_from_user(entries, user_msrs->entries, size))
1283 goto out_free;
1284
1285 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1286 if (r < 0)
1287 goto out_free;
1288
1289 r = -EFAULT;
1290 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1291 goto out_free;
1292
1293 r = n;
1294
1295 out_free:
1296 vfree(entries);
1297 out:
1298 return r;
1299 }
1300
1301 int kvm_dev_ioctl_check_extension(long ext)
1302 {
1303 int r;
1304
1305 switch (ext) {
1306 case KVM_CAP_IRQCHIP:
1307 case KVM_CAP_HLT:
1308 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1309 case KVM_CAP_SET_TSS_ADDR:
1310 case KVM_CAP_EXT_CPUID:
1311 case KVM_CAP_CLOCKSOURCE:
1312 case KVM_CAP_PIT:
1313 case KVM_CAP_NOP_IO_DELAY:
1314 case KVM_CAP_MP_STATE:
1315 case KVM_CAP_SYNC_MMU:
1316 case KVM_CAP_REINJECT_CONTROL:
1317 case KVM_CAP_IRQ_INJECT_STATUS:
1318 case KVM_CAP_ASSIGN_DEV_IRQ:
1319 case KVM_CAP_IRQFD:
1320 case KVM_CAP_IOEVENTFD:
1321 case KVM_CAP_PIT2:
1322 case KVM_CAP_PIT_STATE2:
1323 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
1324 case KVM_CAP_XEN_HVM:
1325 case KVM_CAP_ADJUST_CLOCK:
1326 case KVM_CAP_VCPU_EVENTS:
1327 case KVM_CAP_X86_ROBUST_SINGLESTEP:
1328 r = 1;
1329 break;
1330 case KVM_CAP_COALESCED_MMIO:
1331 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1332 break;
1333 case KVM_CAP_VAPIC:
1334 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1335 break;
1336 case KVM_CAP_NR_VCPUS:
1337 r = KVM_MAX_VCPUS;
1338 break;
1339 case KVM_CAP_NR_MEMSLOTS:
1340 r = KVM_MEMORY_SLOTS;
1341 break;
1342 case KVM_CAP_PV_MMU: /* obsolete */
1343 r = 0;
1344 break;
1345 case KVM_CAP_IOMMU:
1346 r = iommu_found();
1347 break;
1348 case KVM_CAP_MCE:
1349 r = KVM_MAX_MCE_BANKS;
1350 break;
1351 default:
1352 r = 0;
1353 break;
1354 }
1355 return r;
1356
1357 }
1358
1359 long kvm_arch_dev_ioctl(struct file *filp,
1360 unsigned int ioctl, unsigned long arg)
1361 {
1362 void __user *argp = (void __user *)arg;
1363 long r;
1364
1365 switch (ioctl) {
1366 case KVM_GET_MSR_INDEX_LIST: {
1367 struct kvm_msr_list __user *user_msr_list = argp;
1368 struct kvm_msr_list msr_list;
1369 unsigned n;
1370
1371 r = -EFAULT;
1372 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1373 goto out;
1374 n = msr_list.nmsrs;
1375 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1376 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1377 goto out;
1378 r = -E2BIG;
1379 if (n < msr_list.nmsrs)
1380 goto out;
1381 r = -EFAULT;
1382 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1383 num_msrs_to_save * sizeof(u32)))
1384 goto out;
1385 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
1386 &emulated_msrs,
1387 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1388 goto out;
1389 r = 0;
1390 break;
1391 }
1392 case KVM_GET_SUPPORTED_CPUID: {
1393 struct kvm_cpuid2 __user *cpuid_arg = argp;
1394 struct kvm_cpuid2 cpuid;
1395
1396 r = -EFAULT;
1397 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1398 goto out;
1399 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1400 cpuid_arg->entries);
1401 if (r)
1402 goto out;
1403
1404 r = -EFAULT;
1405 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1406 goto out;
1407 r = 0;
1408 break;
1409 }
1410 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1411 u64 mce_cap;
1412
1413 mce_cap = KVM_MCE_CAP_SUPPORTED;
1414 r = -EFAULT;
1415 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1416 goto out;
1417 r = 0;
1418 break;
1419 }
1420 default:
1421 r = -EINVAL;
1422 }
1423 out:
1424 return r;
1425 }
1426
1427 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1428 {
1429 kvm_x86_ops->vcpu_load(vcpu, cpu);
1430 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1431 unsigned long khz = cpufreq_quick_get(cpu);
1432 if (!khz)
1433 khz = tsc_khz;
1434 per_cpu(cpu_tsc_khz, cpu) = khz;
1435 }
1436 kvm_request_guest_time_update(vcpu);
1437 }
1438
1439 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1440 {
1441 kvm_x86_ops->vcpu_put(vcpu);
1442 kvm_put_guest_fpu(vcpu);
1443 }
1444
1445 static int is_efer_nx(void)
1446 {
1447 unsigned long long efer = 0;
1448
1449 rdmsrl_safe(MSR_EFER, &efer);
1450 return efer & EFER_NX;
1451 }
1452
1453 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1454 {
1455 int i;
1456 struct kvm_cpuid_entry2 *e, *entry;
1457
1458 entry = NULL;
1459 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1460 e = &vcpu->arch.cpuid_entries[i];
1461 if (e->function == 0x80000001) {
1462 entry = e;
1463 break;
1464 }
1465 }
1466 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
1467 entry->edx &= ~(1 << 20);
1468 printk(KERN_INFO "kvm: guest NX capability removed\n");
1469 }
1470 }
1471
1472 /* when an old userspace process fills a new kernel module */
1473 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1474 struct kvm_cpuid *cpuid,
1475 struct kvm_cpuid_entry __user *entries)
1476 {
1477 int r, i;
1478 struct kvm_cpuid_entry *cpuid_entries;
1479
1480 r = -E2BIG;
1481 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1482 goto out;
1483 r = -ENOMEM;
1484 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1485 if (!cpuid_entries)
1486 goto out;
1487 r = -EFAULT;
1488 if (copy_from_user(cpuid_entries, entries,
1489 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1490 goto out_free;
1491 for (i = 0; i < cpuid->nent; i++) {
1492 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1493 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1494 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1495 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1496 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1497 vcpu->arch.cpuid_entries[i].index = 0;
1498 vcpu->arch.cpuid_entries[i].flags = 0;
1499 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1500 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1501 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1502 }
1503 vcpu->arch.cpuid_nent = cpuid->nent;
1504 cpuid_fix_nx_cap(vcpu);
1505 r = 0;
1506 kvm_apic_set_version(vcpu);
1507
1508 out_free:
1509 vfree(cpuid_entries);
1510 out:
1511 return r;
1512 }
1513
1514 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1515 struct kvm_cpuid2 *cpuid,
1516 struct kvm_cpuid_entry2 __user *entries)
1517 {
1518 int r;
1519
1520 r = -E2BIG;
1521 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1522 goto out;
1523 r = -EFAULT;
1524 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
1525 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
1526 goto out;
1527 vcpu->arch.cpuid_nent = cpuid->nent;
1528 kvm_apic_set_version(vcpu);
1529 return 0;
1530
1531 out:
1532 return r;
1533 }
1534
1535 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1536 struct kvm_cpuid2 *cpuid,
1537 struct kvm_cpuid_entry2 __user *entries)
1538 {
1539 int r;
1540
1541 r = -E2BIG;
1542 if (cpuid->nent < vcpu->arch.cpuid_nent)
1543 goto out;
1544 r = -EFAULT;
1545 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1546 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
1547 goto out;
1548 return 0;
1549
1550 out:
1551 cpuid->nent = vcpu->arch.cpuid_nent;
1552 return r;
1553 }
1554
1555 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1556 u32 index)
1557 {
1558 entry->function = function;
1559 entry->index = index;
1560 cpuid_count(entry->function, entry->index,
1561 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1562 entry->flags = 0;
1563 }
1564
1565 #define F(x) bit(X86_FEATURE_##x)
1566
1567 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1568 u32 index, int *nent, int maxnent)
1569 {
1570 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
1571 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
1572 #ifdef CONFIG_X86_64
1573 unsigned f_lm = F(LM);
1574 #else
1575 unsigned f_lm = 0;
1576 #endif
1577
1578 /* cpuid 1.edx */
1579 const u32 kvm_supported_word0_x86_features =
1580 F(FPU) | F(VME) | F(DE) | F(PSE) |
1581 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1582 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1583 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1584 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1585 0 /* Reserved, DS, ACPI */ | F(MMX) |
1586 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1587 0 /* HTT, TM, Reserved, PBE */;
1588 /* cpuid 0x80000001.edx */
1589 const u32 kvm_supported_word1_x86_features =
1590 F(FPU) | F(VME) | F(DE) | F(PSE) |
1591 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1592 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1593 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1594 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1595 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1596 F(FXSR) | F(FXSR_OPT) | f_gbpages | 0 /* RDTSCP */ |
1597 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1598 /* cpuid 1.ecx */
1599 const u32 kvm_supported_word4_x86_features =
1600 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1601 0 /* DS-CPL, VMX, SMX, EST */ |
1602 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1603 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1604 0 /* Reserved, DCA */ | F(XMM4_1) |
1605 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
1606 0 /* Reserved, XSAVE, OSXSAVE */;
1607 /* cpuid 0x80000001.ecx */
1608 const u32 kvm_supported_word6_x86_features =
1609 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1610 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1611 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1612 0 /* SKINIT */ | 0 /* WDT */;
1613
1614 /* all calls to cpuid_count() should be made on the same cpu */
1615 get_cpu();
1616 do_cpuid_1_ent(entry, function, index);
1617 ++*nent;
1618
1619 switch (function) {
1620 case 0:
1621 entry->eax = min(entry->eax, (u32)0xb);
1622 break;
1623 case 1:
1624 entry->edx &= kvm_supported_word0_x86_features;
1625 entry->ecx &= kvm_supported_word4_x86_features;
1626 /* we support x2apic emulation even if host does not support
1627 * it since we emulate x2apic in software */
1628 entry->ecx |= F(X2APIC);
1629 break;
1630 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1631 * may return different values. This forces us to get_cpu() before
1632 * issuing the first command, and also to emulate this annoying behavior
1633 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1634 case 2: {
1635 int t, times = entry->eax & 0xff;
1636
1637 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1638 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
1639 for (t = 1; t < times && *nent < maxnent; ++t) {
1640 do_cpuid_1_ent(&entry[t], function, 0);
1641 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1642 ++*nent;
1643 }
1644 break;
1645 }
1646 /* function 4 and 0xb have additional index. */
1647 case 4: {
1648 int i, cache_type;
1649
1650 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1651 /* read more entries until cache_type is zero */
1652 for (i = 1; *nent < maxnent; ++i) {
1653 cache_type = entry[i - 1].eax & 0x1f;
1654 if (!cache_type)
1655 break;
1656 do_cpuid_1_ent(&entry[i], function, i);
1657 entry[i].flags |=
1658 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1659 ++*nent;
1660 }
1661 break;
1662 }
1663 case 0xb: {
1664 int i, level_type;
1665
1666 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1667 /* read more entries until level_type is zero */
1668 for (i = 1; *nent < maxnent; ++i) {
1669 level_type = entry[i - 1].ecx & 0xff00;
1670 if (!level_type)
1671 break;
1672 do_cpuid_1_ent(&entry[i], function, i);
1673 entry[i].flags |=
1674 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1675 ++*nent;
1676 }
1677 break;
1678 }
1679 case 0x80000000:
1680 entry->eax = min(entry->eax, 0x8000001a);
1681 break;
1682 case 0x80000001:
1683 entry->edx &= kvm_supported_word1_x86_features;
1684 entry->ecx &= kvm_supported_word6_x86_features;
1685 break;
1686 }
1687 put_cpu();
1688 }
1689
1690 #undef F
1691
1692 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
1693 struct kvm_cpuid_entry2 __user *entries)
1694 {
1695 struct kvm_cpuid_entry2 *cpuid_entries;
1696 int limit, nent = 0, r = -E2BIG;
1697 u32 func;
1698
1699 if (cpuid->nent < 1)
1700 goto out;
1701 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1702 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
1703 r = -ENOMEM;
1704 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1705 if (!cpuid_entries)
1706 goto out;
1707
1708 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1709 limit = cpuid_entries[0].eax;
1710 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1711 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1712 &nent, cpuid->nent);
1713 r = -E2BIG;
1714 if (nent >= cpuid->nent)
1715 goto out_free;
1716
1717 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1718 limit = cpuid_entries[nent - 1].eax;
1719 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1720 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1721 &nent, cpuid->nent);
1722 r = -E2BIG;
1723 if (nent >= cpuid->nent)
1724 goto out_free;
1725
1726 r = -EFAULT;
1727 if (copy_to_user(entries, cpuid_entries,
1728 nent * sizeof(struct kvm_cpuid_entry2)))
1729 goto out_free;
1730 cpuid->nent = nent;
1731 r = 0;
1732
1733 out_free:
1734 vfree(cpuid_entries);
1735 out:
1736 return r;
1737 }
1738
1739 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1740 struct kvm_lapic_state *s)
1741 {
1742 vcpu_load(vcpu);
1743 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
1744 vcpu_put(vcpu);
1745
1746 return 0;
1747 }
1748
1749 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1750 struct kvm_lapic_state *s)
1751 {
1752 vcpu_load(vcpu);
1753 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1754 kvm_apic_post_state_restore(vcpu);
1755 update_cr8_intercept(vcpu);
1756 vcpu_put(vcpu);
1757
1758 return 0;
1759 }
1760
1761 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1762 struct kvm_interrupt *irq)
1763 {
1764 if (irq->irq < 0 || irq->irq >= 256)
1765 return -EINVAL;
1766 if (irqchip_in_kernel(vcpu->kvm))
1767 return -ENXIO;
1768 vcpu_load(vcpu);
1769
1770 kvm_queue_interrupt(vcpu, irq->irq, false);
1771
1772 vcpu_put(vcpu);
1773
1774 return 0;
1775 }
1776
1777 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1778 {
1779 vcpu_load(vcpu);
1780 kvm_inject_nmi(vcpu);
1781 vcpu_put(vcpu);
1782
1783 return 0;
1784 }
1785
1786 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1787 struct kvm_tpr_access_ctl *tac)
1788 {
1789 if (tac->flags)
1790 return -EINVAL;
1791 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1792 return 0;
1793 }
1794
1795 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1796 u64 mcg_cap)
1797 {
1798 int r;
1799 unsigned bank_num = mcg_cap & 0xff, bank;
1800
1801 r = -EINVAL;
1802 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
1803 goto out;
1804 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1805 goto out;
1806 r = 0;
1807 vcpu->arch.mcg_cap = mcg_cap;
1808 /* Init IA32_MCG_CTL to all 1s */
1809 if (mcg_cap & MCG_CTL_P)
1810 vcpu->arch.mcg_ctl = ~(u64)0;
1811 /* Init IA32_MCi_CTL to all 1s */
1812 for (bank = 0; bank < bank_num; bank++)
1813 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1814 out:
1815 return r;
1816 }
1817
1818 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1819 struct kvm_x86_mce *mce)
1820 {
1821 u64 mcg_cap = vcpu->arch.mcg_cap;
1822 unsigned bank_num = mcg_cap & 0xff;
1823 u64 *banks = vcpu->arch.mce_banks;
1824
1825 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1826 return -EINVAL;
1827 /*
1828 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1829 * reporting is disabled
1830 */
1831 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1832 vcpu->arch.mcg_ctl != ~(u64)0)
1833 return 0;
1834 banks += 4 * mce->bank;
1835 /*
1836 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1837 * reporting is disabled for the bank
1838 */
1839 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1840 return 0;
1841 if (mce->status & MCI_STATUS_UC) {
1842 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1843 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1844 printk(KERN_DEBUG "kvm: set_mce: "
1845 "injects mce exception while "
1846 "previous one is in progress!\n");
1847 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1848 return 0;
1849 }
1850 if (banks[1] & MCI_STATUS_VAL)
1851 mce->status |= MCI_STATUS_OVER;
1852 banks[2] = mce->addr;
1853 banks[3] = mce->misc;
1854 vcpu->arch.mcg_status = mce->mcg_status;
1855 banks[1] = mce->status;
1856 kvm_queue_exception(vcpu, MC_VECTOR);
1857 } else if (!(banks[1] & MCI_STATUS_VAL)
1858 || !(banks[1] & MCI_STATUS_UC)) {
1859 if (banks[1] & MCI_STATUS_VAL)
1860 mce->status |= MCI_STATUS_OVER;
1861 banks[2] = mce->addr;
1862 banks[3] = mce->misc;
1863 banks[1] = mce->status;
1864 } else
1865 banks[1] |= MCI_STATUS_OVER;
1866 return 0;
1867 }
1868
1869 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
1870 struct kvm_vcpu_events *events)
1871 {
1872 vcpu_load(vcpu);
1873
1874 events->exception.injected = vcpu->arch.exception.pending;
1875 events->exception.nr = vcpu->arch.exception.nr;
1876 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
1877 events->exception.error_code = vcpu->arch.exception.error_code;
1878
1879 events->interrupt.injected = vcpu->arch.interrupt.pending;
1880 events->interrupt.nr = vcpu->arch.interrupt.nr;
1881 events->interrupt.soft = vcpu->arch.interrupt.soft;
1882
1883 events->nmi.injected = vcpu->arch.nmi_injected;
1884 events->nmi.pending = vcpu->arch.nmi_pending;
1885 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
1886
1887 events->sipi_vector = vcpu->arch.sipi_vector;
1888
1889 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
1890 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
1891
1892 vcpu_put(vcpu);
1893 }
1894
1895 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
1896 struct kvm_vcpu_events *events)
1897 {
1898 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
1899 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
1900 return -EINVAL;
1901
1902 vcpu_load(vcpu);
1903
1904 vcpu->arch.exception.pending = events->exception.injected;
1905 vcpu->arch.exception.nr = events->exception.nr;
1906 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
1907 vcpu->arch.exception.error_code = events->exception.error_code;
1908
1909 vcpu->arch.interrupt.pending = events->interrupt.injected;
1910 vcpu->arch.interrupt.nr = events->interrupt.nr;
1911 vcpu->arch.interrupt.soft = events->interrupt.soft;
1912 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
1913 kvm_pic_clear_isr_ack(vcpu->kvm);
1914
1915 vcpu->arch.nmi_injected = events->nmi.injected;
1916 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
1917 vcpu->arch.nmi_pending = events->nmi.pending;
1918 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
1919
1920 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
1921 vcpu->arch.sipi_vector = events->sipi_vector;
1922
1923 vcpu_put(vcpu);
1924
1925 return 0;
1926 }
1927
1928 long kvm_arch_vcpu_ioctl(struct file *filp,
1929 unsigned int ioctl, unsigned long arg)
1930 {
1931 struct kvm_vcpu *vcpu = filp->private_data;
1932 void __user *argp = (void __user *)arg;
1933 int r;
1934 struct kvm_lapic_state *lapic = NULL;
1935
1936 switch (ioctl) {
1937 case KVM_GET_LAPIC: {
1938 r = -EINVAL;
1939 if (!vcpu->arch.apic)
1940 goto out;
1941 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1942
1943 r = -ENOMEM;
1944 if (!lapic)
1945 goto out;
1946 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
1947 if (r)
1948 goto out;
1949 r = -EFAULT;
1950 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
1951 goto out;
1952 r = 0;
1953 break;
1954 }
1955 case KVM_SET_LAPIC: {
1956 r = -EINVAL;
1957 if (!vcpu->arch.apic)
1958 goto out;
1959 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1960 r = -ENOMEM;
1961 if (!lapic)
1962 goto out;
1963 r = -EFAULT;
1964 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
1965 goto out;
1966 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
1967 if (r)
1968 goto out;
1969 r = 0;
1970 break;
1971 }
1972 case KVM_INTERRUPT: {
1973 struct kvm_interrupt irq;
1974
1975 r = -EFAULT;
1976 if (copy_from_user(&irq, argp, sizeof irq))
1977 goto out;
1978 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1979 if (r)
1980 goto out;
1981 r = 0;
1982 break;
1983 }
1984 case KVM_NMI: {
1985 r = kvm_vcpu_ioctl_nmi(vcpu);
1986 if (r)
1987 goto out;
1988 r = 0;
1989 break;
1990 }
1991 case KVM_SET_CPUID: {
1992 struct kvm_cpuid __user *cpuid_arg = argp;
1993 struct kvm_cpuid cpuid;
1994
1995 r = -EFAULT;
1996 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1997 goto out;
1998 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1999 if (r)
2000 goto out;
2001 break;
2002 }
2003 case KVM_SET_CPUID2: {
2004 struct kvm_cpuid2 __user *cpuid_arg = argp;
2005 struct kvm_cpuid2 cpuid;
2006
2007 r = -EFAULT;
2008 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2009 goto out;
2010 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2011 cpuid_arg->entries);
2012 if (r)
2013 goto out;
2014 break;
2015 }
2016 case KVM_GET_CPUID2: {
2017 struct kvm_cpuid2 __user *cpuid_arg = argp;
2018 struct kvm_cpuid2 cpuid;
2019
2020 r = -EFAULT;
2021 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2022 goto out;
2023 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2024 cpuid_arg->entries);
2025 if (r)
2026 goto out;
2027 r = -EFAULT;
2028 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2029 goto out;
2030 r = 0;
2031 break;
2032 }
2033 case KVM_GET_MSRS:
2034 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2035 break;
2036 case KVM_SET_MSRS:
2037 r = msr_io(vcpu, argp, do_set_msr, 0);
2038 break;
2039 case KVM_TPR_ACCESS_REPORTING: {
2040 struct kvm_tpr_access_ctl tac;
2041
2042 r = -EFAULT;
2043 if (copy_from_user(&tac, argp, sizeof tac))
2044 goto out;
2045 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2046 if (r)
2047 goto out;
2048 r = -EFAULT;
2049 if (copy_to_user(argp, &tac, sizeof tac))
2050 goto out;
2051 r = 0;
2052 break;
2053 };
2054 case KVM_SET_VAPIC_ADDR: {
2055 struct kvm_vapic_addr va;
2056
2057 r = -EINVAL;
2058 if (!irqchip_in_kernel(vcpu->kvm))
2059 goto out;
2060 r = -EFAULT;
2061 if (copy_from_user(&va, argp, sizeof va))
2062 goto out;
2063 r = 0;
2064 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2065 break;
2066 }
2067 case KVM_X86_SETUP_MCE: {
2068 u64 mcg_cap;
2069
2070 r = -EFAULT;
2071 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2072 goto out;
2073 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2074 break;
2075 }
2076 case KVM_X86_SET_MCE: {
2077 struct kvm_x86_mce mce;
2078
2079 r = -EFAULT;
2080 if (copy_from_user(&mce, argp, sizeof mce))
2081 goto out;
2082 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2083 break;
2084 }
2085 case KVM_GET_VCPU_EVENTS: {
2086 struct kvm_vcpu_events events;
2087
2088 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2089
2090 r = -EFAULT;
2091 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2092 break;
2093 r = 0;
2094 break;
2095 }
2096 case KVM_SET_VCPU_EVENTS: {
2097 struct kvm_vcpu_events events;
2098
2099 r = -EFAULT;
2100 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2101 break;
2102
2103 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2104 break;
2105 }
2106 default:
2107 r = -EINVAL;
2108 }
2109 out:
2110 kfree(lapic);
2111 return r;
2112 }
2113
2114 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2115 {
2116 int ret;
2117
2118 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2119 return -1;
2120 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2121 return ret;
2122 }
2123
2124 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2125 u64 ident_addr)
2126 {
2127 kvm->arch.ept_identity_map_addr = ident_addr;
2128 return 0;
2129 }
2130
2131 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2132 u32 kvm_nr_mmu_pages)
2133 {
2134 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2135 return -EINVAL;
2136
2137 down_write(&kvm->slots_lock);
2138 spin_lock(&kvm->mmu_lock);
2139
2140 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2141 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2142
2143 spin_unlock(&kvm->mmu_lock);
2144 up_write(&kvm->slots_lock);
2145 return 0;
2146 }
2147
2148 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2149 {
2150 return kvm->arch.n_alloc_mmu_pages;
2151 }
2152
2153 gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2154 {
2155 int i;
2156 struct kvm_mem_alias *alias;
2157
2158 for (i = 0; i < kvm->arch.naliases; ++i) {
2159 alias = &kvm->arch.aliases[i];
2160 if (gfn >= alias->base_gfn
2161 && gfn < alias->base_gfn + alias->npages)
2162 return alias->target_gfn + gfn - alias->base_gfn;
2163 }
2164 return gfn;
2165 }
2166
2167 /*
2168 * Set a new alias region. Aliases map a portion of physical memory into
2169 * another portion. This is useful for memory windows, for example the PC
2170 * VGA region.
2171 */
2172 static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2173 struct kvm_memory_alias *alias)
2174 {
2175 int r, n;
2176 struct kvm_mem_alias *p;
2177
2178 r = -EINVAL;
2179 /* General sanity checks */
2180 if (alias->memory_size & (PAGE_SIZE - 1))
2181 goto out;
2182 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2183 goto out;
2184 if (alias->slot >= KVM_ALIAS_SLOTS)
2185 goto out;
2186 if (alias->guest_phys_addr + alias->memory_size
2187 < alias->guest_phys_addr)
2188 goto out;
2189 if (alias->target_phys_addr + alias->memory_size
2190 < alias->target_phys_addr)
2191 goto out;
2192
2193 down_write(&kvm->slots_lock);
2194 spin_lock(&kvm->mmu_lock);
2195
2196 p = &kvm->arch.aliases[alias->slot];
2197 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2198 p->npages = alias->memory_size >> PAGE_SHIFT;
2199 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
2200
2201 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
2202 if (kvm->arch.aliases[n - 1].npages)
2203 break;
2204 kvm->arch.naliases = n;
2205
2206 spin_unlock(&kvm->mmu_lock);
2207 kvm_mmu_zap_all(kvm);
2208
2209 up_write(&kvm->slots_lock);
2210
2211 return 0;
2212
2213 out:
2214 return r;
2215 }
2216
2217 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2218 {
2219 int r;
2220
2221 r = 0;
2222 switch (chip->chip_id) {
2223 case KVM_IRQCHIP_PIC_MASTER:
2224 memcpy(&chip->chip.pic,
2225 &pic_irqchip(kvm)->pics[0],
2226 sizeof(struct kvm_pic_state));
2227 break;
2228 case KVM_IRQCHIP_PIC_SLAVE:
2229 memcpy(&chip->chip.pic,
2230 &pic_irqchip(kvm)->pics[1],
2231 sizeof(struct kvm_pic_state));
2232 break;
2233 case KVM_IRQCHIP_IOAPIC:
2234 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2235 break;
2236 default:
2237 r = -EINVAL;
2238 break;
2239 }
2240 return r;
2241 }
2242
2243 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2244 {
2245 int r;
2246
2247 r = 0;
2248 switch (chip->chip_id) {
2249 case KVM_IRQCHIP_PIC_MASTER:
2250 spin_lock(&pic_irqchip(kvm)->lock);
2251 memcpy(&pic_irqchip(kvm)->pics[0],
2252 &chip->chip.pic,
2253 sizeof(struct kvm_pic_state));
2254 spin_unlock(&pic_irqchip(kvm)->lock);
2255 break;
2256 case KVM_IRQCHIP_PIC_SLAVE:
2257 spin_lock(&pic_irqchip(kvm)->lock);
2258 memcpy(&pic_irqchip(kvm)->pics[1],
2259 &chip->chip.pic,
2260 sizeof(struct kvm_pic_state));
2261 spin_unlock(&pic_irqchip(kvm)->lock);
2262 break;
2263 case KVM_IRQCHIP_IOAPIC:
2264 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
2265 break;
2266 default:
2267 r = -EINVAL;
2268 break;
2269 }
2270 kvm_pic_update_irq(pic_irqchip(kvm));
2271 return r;
2272 }
2273
2274 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2275 {
2276 int r = 0;
2277
2278 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2279 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2280 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2281 return r;
2282 }
2283
2284 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2285 {
2286 int r = 0;
2287
2288 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2289 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2290 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2291 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2292 return r;
2293 }
2294
2295 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2296 {
2297 int r = 0;
2298
2299 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2300 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2301 sizeof(ps->channels));
2302 ps->flags = kvm->arch.vpit->pit_state.flags;
2303 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2304 return r;
2305 }
2306
2307 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2308 {
2309 int r = 0, start = 0;
2310 u32 prev_legacy, cur_legacy;
2311 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2312 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2313 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2314 if (!prev_legacy && cur_legacy)
2315 start = 1;
2316 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2317 sizeof(kvm->arch.vpit->pit_state.channels));
2318 kvm->arch.vpit->pit_state.flags = ps->flags;
2319 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
2320 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2321 return r;
2322 }
2323
2324 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2325 struct kvm_reinject_control *control)
2326 {
2327 if (!kvm->arch.vpit)
2328 return -ENXIO;
2329 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2330 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
2331 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2332 return 0;
2333 }
2334
2335 /*
2336 * Get (and clear) the dirty memory log for a memory slot.
2337 */
2338 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2339 struct kvm_dirty_log *log)
2340 {
2341 int r;
2342 int n;
2343 struct kvm_memory_slot *memslot;
2344 int is_dirty = 0;
2345
2346 down_write(&kvm->slots_lock);
2347
2348 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2349 if (r)
2350 goto out;
2351
2352 /* If nothing is dirty, don't bother messing with page tables. */
2353 if (is_dirty) {
2354 spin_lock(&kvm->mmu_lock);
2355 kvm_mmu_slot_remove_write_access(kvm, log->slot);
2356 spin_unlock(&kvm->mmu_lock);
2357 memslot = &kvm->memslots[log->slot];
2358 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2359 memset(memslot->dirty_bitmap, 0, n);
2360 }
2361 r = 0;
2362 out:
2363 up_write(&kvm->slots_lock);
2364 return r;
2365 }
2366
2367 long kvm_arch_vm_ioctl(struct file *filp,
2368 unsigned int ioctl, unsigned long arg)
2369 {
2370 struct kvm *kvm = filp->private_data;
2371 void __user *argp = (void __user *)arg;
2372 int r = -ENOTTY;
2373 /*
2374 * This union makes it completely explicit to gcc-3.x
2375 * that these two variables' stack usage should be
2376 * combined, not added together.
2377 */
2378 union {
2379 struct kvm_pit_state ps;
2380 struct kvm_pit_state2 ps2;
2381 struct kvm_memory_alias alias;
2382 struct kvm_pit_config pit_config;
2383 } u;
2384
2385 switch (ioctl) {
2386 case KVM_SET_TSS_ADDR:
2387 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2388 if (r < 0)
2389 goto out;
2390 break;
2391 case KVM_SET_IDENTITY_MAP_ADDR: {
2392 u64 ident_addr;
2393
2394 r = -EFAULT;
2395 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2396 goto out;
2397 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2398 if (r < 0)
2399 goto out;
2400 break;
2401 }
2402 case KVM_SET_MEMORY_REGION: {
2403 struct kvm_memory_region kvm_mem;
2404 struct kvm_userspace_memory_region kvm_userspace_mem;
2405
2406 r = -EFAULT;
2407 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2408 goto out;
2409 kvm_userspace_mem.slot = kvm_mem.slot;
2410 kvm_userspace_mem.flags = kvm_mem.flags;
2411 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2412 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2413 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2414 if (r)
2415 goto out;
2416 break;
2417 }
2418 case KVM_SET_NR_MMU_PAGES:
2419 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2420 if (r)
2421 goto out;
2422 break;
2423 case KVM_GET_NR_MMU_PAGES:
2424 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2425 break;
2426 case KVM_SET_MEMORY_ALIAS:
2427 r = -EFAULT;
2428 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
2429 goto out;
2430 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
2431 if (r)
2432 goto out;
2433 break;
2434 case KVM_CREATE_IRQCHIP: {
2435 struct kvm_pic *vpic;
2436
2437 mutex_lock(&kvm->lock);
2438 r = -EEXIST;
2439 if (kvm->arch.vpic)
2440 goto create_irqchip_unlock;
2441 r = -ENOMEM;
2442 vpic = kvm_create_pic(kvm);
2443 if (vpic) {
2444 r = kvm_ioapic_init(kvm);
2445 if (r) {
2446 kfree(vpic);
2447 goto create_irqchip_unlock;
2448 }
2449 } else
2450 goto create_irqchip_unlock;
2451 smp_wmb();
2452 kvm->arch.vpic = vpic;
2453 smp_wmb();
2454 r = kvm_setup_default_irq_routing(kvm);
2455 if (r) {
2456 mutex_lock(&kvm->irq_lock);
2457 kfree(kvm->arch.vpic);
2458 kfree(kvm->arch.vioapic);
2459 kvm->arch.vpic = NULL;
2460 kvm->arch.vioapic = NULL;
2461 mutex_unlock(&kvm->irq_lock);
2462 }
2463 create_irqchip_unlock:
2464 mutex_unlock(&kvm->lock);
2465 break;
2466 }
2467 case KVM_CREATE_PIT:
2468 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2469 goto create_pit;
2470 case KVM_CREATE_PIT2:
2471 r = -EFAULT;
2472 if (copy_from_user(&u.pit_config, argp,
2473 sizeof(struct kvm_pit_config)))
2474 goto out;
2475 create_pit:
2476 down_write(&kvm->slots_lock);
2477 r = -EEXIST;
2478 if (kvm->arch.vpit)
2479 goto create_pit_unlock;
2480 r = -ENOMEM;
2481 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
2482 if (kvm->arch.vpit)
2483 r = 0;
2484 create_pit_unlock:
2485 up_write(&kvm->slots_lock);
2486 break;
2487 case KVM_IRQ_LINE_STATUS:
2488 case KVM_IRQ_LINE: {
2489 struct kvm_irq_level irq_event;
2490
2491 r = -EFAULT;
2492 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2493 goto out;
2494 if (irqchip_in_kernel(kvm)) {
2495 __s32 status;
2496 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2497 irq_event.irq, irq_event.level);
2498 if (ioctl == KVM_IRQ_LINE_STATUS) {
2499 irq_event.status = status;
2500 if (copy_to_user(argp, &irq_event,
2501 sizeof irq_event))
2502 goto out;
2503 }
2504 r = 0;
2505 }
2506 break;
2507 }
2508 case KVM_GET_IRQCHIP: {
2509 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2510 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2511
2512 r = -ENOMEM;
2513 if (!chip)
2514 goto out;
2515 r = -EFAULT;
2516 if (copy_from_user(chip, argp, sizeof *chip))
2517 goto get_irqchip_out;
2518 r = -ENXIO;
2519 if (!irqchip_in_kernel(kvm))
2520 goto get_irqchip_out;
2521 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
2522 if (r)
2523 goto get_irqchip_out;
2524 r = -EFAULT;
2525 if (copy_to_user(argp, chip, sizeof *chip))
2526 goto get_irqchip_out;
2527 r = 0;
2528 get_irqchip_out:
2529 kfree(chip);
2530 if (r)
2531 goto out;
2532 break;
2533 }
2534 case KVM_SET_IRQCHIP: {
2535 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2536 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2537
2538 r = -ENOMEM;
2539 if (!chip)
2540 goto out;
2541 r = -EFAULT;
2542 if (copy_from_user(chip, argp, sizeof *chip))
2543 goto set_irqchip_out;
2544 r = -ENXIO;
2545 if (!irqchip_in_kernel(kvm))
2546 goto set_irqchip_out;
2547 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
2548 if (r)
2549 goto set_irqchip_out;
2550 r = 0;
2551 set_irqchip_out:
2552 kfree(chip);
2553 if (r)
2554 goto out;
2555 break;
2556 }
2557 case KVM_GET_PIT: {
2558 r = -EFAULT;
2559 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
2560 goto out;
2561 r = -ENXIO;
2562 if (!kvm->arch.vpit)
2563 goto out;
2564 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
2565 if (r)
2566 goto out;
2567 r = -EFAULT;
2568 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
2569 goto out;
2570 r = 0;
2571 break;
2572 }
2573 case KVM_SET_PIT: {
2574 r = -EFAULT;
2575 if (copy_from_user(&u.ps, argp, sizeof u.ps))
2576 goto out;
2577 r = -ENXIO;
2578 if (!kvm->arch.vpit)
2579 goto out;
2580 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
2581 if (r)
2582 goto out;
2583 r = 0;
2584 break;
2585 }
2586 case KVM_GET_PIT2: {
2587 r = -ENXIO;
2588 if (!kvm->arch.vpit)
2589 goto out;
2590 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2591 if (r)
2592 goto out;
2593 r = -EFAULT;
2594 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2595 goto out;
2596 r = 0;
2597 break;
2598 }
2599 case KVM_SET_PIT2: {
2600 r = -EFAULT;
2601 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2602 goto out;
2603 r = -ENXIO;
2604 if (!kvm->arch.vpit)
2605 goto out;
2606 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2607 if (r)
2608 goto out;
2609 r = 0;
2610 break;
2611 }
2612 case KVM_REINJECT_CONTROL: {
2613 struct kvm_reinject_control control;
2614 r = -EFAULT;
2615 if (copy_from_user(&control, argp, sizeof(control)))
2616 goto out;
2617 r = kvm_vm_ioctl_reinject(kvm, &control);
2618 if (r)
2619 goto out;
2620 r = 0;
2621 break;
2622 }
2623 case KVM_XEN_HVM_CONFIG: {
2624 r = -EFAULT;
2625 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2626 sizeof(struct kvm_xen_hvm_config)))
2627 goto out;
2628 r = -EINVAL;
2629 if (kvm->arch.xen_hvm_config.flags)
2630 goto out;
2631 r = 0;
2632 break;
2633 }
2634 case KVM_SET_CLOCK: {
2635 struct timespec now;
2636 struct kvm_clock_data user_ns;
2637 u64 now_ns;
2638 s64 delta;
2639
2640 r = -EFAULT;
2641 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2642 goto out;
2643
2644 r = -EINVAL;
2645 if (user_ns.flags)
2646 goto out;
2647
2648 r = 0;
2649 ktime_get_ts(&now);
2650 now_ns = timespec_to_ns(&now);
2651 delta = user_ns.clock - now_ns;
2652 kvm->arch.kvmclock_offset = delta;
2653 break;
2654 }
2655 case KVM_GET_CLOCK: {
2656 struct timespec now;
2657 struct kvm_clock_data user_ns;
2658 u64 now_ns;
2659
2660 ktime_get_ts(&now);
2661 now_ns = timespec_to_ns(&now);
2662 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2663 user_ns.flags = 0;
2664
2665 r = -EFAULT;
2666 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2667 goto out;
2668 r = 0;
2669 break;
2670 }
2671
2672 default:
2673 ;
2674 }
2675 out:
2676 return r;
2677 }
2678
2679 static void kvm_init_msr_list(void)
2680 {
2681 u32 dummy[2];
2682 unsigned i, j;
2683
2684 /* skip the first msrs in the list. KVM-specific */
2685 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
2686 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2687 continue;
2688 if (j < i)
2689 msrs_to_save[j] = msrs_to_save[i];
2690 j++;
2691 }
2692 num_msrs_to_save = j;
2693 }
2694
2695 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2696 const void *v)
2697 {
2698 if (vcpu->arch.apic &&
2699 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2700 return 0;
2701
2702 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
2703 }
2704
2705 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
2706 {
2707 if (vcpu->arch.apic &&
2708 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2709 return 0;
2710
2711 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
2712 }
2713
2714 static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2715 struct kvm_vcpu *vcpu)
2716 {
2717 void *data = val;
2718 int r = X86EMUL_CONTINUE;
2719
2720 while (bytes) {
2721 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2722 unsigned offset = addr & (PAGE_SIZE-1);
2723 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
2724 int ret;
2725
2726 if (gpa == UNMAPPED_GVA) {
2727 r = X86EMUL_PROPAGATE_FAULT;
2728 goto out;
2729 }
2730 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
2731 if (ret < 0) {
2732 r = X86EMUL_UNHANDLEABLE;
2733 goto out;
2734 }
2735
2736 bytes -= toread;
2737 data += toread;
2738 addr += toread;
2739 }
2740 out:
2741 return r;
2742 }
2743
2744 static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2745 struct kvm_vcpu *vcpu)
2746 {
2747 void *data = val;
2748 int r = X86EMUL_CONTINUE;
2749
2750 while (bytes) {
2751 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2752 unsigned offset = addr & (PAGE_SIZE-1);
2753 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2754 int ret;
2755
2756 if (gpa == UNMAPPED_GVA) {
2757 r = X86EMUL_PROPAGATE_FAULT;
2758 goto out;
2759 }
2760 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2761 if (ret < 0) {
2762 r = X86EMUL_UNHANDLEABLE;
2763 goto out;
2764 }
2765
2766 bytes -= towrite;
2767 data += towrite;
2768 addr += towrite;
2769 }
2770 out:
2771 return r;
2772 }
2773
2774
2775 static int emulator_read_emulated(unsigned long addr,
2776 void *val,
2777 unsigned int bytes,
2778 struct kvm_vcpu *vcpu)
2779 {
2780 gpa_t gpa;
2781
2782 if (vcpu->mmio_read_completed) {
2783 memcpy(val, vcpu->mmio_data, bytes);
2784 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2785 vcpu->mmio_phys_addr, *(u64 *)val);
2786 vcpu->mmio_read_completed = 0;
2787 return X86EMUL_CONTINUE;
2788 }
2789
2790 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2791
2792 /* For APIC access vmexit */
2793 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2794 goto mmio;
2795
2796 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2797 == X86EMUL_CONTINUE)
2798 return X86EMUL_CONTINUE;
2799 if (gpa == UNMAPPED_GVA)
2800 return X86EMUL_PROPAGATE_FAULT;
2801
2802 mmio:
2803 /*
2804 * Is this MMIO handled locally?
2805 */
2806 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2807 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
2808 return X86EMUL_CONTINUE;
2809 }
2810
2811 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
2812
2813 vcpu->mmio_needed = 1;
2814 vcpu->mmio_phys_addr = gpa;
2815 vcpu->mmio_size = bytes;
2816 vcpu->mmio_is_write = 0;
2817
2818 return X86EMUL_UNHANDLEABLE;
2819 }
2820
2821 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
2822 const void *val, int bytes)
2823 {
2824 int ret;
2825
2826 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
2827 if (ret < 0)
2828 return 0;
2829 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
2830 return 1;
2831 }
2832
2833 static int emulator_write_emulated_onepage(unsigned long addr,
2834 const void *val,
2835 unsigned int bytes,
2836 struct kvm_vcpu *vcpu)
2837 {
2838 gpa_t gpa;
2839
2840 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2841
2842 if (gpa == UNMAPPED_GVA) {
2843 kvm_inject_page_fault(vcpu, addr, 2);
2844 return X86EMUL_PROPAGATE_FAULT;
2845 }
2846
2847 /* For APIC access vmexit */
2848 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2849 goto mmio;
2850
2851 if (emulator_write_phys(vcpu, gpa, val, bytes))
2852 return X86EMUL_CONTINUE;
2853
2854 mmio:
2855 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
2856 /*
2857 * Is this MMIO handled locally?
2858 */
2859 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
2860 return X86EMUL_CONTINUE;
2861
2862 vcpu->mmio_needed = 1;
2863 vcpu->mmio_phys_addr = gpa;
2864 vcpu->mmio_size = bytes;
2865 vcpu->mmio_is_write = 1;
2866 memcpy(vcpu->mmio_data, val, bytes);
2867
2868 return X86EMUL_CONTINUE;
2869 }
2870
2871 int emulator_write_emulated(unsigned long addr,
2872 const void *val,
2873 unsigned int bytes,
2874 struct kvm_vcpu *vcpu)
2875 {
2876 /* Crossing a page boundary? */
2877 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2878 int rc, now;
2879
2880 now = -addr & ~PAGE_MASK;
2881 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2882 if (rc != X86EMUL_CONTINUE)
2883 return rc;
2884 addr += now;
2885 val += now;
2886 bytes -= now;
2887 }
2888 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2889 }
2890 EXPORT_SYMBOL_GPL(emulator_write_emulated);
2891
2892 static int emulator_cmpxchg_emulated(unsigned long addr,
2893 const void *old,
2894 const void *new,
2895 unsigned int bytes,
2896 struct kvm_vcpu *vcpu)
2897 {
2898 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2899 #ifndef CONFIG_X86_64
2900 /* guests cmpxchg8b have to be emulated atomically */
2901 if (bytes == 8) {
2902 gpa_t gpa;
2903 struct page *page;
2904 char *kaddr;
2905 u64 val;
2906
2907 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2908
2909 if (gpa == UNMAPPED_GVA ||
2910 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2911 goto emul_write;
2912
2913 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2914 goto emul_write;
2915
2916 val = *(u64 *)new;
2917
2918 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2919
2920 kaddr = kmap_atomic(page, KM_USER0);
2921 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2922 kunmap_atomic(kaddr, KM_USER0);
2923 kvm_release_page_dirty(page);
2924 }
2925 emul_write:
2926 #endif
2927
2928 return emulator_write_emulated(addr, new, bytes, vcpu);
2929 }
2930
2931 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2932 {
2933 return kvm_x86_ops->get_segment_base(vcpu, seg);
2934 }
2935
2936 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2937 {
2938 kvm_mmu_invlpg(vcpu, address);
2939 return X86EMUL_CONTINUE;
2940 }
2941
2942 int emulate_clts(struct kvm_vcpu *vcpu)
2943 {
2944 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
2945 return X86EMUL_CONTINUE;
2946 }
2947
2948 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2949 {
2950 struct kvm_vcpu *vcpu = ctxt->vcpu;
2951
2952 switch (dr) {
2953 case 0 ... 3:
2954 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2955 return X86EMUL_CONTINUE;
2956 default:
2957 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
2958 return X86EMUL_UNHANDLEABLE;
2959 }
2960 }
2961
2962 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2963 {
2964 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2965 int exception;
2966
2967 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2968 if (exception) {
2969 /* FIXME: better handling */
2970 return X86EMUL_UNHANDLEABLE;
2971 }
2972 return X86EMUL_CONTINUE;
2973 }
2974
2975 void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2976 {
2977 u8 opcodes[4];
2978 unsigned long rip = kvm_rip_read(vcpu);
2979 unsigned long rip_linear;
2980
2981 if (!printk_ratelimit())
2982 return;
2983
2984 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2985
2986 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
2987
2988 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2989 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
2990 }
2991 EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2992
2993 static struct x86_emulate_ops emulate_ops = {
2994 .read_std = kvm_read_guest_virt,
2995 .read_emulated = emulator_read_emulated,
2996 .write_emulated = emulator_write_emulated,
2997 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2998 };
2999
3000 static void cache_all_regs(struct kvm_vcpu *vcpu)
3001 {
3002 kvm_register_read(vcpu, VCPU_REGS_RAX);
3003 kvm_register_read(vcpu, VCPU_REGS_RSP);
3004 kvm_register_read(vcpu, VCPU_REGS_RIP);
3005 vcpu->arch.regs_dirty = ~0;
3006 }
3007
3008 int emulate_instruction(struct kvm_vcpu *vcpu,
3009 unsigned long cr2,
3010 u16 error_code,
3011 int emulation_type)
3012 {
3013 int r, shadow_mask;
3014 struct decode_cache *c;
3015 struct kvm_run *run = vcpu->run;
3016
3017 kvm_clear_exception_queue(vcpu);
3018 vcpu->arch.mmio_fault_cr2 = cr2;
3019 /*
3020 * TODO: fix emulate.c to use guest_read/write_register
3021 * instead of direct ->regs accesses, can save hundred cycles
3022 * on Intel for instructions that don't read/change RSP, for
3023 * for example.
3024 */
3025 cache_all_regs(vcpu);
3026
3027 vcpu->mmio_is_write = 0;
3028 vcpu->arch.pio.string = 0;
3029
3030 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
3031 int cs_db, cs_l;
3032 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3033
3034 vcpu->arch.emulate_ctxt.vcpu = vcpu;
3035 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
3036 vcpu->arch.emulate_ctxt.mode =
3037 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
3038 ? X86EMUL_MODE_REAL : cs_l
3039 ? X86EMUL_MODE_PROT64 : cs_db
3040 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3041
3042 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
3043
3044 /* Only allow emulation of specific instructions on #UD
3045 * (namely VMMCALL, sysenter, sysexit, syscall)*/
3046 c = &vcpu->arch.emulate_ctxt.decode;
3047 if (emulation_type & EMULTYPE_TRAP_UD) {
3048 if (!c->twobyte)
3049 return EMULATE_FAIL;
3050 switch (c->b) {
3051 case 0x01: /* VMMCALL */
3052 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3053 return EMULATE_FAIL;
3054 break;
3055 case 0x34: /* sysenter */
3056 case 0x35: /* sysexit */
3057 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3058 return EMULATE_FAIL;
3059 break;
3060 case 0x05: /* syscall */
3061 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3062 return EMULATE_FAIL;
3063 break;
3064 default:
3065 return EMULATE_FAIL;
3066 }
3067
3068 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3069 return EMULATE_FAIL;
3070 }
3071
3072 ++vcpu->stat.insn_emulation;
3073 if (r) {
3074 ++vcpu->stat.insn_emulation_fail;
3075 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3076 return EMULATE_DONE;
3077 return EMULATE_FAIL;
3078 }
3079 }
3080
3081 if (emulation_type & EMULTYPE_SKIP) {
3082 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3083 return EMULATE_DONE;
3084 }
3085
3086 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
3087 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3088
3089 if (r == 0)
3090 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
3091
3092 if (vcpu->arch.pio.string)
3093 return EMULATE_DO_MMIO;
3094
3095 if ((r || vcpu->mmio_is_write) && run) {
3096 run->exit_reason = KVM_EXIT_MMIO;
3097 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3098 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3099 run->mmio.len = vcpu->mmio_size;
3100 run->mmio.is_write = vcpu->mmio_is_write;
3101 }
3102
3103 if (r) {
3104 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3105 return EMULATE_DONE;
3106 if (!vcpu->mmio_needed) {
3107 kvm_report_emulation_failure(vcpu, "mmio");
3108 return EMULATE_FAIL;
3109 }
3110 return EMULATE_DO_MMIO;
3111 }
3112
3113 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3114
3115 if (vcpu->mmio_is_write) {
3116 vcpu->mmio_needed = 0;
3117 return EMULATE_DO_MMIO;
3118 }
3119
3120 return EMULATE_DONE;
3121 }
3122 EXPORT_SYMBOL_GPL(emulate_instruction);
3123
3124 static int pio_copy_data(struct kvm_vcpu *vcpu)
3125 {
3126 void *p = vcpu->arch.pio_data;
3127 gva_t q = vcpu->arch.pio.guest_gva;
3128 unsigned bytes;
3129 int ret;
3130
3131 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3132 if (vcpu->arch.pio.in)
3133 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
3134 else
3135 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
3136 return ret;
3137 }
3138
3139 int complete_pio(struct kvm_vcpu *vcpu)
3140 {
3141 struct kvm_pio_request *io = &vcpu->arch.pio;
3142 long delta;
3143 int r;
3144 unsigned long val;
3145
3146 if (!io->string) {
3147 if (io->in) {
3148 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3149 memcpy(&val, vcpu->arch.pio_data, io->size);
3150 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3151 }
3152 } else {
3153 if (io->in) {
3154 r = pio_copy_data(vcpu);
3155 if (r)
3156 return r;
3157 }
3158
3159 delta = 1;
3160 if (io->rep) {
3161 delta *= io->cur_count;
3162 /*
3163 * The size of the register should really depend on
3164 * current address size.
3165 */
3166 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3167 val -= delta;
3168 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
3169 }
3170 if (io->down)
3171 delta = -delta;
3172 delta *= io->size;
3173 if (io->in) {
3174 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3175 val += delta;
3176 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3177 } else {
3178 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3179 val += delta;
3180 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3181 }
3182 }
3183
3184 io->count -= io->cur_count;
3185 io->cur_count = 0;
3186
3187 return 0;
3188 }
3189
3190 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3191 {
3192 /* TODO: String I/O for in kernel device */
3193 int r;
3194
3195 if (vcpu->arch.pio.in)
3196 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
3197 vcpu->arch.pio.size, pd);
3198 else
3199 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
3200 vcpu->arch.pio.size, pd);
3201 return r;
3202 }
3203
3204 static int pio_string_write(struct kvm_vcpu *vcpu)
3205 {
3206 struct kvm_pio_request *io = &vcpu->arch.pio;
3207 void *pd = vcpu->arch.pio_data;
3208 int i, r = 0;
3209
3210 for (i = 0; i < io->cur_count; i++) {
3211 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
3212 io->port, io->size, pd)) {
3213 r = -EOPNOTSUPP;
3214 break;
3215 }
3216 pd += io->size;
3217 }
3218 return r;
3219 }
3220
3221 int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
3222 {
3223 unsigned long val;
3224
3225 vcpu->run->exit_reason = KVM_EXIT_IO;
3226 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
3227 vcpu->run->io.size = vcpu->arch.pio.size = size;
3228 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3229 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3230 vcpu->run->io.port = vcpu->arch.pio.port = port;
3231 vcpu->arch.pio.in = in;
3232 vcpu->arch.pio.string = 0;
3233 vcpu->arch.pio.down = 0;
3234 vcpu->arch.pio.rep = 0;
3235
3236 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3237 size, 1);
3238
3239 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3240 memcpy(vcpu->arch.pio_data, &val, 4);
3241
3242 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3243 complete_pio(vcpu);
3244 return 1;
3245 }
3246 return 0;
3247 }
3248 EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3249
3250 int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
3251 int size, unsigned long count, int down,
3252 gva_t address, int rep, unsigned port)
3253 {
3254 unsigned now, in_page;
3255 int ret = 0;
3256
3257 vcpu->run->exit_reason = KVM_EXIT_IO;
3258 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
3259 vcpu->run->io.size = vcpu->arch.pio.size = size;
3260 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3261 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3262 vcpu->run->io.port = vcpu->arch.pio.port = port;
3263 vcpu->arch.pio.in = in;
3264 vcpu->arch.pio.string = 1;
3265 vcpu->arch.pio.down = down;
3266 vcpu->arch.pio.rep = rep;
3267
3268 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3269 size, count);
3270
3271 if (!count) {
3272 kvm_x86_ops->skip_emulated_instruction(vcpu);
3273 return 1;
3274 }
3275
3276 if (!down)
3277 in_page = PAGE_SIZE - offset_in_page(address);
3278 else
3279 in_page = offset_in_page(address) + size;
3280 now = min(count, (unsigned long)in_page / size);
3281 if (!now)
3282 now = 1;
3283 if (down) {
3284 /*
3285 * String I/O in reverse. Yuck. Kill the guest, fix later.
3286 */
3287 pr_unimpl(vcpu, "guest string pio down\n");
3288 kvm_inject_gp(vcpu, 0);
3289 return 1;
3290 }
3291 vcpu->run->io.count = now;
3292 vcpu->arch.pio.cur_count = now;
3293
3294 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
3295 kvm_x86_ops->skip_emulated_instruction(vcpu);
3296
3297 vcpu->arch.pio.guest_gva = address;
3298
3299 if (!vcpu->arch.pio.in) {
3300 /* string PIO write */
3301 ret = pio_copy_data(vcpu);
3302 if (ret == X86EMUL_PROPAGATE_FAULT) {
3303 kvm_inject_gp(vcpu, 0);
3304 return 1;
3305 }
3306 if (ret == 0 && !pio_string_write(vcpu)) {
3307 complete_pio(vcpu);
3308 if (vcpu->arch.pio.count == 0)
3309 ret = 1;
3310 }
3311 }
3312 /* no string PIO read support yet */
3313
3314 return ret;
3315 }
3316 EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3317
3318 static void bounce_off(void *info)
3319 {
3320 /* nothing */
3321 }
3322
3323 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3324 void *data)
3325 {
3326 struct cpufreq_freqs *freq = data;
3327 struct kvm *kvm;
3328 struct kvm_vcpu *vcpu;
3329 int i, send_ipi = 0;
3330
3331 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3332 return 0;
3333 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3334 return 0;
3335 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
3336
3337 spin_lock(&kvm_lock);
3338 list_for_each_entry(kvm, &vm_list, vm_list) {
3339 kvm_for_each_vcpu(i, vcpu, kvm) {
3340 if (vcpu->cpu != freq->cpu)
3341 continue;
3342 if (!kvm_request_guest_time_update(vcpu))
3343 continue;
3344 if (vcpu->cpu != smp_processor_id())
3345 send_ipi++;
3346 }
3347 }
3348 spin_unlock(&kvm_lock);
3349
3350 if (freq->old < freq->new && send_ipi) {
3351 /*
3352 * We upscale the frequency. Must make the guest
3353 * doesn't see old kvmclock values while running with
3354 * the new frequency, otherwise we risk the guest sees
3355 * time go backwards.
3356 *
3357 * In case we update the frequency for another cpu
3358 * (which might be in guest context) send an interrupt
3359 * to kick the cpu out of guest context. Next time
3360 * guest context is entered kvmclock will be updated,
3361 * so the guest will not see stale values.
3362 */
3363 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3364 }
3365 return 0;
3366 }
3367
3368 static struct notifier_block kvmclock_cpufreq_notifier_block = {
3369 .notifier_call = kvmclock_cpufreq_notifier
3370 };
3371
3372 static void kvm_timer_init(void)
3373 {
3374 int cpu;
3375
3376 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3377 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3378 CPUFREQ_TRANSITION_NOTIFIER);
3379 for_each_online_cpu(cpu) {
3380 unsigned long khz = cpufreq_get(cpu);
3381 if (!khz)
3382 khz = tsc_khz;
3383 per_cpu(cpu_tsc_khz, cpu) = khz;
3384 }
3385 } else {
3386 for_each_possible_cpu(cpu)
3387 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3388 }
3389 }
3390
3391 int kvm_arch_init(void *opaque)
3392 {
3393 int r;
3394 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3395
3396 if (kvm_x86_ops) {
3397 printk(KERN_ERR "kvm: already loaded the other module\n");
3398 r = -EEXIST;
3399 goto out;
3400 }
3401
3402 if (!ops->cpu_has_kvm_support()) {
3403 printk(KERN_ERR "kvm: no hardware support\n");
3404 r = -EOPNOTSUPP;
3405 goto out;
3406 }
3407 if (ops->disabled_by_bios()) {
3408 printk(KERN_ERR "kvm: disabled by bios\n");
3409 r = -EOPNOTSUPP;
3410 goto out;
3411 }
3412
3413 r = kvm_mmu_module_init();
3414 if (r)
3415 goto out;
3416
3417 kvm_init_msr_list();
3418
3419 kvm_x86_ops = ops;
3420 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
3421 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3422 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
3423 PT_DIRTY_MASK, PT64_NX_MASK, 0);
3424
3425 kvm_timer_init();
3426
3427 return 0;
3428
3429 out:
3430 return r;
3431 }
3432
3433 void kvm_arch_exit(void)
3434 {
3435 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3436 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3437 CPUFREQ_TRANSITION_NOTIFIER);
3438 kvm_x86_ops = NULL;
3439 kvm_mmu_module_exit();
3440 }
3441
3442 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3443 {
3444 ++vcpu->stat.halt_exits;
3445 if (irqchip_in_kernel(vcpu->kvm)) {
3446 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3447 return 1;
3448 } else {
3449 vcpu->run->exit_reason = KVM_EXIT_HLT;
3450 return 0;
3451 }
3452 }
3453 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3454
3455 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3456 unsigned long a1)
3457 {
3458 if (is_long_mode(vcpu))
3459 return a0;
3460 else
3461 return a0 | ((gpa_t)a1 << 32);
3462 }
3463
3464 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3465 {
3466 unsigned long nr, a0, a1, a2, a3, ret;
3467 int r = 1;
3468
3469 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3470 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3471 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3472 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3473 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
3474
3475 trace_kvm_hypercall(nr, a0, a1, a2, a3);
3476
3477 if (!is_long_mode(vcpu)) {
3478 nr &= 0xFFFFFFFF;
3479 a0 &= 0xFFFFFFFF;
3480 a1 &= 0xFFFFFFFF;
3481 a2 &= 0xFFFFFFFF;
3482 a3 &= 0xFFFFFFFF;
3483 }
3484
3485 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3486 ret = -KVM_EPERM;
3487 goto out;
3488 }
3489
3490 switch (nr) {
3491 case KVM_HC_VAPIC_POLL_IRQ:
3492 ret = 0;
3493 break;
3494 case KVM_HC_MMU_OP:
3495 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3496 break;
3497 default:
3498 ret = -KVM_ENOSYS;
3499 break;
3500 }
3501 out:
3502 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3503 ++vcpu->stat.hypercalls;
3504 return r;
3505 }
3506 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3507
3508 int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3509 {
3510 char instruction[3];
3511 int ret = 0;
3512 unsigned long rip = kvm_rip_read(vcpu);
3513
3514
3515 /*
3516 * Blow out the MMU to ensure that no other VCPU has an active mapping
3517 * to ensure that the updated hypercall appears atomically across all
3518 * VCPUs.
3519 */
3520 kvm_mmu_zap_all(vcpu->kvm);
3521
3522 kvm_x86_ops->patch_hypercall(vcpu, instruction);
3523 if (emulator_write_emulated(rip, instruction, 3, vcpu)
3524 != X86EMUL_CONTINUE)
3525 ret = -EFAULT;
3526
3527 return ret;
3528 }
3529
3530 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3531 {
3532 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3533 }
3534
3535 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3536 {
3537 struct descriptor_table dt = { limit, base };
3538
3539 kvm_x86_ops->set_gdt(vcpu, &dt);
3540 }
3541
3542 void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3543 {
3544 struct descriptor_table dt = { limit, base };
3545
3546 kvm_x86_ops->set_idt(vcpu, &dt);
3547 }
3548
3549 void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3550 unsigned long *rflags)
3551 {
3552 kvm_lmsw(vcpu, msw);
3553 *rflags = kvm_get_rflags(vcpu);
3554 }
3555
3556 unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3557 {
3558 unsigned long value;
3559
3560 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3561 switch (cr) {
3562 case 0:
3563 value = vcpu->arch.cr0;
3564 break;
3565 case 2:
3566 value = vcpu->arch.cr2;
3567 break;
3568 case 3:
3569 value = vcpu->arch.cr3;
3570 break;
3571 case 4:
3572 value = vcpu->arch.cr4;
3573 break;
3574 case 8:
3575 value = kvm_get_cr8(vcpu);
3576 break;
3577 default:
3578 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3579 return 0;
3580 }
3581
3582 return value;
3583 }
3584
3585 void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3586 unsigned long *rflags)
3587 {
3588 switch (cr) {
3589 case 0:
3590 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
3591 *rflags = kvm_get_rflags(vcpu);
3592 break;
3593 case 2:
3594 vcpu->arch.cr2 = val;
3595 break;
3596 case 3:
3597 kvm_set_cr3(vcpu, val);
3598 break;
3599 case 4:
3600 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
3601 break;
3602 case 8:
3603 kvm_set_cr8(vcpu, val & 0xfUL);
3604 break;
3605 default:
3606 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3607 }
3608 }
3609
3610 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3611 {
3612 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3613 int j, nent = vcpu->arch.cpuid_nent;
3614
3615 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3616 /* when no next entry is found, the current entry[i] is reselected */
3617 for (j = i + 1; ; j = (j + 1) % nent) {
3618 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
3619 if (ej->function == e->function) {
3620 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3621 return j;
3622 }
3623 }
3624 return 0; /* silence gcc, even though control never reaches here */
3625 }
3626
3627 /* find an entry with matching function, matching index (if needed), and that
3628 * should be read next (if it's stateful) */
3629 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3630 u32 function, u32 index)
3631 {
3632 if (e->function != function)
3633 return 0;
3634 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3635 return 0;
3636 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
3637 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
3638 return 0;
3639 return 1;
3640 }
3641
3642 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3643 u32 function, u32 index)
3644 {
3645 int i;
3646 struct kvm_cpuid_entry2 *best = NULL;
3647
3648 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
3649 struct kvm_cpuid_entry2 *e;
3650
3651 e = &vcpu->arch.cpuid_entries[i];
3652 if (is_matching_cpuid_entry(e, function, index)) {
3653 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3654 move_to_next_stateful_cpuid_entry(vcpu, i);
3655 best = e;
3656 break;
3657 }
3658 /*
3659 * Both basic or both extended?
3660 */
3661 if (((e->function ^ function) & 0x80000000) == 0)
3662 if (!best || e->function > best->function)
3663 best = e;
3664 }
3665 return best;
3666 }
3667
3668 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3669 {
3670 struct kvm_cpuid_entry2 *best;
3671
3672 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3673 if (best)
3674 return best->eax & 0xff;
3675 return 36;
3676 }
3677
3678 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3679 {
3680 u32 function, index;
3681 struct kvm_cpuid_entry2 *best;
3682
3683 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3684 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3685 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3686 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3687 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3688 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3689 best = kvm_find_cpuid_entry(vcpu, function, index);
3690 if (best) {
3691 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3692 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3693 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3694 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
3695 }
3696 kvm_x86_ops->skip_emulated_instruction(vcpu);
3697 trace_kvm_cpuid(function,
3698 kvm_register_read(vcpu, VCPU_REGS_RAX),
3699 kvm_register_read(vcpu, VCPU_REGS_RBX),
3700 kvm_register_read(vcpu, VCPU_REGS_RCX),
3701 kvm_register_read(vcpu, VCPU_REGS_RDX));
3702 }
3703 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
3704
3705 /*
3706 * Check if userspace requested an interrupt window, and that the
3707 * interrupt window is open.
3708 *
3709 * No need to exit to userspace if we already have an interrupt queued.
3710 */
3711 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
3712 {
3713 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
3714 vcpu->run->request_interrupt_window &&
3715 kvm_arch_interrupt_allowed(vcpu));
3716 }
3717
3718 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
3719 {
3720 struct kvm_run *kvm_run = vcpu->run;
3721
3722 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
3723 kvm_run->cr8 = kvm_get_cr8(vcpu);
3724 kvm_run->apic_base = kvm_get_apic_base(vcpu);
3725 if (irqchip_in_kernel(vcpu->kvm))
3726 kvm_run->ready_for_interrupt_injection = 1;
3727 else
3728 kvm_run->ready_for_interrupt_injection =
3729 kvm_arch_interrupt_allowed(vcpu) &&
3730 !kvm_cpu_has_interrupt(vcpu) &&
3731 !kvm_event_needs_reinjection(vcpu);
3732 }
3733
3734 static void vapic_enter(struct kvm_vcpu *vcpu)
3735 {
3736 struct kvm_lapic *apic = vcpu->arch.apic;
3737 struct page *page;
3738
3739 if (!apic || !apic->vapic_addr)
3740 return;
3741
3742 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3743
3744 vcpu->arch.apic->vapic_page = page;
3745 }
3746
3747 static void vapic_exit(struct kvm_vcpu *vcpu)
3748 {
3749 struct kvm_lapic *apic = vcpu->arch.apic;
3750
3751 if (!apic || !apic->vapic_addr)
3752 return;
3753
3754 down_read(&vcpu->kvm->slots_lock);
3755 kvm_release_page_dirty(apic->vapic_page);
3756 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3757 up_read(&vcpu->kvm->slots_lock);
3758 }
3759
3760 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3761 {
3762 int max_irr, tpr;
3763
3764 if (!kvm_x86_ops->update_cr8_intercept)
3765 return;
3766
3767 if (!vcpu->arch.apic)
3768 return;
3769
3770 if (!vcpu->arch.apic->vapic_addr)
3771 max_irr = kvm_lapic_find_highest_irr(vcpu);
3772 else
3773 max_irr = -1;
3774
3775 if (max_irr != -1)
3776 max_irr >>= 4;
3777
3778 tpr = kvm_lapic_get_cr8(vcpu);
3779
3780 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3781 }
3782
3783 static void inject_pending_event(struct kvm_vcpu *vcpu)
3784 {
3785 /* try to reinject previous events if any */
3786 if (vcpu->arch.exception.pending) {
3787 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3788 vcpu->arch.exception.has_error_code,
3789 vcpu->arch.exception.error_code);
3790 return;
3791 }
3792
3793 if (vcpu->arch.nmi_injected) {
3794 kvm_x86_ops->set_nmi(vcpu);
3795 return;
3796 }
3797
3798 if (vcpu->arch.interrupt.pending) {
3799 kvm_x86_ops->set_irq(vcpu);
3800 return;
3801 }
3802
3803 /* try to inject new event if pending */
3804 if (vcpu->arch.nmi_pending) {
3805 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3806 vcpu->arch.nmi_pending = false;
3807 vcpu->arch.nmi_injected = true;
3808 kvm_x86_ops->set_nmi(vcpu);
3809 }
3810 } else if (kvm_cpu_has_interrupt(vcpu)) {
3811 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
3812 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3813 false);
3814 kvm_x86_ops->set_irq(vcpu);
3815 }
3816 }
3817 }
3818
3819 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
3820 {
3821 int r;
3822 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3823 vcpu->run->request_interrupt_window;
3824
3825 if (vcpu->requests)
3826 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3827 kvm_mmu_unload(vcpu);
3828
3829 r = kvm_mmu_reload(vcpu);
3830 if (unlikely(r))
3831 goto out;
3832
3833 if (vcpu->requests) {
3834 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
3835 __kvm_migrate_timers(vcpu);
3836 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3837 kvm_write_guest_time(vcpu);
3838 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3839 kvm_mmu_sync_roots(vcpu);
3840 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3841 kvm_x86_ops->tlb_flush(vcpu);
3842 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3843 &vcpu->requests)) {
3844 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
3845 r = 0;
3846 goto out;
3847 }
3848 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3849 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3850 r = 0;
3851 goto out;
3852 }
3853 }
3854
3855 preempt_disable();
3856
3857 kvm_x86_ops->prepare_guest_switch(vcpu);
3858 kvm_load_guest_fpu(vcpu);
3859
3860 local_irq_disable();
3861
3862 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3863 smp_mb__after_clear_bit();
3864
3865 if (vcpu->requests || need_resched() || signal_pending(current)) {
3866 set_bit(KVM_REQ_KICK, &vcpu->requests);
3867 local_irq_enable();
3868 preempt_enable();
3869 r = 1;
3870 goto out;
3871 }
3872
3873 inject_pending_event(vcpu);
3874
3875 /* enable NMI/IRQ window open exits if needed */
3876 if (vcpu->arch.nmi_pending)
3877 kvm_x86_ops->enable_nmi_window(vcpu);
3878 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3879 kvm_x86_ops->enable_irq_window(vcpu);
3880
3881 if (kvm_lapic_enabled(vcpu)) {
3882 update_cr8_intercept(vcpu);
3883 kvm_lapic_sync_to_vapic(vcpu);
3884 }
3885
3886 up_read(&vcpu->kvm->slots_lock);
3887
3888 kvm_guest_enter();
3889
3890 if (unlikely(vcpu->arch.switch_db_regs)) {
3891 set_debugreg(0, 7);
3892 set_debugreg(vcpu->arch.eff_db[0], 0);
3893 set_debugreg(vcpu->arch.eff_db[1], 1);
3894 set_debugreg(vcpu->arch.eff_db[2], 2);
3895 set_debugreg(vcpu->arch.eff_db[3], 3);
3896 }
3897
3898 trace_kvm_entry(vcpu->vcpu_id);
3899 kvm_x86_ops->run(vcpu);
3900
3901 /*
3902 * If the guest has used debug registers, at least dr7
3903 * will be disabled while returning to the host.
3904 * If we don't have active breakpoints in the host, we don't
3905 * care about the messed up debug address registers. But if
3906 * we have some of them active, restore the old state.
3907 */
3908 if (hw_breakpoint_active())
3909 hw_breakpoint_restore();
3910
3911 set_bit(KVM_REQ_KICK, &vcpu->requests);
3912 local_irq_enable();
3913
3914 ++vcpu->stat.exits;
3915
3916 /*
3917 * We must have an instruction between local_irq_enable() and
3918 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3919 * the interrupt shadow. The stat.exits increment will do nicely.
3920 * But we need to prevent reordering, hence this barrier():
3921 */
3922 barrier();
3923
3924 kvm_guest_exit();
3925
3926 preempt_enable();
3927
3928 down_read(&vcpu->kvm->slots_lock);
3929
3930 /*
3931 * Profile KVM exit RIPs:
3932 */
3933 if (unlikely(prof_on == KVM_PROFILING)) {
3934 unsigned long rip = kvm_rip_read(vcpu);
3935 profile_hit(KVM_PROFILING, (void *)rip);
3936 }
3937
3938
3939 kvm_lapic_sync_from_vapic(vcpu);
3940
3941 r = kvm_x86_ops->handle_exit(vcpu);
3942 out:
3943 return r;
3944 }
3945
3946
3947 static int __vcpu_run(struct kvm_vcpu *vcpu)
3948 {
3949 int r;
3950
3951 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
3952 pr_debug("vcpu %d received sipi with vector # %x\n",
3953 vcpu->vcpu_id, vcpu->arch.sipi_vector);
3954 kvm_lapic_reset(vcpu);
3955 r = kvm_arch_vcpu_reset(vcpu);
3956 if (r)
3957 return r;
3958 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3959 }
3960
3961 down_read(&vcpu->kvm->slots_lock);
3962 vapic_enter(vcpu);
3963
3964 r = 1;
3965 while (r > 0) {
3966 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
3967 r = vcpu_enter_guest(vcpu);
3968 else {
3969 up_read(&vcpu->kvm->slots_lock);
3970 kvm_vcpu_block(vcpu);
3971 down_read(&vcpu->kvm->slots_lock);
3972 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3973 {
3974 switch(vcpu->arch.mp_state) {
3975 case KVM_MP_STATE_HALTED:
3976 vcpu->arch.mp_state =
3977 KVM_MP_STATE_RUNNABLE;
3978 case KVM_MP_STATE_RUNNABLE:
3979 break;
3980 case KVM_MP_STATE_SIPI_RECEIVED:
3981 default:
3982 r = -EINTR;
3983 break;
3984 }
3985 }
3986 }
3987
3988 if (r <= 0)
3989 break;
3990
3991 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3992 if (kvm_cpu_has_pending_timer(vcpu))
3993 kvm_inject_pending_timer_irqs(vcpu);
3994
3995 if (dm_request_for_irq_injection(vcpu)) {
3996 r = -EINTR;
3997 vcpu->run->exit_reason = KVM_EXIT_INTR;
3998 ++vcpu->stat.request_irq_exits;
3999 }
4000 if (signal_pending(current)) {
4001 r = -EINTR;
4002 vcpu->run->exit_reason = KVM_EXIT_INTR;
4003 ++vcpu->stat.signal_exits;
4004 }
4005 if (need_resched()) {
4006 up_read(&vcpu->kvm->slots_lock);
4007 kvm_resched(vcpu);
4008 down_read(&vcpu->kvm->slots_lock);
4009 }
4010 }
4011
4012 up_read(&vcpu->kvm->slots_lock);
4013 post_kvm_run_save(vcpu);
4014
4015 vapic_exit(vcpu);
4016
4017 return r;
4018 }
4019
4020 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4021 {
4022 int r;
4023 sigset_t sigsaved;
4024
4025 vcpu_load(vcpu);
4026
4027 if (vcpu->sigset_active)
4028 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4029
4030 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
4031 kvm_vcpu_block(vcpu);
4032 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
4033 r = -EAGAIN;
4034 goto out;
4035 }
4036
4037 /* re-sync apic's tpr */
4038 if (!irqchip_in_kernel(vcpu->kvm))
4039 kvm_set_cr8(vcpu, kvm_run->cr8);
4040
4041 if (vcpu->arch.pio.cur_count) {
4042 r = complete_pio(vcpu);
4043 if (r)
4044 goto out;
4045 }
4046 if (vcpu->mmio_needed) {
4047 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4048 vcpu->mmio_read_completed = 1;
4049 vcpu->mmio_needed = 0;
4050
4051 down_read(&vcpu->kvm->slots_lock);
4052 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
4053 EMULTYPE_NO_DECODE);
4054 up_read(&vcpu->kvm->slots_lock);
4055 if (r == EMULATE_DO_MMIO) {
4056 /*
4057 * Read-modify-write. Back to userspace.
4058 */
4059 r = 0;
4060 goto out;
4061 }
4062 }
4063 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4064 kvm_register_write(vcpu, VCPU_REGS_RAX,
4065 kvm_run->hypercall.ret);
4066
4067 r = __vcpu_run(vcpu);
4068
4069 out:
4070 if (vcpu->sigset_active)
4071 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4072
4073 vcpu_put(vcpu);
4074 return r;
4075 }
4076
4077 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4078 {
4079 vcpu_load(vcpu);
4080
4081 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4082 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4083 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4084 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4085 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4086 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4087 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4088 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4089 #ifdef CONFIG_X86_64
4090 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4091 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4092 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4093 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4094 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4095 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4096 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4097 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
4098 #endif
4099
4100 regs->rip = kvm_rip_read(vcpu);
4101 regs->rflags = kvm_get_rflags(vcpu);
4102
4103 vcpu_put(vcpu);
4104
4105 return 0;
4106 }
4107
4108 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4109 {
4110 vcpu_load(vcpu);
4111
4112 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4113 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4114 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4115 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4116 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4117 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4118 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4119 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
4120 #ifdef CONFIG_X86_64
4121 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4122 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4123 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4124 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4125 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4126 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4127 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4128 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
4129 #endif
4130
4131 kvm_rip_write(vcpu, regs->rip);
4132 kvm_set_rflags(vcpu, regs->rflags);
4133
4134 vcpu->arch.exception.pending = false;
4135
4136 vcpu_put(vcpu);
4137
4138 return 0;
4139 }
4140
4141 void kvm_get_segment(struct kvm_vcpu *vcpu,
4142 struct kvm_segment *var, int seg)
4143 {
4144 kvm_x86_ops->get_segment(vcpu, var, seg);
4145 }
4146
4147 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4148 {
4149 struct kvm_segment cs;
4150
4151 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
4152 *db = cs.db;
4153 *l = cs.l;
4154 }
4155 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4156
4157 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4158 struct kvm_sregs *sregs)
4159 {
4160 struct descriptor_table dt;
4161
4162 vcpu_load(vcpu);
4163
4164 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4165 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4166 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4167 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4168 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4169 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
4170
4171 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4172 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
4173
4174 kvm_x86_ops->get_idt(vcpu, &dt);
4175 sregs->idt.limit = dt.limit;
4176 sregs->idt.base = dt.base;
4177 kvm_x86_ops->get_gdt(vcpu, &dt);
4178 sregs->gdt.limit = dt.limit;
4179 sregs->gdt.base = dt.base;
4180
4181 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4182 sregs->cr0 = vcpu->arch.cr0;
4183 sregs->cr2 = vcpu->arch.cr2;
4184 sregs->cr3 = vcpu->arch.cr3;
4185 sregs->cr4 = vcpu->arch.cr4;
4186 sregs->cr8 = kvm_get_cr8(vcpu);
4187 sregs->efer = vcpu->arch.shadow_efer;
4188 sregs->apic_base = kvm_get_apic_base(vcpu);
4189
4190 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
4191
4192 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
4193 set_bit(vcpu->arch.interrupt.nr,
4194 (unsigned long *)sregs->interrupt_bitmap);
4195
4196 vcpu_put(vcpu);
4197
4198 return 0;
4199 }
4200
4201 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4202 struct kvm_mp_state *mp_state)
4203 {
4204 vcpu_load(vcpu);
4205 mp_state->mp_state = vcpu->arch.mp_state;
4206 vcpu_put(vcpu);
4207 return 0;
4208 }
4209
4210 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4211 struct kvm_mp_state *mp_state)
4212 {
4213 vcpu_load(vcpu);
4214 vcpu->arch.mp_state = mp_state->mp_state;
4215 vcpu_put(vcpu);
4216 return 0;
4217 }
4218
4219 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4220 struct kvm_segment *var, int seg)
4221 {
4222 kvm_x86_ops->set_segment(vcpu, var, seg);
4223 }
4224
4225 static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4226 struct kvm_segment *kvm_desct)
4227 {
4228 kvm_desct->base = get_desc_base(seg_desc);
4229 kvm_desct->limit = get_desc_limit(seg_desc);
4230 if (seg_desc->g) {
4231 kvm_desct->limit <<= 12;
4232 kvm_desct->limit |= 0xfff;
4233 }
4234 kvm_desct->selector = selector;
4235 kvm_desct->type = seg_desc->type;
4236 kvm_desct->present = seg_desc->p;
4237 kvm_desct->dpl = seg_desc->dpl;
4238 kvm_desct->db = seg_desc->d;
4239 kvm_desct->s = seg_desc->s;
4240 kvm_desct->l = seg_desc->l;
4241 kvm_desct->g = seg_desc->g;
4242 kvm_desct->avl = seg_desc->avl;
4243 if (!selector)
4244 kvm_desct->unusable = 1;
4245 else
4246 kvm_desct->unusable = 0;
4247 kvm_desct->padding = 0;
4248 }
4249
4250 static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4251 u16 selector,
4252 struct descriptor_table *dtable)
4253 {
4254 if (selector & 1 << 2) {
4255 struct kvm_segment kvm_seg;
4256
4257 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
4258
4259 if (kvm_seg.unusable)
4260 dtable->limit = 0;
4261 else
4262 dtable->limit = kvm_seg.limit;
4263 dtable->base = kvm_seg.base;
4264 }
4265 else
4266 kvm_x86_ops->get_gdt(vcpu, dtable);
4267 }
4268
4269 /* allowed just for 8 bytes segments */
4270 static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4271 struct desc_struct *seg_desc)
4272 {
4273 struct descriptor_table dtable;
4274 u16 index = selector >> 3;
4275
4276 get_segment_descriptor_dtable(vcpu, selector, &dtable);
4277
4278 if (dtable.limit < index * 8 + 7) {
4279 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4280 return 1;
4281 }
4282 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
4283 }
4284
4285 /* allowed just for 8 bytes segments */
4286 static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4287 struct desc_struct *seg_desc)
4288 {
4289 struct descriptor_table dtable;
4290 u16 index = selector >> 3;
4291
4292 get_segment_descriptor_dtable(vcpu, selector, &dtable);
4293
4294 if (dtable.limit < index * 8 + 7)
4295 return 1;
4296 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
4297 }
4298
4299 static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
4300 struct desc_struct *seg_desc)
4301 {
4302 u32 base_addr = get_desc_base(seg_desc);
4303
4304 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
4305 }
4306
4307 static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4308 {
4309 struct kvm_segment kvm_seg;
4310
4311 kvm_get_segment(vcpu, &kvm_seg, seg);
4312 return kvm_seg.selector;
4313 }
4314
4315 static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4316 u16 selector,
4317 struct kvm_segment *kvm_seg)
4318 {
4319 struct desc_struct seg_desc;
4320
4321 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4322 return 1;
4323 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4324 return 0;
4325 }
4326
4327 static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
4328 {
4329 struct kvm_segment segvar = {
4330 .base = selector << 4,
4331 .limit = 0xffff,
4332 .selector = selector,
4333 .type = 3,
4334 .present = 1,
4335 .dpl = 3,
4336 .db = 0,
4337 .s = 1,
4338 .l = 0,
4339 .g = 0,
4340 .avl = 0,
4341 .unusable = 0,
4342 };
4343 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4344 return 0;
4345 }
4346
4347 static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4348 {
4349 return (seg != VCPU_SREG_LDTR) &&
4350 (seg != VCPU_SREG_TR) &&
4351 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
4352 }
4353
4354 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4355 int type_bits, int seg)
4356 {
4357 struct kvm_segment kvm_seg;
4358
4359 if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
4360 return kvm_load_realmode_segment(vcpu, selector, seg);
4361 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4362 return 1;
4363 kvm_seg.type |= type_bits;
4364
4365 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4366 seg != VCPU_SREG_LDTR)
4367 if (!kvm_seg.s)
4368 kvm_seg.unusable = 1;
4369
4370 kvm_set_segment(vcpu, &kvm_seg, seg);
4371 return 0;
4372 }
4373
4374 static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4375 struct tss_segment_32 *tss)
4376 {
4377 tss->cr3 = vcpu->arch.cr3;
4378 tss->eip = kvm_rip_read(vcpu);
4379 tss->eflags = kvm_get_rflags(vcpu);
4380 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4381 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4382 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4383 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4384 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4385 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4386 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4387 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4388 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4389 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4390 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4391 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4392 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4393 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4394 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4395 }
4396
4397 static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4398 struct tss_segment_32 *tss)
4399 {
4400 kvm_set_cr3(vcpu, tss->cr3);
4401
4402 kvm_rip_write(vcpu, tss->eip);
4403 kvm_set_rflags(vcpu, tss->eflags | 2);
4404
4405 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4406 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4407 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4408 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4409 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4410 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4411 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4412 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
4413
4414 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
4415 return 1;
4416
4417 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4418 return 1;
4419
4420 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4421 return 1;
4422
4423 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4424 return 1;
4425
4426 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4427 return 1;
4428
4429 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
4430 return 1;
4431
4432 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
4433 return 1;
4434 return 0;
4435 }
4436
4437 static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4438 struct tss_segment_16 *tss)
4439 {
4440 tss->ip = kvm_rip_read(vcpu);
4441 tss->flag = kvm_get_rflags(vcpu);
4442 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4443 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4444 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4445 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4446 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4447 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4448 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4449 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
4450
4451 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4452 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4453 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4454 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4455 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4456 }
4457
4458 static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4459 struct tss_segment_16 *tss)
4460 {
4461 kvm_rip_write(vcpu, tss->ip);
4462 kvm_set_rflags(vcpu, tss->flag | 2);
4463 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4464 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4465 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4466 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4467 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4468 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4469 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4470 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
4471
4472 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
4473 return 1;
4474
4475 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4476 return 1;
4477
4478 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4479 return 1;
4480
4481 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4482 return 1;
4483
4484 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4485 return 1;
4486 return 0;
4487 }
4488
4489 static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
4490 u16 old_tss_sel, u32 old_tss_base,
4491 struct desc_struct *nseg_desc)
4492 {
4493 struct tss_segment_16 tss_segment_16;
4494 int ret = 0;
4495
4496 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4497 sizeof tss_segment_16))
4498 goto out;
4499
4500 save_state_to_tss16(vcpu, &tss_segment_16);
4501
4502 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4503 sizeof tss_segment_16))
4504 goto out;
4505
4506 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4507 &tss_segment_16, sizeof tss_segment_16))
4508 goto out;
4509
4510 if (old_tss_sel != 0xffff) {
4511 tss_segment_16.prev_task_link = old_tss_sel;
4512
4513 if (kvm_write_guest(vcpu->kvm,
4514 get_tss_base_addr(vcpu, nseg_desc),
4515 &tss_segment_16.prev_task_link,
4516 sizeof tss_segment_16.prev_task_link))
4517 goto out;
4518 }
4519
4520 if (load_state_from_tss16(vcpu, &tss_segment_16))
4521 goto out;
4522
4523 ret = 1;
4524 out:
4525 return ret;
4526 }
4527
4528 static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
4529 u16 old_tss_sel, u32 old_tss_base,
4530 struct desc_struct *nseg_desc)
4531 {
4532 struct tss_segment_32 tss_segment_32;
4533 int ret = 0;
4534
4535 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4536 sizeof tss_segment_32))
4537 goto out;
4538
4539 save_state_to_tss32(vcpu, &tss_segment_32);
4540
4541 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4542 sizeof tss_segment_32))
4543 goto out;
4544
4545 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4546 &tss_segment_32, sizeof tss_segment_32))
4547 goto out;
4548
4549 if (old_tss_sel != 0xffff) {
4550 tss_segment_32.prev_task_link = old_tss_sel;
4551
4552 if (kvm_write_guest(vcpu->kvm,
4553 get_tss_base_addr(vcpu, nseg_desc),
4554 &tss_segment_32.prev_task_link,
4555 sizeof tss_segment_32.prev_task_link))
4556 goto out;
4557 }
4558
4559 if (load_state_from_tss32(vcpu, &tss_segment_32))
4560 goto out;
4561
4562 ret = 1;
4563 out:
4564 return ret;
4565 }
4566
4567 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4568 {
4569 struct kvm_segment tr_seg;
4570 struct desc_struct cseg_desc;
4571 struct desc_struct nseg_desc;
4572 int ret = 0;
4573 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4574 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
4575
4576 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
4577
4578 /* FIXME: Handle errors. Failure to read either TSS or their
4579 * descriptors should generate a pagefault.
4580 */
4581 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4582 goto out;
4583
4584 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
4585 goto out;
4586
4587 if (reason != TASK_SWITCH_IRET) {
4588 int cpl;
4589
4590 cpl = kvm_x86_ops->get_cpl(vcpu);
4591 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4592 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4593 return 1;
4594 }
4595 }
4596
4597 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
4598 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4599 return 1;
4600 }
4601
4602 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
4603 cseg_desc.type &= ~(1 << 1); //clear the B flag
4604 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
4605 }
4606
4607 if (reason == TASK_SWITCH_IRET) {
4608 u32 eflags = kvm_get_rflags(vcpu);
4609 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4610 }
4611
4612 /* set back link to prev task only if NT bit is set in eflags
4613 note that old_tss_sel is not used afetr this point */
4614 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4615 old_tss_sel = 0xffff;
4616
4617 if (nseg_desc.type & 8)
4618 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4619 old_tss_base, &nseg_desc);
4620 else
4621 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4622 old_tss_base, &nseg_desc);
4623
4624 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4625 u32 eflags = kvm_get_rflags(vcpu);
4626 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4627 }
4628
4629 if (reason != TASK_SWITCH_IRET) {
4630 nseg_desc.type |= (1 << 1);
4631 save_guest_segment_descriptor(vcpu, tss_selector,
4632 &nseg_desc);
4633 }
4634
4635 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4636 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4637 tr_seg.type = 11;
4638 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
4639 out:
4640 return ret;
4641 }
4642 EXPORT_SYMBOL_GPL(kvm_task_switch);
4643
4644 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4645 struct kvm_sregs *sregs)
4646 {
4647 int mmu_reset_needed = 0;
4648 int pending_vec, max_bits;
4649 struct descriptor_table dt;
4650
4651 vcpu_load(vcpu);
4652
4653 dt.limit = sregs->idt.limit;
4654 dt.base = sregs->idt.base;
4655 kvm_x86_ops->set_idt(vcpu, &dt);
4656 dt.limit = sregs->gdt.limit;
4657 dt.base = sregs->gdt.base;
4658 kvm_x86_ops->set_gdt(vcpu, &dt);
4659
4660 vcpu->arch.cr2 = sregs->cr2;
4661 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
4662 vcpu->arch.cr3 = sregs->cr3;
4663
4664 kvm_set_cr8(vcpu, sregs->cr8);
4665
4666 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
4667 kvm_x86_ops->set_efer(vcpu, sregs->efer);
4668 kvm_set_apic_base(vcpu, sregs->apic_base);
4669
4670 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4671
4672 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
4673 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
4674 vcpu->arch.cr0 = sregs->cr0;
4675
4676 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
4677 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4678 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
4679 load_pdptrs(vcpu, vcpu->arch.cr3);
4680 mmu_reset_needed = 1;
4681 }
4682
4683 if (mmu_reset_needed)
4684 kvm_mmu_reset_context(vcpu);
4685
4686 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4687 pending_vec = find_first_bit(
4688 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4689 if (pending_vec < max_bits) {
4690 kvm_queue_interrupt(vcpu, pending_vec, false);
4691 pr_debug("Set back pending irq %d\n", pending_vec);
4692 if (irqchip_in_kernel(vcpu->kvm))
4693 kvm_pic_clear_isr_ack(vcpu->kvm);
4694 }
4695
4696 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4697 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4698 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4699 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4700 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4701 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
4702
4703 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4704 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
4705
4706 update_cr8_intercept(vcpu);
4707
4708 /* Older userspace won't unhalt the vcpu on reset. */
4709 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
4710 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4711 !(vcpu->arch.cr0 & X86_CR0_PE))
4712 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4713
4714 vcpu_put(vcpu);
4715
4716 return 0;
4717 }
4718
4719 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4720 struct kvm_guest_debug *dbg)
4721 {
4722 unsigned long rflags;
4723 int i, r;
4724
4725 vcpu_load(vcpu);
4726
4727 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4728 r = -EBUSY;
4729 if (vcpu->arch.exception.pending)
4730 goto unlock_out;
4731 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4732 kvm_queue_exception(vcpu, DB_VECTOR);
4733 else
4734 kvm_queue_exception(vcpu, BP_VECTOR);
4735 }
4736
4737 /*
4738 * Read rflags as long as potentially injected trace flags are still
4739 * filtered out.
4740 */
4741 rflags = kvm_get_rflags(vcpu);
4742
4743 vcpu->guest_debug = dbg->control;
4744 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4745 vcpu->guest_debug = 0;
4746
4747 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4748 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4749 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4750 vcpu->arch.switch_db_regs =
4751 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4752 } else {
4753 for (i = 0; i < KVM_NR_DB_REGS; i++)
4754 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4755 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4756 }
4757
4758 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
4759 vcpu->arch.singlestep_cs =
4760 get_segment_selector(vcpu, VCPU_SREG_CS);
4761 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
4762 }
4763
4764 /*
4765 * Trigger an rflags update that will inject or remove the trace
4766 * flags.
4767 */
4768 kvm_set_rflags(vcpu, rflags);
4769
4770 kvm_x86_ops->set_guest_debug(vcpu, dbg);
4771
4772 r = 0;
4773
4774 unlock_out:
4775 vcpu_put(vcpu);
4776
4777 return r;
4778 }
4779
4780 /*
4781 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4782 * we have asm/x86/processor.h
4783 */
4784 struct fxsave {
4785 u16 cwd;
4786 u16 swd;
4787 u16 twd;
4788 u16 fop;
4789 u64 rip;
4790 u64 rdp;
4791 u32 mxcsr;
4792 u32 mxcsr_mask;
4793 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4794 #ifdef CONFIG_X86_64
4795 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4796 #else
4797 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4798 #endif
4799 };
4800
4801 /*
4802 * Translate a guest virtual address to a guest physical address.
4803 */
4804 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4805 struct kvm_translation *tr)
4806 {
4807 unsigned long vaddr = tr->linear_address;
4808 gpa_t gpa;
4809
4810 vcpu_load(vcpu);
4811 down_read(&vcpu->kvm->slots_lock);
4812 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
4813 up_read(&vcpu->kvm->slots_lock);
4814 tr->physical_address = gpa;
4815 tr->valid = gpa != UNMAPPED_GVA;
4816 tr->writeable = 1;
4817 tr->usermode = 0;
4818 vcpu_put(vcpu);
4819
4820 return 0;
4821 }
4822
4823 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4824 {
4825 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4826
4827 vcpu_load(vcpu);
4828
4829 memcpy(fpu->fpr, fxsave->st_space, 128);
4830 fpu->fcw = fxsave->cwd;
4831 fpu->fsw = fxsave->swd;
4832 fpu->ftwx = fxsave->twd;
4833 fpu->last_opcode = fxsave->fop;
4834 fpu->last_ip = fxsave->rip;
4835 fpu->last_dp = fxsave->rdp;
4836 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4837
4838 vcpu_put(vcpu);
4839
4840 return 0;
4841 }
4842
4843 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4844 {
4845 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4846
4847 vcpu_load(vcpu);
4848
4849 memcpy(fxsave->st_space, fpu->fpr, 128);
4850 fxsave->cwd = fpu->fcw;
4851 fxsave->swd = fpu->fsw;
4852 fxsave->twd = fpu->ftwx;
4853 fxsave->fop = fpu->last_opcode;
4854 fxsave->rip = fpu->last_ip;
4855 fxsave->rdp = fpu->last_dp;
4856 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4857
4858 vcpu_put(vcpu);
4859
4860 return 0;
4861 }
4862
4863 void fx_init(struct kvm_vcpu *vcpu)
4864 {
4865 unsigned after_mxcsr_mask;
4866
4867 /*
4868 * Touch the fpu the first time in non atomic context as if
4869 * this is the first fpu instruction the exception handler
4870 * will fire before the instruction returns and it'll have to
4871 * allocate ram with GFP_KERNEL.
4872 */
4873 if (!used_math())
4874 kvm_fx_save(&vcpu->arch.host_fx_image);
4875
4876 /* Initialize guest FPU by resetting ours and saving into guest's */
4877 preempt_disable();
4878 kvm_fx_save(&vcpu->arch.host_fx_image);
4879 kvm_fx_finit();
4880 kvm_fx_save(&vcpu->arch.guest_fx_image);
4881 kvm_fx_restore(&vcpu->arch.host_fx_image);
4882 preempt_enable();
4883
4884 vcpu->arch.cr0 |= X86_CR0_ET;
4885 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
4886 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4887 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
4888 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4889 }
4890 EXPORT_SYMBOL_GPL(fx_init);
4891
4892 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4893 {
4894 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4895 return;
4896
4897 vcpu->guest_fpu_loaded = 1;
4898 kvm_fx_save(&vcpu->arch.host_fx_image);
4899 kvm_fx_restore(&vcpu->arch.guest_fx_image);
4900 }
4901 EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4902
4903 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4904 {
4905 if (!vcpu->guest_fpu_loaded)
4906 return;
4907
4908 vcpu->guest_fpu_loaded = 0;
4909 kvm_fx_save(&vcpu->arch.guest_fx_image);
4910 kvm_fx_restore(&vcpu->arch.host_fx_image);
4911 ++vcpu->stat.fpu_reload;
4912 }
4913 EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
4914
4915 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4916 {
4917 if (vcpu->arch.time_page) {
4918 kvm_release_page_dirty(vcpu->arch.time_page);
4919 vcpu->arch.time_page = NULL;
4920 }
4921
4922 kvm_x86_ops->vcpu_free(vcpu);
4923 }
4924
4925 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4926 unsigned int id)
4927 {
4928 return kvm_x86_ops->vcpu_create(kvm, id);
4929 }
4930
4931 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4932 {
4933 int r;
4934
4935 /* We do fxsave: this must be aligned. */
4936 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
4937
4938 vcpu->arch.mtrr_state.have_fixed = 1;
4939 vcpu_load(vcpu);
4940 r = kvm_arch_vcpu_reset(vcpu);
4941 if (r == 0)
4942 r = kvm_mmu_setup(vcpu);
4943 vcpu_put(vcpu);
4944 if (r < 0)
4945 goto free_vcpu;
4946
4947 return 0;
4948 free_vcpu:
4949 kvm_x86_ops->vcpu_free(vcpu);
4950 return r;
4951 }
4952
4953 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
4954 {
4955 vcpu_load(vcpu);
4956 kvm_mmu_unload(vcpu);
4957 vcpu_put(vcpu);
4958
4959 kvm_x86_ops->vcpu_free(vcpu);
4960 }
4961
4962 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4963 {
4964 vcpu->arch.nmi_pending = false;
4965 vcpu->arch.nmi_injected = false;
4966
4967 vcpu->arch.switch_db_regs = 0;
4968 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4969 vcpu->arch.dr6 = DR6_FIXED_1;
4970 vcpu->arch.dr7 = DR7_FIXED_1;
4971
4972 return kvm_x86_ops->vcpu_reset(vcpu);
4973 }
4974
4975 int kvm_arch_hardware_enable(void *garbage)
4976 {
4977 /*
4978 * Since this may be called from a hotplug notifcation,
4979 * we can't get the CPU frequency directly.
4980 */
4981 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4982 int cpu = raw_smp_processor_id();
4983 per_cpu(cpu_tsc_khz, cpu) = 0;
4984 }
4985
4986 kvm_shared_msr_cpu_online();
4987
4988 return kvm_x86_ops->hardware_enable(garbage);
4989 }
4990
4991 void kvm_arch_hardware_disable(void *garbage)
4992 {
4993 kvm_x86_ops->hardware_disable(garbage);
4994 drop_user_return_notifiers(garbage);
4995 }
4996
4997 int kvm_arch_hardware_setup(void)
4998 {
4999 return kvm_x86_ops->hardware_setup();
5000 }
5001
5002 void kvm_arch_hardware_unsetup(void)
5003 {
5004 kvm_x86_ops->hardware_unsetup();
5005 }
5006
5007 void kvm_arch_check_processor_compat(void *rtn)
5008 {
5009 kvm_x86_ops->check_processor_compatibility(rtn);
5010 }
5011
5012 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5013 {
5014 struct page *page;
5015 struct kvm *kvm;
5016 int r;
5017
5018 BUG_ON(vcpu->kvm == NULL);
5019 kvm = vcpu->kvm;
5020
5021 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
5022 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
5023 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5024 else
5025 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
5026
5027 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5028 if (!page) {
5029 r = -ENOMEM;
5030 goto fail;
5031 }
5032 vcpu->arch.pio_data = page_address(page);
5033
5034 r = kvm_mmu_create(vcpu);
5035 if (r < 0)
5036 goto fail_free_pio_data;
5037
5038 if (irqchip_in_kernel(kvm)) {
5039 r = kvm_create_lapic(vcpu);
5040 if (r < 0)
5041 goto fail_mmu_destroy;
5042 }
5043
5044 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5045 GFP_KERNEL);
5046 if (!vcpu->arch.mce_banks) {
5047 r = -ENOMEM;
5048 goto fail_free_lapic;
5049 }
5050 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5051
5052 return 0;
5053 fail_free_lapic:
5054 kvm_free_lapic(vcpu);
5055 fail_mmu_destroy:
5056 kvm_mmu_destroy(vcpu);
5057 fail_free_pio_data:
5058 free_page((unsigned long)vcpu->arch.pio_data);
5059 fail:
5060 return r;
5061 }
5062
5063 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5064 {
5065 kfree(vcpu->arch.mce_banks);
5066 kvm_free_lapic(vcpu);
5067 down_read(&vcpu->kvm->slots_lock);
5068 kvm_mmu_destroy(vcpu);
5069 up_read(&vcpu->kvm->slots_lock);
5070 free_page((unsigned long)vcpu->arch.pio_data);
5071 }
5072
5073 struct kvm *kvm_arch_create_vm(void)
5074 {
5075 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5076
5077 if (!kvm)
5078 return ERR_PTR(-ENOMEM);
5079
5080 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
5081 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
5082
5083 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5084 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5085
5086 rdtscll(kvm->arch.vm_init_tsc);
5087
5088 return kvm;
5089 }
5090
5091 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5092 {
5093 vcpu_load(vcpu);
5094 kvm_mmu_unload(vcpu);
5095 vcpu_put(vcpu);
5096 }
5097
5098 static void kvm_free_vcpus(struct kvm *kvm)
5099 {
5100 unsigned int i;
5101 struct kvm_vcpu *vcpu;
5102
5103 /*
5104 * Unpin any mmu pages first.
5105 */
5106 kvm_for_each_vcpu(i, vcpu, kvm)
5107 kvm_unload_vcpu_mmu(vcpu);
5108 kvm_for_each_vcpu(i, vcpu, kvm)
5109 kvm_arch_vcpu_free(vcpu);
5110
5111 mutex_lock(&kvm->lock);
5112 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5113 kvm->vcpus[i] = NULL;
5114
5115 atomic_set(&kvm->online_vcpus, 0);
5116 mutex_unlock(&kvm->lock);
5117 }
5118
5119 void kvm_arch_sync_events(struct kvm *kvm)
5120 {
5121 kvm_free_all_assigned_devices(kvm);
5122 }
5123
5124 void kvm_arch_destroy_vm(struct kvm *kvm)
5125 {
5126 kvm_iommu_unmap_guest(kvm);
5127 kvm_free_pit(kvm);
5128 kfree(kvm->arch.vpic);
5129 kfree(kvm->arch.vioapic);
5130 kvm_free_vcpus(kvm);
5131 kvm_free_physmem(kvm);
5132 if (kvm->arch.apic_access_page)
5133 put_page(kvm->arch.apic_access_page);
5134 if (kvm->arch.ept_identity_pagetable)
5135 put_page(kvm->arch.ept_identity_pagetable);
5136 kfree(kvm);
5137 }
5138
5139 int kvm_arch_set_memory_region(struct kvm *kvm,
5140 struct kvm_userspace_memory_region *mem,
5141 struct kvm_memory_slot old,
5142 int user_alloc)
5143 {
5144 int npages = mem->memory_size >> PAGE_SHIFT;
5145 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
5146
5147 /*To keep backward compatibility with older userspace,
5148 *x86 needs to hanlde !user_alloc case.
5149 */
5150 if (!user_alloc) {
5151 if (npages && !old.rmap) {
5152 unsigned long userspace_addr;
5153
5154 down_write(&current->mm->mmap_sem);
5155 userspace_addr = do_mmap(NULL, 0,
5156 npages * PAGE_SIZE,
5157 PROT_READ | PROT_WRITE,
5158 MAP_PRIVATE | MAP_ANONYMOUS,
5159 0);
5160 up_write(&current->mm->mmap_sem);
5161
5162 if (IS_ERR((void *)userspace_addr))
5163 return PTR_ERR((void *)userspace_addr);
5164
5165 /* set userspace_addr atomically for kvm_hva_to_rmapp */
5166 spin_lock(&kvm->mmu_lock);
5167 memslot->userspace_addr = userspace_addr;
5168 spin_unlock(&kvm->mmu_lock);
5169 } else {
5170 if (!old.user_alloc && old.rmap) {
5171 int ret;
5172
5173 down_write(&current->mm->mmap_sem);
5174 ret = do_munmap(current->mm, old.userspace_addr,
5175 old.npages * PAGE_SIZE);
5176 up_write(&current->mm->mmap_sem);
5177 if (ret < 0)
5178 printk(KERN_WARNING
5179 "kvm_vm_ioctl_set_memory_region: "
5180 "failed to munmap memory\n");
5181 }
5182 }
5183 }
5184
5185 spin_lock(&kvm->mmu_lock);
5186 if (!kvm->arch.n_requested_mmu_pages) {
5187 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5188 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5189 }
5190
5191 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
5192 spin_unlock(&kvm->mmu_lock);
5193
5194 return 0;
5195 }
5196
5197 void kvm_arch_flush_shadow(struct kvm *kvm)
5198 {
5199 kvm_mmu_zap_all(kvm);
5200 kvm_reload_remote_mmus(kvm);
5201 }
5202
5203 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5204 {
5205 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
5206 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5207 || vcpu->arch.nmi_pending ||
5208 (kvm_arch_interrupt_allowed(vcpu) &&
5209 kvm_cpu_has_interrupt(vcpu));
5210 }
5211
5212 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5213 {
5214 int me;
5215 int cpu = vcpu->cpu;
5216
5217 if (waitqueue_active(&vcpu->wq)) {
5218 wake_up_interruptible(&vcpu->wq);
5219 ++vcpu->stat.halt_wakeup;
5220 }
5221
5222 me = get_cpu();
5223 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5224 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5225 smp_send_reschedule(cpu);
5226 put_cpu();
5227 }
5228
5229 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5230 {
5231 return kvm_x86_ops->interrupt_allowed(vcpu);
5232 }
5233
5234 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5235 {
5236 unsigned long rflags;
5237
5238 rflags = kvm_x86_ops->get_rflags(vcpu);
5239 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5240 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5241 return rflags;
5242 }
5243 EXPORT_SYMBOL_GPL(kvm_get_rflags);
5244
5245 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5246 {
5247 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5248 vcpu->arch.singlestep_cs ==
5249 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5250 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5251 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5252 kvm_x86_ops->set_rflags(vcpu, rflags);
5253 }
5254 EXPORT_SYMBOL_GPL(kvm_set_rflags);
5255
5256 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5257 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5258 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5259 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5260 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
5261 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
5262 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
5263 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
5264 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
5265 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
5266 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree