arch/mips/mm/uasm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * A small micro-assembler. It is intentionally kept simple, does only
   7  * support a subset of instructions, and does not try to hide pipeline
   8  * effects like branch delay slots.
   9  *
  10  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  11  * Copyright (C) 2005, 2007  Maciej W. Rozycki
  12  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/inst.h>
  20 #include <asm/elf.h>
  21 #include <asm/bugs.h>
  22 #include <asm/uasm.h>
  23
  24 enum fields {
  25         RS = 0x001,
  26         RT = 0x002,
  27         RD = 0x004,
  28         RE = 0x008,
  29         SIMM = 0x010,
  30         UIMM = 0x020,
  31         BIMM = 0x040,
  32         JIMM = 0x080,
  33         FUNC = 0x100,
  34         SET = 0x200
  35 };
  36
  37 #define OP_MASK         0x3f
  38 #define OP_SH           26
  39 #define RS_MASK         0x1f
  40 #define RS_SH           21
  41 #define RT_MASK         0x1f
  42 #define RT_SH           16
  43 #define RD_MASK         0x1f
  44 #define RD_SH           11
  45 #define RE_MASK         0x1f
  46 #define RE_SH           6
  47 #define IMM_MASK        0xffff
  48 #define IMM_SH          0
  49 #define JIMM_MASK       0x3ffffff
  50 #define JIMM_SH         0
  51 #define FUNC_MASK       0x3f
  52 #define FUNC_SH         0
  53 #define SET_MASK        0x7
  54 #define SET_SH          0
  55
  56 enum opcode {
  57         insn_invalid,
  58         insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
  59         insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
  60         insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
  61         insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
  62         insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
  63         insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
  64         insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
  65         insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
  66         insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
  67 };
  68
  69 struct insn {
  70         enum opcode opcode;
  71         u32 match;
  72         enum fields fields;
  73 };
  74
  75 /* This macro sets the non-variable bits of an instruction. */
  76 #define M(a, b, c, d, e, f)                                     \
  77         ((a) << OP_SH                                           \
  78          | (b) << RS_SH                                         \
  79          | (c) << RT_SH                                         \
  80          | (d) << RD_SH                                         \
  81          | (e) << RE_SH                                         \
  82          | (f) << FUNC_SH)
  83
  84 static struct insn insn_table[] __cpuinitdata = {
  85         { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
  86         { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
  87         { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
  88         { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
  89         { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  90         { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  91         { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
  92         { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
  93         { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
  94         { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
  95         { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  96         { insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
  97         { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
  98         { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
  99         { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
 100         { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
 101         { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
 102         { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
 103         { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
 104         { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
 105         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
 106         { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
 107         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
 108         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
 109         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
 110         { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
 111         { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
 112         { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 113         { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 114         { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 115         { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
 116         { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 117         { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
 118         { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
 119         { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
 120         { insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 121         { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
 122         { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 123         { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 124         { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 125         { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
 126         { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
 127         { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
 128         { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
 129         { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 130         { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
 131         { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
 132         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
 133         { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
 134         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
 135         { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
 136         { insn_invalid, 0, 0 }
 137 };
 138
 139 #undef M
 140
 141 static inline __cpuinit u32 build_rs(u32 arg)
 142 {
 143         if (arg & ~RS_MASK)
 144                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 145
 146         return (arg & RS_MASK) << RS_SH;
 147 }
 148
 149 static inline __cpuinit u32 build_rt(u32 arg)
 150 {
 151         if (arg & ~RT_MASK)
 152                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 153
 154         return (arg & RT_MASK) << RT_SH;
 155 }
 156
 157 static inline __cpuinit u32 build_rd(u32 arg)
 158 {
 159         if (arg & ~RD_MASK)
 160                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 161
 162         return (arg & RD_MASK) << RD_SH;
 163 }
 164
 165 static inline __cpuinit u32 build_re(u32 arg)
 166 {
 167         if (arg & ~RE_MASK)
 168                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 169
 170         return (arg & RE_MASK) << RE_SH;
 171 }
 172
 173 static inline __cpuinit u32 build_simm(s32 arg)
 174 {
 175         if (arg > 0x7fff || arg < -0x8000)
 176                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 177
 178         return arg & 0xffff;
 179 }
 180
 181 static inline __cpuinit u32 build_uimm(u32 arg)
 182 {
 183         if (arg & ~IMM_MASK)
 184                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 185
 186         return arg & IMM_MASK;
 187 }
 188
 189 static inline __cpuinit u32 build_bimm(s32 arg)
 190 {
 191         if (arg > 0x1ffff || arg < -0x20000)
 192                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 193
 194         if (arg & 0x3)
 195                 printk(KERN_WARNING "Invalid micro-assembler branch target\n");
 196
 197         return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
 198 }
 199
 200 static inline __cpuinit u32 build_jimm(u32 arg)
 201 {
 202         if (arg & ~((JIMM_MASK) << 2))
 203                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 204
 205         return (arg >> 2) & JIMM_MASK;
 206 }
 207
 208 static inline __cpuinit u32 build_func(u32 arg)
 209 {
 210         if (arg & ~FUNC_MASK)
 211                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 212
 213         return arg & FUNC_MASK;
 214 }
 215
 216 static inline __cpuinit u32 build_set(u32 arg)
 217 {
 218         if (arg & ~SET_MASK)
 219                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 220
 221         return arg & SET_MASK;
 222 }
 223
 224 /*
 225  * The order of opcode arguments is implicitly left to right,
 226  * starting with RS and ending with FUNC or IMM.
 227  */
 228 static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
 229 {
 230         struct insn *ip = NULL;
 231         unsigned int i;
 232         va_list ap;
 233         u32 op;
 234
 235         for (i = 0; insn_table[i].opcode != insn_invalid; i++)
 236                 if (insn_table[i].opcode == opc) {
 237                         ip = &insn_table[i];
 238                         break;
 239                 }
 240
 241         if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
 242                 panic("Unsupported Micro-assembler instruction %d", opc);
 243
 244         op = ip->match;
 245         va_start(ap, opc);
 246         if (ip->fields & RS)
 247                 op |= build_rs(va_arg(ap, u32));
 248         if (ip->fields & RT)
 249                 op |= build_rt(va_arg(ap, u32));
 250         if (ip->fields & RD)
 251                 op |= build_rd(va_arg(ap, u32));
 252         if (ip->fields & RE)
 253                 op |= build_re(va_arg(ap, u32));
 254         if (ip->fields & SIMM)
 255                 op |= build_simm(va_arg(ap, s32));
 256         if (ip->fields & UIMM)
 257                 op |= build_uimm(va_arg(ap, u32));
 258         if (ip->fields & BIMM)
 259                 op |= build_bimm(va_arg(ap, s32));
 260         if (ip->fields & JIMM)
 261                 op |= build_jimm(va_arg(ap, u32));
 262         if (ip->fields & FUNC)
 263                 op |= build_func(va_arg(ap, u32));
 264         if (ip->fields & SET)
 265                 op |= build_set(va_arg(ap, u32));
 266         va_end(ap);
 267
 268         **buf = op;
 269         (*buf)++;
 270 }
 271
 272 #define I_u1u2u3(op)                                    \
 273 Ip_u1u2u3(op)                                           \
 274 {                                                       \
 275         build_insn(buf, insn##op, a, b, c);             \
 276 }
 277
 278 #define I_u2u1u3(op)                                    \
 279 Ip_u2u1u3(op)                                           \
 280 {                                                       \
 281         build_insn(buf, insn##op, b, a, c);             \
 282 }
 283
 284 #define I_u3u1u2(op)                                    \
 285 Ip_u3u1u2(op)                                           \
 286 {                                                       \
 287         build_insn(buf, insn##op, b, c, a);             \
 288 }
 289
 290 #define I_u1u2s3(op)                                    \
 291 Ip_u1u2s3(op)                                           \
 292 {                                                       \
 293         build_insn(buf, insn##op, a, b, c);             \
 294 }
 295
 296 #define I_u2s3u1(op)                                    \
 297 Ip_u2s3u1(op)                                           \
 298 {                                                       \
 299         build_insn(buf, insn##op, c, a, b);             \
 300 }
 301
 302 #define I_u2u1s3(op)                                    \
 303 Ip_u2u1s3(op)                                           \
 304 {                                                       \
 305         build_insn(buf, insn##op, b, a, c);             \
 306 }
 307
 308 #define I_u2u1msbu3(op)                                 \
 309 Ip_u2u1msbu3(op)                                        \
 310 {                                                       \
 311         build_insn(buf, insn##op, b, a, c+d-1, c);      \
 312 }
 313
 314 #define I_u1u2(op)                                      \
 315 Ip_u1u2(op)                                             \
 316 {                                                       \
 317         build_insn(buf, insn##op, a, b);                \
 318 }
 319
 320 #define I_u1s2(op)                                      \
 321 Ip_u1s2(op)                                             \
 322 {                                                       \
 323         build_insn(buf, insn##op, a, b);                \
 324 }
 325
 326 #define I_u1(op)                                        \
 327 Ip_u1(op)                                               \
 328 {                                                       \
 329         build_insn(buf, insn##op, a);                   \
 330 }
 331
 332 #define I_0(op)                                         \
 333 Ip_0(op)                                                \
 334 {                                                       \
 335         build_insn(buf, insn##op);                      \
 336 }
 337
 338 I_u2u1s3(_addiu)
 339 I_u3u1u2(_addu)
 340 I_u2u1u3(_andi)
 341 I_u3u1u2(_and)
 342 I_u1u2s3(_beq)
 343 I_u1u2s3(_beql)
 344 I_u1s2(_bgez)
 345 I_u1s2(_bgezl)
 346 I_u1s2(_bltz)
 347 I_u1s2(_bltzl)
 348 I_u1u2s3(_bne)
 349 I_u2s3u1(_cache)
 350 I_u1u2u3(_dmfc0)
 351 I_u1u2u3(_dmtc0)
 352 I_u2u1s3(_daddiu)
 353 I_u3u1u2(_daddu)
 354 I_u2u1u3(_dsll)
 355 I_u2u1u3(_dsll32)
 356 I_u2u1u3(_dsra)
 357 I_u2u1u3(_dsrl)
 358 I_u2u1u3(_dsrl32)
 359 I_u2u1u3(_drotr)
 360 I_u3u1u2(_dsubu)
 361 I_0(_eret)
 362 I_u1(_j)
 363 I_u1(_jal)
 364 I_u1(_jr)
 365 I_u2s3u1(_ld)
 366 I_u2s3u1(_ll)
 367 I_u2s3u1(_lld)
 368 I_u1s2(_lui)
 369 I_u2s3u1(_lw)
 370 I_u1u2u3(_mfc0)
 371 I_u1u2u3(_mtc0)
 372 I_u2u1u3(_ori)
 373 I_u2s3u1(_pref)
 374 I_0(_rfe)
 375 I_u2s3u1(_sc)
 376 I_u2s3u1(_scd)
 377 I_u2s3u1(_sd)
 378 I_u2u1u3(_sll)
 379 I_u2u1u3(_sra)
 380 I_u2u1u3(_srl)
 381 I_u3u1u2(_subu)
 382 I_u2s3u1(_sw)
 383 I_0(_tlbp)
 384 I_0(_tlbwi)
 385 I_0(_tlbwr)
 386 I_u3u1u2(_xor)
 387 I_u2u1u3(_xori)
 388 I_u2u1msbu3(_dins);
 389
 390 /* Handle labels. */
 391 void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
 392 {
 393         (*lab)->addr = addr;
 394         (*lab)->lab = lid;
 395         (*lab)++;
 396 }
 397
 398 int __cpuinit uasm_in_compat_space_p(long addr)
 399 {
 400         /* Is this address in 32bit compat space? */
 401 #ifdef CONFIG_64BIT
 402         return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
 403 #else
 404         return 1;
 405 #endif
 406 }
 407
 408 static int __cpuinit uasm_rel_highest(long val)
 409 {
 410 #ifdef CONFIG_64BIT
 411         return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
 412 #else
 413         return 0;
 414 #endif
 415 }
 416
 417 static int __cpuinit uasm_rel_higher(long val)
 418 {
 419 #ifdef CONFIG_64BIT
 420         return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
 421 #else
 422         return 0;
 423 #endif
 424 }
 425
 426 int __cpuinit uasm_rel_hi(long val)
 427 {
 428         return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
 429 }
 430
 431 int __cpuinit uasm_rel_lo(long val)
 432 {
 433         return ((val & 0xffff) ^ 0x8000) - 0x8000;
 434 }
 435
 436 void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
 437 {
 438         if (!uasm_in_compat_space_p(addr)) {
 439                 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
 440                 if (uasm_rel_higher(addr))
 441                         uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
 442                 if (uasm_rel_hi(addr)) {
 443                         uasm_i_dsll(buf, rs, rs, 16);
 444                         uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
 445                         uasm_i_dsll(buf, rs, rs, 16);
 446                 } else
 447                         uasm_i_dsll32(buf, rs, rs, 0);
 448         } else
 449                 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
 450 }
 451
 452 void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
 453 {
 454         UASM_i_LA_mostly(buf, rs, addr);
 455         if (uasm_rel_lo(addr)) {
 456                 if (!uasm_in_compat_space_p(addr))
 457                         uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
 458                 else
 459                         uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
 460         }
 461 }
 462
 463 /* Handle relocations. */
 464 void __cpuinit
 465 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
 466 {
 467         (*rel)->addr = addr;
 468         (*rel)->type = R_MIPS_PC16;
 469         (*rel)->lab = lid;
 470         (*rel)++;
 471 }
 472
 473 static inline void __cpuinit
 474 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 475 {
 476         long laddr = (long)lab->addr;
 477         long raddr = (long)rel->addr;
 478
 479         switch (rel->type) {
 480         case R_MIPS_PC16:
 481                 *rel->addr |= build_bimm(laddr - (raddr + 4));
 482                 break;
 483
 484         default:
 485                 panic("Unsupported Micro-assembler relocation %d",
 486                       rel->type);
 487         }
 488 }
 489
 490 void __cpuinit
 491 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 492 {
 493         struct uasm_label *l;
 494
 495         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 496                 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
 497                         if (rel->lab == l->lab)
 498                                 __resolve_relocs(rel, l);
 499 }
 500
 501 void __cpuinit
 502 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
 503 {
 504         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 505                 if (rel->addr >= first && rel->addr < end)
 506                         rel->addr += off;
 507 }
 508
 509 void __cpuinit
 510 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
 511 {
 512         for (; lab->lab != UASM_LABEL_INVALID; lab++)
 513                 if (lab->addr >= first && lab->addr < end)
 514                         lab->addr += off;
 515 }
 516
 517 void __cpuinit
 518 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
 519                   u32 *end, u32 *target)
 520 {
 521         long off = (long)(target - first);
 522
 523         memcpy(target, first, (end - first) * sizeof(u32));
 524
 525         uasm_move_relocs(rel, first, end, off);
 526         uasm_move_labels(lab, first, end, off);
 527 }
 528
 529 int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
 530 {
 531         for (; rel->lab != UASM_LABEL_INVALID; rel++) {
 532                 if (rel->addr == addr
 533                     && (rel->type == R_MIPS_PC16
 534                         || rel->type == R_MIPS_26))
 535                         return 1;
 536         }
 537
 538         return 0;
 539 }
 540
 541 /* Convenience functions for labeled branches. */
 542 void __cpuinit
 543 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 544 {
 545         uasm_r_mips_pc16(r, *p, lid);
 546         uasm_i_bltz(p, reg, 0);
 547 }
 548
 549 void __cpuinit
 550 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
 551 {
 552         uasm_r_mips_pc16(r, *p, lid);
 553         uasm_i_b(p, 0);
 554 }
 555
 556 void __cpuinit
 557 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 558 {
 559         uasm_r_mips_pc16(r, *p, lid);
 560         uasm_i_beqz(p, reg, 0);
 561 }
 562
 563 void __cpuinit
 564 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 565 {
 566         uasm_r_mips_pc16(r, *p, lid);
 567         uasm_i_beqzl(p, reg, 0);
 568 }
 569
 570 void __cpuinit
 571 uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
 572         unsigned int reg2, int lid)
 573 {
 574         uasm_r_mips_pc16(r, *p, lid);
 575         uasm_i_bne(p, reg1, reg2, 0);
 576 }
 577
 578 void __cpuinit
 579 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 580 {
 581         uasm_r_mips_pc16(r, *p, lid);
 582         uasm_i_bnez(p, reg, 0);
 583 }
 584
 585 void __cpuinit
 586 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 587 {
 588         uasm_r_mips_pc16(r, *p, lid);
 589         uasm_i_bgezl(p, reg, 0);
 590 }
 591
 592 void __cpuinit
 593 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 594 {
 595         uasm_r_mips_pc16(r, *p, lid);
 596         uasm_i_bgez(p, reg, 0);
 597 }