2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
33 /* This files gather functions specifics to : rs400,rs480 */
34 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
);
36 void rs400_gart_adjust_size(struct radeon_device
*rdev
)
39 switch (rdev
->mc
.gtt_size
/(1024*1024)) {
49 DRM_ERROR("Unable to use IGP GART size %uM\n",
50 (unsigned)(rdev
->mc
.gtt_size
>> 20));
51 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
52 DRM_ERROR("Forcing to 32M GART size\n");
53 rdev
->mc
.gtt_size
= 32 * 1024 * 1024;
56 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
57 /* FIXME: RS400 & RS480 seems to have issue with GART size
58 * if 4G of system memory (needs more testing) */
59 rdev
->mc
.gtt_size
= 32 * 1024 * 1024;
60 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
64 void rs400_gart_tlb_flush(struct radeon_device
*rdev
)
67 unsigned int timeout
= rdev
->usec_timeout
;
69 WREG32_MC(RS480_GART_CACHE_CNTRL
, RS480_GART_CACHE_INVALIDATE
);
71 tmp
= RREG32_MC(RS480_GART_CACHE_CNTRL
);
72 if ((tmp
& RS480_GART_CACHE_INVALIDATE
) == 0)
76 } while (timeout
> 0);
77 WREG32_MC(RS480_GART_CACHE_CNTRL
, 0);
80 int rs400_gart_init(struct radeon_device
*rdev
)
84 if (rdev
->gart
.table
.ram
.ptr
) {
85 WARN(1, "RS400 GART already initialized.\n");
89 switch(rdev
->mc
.gtt_size
/ (1024 * 1024)) {
101 /* Initialize common gart structure */
102 r
= radeon_gart_init(rdev
);
105 if (rs400_debugfs_pcie_gart_info_init(rdev
))
106 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
107 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 4;
108 return radeon_gart_table_ram_alloc(rdev
);
111 int rs400_gart_enable(struct radeon_device
*rdev
)
116 radeon_gart_restore(rdev
);
117 tmp
= RREG32_MC(RS690_AIC_CTRL_SCRATCH
);
118 tmp
|= RS690_DIS_OUT_OF_PCI_GART_ACCESS
;
119 WREG32_MC(RS690_AIC_CTRL_SCRATCH
, tmp
);
120 /* Check gart size */
121 switch(rdev
->mc
.gtt_size
/ (1024 * 1024)) {
123 size_reg
= RS480_VA_SIZE_32MB
;
126 size_reg
= RS480_VA_SIZE_64MB
;
129 size_reg
= RS480_VA_SIZE_128MB
;
132 size_reg
= RS480_VA_SIZE_256MB
;
135 size_reg
= RS480_VA_SIZE_512MB
;
138 size_reg
= RS480_VA_SIZE_1GB
;
141 size_reg
= RS480_VA_SIZE_2GB
;
146 /* It should be fine to program it to max value */
147 if (rdev
->family
== CHIP_RS690
|| (rdev
->family
== CHIP_RS740
)) {
148 WREG32_MC(RS690_MCCFG_AGP_BASE
, 0xFFFFFFFF);
149 WREG32_MC(RS690_MCCFG_AGP_BASE_2
, 0);
151 WREG32(RADEON_AGP_BASE
, 0xFFFFFFFF);
152 WREG32(RS480_AGP_BASE_2
, 0);
154 tmp
= REG_SET(RS690_MC_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
155 tmp
|= REG_SET(RS690_MC_AGP_START
, rdev
->mc
.gtt_start
>> 16);
156 if ((rdev
->family
== CHIP_RS690
) || (rdev
->family
== CHIP_RS740
)) {
157 WREG32_MC(RS690_MCCFG_AGP_LOCATION
, tmp
);
158 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RS600_BUS_MASTER_DIS
;
159 WREG32(RADEON_BUS_CNTL
, tmp
);
161 WREG32(RADEON_MC_AGP_LOCATION
, tmp
);
162 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RADEON_BUS_MASTER_DIS
;
163 WREG32(RADEON_BUS_CNTL
, tmp
);
165 /* Table should be in 32bits address space so ignore bits above. */
166 tmp
= (u32
)rdev
->gart
.table_addr
& 0xfffff000;
167 tmp
|= (upper_32_bits(rdev
->gart
.table_addr
) & 0xff) << 4;
169 WREG32_MC(RS480_GART_BASE
, tmp
);
170 /* TODO: more tweaking here */
171 WREG32_MC(RS480_GART_FEATURE_ID
,
173 RS480_GTW_LAC_EN
| RS480_1LEVEL_GART
));
174 /* Disable snooping */
175 WREG32_MC(RS480_AGP_MODE_CNTL
,
176 (1 << RS480_REQ_TYPE_SNOOP_SHIFT
) | RS480_REQ_TYPE_SNOOP_DIS
);
177 /* Disable AGP mode */
178 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
179 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
180 if ((rdev
->family
== CHIP_RS690
) || (rdev
->family
== CHIP_RS740
)) {
181 WREG32_MC(RS480_MC_MISC_CNTL
,
182 (RS480_GART_INDEX_REG_EN
| RS690_BLOCK_GFX_D3_EN
));
184 WREG32_MC(RS480_MC_MISC_CNTL
, RS480_GART_INDEX_REG_EN
);
187 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE
, (RS480_GART_EN
| size_reg
));
188 rs400_gart_tlb_flush(rdev
);
189 rdev
->gart
.ready
= true;
193 void rs400_gart_disable(struct radeon_device
*rdev
)
197 tmp
= RREG32_MC(RS690_AIC_CTRL_SCRATCH
);
198 tmp
|= RS690_DIS_OUT_OF_PCI_GART_ACCESS
;
199 WREG32_MC(RS690_AIC_CTRL_SCRATCH
, tmp
);
200 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE
, 0);
203 void rs400_gart_fini(struct radeon_device
*rdev
)
205 rs400_gart_disable(rdev
);
206 radeon_gart_table_ram_free(rdev
);
207 radeon_gart_fini(rdev
);
210 int rs400_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
214 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
218 entry
= (lower_32_bits(addr
) & PAGE_MASK
) |
219 ((upper_32_bits(addr
) & 0xff) << 4) |
221 entry
= cpu_to_le32(entry
);
222 rdev
->gart
.table
.ram
.ptr
[i
] = entry
;
226 int rs400_mc_wait_for_idle(struct radeon_device
*rdev
)
231 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
233 tmp
= RREG32(0x0150);
234 if (tmp
& (1 << 2)) {
242 void rs400_gpu_init(struct radeon_device
*rdev
)
244 /* FIXME: HDP same place on rs400 ? */
245 r100_hdp_reset(rdev
);
246 /* FIXME: is this correct ? */
247 r420_pipes_init(rdev
);
248 if (rs400_mc_wait_for_idle(rdev
)) {
249 printk(KERN_WARNING
"rs400: Failed to wait MC idle while "
250 "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
254 void rs400_mc_init(struct radeon_device
*rdev
)
258 rs400_gart_adjust_size(rdev
);
259 rdev
->mc
.igp_sideport_enabled
= radeon_combios_sideport_present(rdev
);
260 /* DDR for all card after R300 & IGP */
261 rdev
->mc
.vram_is_ddr
= true;
262 rdev
->mc
.vram_width
= 128;
263 r100_vram_init_sizes(rdev
);
264 base
= (RREG32(RADEON_NB_TOM
) & 0xffff) << 16;
265 radeon_vram_location(rdev
, &rdev
->mc
, base
);
266 radeon_gtt_location(rdev
, &rdev
->mc
);
269 uint32_t rs400_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
)
273 WREG32(RS480_NB_MC_INDEX
, reg
& 0xff);
274 r
= RREG32(RS480_NB_MC_DATA
);
275 WREG32(RS480_NB_MC_INDEX
, 0xff);
279 void rs400_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
281 WREG32(RS480_NB_MC_INDEX
, ((reg
) & 0xff) | RS480_NB_MC_IND_WR_EN
);
282 WREG32(RS480_NB_MC_DATA
, (v
));
283 WREG32(RS480_NB_MC_INDEX
, 0xff);
286 #if defined(CONFIG_DEBUG_FS)
287 static int rs400_debugfs_gart_info(struct seq_file
*m
, void *data
)
289 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
290 struct drm_device
*dev
= node
->minor
->dev
;
291 struct radeon_device
*rdev
= dev
->dev_private
;
294 tmp
= RREG32(RADEON_HOST_PATH_CNTL
);
295 seq_printf(m
, "HOST_PATH_CNTL 0x%08x\n", tmp
);
296 tmp
= RREG32(RADEON_BUS_CNTL
);
297 seq_printf(m
, "BUS_CNTL 0x%08x\n", tmp
);
298 tmp
= RREG32_MC(RS690_AIC_CTRL_SCRATCH
);
299 seq_printf(m
, "AIC_CTRL_SCRATCH 0x%08x\n", tmp
);
300 if (rdev
->family
== CHIP_RS690
|| (rdev
->family
== CHIP_RS740
)) {
301 tmp
= RREG32_MC(RS690_MCCFG_AGP_BASE
);
302 seq_printf(m
, "MCCFG_AGP_BASE 0x%08x\n", tmp
);
303 tmp
= RREG32_MC(RS690_MCCFG_AGP_BASE_2
);
304 seq_printf(m
, "MCCFG_AGP_BASE_2 0x%08x\n", tmp
);
305 tmp
= RREG32_MC(RS690_MCCFG_AGP_LOCATION
);
306 seq_printf(m
, "MCCFG_AGP_LOCATION 0x%08x\n", tmp
);
307 tmp
= RREG32_MC(0x100);
308 seq_printf(m
, "MCCFG_FB_LOCATION 0x%08x\n", tmp
);
310 seq_printf(m
, "HDP_FB_LOCATION 0x%08x\n", tmp
);
312 tmp
= RREG32(RADEON_AGP_BASE
);
313 seq_printf(m
, "AGP_BASE 0x%08x\n", tmp
);
314 tmp
= RREG32(RS480_AGP_BASE_2
);
315 seq_printf(m
, "AGP_BASE_2 0x%08x\n", tmp
);
316 tmp
= RREG32(RADEON_MC_AGP_LOCATION
);
317 seq_printf(m
, "MC_AGP_LOCATION 0x%08x\n", tmp
);
319 tmp
= RREG32_MC(RS480_GART_BASE
);
320 seq_printf(m
, "GART_BASE 0x%08x\n", tmp
);
321 tmp
= RREG32_MC(RS480_GART_FEATURE_ID
);
322 seq_printf(m
, "GART_FEATURE_ID 0x%08x\n", tmp
);
323 tmp
= RREG32_MC(RS480_AGP_MODE_CNTL
);
324 seq_printf(m
, "AGP_MODE_CONTROL 0x%08x\n", tmp
);
325 tmp
= RREG32_MC(RS480_MC_MISC_CNTL
);
326 seq_printf(m
, "MC_MISC_CNTL 0x%08x\n", tmp
);
327 tmp
= RREG32_MC(0x5F);
328 seq_printf(m
, "MC_MISC_UMA_CNTL 0x%08x\n", tmp
);
329 tmp
= RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE
);
330 seq_printf(m
, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp
);
331 tmp
= RREG32_MC(RS480_GART_CACHE_CNTRL
);
332 seq_printf(m
, "GART_CACHE_CNTRL 0x%08x\n", tmp
);
333 tmp
= RREG32_MC(0x3B);
334 seq_printf(m
, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp
);
335 tmp
= RREG32_MC(0x3C);
336 seq_printf(m
, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp
);
337 tmp
= RREG32_MC(0x30);
338 seq_printf(m
, "GART_ERROR_0 0x%08x\n", tmp
);
339 tmp
= RREG32_MC(0x31);
340 seq_printf(m
, "GART_ERROR_1 0x%08x\n", tmp
);
341 tmp
= RREG32_MC(0x32);
342 seq_printf(m
, "GART_ERROR_2 0x%08x\n", tmp
);
343 tmp
= RREG32_MC(0x33);
344 seq_printf(m
, "GART_ERROR_3 0x%08x\n", tmp
);
345 tmp
= RREG32_MC(0x34);
346 seq_printf(m
, "GART_ERROR_4 0x%08x\n", tmp
);
347 tmp
= RREG32_MC(0x35);
348 seq_printf(m
, "GART_ERROR_5 0x%08x\n", tmp
);
349 tmp
= RREG32_MC(0x36);
350 seq_printf(m
, "GART_ERROR_6 0x%08x\n", tmp
);
351 tmp
= RREG32_MC(0x37);
352 seq_printf(m
, "GART_ERROR_7 0x%08x\n", tmp
);
356 static struct drm_info_list rs400_gart_info_list
[] = {
357 {"rs400_gart_info", rs400_debugfs_gart_info
, 0, NULL
},
361 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
)
363 #if defined(CONFIG_DEBUG_FS)
364 return radeon_debugfs_add_files(rdev
, rs400_gart_info_list
, 1);
370 void rs400_mc_program(struct radeon_device
*rdev
)
372 struct r100_mc_save save
;
374 /* Stops all mc clients */
375 r100_mc_stop(rdev
, &save
);
377 /* Wait for mc idle */
378 if (rs400_mc_wait_for_idle(rdev
))
379 dev_warn(rdev
->dev
, "rs400: Wait MC idle timeout before updating MC.\n");
380 WREG32(R_000148_MC_FB_LOCATION
,
381 S_000148_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
382 S_000148_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
384 r100_mc_resume(rdev
, &save
);
387 static int rs400_startup(struct radeon_device
*rdev
)
391 rs400_mc_program(rdev
);
393 r300_clock_startup(rdev
);
394 /* Initialize GPU configuration (# pipes, ...) */
395 rs400_gpu_init(rdev
);
396 r100_enable_bm(rdev
);
397 /* Initialize GART (initialize after TTM so we can allocate
398 * memory through TTM but finalize after TTM) */
399 r
= rs400_gart_enable(rdev
);
404 rdev
->config
.r300
.hdp_cntl
= RREG32(RADEON_HOST_PATH_CNTL
);
406 r
= r100_cp_init(rdev
, 1024 * 1024);
408 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
411 r
= r100_wb_init(rdev
);
413 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
414 r
= r100_ib_init(rdev
);
416 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
422 int rs400_resume(struct radeon_device
*rdev
)
424 /* Make sur GART are not working */
425 rs400_gart_disable(rdev
);
426 /* Resume clock before doing reset */
427 r300_clock_startup(rdev
);
428 /* setup MC before calling post tables */
429 rs400_mc_program(rdev
);
430 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
431 if (radeon_gpu_reset(rdev
)) {
432 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
433 RREG32(R_000E40_RBBM_STATUS
),
434 RREG32(R_0007C0_CP_STAT
));
437 radeon_combios_asic_init(rdev
->ddev
);
438 /* Resume clock after posting */
439 r300_clock_startup(rdev
);
440 /* Initialize surface registers */
441 radeon_surface_init(rdev
);
442 return rs400_startup(rdev
);
445 int rs400_suspend(struct radeon_device
*rdev
)
447 r100_cp_disable(rdev
);
448 r100_wb_disable(rdev
);
449 r100_irq_disable(rdev
);
450 rs400_gart_disable(rdev
);
454 void rs400_fini(struct radeon_device
*rdev
)
459 radeon_gem_fini(rdev
);
460 rs400_gart_fini(rdev
);
461 radeon_irq_kms_fini(rdev
);
462 radeon_fence_driver_fini(rdev
);
463 radeon_bo_fini(rdev
);
464 radeon_atombios_fini(rdev
);
469 int rs400_init(struct radeon_device
*rdev
)
474 r100_vga_render_disable(rdev
);
475 /* Initialize scratch registers */
476 radeon_scratch_init(rdev
);
477 /* Initialize surface registers */
478 radeon_surface_init(rdev
);
479 /* TODO: disable VGA need to use VGA request */
481 if (!radeon_get_bios(rdev
)) {
482 if (ASIC_IS_AVIVO(rdev
))
485 if (rdev
->is_atom_bios
) {
486 dev_err(rdev
->dev
, "Expecting combios for RS400/RS480 GPU\n");
489 r
= radeon_combios_init(rdev
);
493 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
494 if (radeon_gpu_reset(rdev
)) {
496 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
497 RREG32(R_000E40_RBBM_STATUS
),
498 RREG32(R_0007C0_CP_STAT
));
500 /* check if cards are posted or not */
501 if (radeon_boot_test_post_card(rdev
) == false)
504 /* Initialize clocks */
505 radeon_get_clock_info(rdev
->ddev
);
506 /* Initialize power management */
507 radeon_pm_init(rdev
);
508 /* initialize memory controller */
511 r
= radeon_fence_driver_init(rdev
);
514 r
= radeon_irq_kms_init(rdev
);
518 r
= radeon_bo_init(rdev
);
521 r
= rs400_gart_init(rdev
);
524 r300_set_reg_safe(rdev
);
525 rdev
->accel_working
= true;
526 r
= rs400_startup(rdev
);
528 /* Somethings want wront with the accel init stop accel */
529 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
533 rs400_gart_fini(rdev
);
534 radeon_irq_kms_fini(rdev
);
535 rdev
->accel_working
= false;