drivers/staging/gma500/psb_irq.c

   1 /**************************************************************************
   2  * Copyright (c) 2007, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
  19  * develop this driver.
  20  *
  21  **************************************************************************/
  22 /*
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include "psb_drv.h"
  27 #include "psb_reg.h"
  28 #include "psb_intel_reg.h"
  29 #include "psb_powermgmt.h"
  30
  31
  32 /*
  33  * inline functions
  34  */
  35
  36 static inline u32
  37 psb_pipestat(int pipe)
  38 {
  39         if (pipe == 0)
  40                 return PIPEASTAT;
  41         if (pipe == 1)
  42                 return PIPEBSTAT;
  43         if (pipe == 2)
  44                 return PIPECSTAT;
  45         BUG();
  46 }
  47
  48 static inline u32
  49 mid_pipe_event(int pipe)
  50 {
  51         if (pipe == 0)
  52                 return _PSB_PIPEA_EVENT_FLAG;
  53         if (pipe == 1)
  54                 return _MDFLD_PIPEB_EVENT_FLAG;
  55         if (pipe == 2)
  56                 return _MDFLD_PIPEC_EVENT_FLAG;
  57         BUG();
  58 }
  59
  60 static inline u32
  61 mid_pipe_vsync(int pipe)
  62 {
  63         if (pipe == 0)
  64                 return _PSB_VSYNC_PIPEA_FLAG;
  65         if (pipe == 1)
  66                 return _PSB_VSYNC_PIPEB_FLAG;
  67         if (pipe == 2)
  68                 return _MDFLD_PIPEC_VBLANK_FLAG;
  69         BUG();
  70 }
  71
  72 static inline u32
  73 mid_pipeconf(int pipe)
  74 {
  75         if (pipe == 0)
  76                 return PIPEACONF;
  77         if (pipe == 1)
  78                 return PIPEBCONF;
  79         if (pipe == 2)
  80                 return PIPECCONF;
  81         BUG();
  82 }
  83
  84 void
  85 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  86 {
  87         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  88                 u32 reg = psb_pipestat(pipe);
  89                 dev_priv->pipestat[pipe] |= mask;
  90                 /* Enable the interrupt, clear any pending status */
  91                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
  92                                                         OSPM_UHB_ONLY_IF_ON)) {
  93                         u32 writeVal = PSB_RVDC32(reg);
  94                         writeVal |= (mask | (mask >> 16));
  95                         PSB_WVDC32(writeVal, reg);
  96                         (void) PSB_RVDC32(reg);
  97                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
  98                 }
  99         }
 100 }
 101
 102 void
 103 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
 104 {
 105         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 106                 u32 reg = psb_pipestat(pipe);
 107                 dev_priv->pipestat[pipe] &= ~mask;
 108                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
 109                                                         OSPM_UHB_ONLY_IF_ON)) {
 110                         u32 writeVal = PSB_RVDC32(reg);
 111                         writeVal &= ~mask;
 112                         PSB_WVDC32(writeVal, reg);
 113                         (void) PSB_RVDC32(reg);
 114                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 115                 }
 116         }
 117 }
 118
 119 void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 120 {
 121         if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
 122                                                         OSPM_UHB_ONLY_IF_ON)) {
 123                 u32 pipe_event = mid_pipe_event(pipe);
 124                 dev_priv->vdc_irq_mask |= pipe_event;
 125                 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 126                 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 127                 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 128         }
 129 }
 130
 131 void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 132 {
 133         if (dev_priv->pipestat[pipe] == 0) {
 134                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
 135                                                         OSPM_UHB_ONLY_IF_ON)) {
 136                         u32 pipe_event = mid_pipe_event(pipe);
 137                         dev_priv->vdc_irq_mask &= ~pipe_event;
 138                         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 139                         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 140                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 141                 }
 142         }
 143 }
 144
 145 /**
 146  * Display controller interrupt handler for vsync/vblank.
 147  *
 148  */
 149 static void mid_vblank_handler(struct drm_device *dev, uint32_t pipe)
 150 {
 151         drm_handle_vblank(dev, pipe);
 152 }
 153
 154
 155 /**
 156  * Display controller interrupt handler for pipe event.
 157  *
 158  */
 159 #define WAIT_STATUS_CLEAR_LOOP_COUNT 0xffff
 160 static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe)
 161 {
 162         struct drm_psb_private *dev_priv =
 163             (struct drm_psb_private *) dev->dev_private;
 164
 165         uint32_t pipe_stat_val = 0;
 166         uint32_t pipe_stat_reg = psb_pipestat(pipe);
 167         uint32_t pipe_enable = dev_priv->pipestat[pipe];
 168         uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
 169         uint32_t i = 0;
 170
 171         spin_lock(&dev_priv->irqmask_lock);
 172
 173         pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
 174         pipe_stat_val &= pipe_enable | pipe_status;
 175         pipe_stat_val &= pipe_stat_val >> 16;
 176
 177         spin_unlock(&dev_priv->irqmask_lock);
 178
 179         /* clear the 2nd level interrupt status bits */
 180         /**
 181         * FIXME: shouldn't use while loop here. However, the interrupt
 182         * status 'sticky' bits cannot be cleared by setting '1' to that
 183         * bit once...
 184         */
 185         for (i = 0; i < WAIT_STATUS_CLEAR_LOOP_COUNT; i++) {
 186                 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
 187                 (void) PSB_RVDC32(pipe_stat_reg);
 188
 189                 if ((PSB_RVDC32(pipe_stat_reg) & pipe_status) == 0)
 190                         break;
 191         }
 192
 193         if (i == WAIT_STATUS_CLEAR_LOOP_COUNT)
 194                 DRM_ERROR("%s, can't clear the status bits in pipe_stat_reg, its value = 0x%x.\n",
 195                         __func__, PSB_RVDC32(pipe_stat_reg));
 196
 197         if (pipe_stat_val & PIPE_VBLANK_STATUS)
 198                 mid_vblank_handler(dev, pipe);
 199
 200         if (pipe_stat_val & PIPE_TE_STATUS)
 201                 drm_handle_vblank(dev, pipe);
 202 }
 203
 204 /*
 205  * Display controller interrupt handler.
 206  */
 207 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
 208 {
 209         if (vdc_stat & _PSB_PIPEA_EVENT_FLAG)
 210                 mid_pipe_event_handler(dev, 0);
 211 }
 212
 213 irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
 214 {
 215         struct drm_device *dev = (struct drm_device *) arg;
 216         struct drm_psb_private *dev_priv =
 217             (struct drm_psb_private *) dev->dev_private;
 218
 219         uint32_t vdc_stat, dsp_int = 0, sgx_int = 0;
 220         int handled = 0;
 221
 222         spin_lock(&dev_priv->irqmask_lock);
 223
 224         vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
 225
 226         if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG) {
 227                 PSB_DEBUG_IRQ("Got DISP interrupt\n");
 228                 dsp_int = 1;
 229         }
 230
 231         if (vdc_stat & _PSB_IRQ_SGX_FLAG) {
 232                 PSB_DEBUG_IRQ("Got SGX interrupt\n");
 233                 sgx_int = 1;
 234         }
 235         if (vdc_stat & _PSB_IRQ_MSVDX_FLAG)
 236                 PSB_DEBUG_IRQ("Got MSVDX interrupt\n");
 237
 238         if (vdc_stat & _LNC_IRQ_TOPAZ_FLAG)
 239                 PSB_DEBUG_IRQ("Got TOPAZ interrupt\n");
 240
 241
 242         vdc_stat &= dev_priv->vdc_irq_mask;
 243         spin_unlock(&dev_priv->irqmask_lock);
 244
 245         if (dsp_int && ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND)) {
 246                 psb_vdc_interrupt(dev, vdc_stat);
 247                 handled = 1;
 248         }
 249
 250         if (sgx_int) {
 251                 /* Not expected - we have it masked, shut it up */
 252                 u32 s, s2;
 253                 s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
 254                 s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
 255                 PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
 256                 PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
 257                 /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
 258                    we may as well poll even if we add that ! */
 259                 handled = 1;
 260         }
 261
 262         PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
 263         (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
 264         DRM_READMEMORYBARRIER();
 265
 266         if (!handled)
 267                 return IRQ_NONE;
 268
 269         return IRQ_HANDLED;
 270 }
 271
 272 void psb_irq_preinstall(struct drm_device *dev)
 273 {
 274         psb_irq_preinstall_islands(dev, OSPM_ALL_ISLANDS);
 275 }
 276
 277 /**
 278  * FIXME: should I remove display irq enable here??
 279  */
 280 void psb_irq_preinstall_islands(struct drm_device *dev, int hw_islands)
 281 {
 282         struct drm_psb_private *dev_priv =
 283             (struct drm_psb_private *) dev->dev_private;
 284         unsigned long irqflags;
 285
 286         PSB_DEBUG_ENTRY("\n");
 287
 288         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 289
 290         if (hw_islands & OSPM_DISPLAY_ISLAND) {
 291                 if (ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND)) {
 292                         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 293                         if (dev->vblank_enabled[0])
 294                                 dev_priv->vdc_irq_mask |=
 295                                                 _PSB_PIPEA_EVENT_FLAG;
 296                         if (dev->vblank_enabled[1])
 297                                 dev_priv->vdc_irq_mask |=
 298                                                 _MDFLD_PIPEB_EVENT_FLAG;
 299                         if (dev->vblank_enabled[2])
 300                                 dev_priv->vdc_irq_mask |=
 301                                                 _MDFLD_PIPEC_EVENT_FLAG;
 302                 }
 303         }
 304 /* NO I DONT WANT ANY IRQS GRRR FIXMEAC */
 305         if (hw_islands & OSPM_GRAPHICS_ISLAND)
 306                 dev_priv->vdc_irq_mask |= _PSB_IRQ_SGX_FLAG;
 307 /* */
 308         /*This register is safe even if display island is off*/
 309         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 310
 311         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 312 }
 313
 314 int psb_irq_postinstall(struct drm_device *dev)
 315 {
 316         return psb_irq_postinstall_islands(dev, OSPM_ALL_ISLANDS);
 317 }
 318
 319 int psb_irq_postinstall_islands(struct drm_device *dev, int hw_islands)
 320 {
 321
 322         struct drm_psb_private *dev_priv =
 323             (struct drm_psb_private *) dev->dev_private;
 324         unsigned long irqflags;
 325
 326         PSB_DEBUG_ENTRY("\n");
 327
 328         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 329
 330         /*This register is safe even if display island is off*/
 331         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 332
 333         if (hw_islands & OSPM_DISPLAY_ISLAND) {
 334                 if (true/*powermgmt_is_hw_on(dev->pdev, PSB_DISPLAY_ISLAND)*/) {
 335                         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 336
 337                         if (dev->vblank_enabled[0])
 338                                 psb_enable_pipestat(dev_priv, 0,
 339                                     PIPE_VBLANK_INTERRUPT_ENABLE);
 340                         else
 341                                 psb_disable_pipestat(dev_priv, 0,
 342                                     PIPE_VBLANK_INTERRUPT_ENABLE);
 343
 344                         if (dev->vblank_enabled[1])
 345                                         psb_enable_pipestat(dev_priv, 1,
 346                                             PIPE_VBLANK_INTERRUPT_ENABLE);
 347                         else
 348                                 psb_disable_pipestat(dev_priv, 1,
 349                                     PIPE_VBLANK_INTERRUPT_ENABLE);
 350
 351                         if (dev->vblank_enabled[2])
 352                                 psb_enable_pipestat(dev_priv, 2,
 353                                     PIPE_VBLANK_INTERRUPT_ENABLE);
 354                         else
 355                                 psb_disable_pipestat(dev_priv, 2,
 356                                     PIPE_VBLANK_INTERRUPT_ENABLE);
 357                 }
 358         }
 359
 360         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 361
 362         return 0;
 363 }
 364
 365 void psb_irq_uninstall(struct drm_device *dev)
 366 {
 367         psb_irq_uninstall_islands(dev, OSPM_ALL_ISLANDS);
 368 }
 369
 370 void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands)
 371 {
 372         struct drm_psb_private *dev_priv =
 373             (struct drm_psb_private *) dev->dev_private;
 374         unsigned long irqflags;
 375
 376         PSB_DEBUG_ENTRY("\n");
 377
 378         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 379
 380         if (hw_islands & OSPM_DISPLAY_ISLAND) {
 381                 if (true/*powermgmt_is_hw_on(dev->pdev, PSB_DISPLAY_ISLAND)*/) {
 382                         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 383
 384                         if (dev->vblank_enabled[0])
 385                                 psb_disable_pipestat(dev_priv, 0,
 386                                     PIPE_VBLANK_INTERRUPT_ENABLE);
 387
 388                         if (dev->vblank_enabled[1])
 389                                 psb_disable_pipestat(dev_priv, 1,
 390                                     PIPE_VBLANK_INTERRUPT_ENABLE);
 391
 392                         if (dev->vblank_enabled[2])
 393                                 psb_disable_pipestat(dev_priv, 2,
 394                                     PIPE_VBLANK_INTERRUPT_ENABLE);
 395                 }
 396                 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
 397                                           _PSB_IRQ_MSVDX_FLAG |
 398                                           _LNC_IRQ_TOPAZ_FLAG;
 399         }
 400         /*TODO: remove following code*/
 401         if (hw_islands & OSPM_GRAPHICS_ISLAND)
 402                 dev_priv->vdc_irq_mask &= ~_PSB_IRQ_SGX_FLAG;
 403
 404         /*These two registers are safe even if display island is off*/
 405         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 406         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 407
 408         wmb();
 409
 410         /*This register is safe even if display island is off*/
 411         PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
 412
 413         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 414 }
 415
 416 void psb_irq_turn_on_dpst(struct drm_device *dev)
 417 {
 418         struct drm_psb_private *dev_priv =
 419                 (struct drm_psb_private *) dev->dev_private;
 420         u32 hist_reg;
 421         u32 pwm_reg;
 422
 423         if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
 424                                                         OSPM_UHB_ONLY_IF_ON)) {
 425                 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
 426                 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
 427                 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
 428                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 429
 430                 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
 431                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 432                 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
 433                                                 | PWM_PHASEIN_INT_ENABLE,
 434                                                            PWM_CONTROL_LOGIC);
 435                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 436
 437                 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 438
 439                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 440                 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
 441                                                         HISTOGRAM_INT_CONTROL);
 442                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 443                 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
 444                                                         PWM_CONTROL_LOGIC);
 445
 446                 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 447         }
 448 }
 449
 450 int psb_irq_enable_dpst(struct drm_device *dev)
 451 {
 452         struct drm_psb_private *dev_priv =
 453                 (struct drm_psb_private *) dev->dev_private;
 454         unsigned long irqflags;
 455
 456         PSB_DEBUG_ENTRY("\n");
 457
 458         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 459
 460         /* enable DPST */
 461         mid_enable_pipe_event(dev_priv, 0);
 462         psb_irq_turn_on_dpst(dev);
 463
 464         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 465         return 0;
 466 }
 467
 468 void psb_irq_turn_off_dpst(struct drm_device *dev)
 469 {
 470         struct drm_psb_private *dev_priv =
 471             (struct drm_psb_private *) dev->dev_private;
 472         u32 hist_reg;
 473         u32 pwm_reg;
 474
 475         if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
 476                                                         OSPM_UHB_ONLY_IF_ON)) {
 477                 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
 478                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 479
 480                 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 481
 482                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 483                 PSB_WVDC32(pwm_reg & !(PWM_PHASEIN_INT_ENABLE),
 484                                                         PWM_CONTROL_LOGIC);
 485                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 486
 487                 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 488         }
 489 }
 490
 491 int psb_irq_disable_dpst(struct drm_device *dev)
 492 {
 493         struct drm_psb_private *dev_priv =
 494             (struct drm_psb_private *) dev->dev_private;
 495         unsigned long irqflags;
 496
 497         PSB_DEBUG_ENTRY("\n");
 498
 499         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 500
 501         mid_disable_pipe_event(dev_priv, 0);
 502         psb_irq_turn_off_dpst(dev);
 503
 504         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 505
 506         return 0;
 507 }
 508
 509 #ifdef PSB_FIXME
 510 static int psb_vblank_do_wait(struct drm_device *dev,
 511                               unsigned int *sequence, atomic_t *counter)
 512 {
 513         unsigned int cur_vblank;
 514         int ret = 0;
 515         DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
 516                     (((cur_vblank = atomic_read(counter))
 517                       - *sequence) <= (1 << 23)));
 518         *sequence = cur_vblank;
 519
 520         return ret;
 521 }
 522 #endif
 523
 524 /*
 525  * It is used to enable VBLANK interrupt
 526  */
 527 int psb_enable_vblank(struct drm_device *dev, int pipe)
 528 {
 529         struct drm_psb_private *dev_priv =
 530             (struct drm_psb_private *) dev->dev_private;
 531         unsigned long irqflags;
 532         uint32_t reg_val = 0;
 533         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 534
 535         PSB_DEBUG_ENTRY("\n");
 536
 537         if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
 538                                                         OSPM_UHB_ONLY_IF_ON)) {
 539                 reg_val = REG_READ(pipeconf_reg);
 540                 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 541         }
 542
 543         if (!(reg_val & PIPEACONF_ENABLE))
 544                 return -EINVAL;
 545
 546         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 547
 548         drm_psb_disable_vsync = 0;
 549         mid_enable_pipe_event(dev_priv, pipe);
 550         psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 551
 552         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 553
 554         return 0;
 555 }
 556
 557 /*
 558  * It is used to disable VBLANK interrupt
 559  */
 560 void psb_disable_vblank(struct drm_device *dev, int pipe)
 561 {
 562         struct drm_psb_private *dev_priv =
 563             (struct drm_psb_private *) dev->dev_private;
 564         unsigned long irqflags;
 565
 566         PSB_DEBUG_ENTRY("\n");
 567
 568         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 569
 570         drm_psb_disable_vsync = 1;
 571         mid_disable_pipe_event(dev_priv, pipe);
 572         psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 573
 574         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 575 }
 576
 577 /* Called from drm generic code, passed a 'crtc', which
 578  * we use as a pipe index
 579  */
 580 u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
 581 {
 582         uint32_t high_frame = PIPEAFRAMEHIGH;
 583         uint32_t low_frame = PIPEAFRAMEPIXEL;
 584         uint32_t pipeconf_reg = PIPEACONF;
 585         uint32_t reg_val = 0;
 586         uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
 587
 588         switch (pipe) {
 589         case 0:
 590                 break;
 591         case 1:
 592                 high_frame = PIPEBFRAMEHIGH;
 593                 low_frame = PIPEBFRAMEPIXEL;
 594                 pipeconf_reg = PIPEBCONF;
 595                 break;
 596         case 2:
 597                 high_frame = PIPECFRAMEHIGH;
 598                 low_frame = PIPECFRAMEPIXEL;
 599                 pipeconf_reg = PIPECCONF;
 600                 break;
 601         default:
 602                 DRM_ERROR("%s, invalded pipe.\n", __func__);
 603                 return 0;
 604         }
 605
 606         if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false))
 607                 return 0;
 608
 609         reg_val = REG_READ(pipeconf_reg);
 610
 611         if (!(reg_val & PIPEACONF_ENABLE)) {
 612                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n",
 613                                                                 pipe);
 614                 goto psb_get_vblank_counter_exit;
 615         }
 616
 617         /*
 618          * High & low register fields aren't synchronized, so make sure
 619          * we get a low value that's stable across two reads of the high
 620          * register.
 621          */
 622         do {
 623                 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 624                          PIPE_FRAME_HIGH_SHIFT);
 625                 low =  ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 626                         PIPE_FRAME_LOW_SHIFT);
 627                 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 628                          PIPE_FRAME_HIGH_SHIFT);
 629         } while (high1 != high2);
 630
 631         count = (high1 << 8) | low;
 632
 633 psb_get_vblank_counter_exit:
 634
 635         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
 636
 637         return count;
 638 }
 639