?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mmc: tmio_mmc: drop dma_sglen state variable
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mmc / host / tmio_mmc.c
blob699b6ab209b24c0f3b1d6e6626ca78ee67487477
1 /*
2 * linux/drivers/mmc/tmio_mmc.c
3 *
4 * Copyright (C) 2004 Ian Molton
5 * Copyright (C) 2007 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Driver for the MMC / SD / SDIO cell found in:
12 *
13 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
14 *
15 * This driver draws mainly on scattered spec sheets, Reverse engineering
16 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
17 * support). (Further 4 bit support from a later datasheet).
18 *
19 * TODO:
20 * Investigate using a workqueue for PIO transfers
21 * Eliminate FIXMEs
22 * SDIO support
23 * Better Power management
24 * Handle MMC errors better
25 * double buffer support
26 *
27 */
28
29 #include <linux/delay.h>
30 #include <linux/device.h>
31 #include <linux/dmaengine.h>
32 #include <linux/highmem.h>
33 #include <linux/interrupt.h>
34 #include <linux/io.h>
35 #include <linux/irq.h>
36 #include <linux/mfd/core.h>
37 #include <linux/mfd/tmio.h>
38 #include <linux/mmc/host.h>
39 #include <linux/module.h>
40 #include <linux/pagemap.h>
41 #include <linux/scatterlist.h>
42 #include <linux/workqueue.h>
43 #include <linux/spinlock.h>
44
45 #define CTL_SD_CMD 0x00
46 #define CTL_ARG_REG 0x04
47 #define CTL_STOP_INTERNAL_ACTION 0x08
48 #define CTL_XFER_BLK_COUNT 0xa
49 #define CTL_RESPONSE 0x0c
50 #define CTL_STATUS 0x1c
51 #define CTL_IRQ_MASK 0x20
52 #define CTL_SD_CARD_CLK_CTL 0x24
53 #define CTL_SD_XFER_LEN 0x26
54 #define CTL_SD_MEM_CARD_OPT 0x28
55 #define CTL_SD_ERROR_DETAIL_STATUS 0x2c
56 #define CTL_SD_DATA_PORT 0x30
57 #define CTL_TRANSACTION_CTL 0x34
58 #define CTL_SDIO_STATUS 0x36
59 #define CTL_SDIO_IRQ_MASK 0x38
60 #define CTL_RESET_SD 0xe0
61 #define CTL_SDIO_REGS 0x100
62 #define CTL_CLK_AND_WAIT_CTL 0x138
63 #define CTL_RESET_SDIO 0x1e0
64
65 /* Definitions for values the CTRL_STATUS register can take. */
66 #define TMIO_STAT_CMDRESPEND 0x00000001
67 #define TMIO_STAT_DATAEND 0x00000004
68 #define TMIO_STAT_CARD_REMOVE 0x00000008
69 #define TMIO_STAT_CARD_INSERT 0x00000010
70 #define TMIO_STAT_SIGSTATE 0x00000020
71 #define TMIO_STAT_WRPROTECT 0x00000080
72 #define TMIO_STAT_CARD_REMOVE_A 0x00000100
73 #define TMIO_STAT_CARD_INSERT_A 0x00000200
74 #define TMIO_STAT_SIGSTATE_A 0x00000400
75 #define TMIO_STAT_CMD_IDX_ERR 0x00010000
76 #define TMIO_STAT_CRCFAIL 0x00020000
77 #define TMIO_STAT_STOPBIT_ERR 0x00040000
78 #define TMIO_STAT_DATATIMEOUT 0x00080000
79 #define TMIO_STAT_RXOVERFLOW 0x00100000
80 #define TMIO_STAT_TXUNDERRUN 0x00200000
81 #define TMIO_STAT_CMDTIMEOUT 0x00400000
82 #define TMIO_STAT_RXRDY 0x01000000
83 #define TMIO_STAT_TXRQ 0x02000000
84 #define TMIO_STAT_ILL_FUNC 0x20000000
85 #define TMIO_STAT_CMD_BUSY 0x40000000
86 #define TMIO_STAT_ILL_ACCESS 0x80000000
87
88 /* Definitions for values the CTRL_SDIO_STATUS register can take. */
89 #define TMIO_SDIO_STAT_IOIRQ 0x0001
90 #define TMIO_SDIO_STAT_EXPUB52 0x4000
91 #define TMIO_SDIO_STAT_EXWT 0x8000
92 #define TMIO_SDIO_MASK_ALL 0xc007
93
94 /* Define some IRQ masks */
95 /* This is the mask used at reset by the chip */
96 #define TMIO_MASK_ALL 0x837f031d
97 #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
98 #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
99 #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
100 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
101 #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
102
103 #define enable_mmc_irqs(host, i) \
104 do { \
105 u32 mask;\
106 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \
107 mask &= ~((i) & TMIO_MASK_IRQ); \
108 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
109 } while (0)
110
111 #define disable_mmc_irqs(host, i) \
112 do { \
113 u32 mask;\
114 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \
115 mask |= ((i) & TMIO_MASK_IRQ); \
116 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
117 } while (0)
118
119 #define ack_mmc_irqs(host, i) \
120 do { \
121 sd_ctrl_write32((host), CTL_STATUS, ~(i)); \
122 } while (0)
123
124 /* This is arbitrary, just noone needed any higher alignment yet */
125 #define MAX_ALIGN 4
126
127 struct tmio_mmc_host {
128 void __iomem *ctl;
129 unsigned long bus_shift;
130 struct mmc_command *cmd;
131 struct mmc_request *mrq;
132 struct mmc_data *data;
133 struct mmc_host *mmc;
134 int irq;
135 unsigned int sdio_irq_enabled;
136
137 /* Callbacks for clock / power control */
138 void (*set_pwr)(struct platform_device *host, int state);
139 void (*set_clk_div)(struct platform_device *host, int state);
140
141 /* pio related stuff */
142 struct scatterlist *sg_ptr;
143 struct scatterlist *sg_orig;
144 unsigned int sg_len;
145 unsigned int sg_off;
146
147 struct platform_device *pdev;
148
149 /* DMA support */
150 struct dma_chan *chan_rx;
151 struct dma_chan *chan_tx;
152 struct tasklet_struct dma_complete;
153 struct tasklet_struct dma_issue;
154 #ifdef CONFIG_TMIO_MMC_DMA
155 u8 bounce_buf[PAGE_CACHE_SIZE] __attribute__((aligned(MAX_ALIGN)));
156 struct scatterlist bounce_sg;
157 #endif
158
159 /* Track lost interrupts */
160 struct delayed_work delayed_reset_work;
161 spinlock_t lock;
162 unsigned long last_req_ts;
163 };
164
165 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host);
166
167 static u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
168 {
169 return readw(host->ctl + (addr << host->bus_shift));
170 }
171
172 static void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
173 u16 *buf, int count)
174 {
175 readsw(host->ctl + (addr << host->bus_shift), buf, count);
176 }
177
178 static u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
179 {
180 return readw(host->ctl + (addr << host->bus_shift)) |
181 readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
182 }
183
184 static void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
185 {
186 writew(val, host->ctl + (addr << host->bus_shift));
187 }
188
189 static void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
190 u16 *buf, int count)
191 {
192 writesw(host->ctl + (addr << host->bus_shift), buf, count);
193 }
194
195 static void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
196 {
197 writew(val, host->ctl + (addr << host->bus_shift));
198 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
199 }
200
201 static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
202 {
203 host->sg_len = data->sg_len;
204 host->sg_ptr = data->sg;
205 host->sg_orig = data->sg;
206 host->sg_off = 0;
207 }
208
209 static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
210 {
211 host->sg_ptr = sg_next(host->sg_ptr);
212 host->sg_off = 0;
213 return --host->sg_len;
214 }
215
216 static char *tmio_mmc_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
217 {
218 local_irq_save(*flags);
219 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
220 }
221
222 static void tmio_mmc_kunmap_atomic(void *virt, unsigned long *flags)
223 {
224 kunmap_atomic(virt, KM_BIO_SRC_IRQ);
225 local_irq_restore(*flags);
226 }
227
228 #ifdef CONFIG_MMC_DEBUG
229
230 #define STATUS_TO_TEXT(a, status, i) \
231 do { \
232 if (status & TMIO_STAT_##a) { \
233 if (i++) \
234 printk(" | "); \
235 printk(#a); \
236 } \
237 } while (0)
238
239 void pr_debug_status(u32 status)
240 {
241 int i = 0;
242 printk(KERN_DEBUG "status: %08x = ", status);
243 STATUS_TO_TEXT(CARD_REMOVE, status, i);
244 STATUS_TO_TEXT(CARD_INSERT, status, i);
245 STATUS_TO_TEXT(SIGSTATE, status, i);
246 STATUS_TO_TEXT(WRPROTECT, status, i);
247 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
248 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
249 STATUS_TO_TEXT(SIGSTATE_A, status, i);
250 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
251 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
252 STATUS_TO_TEXT(ILL_FUNC, status, i);
253 STATUS_TO_TEXT(CMD_BUSY, status, i);
254 STATUS_TO_TEXT(CMDRESPEND, status, i);
255 STATUS_TO_TEXT(DATAEND, status, i);
256 STATUS_TO_TEXT(CRCFAIL, status, i);
257 STATUS_TO_TEXT(DATATIMEOUT, status, i);
258 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
259 STATUS_TO_TEXT(RXOVERFLOW, status, i);
260 STATUS_TO_TEXT(TXUNDERRUN, status, i);
261 STATUS_TO_TEXT(RXRDY, status, i);
262 STATUS_TO_TEXT(TXRQ, status, i);
263 STATUS_TO_TEXT(ILL_ACCESS, status, i);
264 printk("\n");
265 }
266
267 #else
268 #define pr_debug_status(s) do { } while (0)
269 #endif
270
271 static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
272 {
273 struct tmio_mmc_host *host = mmc_priv(mmc);
274
275 if (enable) {
276 host->sdio_irq_enabled = 1;
277 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
278 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK,
279 (TMIO_SDIO_MASK_ALL & ~TMIO_SDIO_STAT_IOIRQ));
280 } else {
281 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, TMIO_SDIO_MASK_ALL);
282 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
283 host->sdio_irq_enabled = 0;
284 }
285 }
286
287 static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
288 {
289 u32 clk = 0, clock;
290
291 if (new_clock) {
292 for (clock = host->mmc->f_min, clk = 0x80000080;
293 new_clock >= (clock<<1); clk >>= 1)
294 clock <<= 1;
295 clk |= 0x100;
296 }
297
298 if (host->set_clk_div)
299 host->set_clk_div(host->pdev, (clk>>22) & 1);
300
301 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
302 }
303
304 static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
305 {
306 struct mfd_cell *cell = host->pdev->dev.platform_data;
307 struct tmio_mmc_data *pdata = cell->driver_data;
308
309 /*
310 * Testing on sh-mobile showed that SDIO IRQs are unmasked when
311 * CTL_CLK_AND_WAIT_CTL gets written, so we have to disable the
312 * device IRQ here and restore the SDIO IRQ mask before
313 * re-enabling the device IRQ.
314 */
315 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
316 disable_irq(host->irq);
317 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
318 msleep(10);
319 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
320 tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled);
321 enable_irq(host->irq);
322 }
323 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
324 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
325 msleep(10);
326 }
327
328 static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
329 {
330 struct mfd_cell *cell = host->pdev->dev.platform_data;
331 struct tmio_mmc_data *pdata = cell->driver_data;
332
333 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
334 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
335 msleep(10);
336 /* see comment in tmio_mmc_clk_stop above */
337 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
338 disable_irq(host->irq);
339 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
340 msleep(10);
341 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
342 tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled);
343 enable_irq(host->irq);
344 }
345 }
346
347 static void reset(struct tmio_mmc_host *host)
348 {
349 /* FIXME - should we set stop clock reg here */
350 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
351 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
352 msleep(10);
353 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
354 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
355 msleep(10);
356 }
357
358 static void tmio_mmc_reset_work(struct work_struct *work)
359 {
360 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
361 delayed_reset_work.work);
362 struct mmc_request *mrq;
363 unsigned long flags;
364
365 spin_lock_irqsave(&host->lock, flags);
366 mrq = host->mrq;
367
368 /* request already finished */
369 if (!mrq
370 || time_is_after_jiffies(host->last_req_ts +
371 msecs_to_jiffies(2000))) {
372 spin_unlock_irqrestore(&host->lock, flags);
373 return;
374 }
375
376 dev_warn(&host->pdev->dev,
377 "timeout waiting for hardware interrupt (CMD%u)\n",
378 mrq->cmd->opcode);
379
380 if (host->data)
381 host->data->error = -ETIMEDOUT;
382 else if (host->cmd)
383 host->cmd->error = -ETIMEDOUT;
384 else
385 mrq->cmd->error = -ETIMEDOUT;
386
387 host->cmd = NULL;
388 host->data = NULL;
389 host->mrq = NULL;
390
391 spin_unlock_irqrestore(&host->lock, flags);
392
393 reset(host);
394
395 mmc_request_done(host->mmc, mrq);
396 }
397
398 static void
399 tmio_mmc_finish_request(struct tmio_mmc_host *host)
400 {
401 struct mmc_request *mrq = host->mrq;
402
403 if (!mrq)
404 return;
405
406 host->mrq = NULL;
407 host->cmd = NULL;
408 host->data = NULL;
409
410 cancel_delayed_work(&host->delayed_reset_work);
411
412 mmc_request_done(host->mmc, mrq);
413 }
414
415 /* These are the bitmasks the tmio chip requires to implement the MMC response
416 * types. Note that R1 and R6 are the same in this scheme. */
417 #define APP_CMD 0x0040
418 #define RESP_NONE 0x0300
419 #define RESP_R1 0x0400
420 #define RESP_R1B 0x0500
421 #define RESP_R2 0x0600
422 #define RESP_R3 0x0700
423 #define DATA_PRESENT 0x0800
424 #define TRANSFER_READ 0x1000
425 #define TRANSFER_MULTI 0x2000
426 #define SECURITY_CMD 0x4000
427
428 static int
429 tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
430 {
431 struct mmc_data *data = host->data;
432 int c = cmd->opcode;
433
434 /* Command 12 is handled by hardware */
435 if (cmd->opcode == 12 && !cmd->arg) {
436 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
437 return 0;
438 }
439
440 switch (mmc_resp_type(cmd)) {
441 case MMC_RSP_NONE: c |= RESP_NONE; break;
442 case MMC_RSP_R1: c |= RESP_R1; break;
443 case MMC_RSP_R1B: c |= RESP_R1B; break;
444 case MMC_RSP_R2: c |= RESP_R2; break;
445 case MMC_RSP_R3: c |= RESP_R3; break;
446 default:
447 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
448 return -EINVAL;
449 }
450
451 host->cmd = cmd;
452
453 /* FIXME - this seems to be ok commented out but the spec suggest this bit
454 * should be set when issuing app commands.
455 * if(cmd->flags & MMC_FLAG_ACMD)
456 * c |= APP_CMD;
457 */
458 if (data) {
459 c |= DATA_PRESENT;
460 if (data->blocks > 1) {
461 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
462 c |= TRANSFER_MULTI;
463 }
464 if (data->flags & MMC_DATA_READ)
465 c |= TRANSFER_READ;
466 }
467
468 enable_mmc_irqs(host, TMIO_MASK_CMD);
469
470 /* Fire off the command */
471 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
472 sd_ctrl_write16(host, CTL_SD_CMD, c);
473
474 return 0;
475 }
476
477 /*
478 * This chip always returns (at least?) as much data as you ask for.
479 * I'm unsure what happens if you ask for less than a block. This should be
480 * looked into to ensure that a funny length read doesnt hose the controller.
481 */
482 static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
483 {
484 struct mmc_data *data = host->data;
485 void *sg_virt;
486 unsigned short *buf;
487 unsigned int count;
488 unsigned long flags;
489
490 if (!data) {
491 pr_debug("Spurious PIO IRQ\n");
492 return;
493 }
494
495 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
496 buf = (unsigned short *)(sg_virt + host->sg_off);
497
498 count = host->sg_ptr->length - host->sg_off;
499 if (count > data->blksz)
500 count = data->blksz;
501
502 pr_debug("count: %08x offset: %08x flags %08x\n",
503 count, host->sg_off, data->flags);
504
505 /* Transfer the data */
506 if (data->flags & MMC_DATA_READ)
507 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
508 else
509 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
510
511 host->sg_off += count;
512
513 tmio_mmc_kunmap_atomic(sg_virt, &flags);
514
515 if (host->sg_off == host->sg_ptr->length)
516 tmio_mmc_next_sg(host);
517
518 return;
519 }
520
521 /* needs to be called with host->lock held */
522 static void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
523 {
524 struct mmc_data *data = host->data;
525 struct mmc_command *stop;
526
527 host->data = NULL;
528
529 if (!data) {
530 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
531 return;
532 }
533 stop = data->stop;
534
535 /* FIXME - return correct transfer count on errors */
536 if (!data->error)
537 data->bytes_xfered = data->blocks * data->blksz;
538 else
539 data->bytes_xfered = 0;
540
541 pr_debug("Completed data request\n");
542
543 /*
544 * FIXME: other drivers allow an optional stop command of any given type
545 * which we dont do, as the chip can auto generate them.
546 * Perhaps we can be smarter about when to use auto CMD12 and
547 * only issue the auto request when we know this is the desired
548 * stop command, allowing fallback to the stop command the
549 * upper layers expect. For now, we do what works.
550 */
551
552 if (data->flags & MMC_DATA_READ) {
553 if (!host->chan_rx)
554 disable_mmc_irqs(host, TMIO_MASK_READOP);
555 else
556 tmio_check_bounce_buffer(host);
557 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
558 host->mrq);
559 } else {
560 if (!host->chan_tx)
561 disable_mmc_irqs(host, TMIO_MASK_WRITEOP);
562 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
563 host->mrq);
564 }
565
566 if (stop) {
567 if (stop->opcode == 12 && !stop->arg)
568 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
569 else
570 BUG();
571 }
572
573 tmio_mmc_finish_request(host);
574 }
575
576 static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
577 {
578 struct mmc_data *data;
579 spin_lock(&host->lock);
580 data = host->data;
581
582 if (!data)
583 goto out;
584
585 if (host->chan_tx && (data->flags & MMC_DATA_WRITE)) {
586 /*
587 * Has all data been written out yet? Testing on SuperH showed,
588 * that in most cases the first interrupt comes already with the
589 * BUSY status bit clear, but on some operations, like mount or
590 * in the beginning of a write / sync / umount, there is one
591 * DATAEND interrupt with the BUSY bit set, in this cases
592 * waiting for one more interrupt fixes the problem.
593 */
594 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
595 disable_mmc_irqs(host, TMIO_STAT_DATAEND);
596 tasklet_schedule(&host->dma_complete);
597 }
598 } else if (host->chan_rx && (data->flags & MMC_DATA_READ)) {
599 disable_mmc_irqs(host, TMIO_STAT_DATAEND);
600 tasklet_schedule(&host->dma_complete);
601 } else {
602 tmio_mmc_do_data_irq(host);
603 }
604 out:
605 spin_unlock(&host->lock);
606 }
607
608 static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
609 unsigned int stat)
610 {
611 struct mmc_command *cmd = host->cmd;
612 int i, addr;
613
614 spin_lock(&host->lock);
615
616 if (!host->cmd) {
617 pr_debug("Spurious CMD irq\n");
618 goto out;
619 }
620
621 host->cmd = NULL;
622
623 /* This controller is sicker than the PXA one. Not only do we need to
624 * drop the top 8 bits of the first response word, we also need to
625 * modify the order of the response for short response command types.
626 */
627
628 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
629 cmd->resp[i] = sd_ctrl_read32(host, addr);
630
631 if (cmd->flags & MMC_RSP_136) {
632 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
633 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
634 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
635 cmd->resp[3] <<= 8;
636 } else if (cmd->flags & MMC_RSP_R3) {
637 cmd->resp[0] = cmd->resp[3];
638 }
639
640 if (stat & TMIO_STAT_CMDTIMEOUT)
641 cmd->error = -ETIMEDOUT;
642 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
643 cmd->error = -EILSEQ;
644
645 /* If there is data to handle we enable data IRQs here, and
646 * we will ultimatley finish the request in the data_end handler.
647 * If theres no data or we encountered an error, finish now.
648 */
649 if (host->data && !cmd->error) {
650 if (host->data->flags & MMC_DATA_READ) {
651 if (!host->chan_rx)
652 enable_mmc_irqs(host, TMIO_MASK_READOP);
653 } else {
654 if (!host->chan_tx)
655 enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
656 else
657 tasklet_schedule(&host->dma_issue);
658 }
659 } else {
660 tmio_mmc_finish_request(host);
661 }
662
663 out:
664 spin_unlock(&host->lock);
665
666 return;
667 }
668
669 static irqreturn_t tmio_mmc_irq(int irq, void *devid)
670 {
671 struct tmio_mmc_host *host = devid;
672 struct mfd_cell *cell = host->pdev->dev.platform_data;
673 struct tmio_mmc_data *pdata = cell->driver_data;
674 unsigned int ireg, irq_mask, status;
675 unsigned int sdio_ireg, sdio_irq_mask, sdio_status;
676
677 pr_debug("MMC IRQ begin\n");
678
679 status = sd_ctrl_read32(host, CTL_STATUS);
680 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
681 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
682
683 sdio_ireg = 0;
684 if (!ireg && pdata->flags & TMIO_MMC_SDIO_IRQ) {
685 sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
686 sdio_irq_mask = sd_ctrl_read16(host, CTL_SDIO_IRQ_MASK);
687 sdio_ireg = sdio_status & TMIO_SDIO_MASK_ALL & ~sdio_irq_mask;
688
689 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status & ~TMIO_SDIO_MASK_ALL);
690
691 if (sdio_ireg && !host->sdio_irq_enabled) {
692 pr_warning("tmio_mmc: Spurious SDIO IRQ, disabling! 0x%04x 0x%04x 0x%04x\n",
693 sdio_status, sdio_irq_mask, sdio_ireg);
694 tmio_mmc_enable_sdio_irq(host->mmc, 0);
695 goto out;
696 }
697
698 if (host->mmc->caps & MMC_CAP_SDIO_IRQ &&
699 sdio_ireg & TMIO_SDIO_STAT_IOIRQ)
700 mmc_signal_sdio_irq(host->mmc);
701
702 if (sdio_ireg)
703 goto out;
704 }
705
706 pr_debug_status(status);
707 pr_debug_status(ireg);
708
709 if (!ireg) {
710 disable_mmc_irqs(host, status & ~irq_mask);
711
712 pr_warning("tmio_mmc: Spurious irq, disabling! "
713 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
714 pr_debug_status(status);
715
716 goto out;
717 }
718
719 while (ireg) {
720 /* Card insert / remove attempts */
721 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
722 ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
723 TMIO_STAT_CARD_REMOVE);
724 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
725 }
726
727 /* CRC and other errors */
728 /* if (ireg & TMIO_STAT_ERR_IRQ)
729 * handled |= tmio_error_irq(host, irq, stat);
730 */
731
732 /* Command completion */
733 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
734 ack_mmc_irqs(host,
735 TMIO_STAT_CMDRESPEND |
736 TMIO_STAT_CMDTIMEOUT);
737 tmio_mmc_cmd_irq(host, status);
738 }
739
740 /* Data transfer */
741 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
742 ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
743 tmio_mmc_pio_irq(host);
744 }
745
746 /* Data transfer completion */
747 if (ireg & TMIO_STAT_DATAEND) {
748 ack_mmc_irqs(host, TMIO_STAT_DATAEND);
749 tmio_mmc_data_irq(host);
750 }
751
752 /* Check status - keep going until we've handled it all */
753 status = sd_ctrl_read32(host, CTL_STATUS);
754 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
755 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
756
757 pr_debug("Status at end of loop: %08x\n", status);
758 pr_debug_status(status);
759 }
760 pr_debug("MMC IRQ end\n");
761
762 out:
763 return IRQ_HANDLED;
764 }
765
766 #ifdef CONFIG_TMIO_MMC_DMA
767 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host)
768 {
769 if (host->sg_ptr == &host->bounce_sg) {
770 unsigned long flags;
771 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
772 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
773 tmio_mmc_kunmap_atomic(sg_vaddr, &flags);
774 }
775 }
776
777 static void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable)
778 {
779 #if defined(CONFIG_SUPERH) || defined(CONFIG_ARCH_SHMOBILE)
780 /* Switch DMA mode on or off - SuperH specific? */
781 sd_ctrl_write16(host, 0xd8, enable ? 2 : 0);
782 #endif
783 }
784
785 static void tmio_dma_complete(void *arg)
786 {
787 struct tmio_mmc_host *host = arg;
788
789 dev_dbg(&host->pdev->dev, "Command completed\n");
790
791 if (!host->data)
792 dev_warn(&host->pdev->dev, "NULL data in DMA completion!\n");
793 else
794 enable_mmc_irqs(host, TMIO_STAT_DATAEND);
795 }
796
797 static void tmio_mmc_start_dma_rx(struct tmio_mmc_host *host)
798 {
799 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
800 struct dma_async_tx_descriptor *desc = NULL;
801 struct dma_chan *chan = host->chan_rx;
802 struct mfd_cell *cell = host->pdev->dev.platform_data;
803 struct tmio_mmc_data *pdata = cell->driver_data;
804 dma_cookie_t cookie;
805 int ret, i;
806 bool aligned = true, multiple = true;
807 unsigned int align = (1 << pdata->dma->alignment_shift) - 1;
808
809 for_each_sg(sg, sg_tmp, host->sg_len, i) {
810 if (sg_tmp->offset & align)
811 aligned = false;
812 if (sg_tmp->length & align) {
813 multiple = false;
814 break;
815 }
816 }
817
818 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE ||
819 align >= MAX_ALIGN)) || !multiple) {
820 ret = -EINVAL;
821 goto pio;
822 }
823
824 /* The only sg element can be unaligned, use our bounce buffer then */
825 if (!aligned) {
826 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
827 host->sg_ptr = &host->bounce_sg;
828 sg = host->sg_ptr;
829 }
830
831 ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
832 if (ret > 0)
833 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
834 DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
835
836 if (desc) {
837 desc->callback = tmio_dma_complete;
838 desc->callback_param = host;
839 cookie = desc->tx_submit(desc);
840 if (cookie < 0) {
841 desc = NULL;
842 ret = cookie;
843 } else {
844 chan->device->device_issue_pending(chan);
845 }
846 }
847 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
848 __func__, host->sg_len, ret, cookie, host->mrq);
849
850 pio:
851 if (!desc) {
852 /* DMA failed, fall back to PIO */
853 if (ret >= 0)
854 ret = -EIO;
855 host->chan_rx = NULL;
856 dma_release_channel(chan);
857 /* Free the Tx channel too */
858 chan = host->chan_tx;
859 if (chan) {
860 host->chan_tx = NULL;
861 dma_release_channel(chan);
862 }
863 dev_warn(&host->pdev->dev,
864 "DMA failed: %d, falling back to PIO\n", ret);
865 tmio_mmc_enable_dma(host, false);
866 }
867
868 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
869 desc, cookie, host->sg_len);
870 }
871
872 static void tmio_mmc_start_dma_tx(struct tmio_mmc_host *host)
873 {
874 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
875 struct dma_async_tx_descriptor *desc = NULL;
876 struct dma_chan *chan = host->chan_tx;
877 struct mfd_cell *cell = host->pdev->dev.platform_data;
878 struct tmio_mmc_data *pdata = cell->driver_data;
879 dma_cookie_t cookie;
880 int ret, i;
881 bool aligned = true, multiple = true;
882 unsigned int align = (1 << pdata->dma->alignment_shift) - 1;
883
884 for_each_sg(sg, sg_tmp, host->sg_len, i) {
885 if (sg_tmp->offset & align)
886 aligned = false;
887 if (sg_tmp->length & align) {
888 multiple = false;
889 break;
890 }
891 }
892
893 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE ||
894 align >= MAX_ALIGN)) || !multiple) {
895 ret = -EINVAL;
896 goto pio;
897 }
898
899 /* The only sg element can be unaligned, use our bounce buffer then */
900 if (!aligned) {
901 unsigned long flags;
902 void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
903 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
904 memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
905 tmio_mmc_kunmap_atomic(sg_vaddr, &flags);
906 host->sg_ptr = &host->bounce_sg;
907 sg = host->sg_ptr;
908 }
909
910 ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
911 if (ret > 0)
912 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
913 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
914
915 if (desc) {
916 desc->callback = tmio_dma_complete;
917 desc->callback_param = host;
918 cookie = desc->tx_submit(desc);
919 if (cookie < 0) {
920 desc = NULL;
921 ret = cookie;
922 }
923 }
924 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
925 __func__, host->sg_len, ret, cookie, host->mrq);
926
927 pio:
928 if (!desc) {
929 /* DMA failed, fall back to PIO */
930 if (ret >= 0)
931 ret = -EIO;
932 host->chan_tx = NULL;
933 dma_release_channel(chan);
934 /* Free the Rx channel too */
935 chan = host->chan_rx;
936 if (chan) {
937 host->chan_rx = NULL;
938 dma_release_channel(chan);
939 }
940 dev_warn(&host->pdev->dev,
941 "DMA failed: %d, falling back to PIO\n", ret);
942 tmio_mmc_enable_dma(host, false);
943 }
944
945 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d\n", __func__,
946 desc, cookie);
947 }
948
949 static void tmio_mmc_start_dma(struct tmio_mmc_host *host,
950 struct mmc_data *data)
951 {
952 if (data->flags & MMC_DATA_READ) {
953 if (host->chan_rx)
954 tmio_mmc_start_dma_rx(host);
955 } else {
956 if (host->chan_tx)
957 tmio_mmc_start_dma_tx(host);
958 }
959 }
960
961 static void tmio_issue_tasklet_fn(unsigned long priv)
962 {
963 struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
964 struct dma_chan *chan = host->chan_tx;
965
966 chan->device->device_issue_pending(chan);
967 }
968
969 static void tmio_tasklet_fn(unsigned long arg)
970 {
971 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
972 unsigned long flags;
973
974 spin_lock_irqsave(&host->lock, flags);
975
976 if (!host->data)
977 goto out;
978
979 if (host->data->flags & MMC_DATA_READ)
980 dma_unmap_sg(host->chan_rx->device->dev,
981 host->sg_ptr, host->sg_len,
982 DMA_FROM_DEVICE);
983 else
984 dma_unmap_sg(host->chan_tx->device->dev,
985 host->sg_ptr, host->sg_len,
986 DMA_TO_DEVICE);
987
988 tmio_mmc_do_data_irq(host);
989 out:
990 spin_unlock_irqrestore(&host->lock, flags);
991 }
992
993 /* It might be necessary to make filter MFD specific */
994 static bool tmio_mmc_filter(struct dma_chan *chan, void *arg)
995 {
996 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
997 chan->private = arg;
998 return true;
999 }
1000
1001 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
1002 struct tmio_mmc_data *pdata)
1003 {
1004 /* We can only either use DMA for both Tx and Rx or not use it at all */
1005 if (pdata->dma) {
1006 dma_cap_mask_t mask;
1007
1008 dma_cap_zero(mask);
1009 dma_cap_set(DMA_SLAVE, mask);
1010
1011 host->chan_tx = dma_request_channel(mask, tmio_mmc_filter,
1012 pdata->dma->chan_priv_tx);
1013 dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
1014 host->chan_tx);
1015
1016 if (!host->chan_tx)
1017 return;
1018
1019 host->chan_rx = dma_request_channel(mask, tmio_mmc_filter,
1020 pdata->dma->chan_priv_rx);
1021 dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
1022 host->chan_rx);
1023
1024 if (!host->chan_rx) {
1025 dma_release_channel(host->chan_tx);
1026 host->chan_tx = NULL;
1027 return;
1028 }
1029
1030 tasklet_init(&host->dma_complete, tmio_tasklet_fn, (unsigned long)host);
1031 tasklet_init(&host->dma_issue, tmio_issue_tasklet_fn, (unsigned long)host);
1032
1033 tmio_mmc_enable_dma(host, true);
1034 }
1035 }
1036
1037 static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
1038 {
1039 if (host->chan_tx) {
1040 struct dma_chan *chan = host->chan_tx;
1041 host->chan_tx = NULL;
1042 dma_release_channel(chan);
1043 }
1044 if (host->chan_rx) {
1045 struct dma_chan *chan = host->chan_rx;
1046 host->chan_rx = NULL;
1047 dma_release_channel(chan);
1048 }
1049 }
1050 #else
1051 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host)
1052 {
1053 }
1054
1055 static void tmio_mmc_start_dma(struct tmio_mmc_host *host,
1056 struct mmc_data *data)
1057 {
1058 }
1059
1060 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
1061 struct tmio_mmc_data *pdata)
1062 {
1063 host->chan_tx = NULL;
1064 host->chan_rx = NULL;
1065 }
1066
1067 static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
1068 {
1069 }
1070 #endif
1071
1072 static int tmio_mmc_start_data(struct tmio_mmc_host *host,
1073 struct mmc_data *data)
1074 {
1075 struct mfd_cell *cell = host->pdev->dev.platform_data;
1076 struct tmio_mmc_data *pdata = cell->driver_data;
1077
1078 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
1079 data->blksz, data->blocks);
1080
1081 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
1082 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1083 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
1084
1085 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
1086 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
1087 mmc_hostname(host->mmc), data->blksz);
1088 return -EINVAL;
1089 }
1090 }
1091
1092 tmio_mmc_init_sg(host, data);
1093 host->data = data;
1094
1095 /* Set transfer length / blocksize */
1096 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
1097 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
1098
1099 tmio_mmc_start_dma(host, data);
1100
1101 return 0;
1102 }
1103
1104 /* Process requests from the MMC layer */
1105 static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1106 {
1107 struct tmio_mmc_host *host = mmc_priv(mmc);
1108 int ret;
1109
1110 if (host->mrq)
1111 pr_debug("request not null\n");
1112
1113 host->last_req_ts = jiffies;
1114 wmb();
1115 host->mrq = mrq;
1116
1117 if (mrq->data) {
1118 ret = tmio_mmc_start_data(host, mrq->data);
1119 if (ret)
1120 goto fail;
1121 }
1122
1123 ret = tmio_mmc_start_command(host, mrq->cmd);
1124 if (!ret) {
1125 schedule_delayed_work(&host->delayed_reset_work,
1126 msecs_to_jiffies(2000));
1127 return;
1128 }
1129
1130 fail:
1131 host->mrq = NULL;
1132 mrq->cmd->error = ret;
1133 mmc_request_done(mmc, mrq);
1134 }
1135
1136 /* Set MMC clock / power.
1137 * Note: This controller uses a simple divider scheme therefore it cannot
1138 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
1139 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
1140 * slowest setting.
1141 */
1142 static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1143 {
1144 struct tmio_mmc_host *host = mmc_priv(mmc);
1145
1146 if (ios->clock)
1147 tmio_mmc_set_clock(host, ios->clock);
1148
1149 /* Power sequence - OFF -> ON -> UP */
1150 switch (ios->power_mode) {
1151 case MMC_POWER_OFF: /* power down SD bus */
1152 if (host->set_pwr)
1153 host->set_pwr(host->pdev, 0);
1154 tmio_mmc_clk_stop(host);
1155 break;
1156 case MMC_POWER_ON: /* power up SD bus */
1157 if (host->set_pwr)
1158 host->set_pwr(host->pdev, 1);
1159 break;
1160 case MMC_POWER_UP: /* start bus clock */
1161 tmio_mmc_clk_start(host);
1162 break;
1163 }
1164
1165 switch (ios->bus_width) {
1166 case MMC_BUS_WIDTH_1:
1167 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
1168 break;
1169 case MMC_BUS_WIDTH_4:
1170 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
1171 break;
1172 }
1173
1174 /* Let things settle. delay taken from winCE driver */
1175 udelay(140);
1176 }
1177
1178 static int tmio_mmc_get_ro(struct mmc_host *mmc)
1179 {
1180 struct tmio_mmc_host *host = mmc_priv(mmc);
1181 struct mfd_cell *cell = host->pdev->dev.platform_data;
1182 struct tmio_mmc_data *pdata = cell->driver_data;
1183
1184 return ((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
1185 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)) ? 0 : 1;
1186 }
1187
1188 static int tmio_mmc_get_cd(struct mmc_host *mmc)
1189 {
1190 struct tmio_mmc_host *host = mmc_priv(mmc);
1191 struct mfd_cell *cell = host->pdev->dev.platform_data;
1192 struct tmio_mmc_data *pdata = cell->driver_data;
1193
1194 if (!pdata->get_cd)
1195 return -ENOSYS;
1196 else
1197 return pdata->get_cd(host->pdev);
1198 }
1199
1200 static const struct mmc_host_ops tmio_mmc_ops = {
1201 .request = tmio_mmc_request,
1202 .set_ios = tmio_mmc_set_ios,
1203 .get_ro = tmio_mmc_get_ro,
1204 .get_cd = tmio_mmc_get_cd,
1205 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
1206 };
1207
1208 #ifdef CONFIG_PM
1209 static int tmio_mmc_suspend(struct platform_device *dev, pm_message_t state)
1210 {
1211 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1212 struct mmc_host *mmc = platform_get_drvdata(dev);
1213 int ret;
1214
1215 ret = mmc_suspend_host(mmc);
1216
1217 /* Tell MFD core it can disable us now.*/
1218 if (!ret && cell->disable)
1219 cell->disable(dev);
1220
1221 return ret;
1222 }
1223
1224 static int tmio_mmc_resume(struct platform_device *dev)
1225 {
1226 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1227 struct mmc_host *mmc = platform_get_drvdata(dev);
1228 int ret = 0;
1229
1230 /* Tell the MFD core we are ready to be enabled */
1231 if (cell->resume) {
1232 ret = cell->resume(dev);
1233 if (ret)
1234 goto out;
1235 }
1236
1237 mmc_resume_host(mmc);
1238
1239 out:
1240 return ret;
1241 }
1242 #else
1243 #define tmio_mmc_suspend NULL
1244 #define tmio_mmc_resume NULL
1245 #endif
1246
1247 static int __devinit tmio_mmc_probe(struct platform_device *dev)
1248 {
1249 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1250 struct tmio_mmc_data *pdata;
1251 struct resource *res_ctl;
1252 struct tmio_mmc_host *host;
1253 struct mmc_host *mmc;
1254 int ret = -EINVAL;
1255 u32 irq_mask = TMIO_MASK_CMD;
1256
1257 if (dev->num_resources != 2)
1258 goto out;
1259
1260 res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0);
1261 if (!res_ctl)
1262 goto out;
1263
1264 pdata = cell->driver_data;
1265 if (!pdata || !pdata->hclk)
1266 goto out;
1267
1268 ret = -ENOMEM;
1269
1270 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev);
1271 if (!mmc)
1272 goto out;
1273
1274 host = mmc_priv(mmc);
1275 host->mmc = mmc;
1276 host->pdev = dev;
1277 platform_set_drvdata(dev, mmc);
1278
1279 host->set_pwr = pdata->set_pwr;
1280 host->set_clk_div = pdata->set_clk_div;
1281
1282 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
1283 host->bus_shift = resource_size(res_ctl) >> 10;
1284
1285 host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
1286 if (!host->ctl)
1287 goto host_free;
1288
1289 mmc->ops = &tmio_mmc_ops;
1290 mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities;
1291 mmc->f_max = pdata->hclk;
1292 mmc->f_min = mmc->f_max / 512;
1293 mmc->max_segs = 32;
1294 mmc->max_blk_size = 512;
1295 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
1296 mmc->max_segs;
1297 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1298 mmc->max_seg_size = mmc->max_req_size;
1299 if (pdata->ocr_mask)
1300 mmc->ocr_avail = pdata->ocr_mask;
1301 else
1302 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1303
1304 /* Tell the MFD core we are ready to be enabled */
1305 if (cell->enable) {
1306 ret = cell->enable(dev);
1307 if (ret)
1308 goto unmap_ctl;
1309 }
1310
1311 tmio_mmc_clk_stop(host);
1312 reset(host);
1313
1314 ret = platform_get_irq(dev, 0);
1315 if (ret >= 0)
1316 host->irq = ret;
1317 else
1318 goto cell_disable;
1319
1320 disable_mmc_irqs(host, TMIO_MASK_ALL);
1321 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
1322 tmio_mmc_enable_sdio_irq(mmc, 0);
1323
1324 ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED |
1325 IRQF_TRIGGER_FALLING, dev_name(&dev->dev), host);
1326 if (ret)
1327 goto cell_disable;
1328
1329 spin_lock_init(&host->lock);
1330
1331 /* Init delayed work for request timeouts */
1332 INIT_DELAYED_WORK(&host->delayed_reset_work, tmio_mmc_reset_work);
1333
1334 /* See if we also get DMA */
1335 tmio_mmc_request_dma(host, pdata);
1336
1337 mmc_add_host(mmc);
1338
1339 pr_info("%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc),
1340 (unsigned long)host->ctl, host->irq);
1341
1342 /* Unmask the IRQs we want to know about */
1343 if (!host->chan_rx)
1344 irq_mask |= TMIO_MASK_READOP;
1345 if (!host->chan_tx)
1346 irq_mask |= TMIO_MASK_WRITEOP;
1347 enable_mmc_irqs(host, irq_mask);
1348
1349 return 0;
1350
1351 cell_disable:
1352 if (cell->disable)
1353 cell->disable(dev);
1354 unmap_ctl:
1355 iounmap(host->ctl);
1356 host_free:
1357 mmc_free_host(mmc);
1358 out:
1359 return ret;
1360 }
1361
1362 static int __devexit tmio_mmc_remove(struct platform_device *dev)
1363 {
1364 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1365 struct mmc_host *mmc = platform_get_drvdata(dev);
1366
1367 platform_set_drvdata(dev, NULL);
1368
1369 if (mmc) {
1370 struct tmio_mmc_host *host = mmc_priv(mmc);
1371 mmc_remove_host(mmc);
1372 cancel_delayed_work_sync(&host->delayed_reset_work);
1373 tmio_mmc_release_dma(host);
1374 free_irq(host->irq, host);
1375 if (cell->disable)
1376 cell->disable(dev);
1377 iounmap(host->ctl);
1378 mmc_free_host(mmc);
1379 }
1380
1381 return 0;
1382 }
1383
1384 /* ------------------- device registration ----------------------- */
1385
1386 static struct platform_driver tmio_mmc_driver = {
1387 .driver = {
1388 .name = "tmio-mmc",
1389 .owner = THIS_MODULE,
1390 },
1391 .probe = tmio_mmc_probe,
1392 .remove = __devexit_p(tmio_mmc_remove),
1393 .suspend = tmio_mmc_suspend,
1394 .resume = tmio_mmc_resume,
1395 };
1396
1397
1398 static int __init tmio_mmc_init(void)
1399 {
1400 return platform_driver_register(&tmio_mmc_driver);
1401 }
1402
1403 static void __exit tmio_mmc_exit(void)
1404 {
1405 platform_driver_unregister(&tmio_mmc_driver);
1406 }
1407
1408 module_init(tmio_mmc_init);
1409 module_exit(tmio_mmc_exit);
1410
1411 MODULE_DESCRIPTION("Toshiba TMIO SD/MMC driver");
1412 MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
1413 MODULE_LICENSE("GPL v2");
1414 MODULE_ALIAS("platform:tmio-mmc");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree