drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "atom.h"
  38
  39 /*
  40  * Clear GPU surface registers.
  41  */
  42 void radeon_surface_init(struct radeon_device *rdev)
  43 {
  44         /* FIXME: check this out */
  45         if (rdev->family < CHIP_R600) {
  46                 int i;
  47
  48                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  49                         if (rdev->surface_regs[i].bo)
  50                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
  51                         else
  52                                 radeon_clear_surface_reg(rdev, i);
  53                 }
  54                 /* enable surfaces */
  55                 WREG32(RADEON_SURFACE_CNTL, 0);
  56         }
  57 }
  58
  59 /*
  60  * GPU scratch registers helpers function.
  61  */
  62 void radeon_scratch_init(struct radeon_device *rdev)
  63 {
  64         int i;
  65
  66         /* FIXME: check this out */
  67         if (rdev->family < CHIP_R300) {
  68                 rdev->scratch.num_reg = 5;
  69         } else {
  70                 rdev->scratch.num_reg = 7;
  71         }
  72         for (i = 0; i < rdev->scratch.num_reg; i++) {
  73                 rdev->scratch.free[i] = true;
  74                 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  75         }
  76 }
  77
  78 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  79 {
  80         int i;
  81
  82         for (i = 0; i < rdev->scratch.num_reg; i++) {
  83                 if (rdev->scratch.free[i]) {
  84                         rdev->scratch.free[i] = false;
  85                         *reg = rdev->scratch.reg[i];
  86                         return 0;
  87                 }
  88         }
  89         return -EINVAL;
  90 }
  91
  92 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  93 {
  94         int i;
  95
  96         for (i = 0; i < rdev->scratch.num_reg; i++) {
  97                 if (rdev->scratch.reg[i] == reg) {
  98                         rdev->scratch.free[i] = true;
  99                         return;
 100                 }
 101         }
 102 }
 103
 104 /**
 105  * radeon_vram_location - try to find VRAM location
 106  * @rdev: radeon device structure holding all necessary informations
 107  * @mc: memory controller structure holding memory informations
 108  * @base: base address at which to put VRAM
 109  *
 110  * Function will place try to place VRAM at base address provided
 111  * as parameter (which is so far either PCI aperture address or
 112  * for IGP TOM base address).
 113  *
 114  * If there is not enough space to fit the unvisible VRAM in the 32bits
 115  * address space then we limit the VRAM size to the aperture.
 116  *
 117  * If we are using AGP and if the AGP aperture doesn't allow us to have
 118  * room for all the VRAM than we restrict the VRAM to the PCI aperture
 119  * size and print a warning.
 120  *
 121  * This function will never fails, worst case are limiting VRAM.
 122  *
 123  * Note: GTT start, end, size should be initialized before calling this
 124  * function on AGP platform.
 125  *
 126  * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
 127  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 128  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 129  * not IGP.
 130  *
 131  * Note: we use mc_vram_size as on some board we need to program the mc to
 132  * cover the whole aperture even if VRAM size is inferior to aperture size
 133  * Novell bug 204882 + along with lots of ubuntu ones
 134  *
 135  * Note: when limiting vram it's safe to overwritte real_vram_size because
 136  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 137  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 138  * ones)
 139  *
 140  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 141  * explicitly check for that thought.
 142  *
 143  * FIXME: when reducing VRAM size align new size on power of 2.
 144  */
 145 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 146 {
 147         mc->vram_start = base;
 148         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
 149                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 150                 mc->real_vram_size = mc->aper_size;
 151                 mc->mc_vram_size = mc->aper_size;
 152         }
 153         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 154         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) {
 155                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 156                 mc->real_vram_size = mc->aper_size;
 157                 mc->mc_vram_size = mc->aper_size;
 158         }
 159         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 160         dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
 161                         mc->mc_vram_size >> 20, mc->vram_start,
 162                         mc->vram_end, mc->real_vram_size >> 20);
 163 }
 164
 165 /**
 166  * radeon_gtt_location - try to find GTT location
 167  * @rdev: radeon device structure holding all necessary informations
 168  * @mc: memory controller structure holding memory informations
 169  *
 170  * Function will place try to place GTT before or after VRAM.
 171  *
 172  * If GTT size is bigger than space left then we ajust GTT size.
 173  * Thus function will never fails.
 174  *
 175  * FIXME: when reducing GTT size align new size on power of 2.
 176  */
 177 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 178 {
 179         u64 size_af, size_bf;
 180
 181         size_af = 0xFFFFFFFF - mc->vram_end;
 182         size_bf = mc->vram_start;
 183         if (size_bf > size_af) {
 184                 if (mc->gtt_size > size_bf) {
 185                         dev_warn(rdev->dev, "limiting GTT\n");
 186                         mc->gtt_size = size_bf;
 187                 }
 188                 mc->gtt_start = mc->vram_start - mc->gtt_size;
 189         } else {
 190                 if (mc->gtt_size > size_af) {
 191                         dev_warn(rdev->dev, "limiting GTT\n");
 192                         mc->gtt_size = size_af;
 193                 }
 194                 mc->gtt_start = mc->vram_end + 1;
 195         }
 196         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 197         dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
 198                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 199 }
 200
 201 /*
 202  * GPU helpers function.
 203  */
 204 bool radeon_card_posted(struct radeon_device *rdev)
 205 {
 206         uint32_t reg;
 207
 208         /* first check CRTCs */
 209         if (ASIC_IS_DCE4(rdev)) {
 210                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 211                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
 212                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 213                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
 214                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 215                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 216                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 217                         return true;
 218         } else if (ASIC_IS_AVIVO(rdev)) {
 219                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 220                       RREG32(AVIVO_D2CRTC_CONTROL);
 221                 if (reg & AVIVO_CRTC_EN) {
 222                         return true;
 223                 }
 224         } else {
 225                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 226                       RREG32(RADEON_CRTC2_GEN_CNTL);
 227                 if (reg & RADEON_CRTC_EN) {
 228                         return true;
 229                 }
 230         }
 231
 232         /* then check MEM_SIZE, in case the crtcs are off */
 233         if (rdev->family >= CHIP_R600)
 234                 reg = RREG32(R600_CONFIG_MEMSIZE);
 235         else
 236                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 237
 238         if (reg)
 239                 return true;
 240
 241         return false;
 242
 243 }
 244
 245 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 246 {
 247         fixed20_12 a;
 248         u32 sclk, mclk;
 249
 250         if (rdev->flags & RADEON_IS_IGP) {
 251                 sclk = radeon_get_engine_clock(rdev);
 252                 mclk = rdev->clock.default_mclk;
 253
 254                 a.full = rfixed_const(100);
 255                 rdev->pm.sclk.full = rfixed_const(sclk);
 256                 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 257                 rdev->pm.mclk.full = rfixed_const(mclk);
 258                 rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a);
 259
 260                 a.full = rfixed_const(16);
 261                 /* core_bandwidth = sclk(Mhz) * 16 */
 262                 rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
 263         } else {
 264                 sclk = radeon_get_engine_clock(rdev);
 265                 mclk = radeon_get_memory_clock(rdev);
 266
 267                 a.full = rfixed_const(100);
 268                 rdev->pm.sclk.full = rfixed_const(sclk);
 269                 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 270                 rdev->pm.mclk.full = rfixed_const(mclk);
 271                 rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a);
 272         }
 273 }
 274
 275 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 276 {
 277         if (radeon_card_posted(rdev))
 278                 return true;
 279
 280         if (rdev->bios) {
 281                 DRM_INFO("GPU not posted. posting now...\n");
 282                 if (rdev->is_atom_bios)
 283                         atom_asic_init(rdev->mode_info.atom_context);
 284                 else
 285                         radeon_combios_asic_init(rdev->ddev);
 286                 return true;
 287         } else {
 288                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 289                 return false;
 290         }
 291 }
 292
 293 int radeon_dummy_page_init(struct radeon_device *rdev)
 294 {
 295         if (rdev->dummy_page.page)
 296                 return 0;
 297         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 298         if (rdev->dummy_page.page == NULL)
 299                 return -ENOMEM;
 300         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 301                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 302         if (!rdev->dummy_page.addr) {
 303                 __free_page(rdev->dummy_page.page);
 304                 rdev->dummy_page.page = NULL;
 305                 return -ENOMEM;
 306         }
 307         return 0;
 308 }
 309
 310 void radeon_dummy_page_fini(struct radeon_device *rdev)
 311 {
 312         if (rdev->dummy_page.page == NULL)
 313                 return;
 314         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 315                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 316         __free_page(rdev->dummy_page.page);
 317         rdev->dummy_page.page = NULL;
 318 }
 319
 320
 321 /* ATOM accessor methods */
 322 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 323 {
 324         struct radeon_device *rdev = info->dev->dev_private;
 325         uint32_t r;
 326
 327         r = rdev->pll_rreg(rdev, reg);
 328         return r;
 329 }
 330
 331 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 332 {
 333         struct radeon_device *rdev = info->dev->dev_private;
 334
 335         rdev->pll_wreg(rdev, reg, val);
 336 }
 337
 338 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 339 {
 340         struct radeon_device *rdev = info->dev->dev_private;
 341         uint32_t r;
 342
 343         r = rdev->mc_rreg(rdev, reg);
 344         return r;
 345 }
 346
 347 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 348 {
 349         struct radeon_device *rdev = info->dev->dev_private;
 350
 351         rdev->mc_wreg(rdev, reg, val);
 352 }
 353
 354 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 355 {
 356         struct radeon_device *rdev = info->dev->dev_private;
 357
 358         WREG32(reg*4, val);
 359 }
 360
 361 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 362 {
 363         struct radeon_device *rdev = info->dev->dev_private;
 364         uint32_t r;
 365
 366         r = RREG32(reg*4);
 367         return r;
 368 }
 369
 370 int radeon_atombios_init(struct radeon_device *rdev)
 371 {
 372         struct card_info *atom_card_info =
 373             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 374
 375         if (!atom_card_info)
 376                 return -ENOMEM;
 377
 378         rdev->mode_info.atom_card_info = atom_card_info;
 379         atom_card_info->dev = rdev->ddev;
 380         atom_card_info->reg_read = cail_reg_read;
 381         atom_card_info->reg_write = cail_reg_write;
 382         atom_card_info->mc_read = cail_mc_read;
 383         atom_card_info->mc_write = cail_mc_write;
 384         atom_card_info->pll_read = cail_pll_read;
 385         atom_card_info->pll_write = cail_pll_write;
 386
 387         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 388         mutex_init(&rdev->mode_info.atom_context->mutex);
 389         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 390         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 391         return 0;
 392 }
 393
 394 void radeon_atombios_fini(struct radeon_device *rdev)
 395 {
 396         if (rdev->mode_info.atom_context) {
 397                 kfree(rdev->mode_info.atom_context->scratch);
 398                 kfree(rdev->mode_info.atom_context);
 399         }
 400         kfree(rdev->mode_info.atom_card_info);
 401 }
 402
 403 int radeon_combios_init(struct radeon_device *rdev)
 404 {
 405         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 406         return 0;
 407 }
 408
 409 void radeon_combios_fini(struct radeon_device *rdev)
 410 {
 411 }
 412
 413 /* if we get transitioned to only one device, tak VGA back */
 414 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 415 {
 416         struct radeon_device *rdev = cookie;
 417         radeon_vga_set_state(rdev, state);
 418         if (state)
 419                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 420                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 421         else
 422                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 423 }
 424
 425 void radeon_check_arguments(struct radeon_device *rdev)
 426 {
 427         /* vramlimit must be a power of two */
 428         switch (radeon_vram_limit) {
 429         case 0:
 430         case 4:
 431         case 8:
 432         case 16:
 433         case 32:
 434         case 64:
 435         case 128:
 436         case 256:
 437         case 512:
 438         case 1024:
 439         case 2048:
 440         case 4096:
 441                 break;
 442         default:
 443                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
 444                                 radeon_vram_limit);
 445                 radeon_vram_limit = 0;
 446                 break;
 447         }
 448         radeon_vram_limit = radeon_vram_limit << 20;
 449         /* gtt size must be power of two and greater or equal to 32M */
 450         switch (radeon_gart_size) {
 451         case 4:
 452         case 8:
 453         case 16:
 454                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
 455                                 radeon_gart_size);
 456                 radeon_gart_size = 512;
 457                 break;
 458         case 32:
 459         case 64:
 460         case 128:
 461         case 256:
 462         case 512:
 463         case 1024:
 464         case 2048:
 465         case 4096:
 466                 break;
 467         default:
 468                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
 469                                 radeon_gart_size);
 470                 radeon_gart_size = 512;
 471                 break;
 472         }
 473         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 474         /* AGP mode can only be -1, 1, 2, 4, 8 */
 475         switch (radeon_agpmode) {
 476         case -1:
 477         case 0:
 478         case 1:
 479         case 2:
 480         case 4:
 481         case 8:
 482                 break;
 483         default:
 484                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
 485                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
 486                 radeon_agpmode = 0;
 487                 break;
 488         }
 489 }
 490
 491 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 492 {
 493         struct drm_device *dev = pci_get_drvdata(pdev);
 494         struct radeon_device *rdev = dev->dev_private;
 495         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 496         if (state == VGA_SWITCHEROO_ON) {
 497                 printk(KERN_INFO "radeon: switched on\n");
 498                 /* don't suspend or resume card normally */
 499                 rdev->powered_down = false;
 500                 radeon_resume_kms(dev);
 501         } else {
 502                 printk(KERN_INFO "radeon: switched off\n");
 503                 radeon_suspend_kms(dev, pmm);
 504                 /* don't suspend or resume card normally */
 505                 rdev->powered_down = true;
 506         }
 507 }
 508
 509 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
 510 {
 511         struct drm_device *dev = pci_get_drvdata(pdev);
 512         bool can_switch;
 513
 514         spin_lock(&dev->count_lock);
 515         can_switch = (dev->open_count == 0);
 516         spin_unlock(&dev->count_lock);
 517         return can_switch;
 518 }
 519
 520
 521 int radeon_device_init(struct radeon_device *rdev,
 522                        struct drm_device *ddev,
 523                        struct pci_dev *pdev,
 524                        uint32_t flags)
 525 {
 526         int r;
 527         int dma_bits;
 528
 529         DRM_INFO("radeon: Initializing kernel modesetting.\n");
 530         rdev->shutdown = false;
 531         rdev->dev = &pdev->dev;
 532         rdev->ddev = ddev;
 533         rdev->pdev = pdev;
 534         rdev->flags = flags;
 535         rdev->family = flags & RADEON_FAMILY_MASK;
 536         rdev->is_atom_bios = false;
 537         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 538         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 539         rdev->gpu_lockup = false;
 540         rdev->accel_working = false;
 541         /* mutex initialization are all done here so we
 542          * can recall function without having locking issues */
 543         mutex_init(&rdev->cs_mutex);
 544         mutex_init(&rdev->ib_pool.mutex);
 545         mutex_init(&rdev->cp.mutex);
 546         mutex_init(&rdev->dc_hw_i2c_mutex);
 547         if (rdev->family >= CHIP_R600)
 548                 spin_lock_init(&rdev->ih.lock);
 549         mutex_init(&rdev->gem.mutex);
 550         mutex_init(&rdev->pm.mutex);
 551         rwlock_init(&rdev->fence_drv.lock);
 552         INIT_LIST_HEAD(&rdev->gem.objects);
 553         init_waitqueue_head(&rdev->irq.vblank_queue);
 554
 555         /* setup workqueue */
 556         rdev->wq = create_workqueue("radeon");
 557         if (rdev->wq == NULL)
 558                 return -ENOMEM;
 559
 560         /* Set asic functions */
 561         r = radeon_asic_init(rdev);
 562         if (r)
 563                 return r;
 564         radeon_check_arguments(rdev);
 565
 566         /* all of the newer IGP chips have an internal gart
 567          * However some rs4xx report as AGP, so remove that here.
 568          */
 569         if ((rdev->family >= CHIP_RS400) &&
 570             (rdev->flags & RADEON_IS_IGP)) {
 571                 rdev->flags &= ~RADEON_IS_AGP;
 572         }
 573
 574         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 575                 radeon_agp_disable(rdev);
 576         }
 577
 578         /* set DMA mask + need_dma32 flags.
 579          * PCIE - can handle 40-bits.
 580          * IGP - can handle 40-bits (in theory)
 581          * AGP - generally dma32 is safest
 582          * PCI - only dma32
 583          */
 584         rdev->need_dma32 = false;
 585         if (rdev->flags & RADEON_IS_AGP)
 586                 rdev->need_dma32 = true;
 587         if (rdev->flags & RADEON_IS_PCI)
 588                 rdev->need_dma32 = true;
 589
 590         dma_bits = rdev->need_dma32 ? 32 : 40;
 591         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 592         if (r) {
 593                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 594         }
 595
 596         /* Registers mapping */
 597         /* TODO: block userspace mapping of io register */
 598         rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
 599         rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
 600         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 601         if (rdev->rmmio == NULL) {
 602                 return -ENOMEM;
 603         }
 604         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 605         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 606
 607         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
 608         /* this will fail for cards that aren't VGA class devices, just
 609          * ignore it */
 610         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 611         vga_switcheroo_register_client(rdev->pdev,
 612                                        radeon_switcheroo_set_state,
 613                                        radeon_switcheroo_can_switch);
 614
 615         r = radeon_init(rdev);
 616         if (r)
 617                 return r;
 618
 619         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
 620                 /* Acceleration not working on AGP card try again
 621                  * with fallback to PCI or PCIE GART
 622                  */
 623                 radeon_gpu_reset(rdev);
 624                 radeon_fini(rdev);
 625                 radeon_agp_disable(rdev);
 626                 r = radeon_init(rdev);
 627                 if (r)
 628                         return r;
 629         }
 630         if (radeon_testing) {
 631                 radeon_test_moves(rdev);
 632         }
 633         if (radeon_benchmarking) {
 634                 radeon_benchmark(rdev);
 635         }
 636         return 0;
 637 }
 638
 639 void radeon_device_fini(struct radeon_device *rdev)
 640 {
 641         DRM_INFO("radeon: finishing device.\n");
 642         rdev->shutdown = true;
 643         radeon_fini(rdev);
 644         destroy_workqueue(rdev->wq);
 645         vga_switcheroo_unregister_client(rdev->pdev);
 646         vga_client_register(rdev->pdev, NULL, NULL, NULL);
 647         iounmap(rdev->rmmio);
 648         rdev->rmmio = NULL;
 649 }
 650
 651
 652 /*
 653  * Suspend & resume.
 654  */
 655 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 656 {
 657         struct radeon_device *rdev;
 658         struct drm_crtc *crtc;
 659         int r;
 660
 661         if (dev == NULL || dev->dev_private == NULL) {
 662                 return -ENODEV;
 663         }
 664         if (state.event == PM_EVENT_PRETHAW) {
 665                 return 0;
 666         }
 667         rdev = dev->dev_private;
 668
 669         if (rdev->powered_down)
 670                 return 0;
 671         /* unpin the front buffers */
 672         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 673                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
 674                 struct radeon_bo *robj;
 675
 676                 if (rfb == NULL || rfb->obj == NULL) {
 677                         continue;
 678                 }
 679                 robj = rfb->obj->driver_private;
 680                 if (robj != rdev->fbdev_rbo) {
 681                         r = radeon_bo_reserve(robj, false);
 682                         if (unlikely(r == 0)) {
 683                                 radeon_bo_unpin(robj);
 684                                 radeon_bo_unreserve(robj);
 685                         }
 686                 }
 687         }
 688         /* evict vram memory */
 689         radeon_bo_evict_vram(rdev);
 690         /* wait for gpu to finish processing current batch */
 691         radeon_fence_wait_last(rdev);
 692
 693         radeon_save_bios_scratch_regs(rdev);
 694
 695         radeon_suspend(rdev);
 696         radeon_hpd_fini(rdev);
 697         /* evict remaining vram memory */
 698         radeon_bo_evict_vram(rdev);
 699
 700         pci_save_state(dev->pdev);
 701         if (state.event == PM_EVENT_SUSPEND) {
 702                 /* Shut down the device */
 703                 pci_disable_device(dev->pdev);
 704                 pci_set_power_state(dev->pdev, PCI_D3hot);
 705         }
 706         acquire_console_sem();
 707         fb_set_suspend(rdev->fbdev_info, 1);
 708         release_console_sem();
 709         return 0;
 710 }
 711
 712 int radeon_resume_kms(struct drm_device *dev)
 713 {
 714         struct radeon_device *rdev = dev->dev_private;
 715
 716         if (rdev->powered_down)
 717                 return 0;
 718
 719         acquire_console_sem();
 720         pci_set_power_state(dev->pdev, PCI_D0);
 721         pci_restore_state(dev->pdev);
 722         if (pci_enable_device(dev->pdev)) {
 723                 release_console_sem();
 724                 return -1;
 725         }
 726         pci_set_master(dev->pdev);
 727         /* resume AGP if in use */
 728         radeon_agp_resume(rdev);
 729         radeon_resume(rdev);
 730         radeon_restore_bios_scratch_regs(rdev);
 731         fb_set_suspend(rdev->fbdev_info, 0);
 732         release_console_sem();
 733
 734         /* reset hpd state */
 735         radeon_hpd_init(rdev);
 736         /* blat the mode back in */
 737         drm_helper_resume_force_mode(dev);
 738         return 0;
 739 }
 740
 741
 742 /*
 743  * Debugfs
 744  */
 745 struct radeon_debugfs {
 746         struct drm_info_list    *files;
 747         unsigned                num_files;
 748 };
 749 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
 750 static unsigned _radeon_debugfs_count = 0;
 751
 752 int radeon_debugfs_add_files(struct radeon_device *rdev,
 753                              struct drm_info_list *files,
 754                              unsigned nfiles)
 755 {
 756         unsigned i;
 757
 758         for (i = 0; i < _radeon_debugfs_count; i++) {
 759                 if (_radeon_debugfs[i].files == files) {
 760                         /* Already registered */
 761                         return 0;
 762                 }
 763         }
 764         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
 765                 DRM_ERROR("Reached maximum number of debugfs files.\n");
 766                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
 767                 return -EINVAL;
 768         }
 769         _radeon_debugfs[_radeon_debugfs_count].files = files;
 770         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
 771         _radeon_debugfs_count++;
 772 #if defined(CONFIG_DEBUG_FS)
 773         drm_debugfs_create_files(files, nfiles,
 774                                  rdev->ddev->control->debugfs_root,
 775                                  rdev->ddev->control);
 776         drm_debugfs_create_files(files, nfiles,
 777                                  rdev->ddev->primary->debugfs_root,
 778                                  rdev->ddev->primary);
 779 #endif
 780         return 0;
 781 }
 782
 783 #if defined(CONFIG_DEBUG_FS)
 784 int radeon_debugfs_init(struct drm_minor *minor)
 785 {
 786         return 0;
 787 }
 788
 789 void radeon_debugfs_cleanup(struct drm_minor *minor)
 790 {
 791         unsigned i;
 792
 793         for (i = 0; i < _radeon_debugfs_count; i++) {
 794                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
 795                                          _radeon_debugfs[i].num_files, minor);
 796         }
 797 }
 798 #endif