2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
31 #include "radeon_reg.h"
33 #include "radeon_asic.h"
37 #include "r420_reg_safe.h"
39 static void r420_set_reg_safe(struct radeon_device
*rdev
)
41 rdev
->config
.r300
.reg_safe_bm
= r420_reg_safe_bm
;
42 rdev
->config
.r300
.reg_safe_bm_size
= ARRAY_SIZE(r420_reg_safe_bm
);
45 void r420_pipes_init(struct radeon_device
*rdev
)
48 unsigned gb_pipe_select
;
51 /* GA_ENHANCE workaround TCL deadlock issue */
52 WREG32(R300_GA_ENHANCE
, R300_GA_DEADLOCK_CNTL
| R300_GA_FASTSYNC_CNTL
|
54 /* add idle wait as per freedesktop.org bug 24041 */
55 if (r100_gui_wait_for_idle(rdev
)) {
56 printk(KERN_WARNING
"Failed to wait GUI idle while "
57 "programming pipes. Bad things might happen.\n");
59 /* get max number of pipes */
60 gb_pipe_select
= RREG32(0x402C);
61 num_pipes
= ((gb_pipe_select
>> 12) & 3) + 1;
62 rdev
->num_gb_pipes
= num_pipes
;
81 WREG32(R500_SU_REG_DEST
, (1 << num_pipes
) - 1);
82 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
83 tmp
|= R300_TILE_SIZE_16
| R300_ENABLE_TILING
;
84 WREG32(R300_GB_TILE_CONFIG
, tmp
);
85 if (r100_gui_wait_for_idle(rdev
)) {
86 printk(KERN_WARNING
"Failed to wait GUI idle while "
87 "programming pipes. Bad things might happen.\n");
90 tmp
= RREG32(R300_DST_PIPE_CONFIG
);
91 WREG32(R300_DST_PIPE_CONFIG
, tmp
| R300_PIPE_AUTO_CONFIG
);
93 WREG32(R300_RB2D_DSTCACHE_MODE
,
94 RREG32(R300_RB2D_DSTCACHE_MODE
) |
95 R300_DC_AUTOFLUSH_ENABLE
|
96 R300_DC_DC_DISABLE_IGNORE_PE
);
98 if (r100_gui_wait_for_idle(rdev
)) {
99 printk(KERN_WARNING
"Failed to wait GUI idle while "
100 "programming pipes. Bad things might happen.\n");
103 if (rdev
->family
== CHIP_RV530
) {
104 tmp
= RREG32(RV530_GB_PIPE_SELECT2
);
106 rdev
->num_z_pipes
= 2;
108 rdev
->num_z_pipes
= 1;
110 rdev
->num_z_pipes
= 1;
112 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
113 rdev
->num_gb_pipes
, rdev
->num_z_pipes
);
116 u32
r420_mc_rreg(struct radeon_device
*rdev
, u32 reg
)
120 WREG32(R_0001F8_MC_IND_INDEX
, S_0001F8_MC_IND_ADDR(reg
));
121 r
= RREG32(R_0001FC_MC_IND_DATA
);
125 void r420_mc_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
127 WREG32(R_0001F8_MC_IND_INDEX
, S_0001F8_MC_IND_ADDR(reg
) |
128 S_0001F8_MC_IND_WR_EN(1));
129 WREG32(R_0001FC_MC_IND_DATA
, v
);
132 static void r420_debugfs(struct radeon_device
*rdev
)
134 if (r100_debugfs_rbbm_init(rdev
)) {
135 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
137 if (r420_debugfs_pipes_info_init(rdev
)) {
138 DRM_ERROR("Failed to register debugfs file for pipes !\n");
142 static void r420_clock_resume(struct radeon_device
*rdev
)
146 if (radeon_dynclks
!= -1 && radeon_dynclks
)
147 radeon_atom_set_clock_gating(rdev
, 1);
148 sclk_cntl
= RREG32_PLL(R_00000D_SCLK_CNTL
);
149 sclk_cntl
|= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
150 if (rdev
->family
== CHIP_R420
)
151 sclk_cntl
|= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
152 WREG32_PLL(R_00000D_SCLK_CNTL
, sclk_cntl
);
155 static void r420_cp_errata_init(struct radeon_device
*rdev
)
157 /* RV410 and R420 can lock up if CP DMA to host memory happens
158 * while the 2D engine is busy.
160 * The proper workaround is to queue a RESYNC at the beginning
161 * of the CP init, apparently.
163 radeon_scratch_get(rdev
, &rdev
->config
.r300
.resync_scratch
);
164 radeon_ring_lock(rdev
, 8);
165 radeon_ring_write(rdev
, PACKET0(R300_CP_RESYNC_ADDR
, 1));
166 radeon_ring_write(rdev
, rdev
->config
.r300
.resync_scratch
);
167 radeon_ring_write(rdev
, 0xDEADBEEF);
168 radeon_ring_unlock_commit(rdev
);
171 static void r420_cp_errata_fini(struct radeon_device
*rdev
)
173 /* Catch the RESYNC we dispatched all the way back,
174 * at the very beginning of the CP init.
176 radeon_ring_lock(rdev
, 8);
177 radeon_ring_write(rdev
, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
178 radeon_ring_write(rdev
, R300_RB3D_DC_FINISH
);
179 radeon_ring_unlock_commit(rdev
);
180 radeon_scratch_free(rdev
, rdev
->config
.r300
.resync_scratch
);
183 static int r420_startup(struct radeon_device
*rdev
)
187 /* set common regs */
188 r100_set_common_regs(rdev
);
190 r300_mc_program(rdev
);
192 r420_clock_resume(rdev
);
193 /* Initialize GART (initialize after TTM so we can allocate
194 * memory through TTM but finalize after TTM) */
195 if (rdev
->flags
& RADEON_IS_PCIE
) {
196 r
= rv370_pcie_gart_enable(rdev
);
200 if (rdev
->flags
& RADEON_IS_PCI
) {
201 r
= r100_pci_gart_enable(rdev
);
205 r420_pipes_init(rdev
);
208 rdev
->config
.r300
.hdp_cntl
= RREG32(RADEON_HOST_PATH_CNTL
);
210 r
= r100_cp_init(rdev
, 1024 * 1024);
212 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
215 r420_cp_errata_init(rdev
);
216 r
= r100_wb_init(rdev
);
218 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
220 r
= r100_ib_init(rdev
);
222 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
228 int r420_resume(struct radeon_device
*rdev
)
230 /* Make sur GART are not working */
231 if (rdev
->flags
& RADEON_IS_PCIE
)
232 rv370_pcie_gart_disable(rdev
);
233 if (rdev
->flags
& RADEON_IS_PCI
)
234 r100_pci_gart_disable(rdev
);
235 /* Resume clock before doing reset */
236 r420_clock_resume(rdev
);
237 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
238 if (radeon_gpu_reset(rdev
)) {
239 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
240 RREG32(R_000E40_RBBM_STATUS
),
241 RREG32(R_0007C0_CP_STAT
));
243 /* check if cards are posted or not */
244 if (rdev
->is_atom_bios
) {
245 atom_asic_init(rdev
->mode_info
.atom_context
);
247 radeon_combios_asic_init(rdev
->ddev
);
249 /* Resume clock after posting */
250 r420_clock_resume(rdev
);
251 /* Initialize surface registers */
252 radeon_surface_init(rdev
);
253 return r420_startup(rdev
);
256 int r420_suspend(struct radeon_device
*rdev
)
258 r420_cp_errata_fini(rdev
);
259 r100_cp_disable(rdev
);
260 r100_wb_disable(rdev
);
261 r100_irq_disable(rdev
);
262 if (rdev
->flags
& RADEON_IS_PCIE
)
263 rv370_pcie_gart_disable(rdev
);
264 if (rdev
->flags
& RADEON_IS_PCI
)
265 r100_pci_gart_disable(rdev
);
269 void r420_fini(struct radeon_device
*rdev
)
271 radeon_pm_fini(rdev
);
275 radeon_gem_fini(rdev
);
276 if (rdev
->flags
& RADEON_IS_PCIE
)
277 rv370_pcie_gart_fini(rdev
);
278 if (rdev
->flags
& RADEON_IS_PCI
)
279 r100_pci_gart_fini(rdev
);
280 radeon_agp_fini(rdev
);
281 radeon_irq_kms_fini(rdev
);
282 radeon_fence_driver_fini(rdev
);
283 radeon_bo_fini(rdev
);
284 if (rdev
->is_atom_bios
) {
285 radeon_atombios_fini(rdev
);
287 radeon_combios_fini(rdev
);
293 int r420_init(struct radeon_device
*rdev
)
297 /* Initialize scratch registers */
298 radeon_scratch_init(rdev
);
299 /* Initialize surface registers */
300 radeon_surface_init(rdev
);
301 /* TODO: disable VGA need to use VGA request */
303 if (!radeon_get_bios(rdev
)) {
304 if (ASIC_IS_AVIVO(rdev
))
307 if (rdev
->is_atom_bios
) {
308 r
= radeon_atombios_init(rdev
);
313 r
= radeon_combios_init(rdev
);
318 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
319 if (radeon_gpu_reset(rdev
)) {
321 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
322 RREG32(R_000E40_RBBM_STATUS
),
323 RREG32(R_0007C0_CP_STAT
));
325 /* check if cards are posted or not */
326 if (radeon_boot_test_post_card(rdev
) == false)
329 /* Initialize clocks */
330 radeon_get_clock_info(rdev
->ddev
);
331 /* Initialize power management */
332 radeon_pm_init(rdev
);
334 if (rdev
->flags
& RADEON_IS_AGP
) {
335 r
= radeon_agp_init(rdev
);
337 radeon_agp_disable(rdev
);
340 /* initialize memory controller */
344 r
= radeon_fence_driver_init(rdev
);
348 r
= radeon_irq_kms_init(rdev
);
353 r
= radeon_bo_init(rdev
);
357 if (rdev
->family
== CHIP_R420
)
358 r100_enable_bm(rdev
);
360 if (rdev
->flags
& RADEON_IS_PCIE
) {
361 r
= rv370_pcie_gart_init(rdev
);
365 if (rdev
->flags
& RADEON_IS_PCI
) {
366 r
= r100_pci_gart_init(rdev
);
370 r420_set_reg_safe(rdev
);
371 rdev
->accel_working
= true;
372 r
= r420_startup(rdev
);
374 /* Somethings want wront with the accel init stop accel */
375 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
379 radeon_irq_kms_fini(rdev
);
380 if (rdev
->flags
& RADEON_IS_PCIE
)
381 rv370_pcie_gart_fini(rdev
);
382 if (rdev
->flags
& RADEON_IS_PCI
)
383 r100_pci_gart_fini(rdev
);
384 radeon_agp_fini(rdev
);
385 rdev
->accel_working
= false;
393 #if defined(CONFIG_DEBUG_FS)
394 static int r420_debugfs_pipes_info(struct seq_file
*m
, void *data
)
396 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
397 struct drm_device
*dev
= node
->minor
->dev
;
398 struct radeon_device
*rdev
= dev
->dev_private
;
401 tmp
= RREG32(R400_GB_PIPE_SELECT
);
402 seq_printf(m
, "GB_PIPE_SELECT 0x%08x\n", tmp
);
403 tmp
= RREG32(R300_GB_TILE_CONFIG
);
404 seq_printf(m
, "GB_TILE_CONFIG 0x%08x\n", tmp
);
405 tmp
= RREG32(R300_DST_PIPE_CONFIG
);
406 seq_printf(m
, "DST_PIPE_CONFIG 0x%08x\n", tmp
);
410 static struct drm_info_list r420_pipes_info_list
[] = {
411 {"r420_pipes_info", r420_debugfs_pipes_info
, 0, NULL
},
415 int r420_debugfs_pipes_info_init(struct radeon_device
*rdev
)
417 #if defined(CONFIG_DEBUG_FS)
418 return radeon_debugfs_add_files(rdev
, r420_pipes_info_list
, 1);