idle governor: Avoid lock acquisition to read pm_qos before entering idle
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / ia64 / kernel / mca.c
blob1753f6a30d55e6d66c5e3198a9b271601c89a39e
1 /*
2 * File: mca.c
3 * Purpose: Generic MCA handling layer
5 * Copyright (C) 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Copyright (C) 2002 Dell Inc.
9 * Copyright (C) Matt Domsch <Matt_Domsch@dell.com>
11 * Copyright (C) 2002 Intel
12 * Copyright (C) Jenna Hall <jenna.s.hall@intel.com>
14 * Copyright (C) 2001 Intel
15 * Copyright (C) Fred Lewis <frederick.v.lewis@intel.com>
17 * Copyright (C) 2000 Intel
18 * Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com>
20 * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc.
21 * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
23 * Copyright (C) 2006 FUJITSU LIMITED
24 * Copyright (C) Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
26 * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
27 * Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
28 * added min save state dump, added INIT handler.
30 * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com>
31 * Added setup of CMCI and CPEI IRQs, logging of corrected platform
32 * errors, completed code for logging of corrected & uncorrected
33 * machine check errors, and updated for conformance with Nov. 2000
34 * revision of the SAL 3.0 spec.
36 * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com>
37 * Aligned MCA stack to 16 bytes, added platform vs. CPU error flag,
38 * set SAL default return values, changed error record structure to
39 * linked list, added init call to sal_get_state_info_size().
41 * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com>
42 * GUID cleanups.
44 * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com>
45 * Added INIT backtrace support.
47 * 2003-12-08 Keith Owens <kaos@sgi.com>
48 * smp_call_function() must not be called from interrupt context
49 * (can deadlock on tasklist_lock).
50 * Use keventd to call smp_call_function().
52 * 2004-02-01 Keith Owens <kaos@sgi.com>
53 * Avoid deadlock when using printk() for MCA and INIT records.
54 * Delete all record printing code, moved to salinfo_decode in user
55 * space. Mark variables and functions static where possible.
56 * Delete dead variables and functions. Reorder to remove the need
57 * for forward declarations and to consolidate related code.
59 * 2005-08-12 Keith Owens <kaos@sgi.com>
60 * Convert MCA/INIT handlers to use per event stacks and SAL/OS
61 * state.
63 * 2005-10-07 Keith Owens <kaos@sgi.com>
64 * Add notify_die() hooks.
66 * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
67 * Add printing support for MCA/INIT.
69 * 2007-04-27 Russ Anderson <rja@sgi.com>
70 * Support multiple cpus going through OS_MCA in the same event.
72 #include <linux/jiffies.h>
73 #include <linux/types.h>
74 #include <linux/init.h>
75 #include <linux/sched.h>
76 #include <linux/interrupt.h>
77 #include <linux/irq.h>
78 #include <linux/bootmem.h>
79 #include <linux/acpi.h>
80 #include <linux/timer.h>
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/smp.h>
84 #include <linux/workqueue.h>
85 #include <linux/cpumask.h>
86 #include <linux/kdebug.h>
87 #include <linux/cpu.h>
88 #include <linux/gfp.h>
90 #include <asm/delay.h>
91 #include <asm/machvec.h>
92 #include <asm/meminit.h>
93 #include <asm/page.h>
94 #include <asm/ptrace.h>
95 #include <asm/system.h>
96 #include <asm/sal.h>
97 #include <asm/mca.h>
98 #include <asm/kexec.h>
100 #include <asm/irq.h>
101 #include <asm/hw_irq.h>
102 #include <asm/tlb.h>
104 #include "mca_drv.h"
105 #include "entry.h"
107 #if defined(IA64_MCA_DEBUG_INFO)
108 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
109 #else
110 # define IA64_MCA_DEBUG(fmt...)
111 #endif
113 #define NOTIFY_INIT(event, regs, arg, spin) \
114 do { \
115 if ((notify_die((event), "INIT", (regs), (arg), 0, 0) \
116 == NOTIFY_STOP) && ((spin) == 1)) \
117 ia64_mca_spin(__func__); \
118 } while (0)
120 #define NOTIFY_MCA(event, regs, arg, spin) \
121 do { \
122 if ((notify_die((event), "MCA", (regs), (arg), 0, 0) \
123 == NOTIFY_STOP) && ((spin) == 1)) \
124 ia64_mca_spin(__func__); \
125 } while (0)
127 /* Used by mca_asm.S */
128 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
129 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
130 DEFINE_PER_CPU(u64, ia64_mca_pal_pte); /* PTE to map PAL code */
131 DEFINE_PER_CPU(u64, ia64_mca_pal_base); /* vaddr PAL code granule */
132 DEFINE_PER_CPU(u64, ia64_mca_tr_reload); /* Flag for TR reload */
134 unsigned long __per_cpu_mca[NR_CPUS];
136 /* In mca_asm.S */
137 extern void ia64_os_init_dispatch_monarch (void);
138 extern void ia64_os_init_dispatch_slave (void);
140 static int monarch_cpu = -1;
142 static ia64_mc_info_t ia64_mc_info;
144 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
145 #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */
146 #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */
147 #define CPE_HISTORY_LENGTH 5
148 #define CMC_HISTORY_LENGTH 5
150 #ifdef CONFIG_ACPI
151 static struct timer_list cpe_poll_timer;
152 #endif
153 static struct timer_list cmc_poll_timer;
155 * This variable tells whether we are currently in polling mode.
156 * Start with this in the wrong state so we won't play w/ timers
157 * before the system is ready.
159 static int cmc_polling_enabled = 1;
162 * Clearing this variable prevents CPE polling from getting activated
163 * in mca_late_init. Use it if your system doesn't provide a CPEI,
164 * but encounters problems retrieving CPE logs. This should only be
165 * necessary for debugging.
167 static int cpe_poll_enabled = 1;
169 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
171 static int mca_init __initdata;
174 * limited & delayed printing support for MCA/INIT handler
177 #define mprintk(fmt...) ia64_mca_printk(fmt)
179 #define MLOGBUF_SIZE (512+256*NR_CPUS)
180 #define MLOGBUF_MSGMAX 256
181 static char mlogbuf[MLOGBUF_SIZE];
182 static DEFINE_SPINLOCK(mlogbuf_wlock); /* mca context only */
183 static DEFINE_SPINLOCK(mlogbuf_rlock); /* normal context only */
184 static unsigned long mlogbuf_start;
185 static unsigned long mlogbuf_end;
186 static unsigned int mlogbuf_finished = 0;
187 static unsigned long mlogbuf_timestamp = 0;
189 static int loglevel_save = -1;
190 #define BREAK_LOGLEVEL(__console_loglevel) \
191 oops_in_progress = 1; \
192 if (loglevel_save < 0) \
193 loglevel_save = __console_loglevel; \
194 __console_loglevel = 15;
196 #define RESTORE_LOGLEVEL(__console_loglevel) \
197 if (loglevel_save >= 0) { \
198 __console_loglevel = loglevel_save; \
199 loglevel_save = -1; \
201 mlogbuf_finished = 0; \
202 oops_in_progress = 0;
205 * Push messages into buffer, print them later if not urgent.
207 void ia64_mca_printk(const char *fmt, ...)
209 va_list args;
210 int printed_len;
211 char temp_buf[MLOGBUF_MSGMAX];
212 char *p;
214 va_start(args, fmt);
215 printed_len = vscnprintf(temp_buf, sizeof(temp_buf), fmt, args);
216 va_end(args);
218 /* Copy the output into mlogbuf */
219 if (oops_in_progress) {
220 /* mlogbuf was abandoned, use printk directly instead. */
221 printk(temp_buf);
222 } else {
223 spin_lock(&mlogbuf_wlock);
224 for (p = temp_buf; *p; p++) {
225 unsigned long next = (mlogbuf_end + 1) % MLOGBUF_SIZE;
226 if (next != mlogbuf_start) {
227 mlogbuf[mlogbuf_end] = *p;
228 mlogbuf_end = next;
229 } else {
230 /* buffer full */
231 break;
234 mlogbuf[mlogbuf_end] = '\0';
235 spin_unlock(&mlogbuf_wlock);
238 EXPORT_SYMBOL(ia64_mca_printk);
241 * Print buffered messages.
242 * NOTE: call this after returning normal context. (ex. from salinfod)
244 void ia64_mlogbuf_dump(void)
246 char temp_buf[MLOGBUF_MSGMAX];
247 char *p;
248 unsigned long index;
249 unsigned long flags;
250 unsigned int printed_len;
252 /* Get output from mlogbuf */
253 while (mlogbuf_start != mlogbuf_end) {
254 temp_buf[0] = '\0';
255 p = temp_buf;
256 printed_len = 0;
258 spin_lock_irqsave(&mlogbuf_rlock, flags);
260 index = mlogbuf_start;
261 while (index != mlogbuf_end) {
262 *p = mlogbuf[index];
263 index = (index + 1) % MLOGBUF_SIZE;
264 if (!*p)
265 break;
266 p++;
267 if (++printed_len >= MLOGBUF_MSGMAX - 1)
268 break;
270 *p = '\0';
271 if (temp_buf[0])
272 printk(temp_buf);
273 mlogbuf_start = index;
275 mlogbuf_timestamp = 0;
276 spin_unlock_irqrestore(&mlogbuf_rlock, flags);
279 EXPORT_SYMBOL(ia64_mlogbuf_dump);
282 * Call this if system is going to down or if immediate flushing messages to
283 * console is required. (ex. recovery was failed, crash dump is going to be
284 * invoked, long-wait rendezvous etc.)
285 * NOTE: this should be called from monarch.
287 static void ia64_mlogbuf_finish(int wait)
289 BREAK_LOGLEVEL(console_loglevel);
291 spin_lock_init(&mlogbuf_rlock);
292 ia64_mlogbuf_dump();
293 printk(KERN_EMERG "mlogbuf_finish: printing switched to urgent mode, "
294 "MCA/INIT might be dodgy or fail.\n");
296 if (!wait)
297 return;
299 /* wait for console */
300 printk("Delaying for 5 seconds...\n");
301 udelay(5*1000000);
303 mlogbuf_finished = 1;
307 * Print buffered messages from INIT context.
309 static void ia64_mlogbuf_dump_from_init(void)
311 if (mlogbuf_finished)
312 return;
314 if (mlogbuf_timestamp &&
315 time_before(jiffies, mlogbuf_timestamp + 30 * HZ)) {
316 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT "
317 " and the system seems to be messed up.\n");
318 ia64_mlogbuf_finish(0);
319 return;
322 if (!spin_trylock(&mlogbuf_rlock)) {
323 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT. "
324 "Generated messages other than stack dump will be "
325 "buffered to mlogbuf and will be printed later.\n");
326 printk(KERN_ERR "INIT: If messages would not printed after "
327 "this INIT, wait 30sec and assert INIT again.\n");
328 if (!mlogbuf_timestamp)
329 mlogbuf_timestamp = jiffies;
330 return;
332 spin_unlock(&mlogbuf_rlock);
333 ia64_mlogbuf_dump();
336 static void inline
337 ia64_mca_spin(const char *func)
339 if (monarch_cpu == smp_processor_id())
340 ia64_mlogbuf_finish(0);
341 mprintk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
342 while (1)
343 cpu_relax();
346 * IA64_MCA log support
348 #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */
349 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
351 typedef struct ia64_state_log_s
353 spinlock_t isl_lock;
354 int isl_index;
355 unsigned long isl_count;
356 ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
357 } ia64_state_log_t;
359 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
361 #define IA64_LOG_ALLOCATE(it, size) \
362 {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
363 (ia64_err_rec_t *)alloc_bootmem(size); \
364 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
365 (ia64_err_rec_t *)alloc_bootmem(size);}
366 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
367 #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
368 #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
369 #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index
370 #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index
371 #define IA64_LOG_INDEX_INC(it) \
372 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
373 ia64_state_log[it].isl_count++;}
374 #define IA64_LOG_INDEX_DEC(it) \
375 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
376 #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
377 #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
378 #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count
381 * ia64_log_init
382 * Reset the OS ia64 log buffer
383 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
384 * Outputs : None
386 static void __init
387 ia64_log_init(int sal_info_type)
389 u64 max_size = 0;
391 IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
392 IA64_LOG_LOCK_INIT(sal_info_type);
394 // SAL will tell us the maximum size of any error record of this type
395 max_size = ia64_sal_get_state_info_size(sal_info_type);
396 if (!max_size)
397 /* alloc_bootmem() doesn't like zero-sized allocations! */
398 return;
400 // set up OS data structures to hold error info
401 IA64_LOG_ALLOCATE(sal_info_type, max_size);
402 memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
403 memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
407 * ia64_log_get
409 * Get the current MCA log from SAL and copy it into the OS log buffer.
411 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
412 * irq_safe whether you can use printk at this point
413 * Outputs : size (total record length)
414 * *buffer (ptr to error record)
417 static u64
418 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
420 sal_log_record_header_t *log_buffer;
421 u64 total_len = 0;
422 unsigned long s;
424 IA64_LOG_LOCK(sal_info_type);
426 /* Get the process state information */
427 log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
429 total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
431 if (total_len) {
432 IA64_LOG_INDEX_INC(sal_info_type);
433 IA64_LOG_UNLOCK(sal_info_type);
434 if (irq_safe) {
435 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. Record length = %ld\n",
436 __func__, sal_info_type, total_len);
438 *buffer = (u8 *) log_buffer;
439 return total_len;
440 } else {
441 IA64_LOG_UNLOCK(sal_info_type);
442 return 0;
447 * ia64_mca_log_sal_error_record
449 * This function retrieves a specified error record type from SAL
450 * and wakes up any processes waiting for error records.
452 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE)
453 * FIXME: remove MCA and irq_safe.
455 static void
456 ia64_mca_log_sal_error_record(int sal_info_type)
458 u8 *buffer;
459 sal_log_record_header_t *rh;
460 u64 size;
461 int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
462 #ifdef IA64_MCA_DEBUG_INFO
463 static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
464 #endif
466 size = ia64_log_get(sal_info_type, &buffer, irq_safe);
467 if (!size)
468 return;
470 salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
472 if (irq_safe)
473 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
474 smp_processor_id(),
475 sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
477 /* Clear logs from corrected errors in case there's no user-level logger */
478 rh = (sal_log_record_header_t *)buffer;
479 if (rh->severity == sal_log_severity_corrected)
480 ia64_sal_clear_state_info(sal_info_type);
484 * search_mca_table
485 * See if the MCA surfaced in an instruction range
486 * that has been tagged as recoverable.
488 * Inputs
489 * first First address range to check
490 * last Last address range to check
491 * ip Instruction pointer, address we are looking for
493 * Return value:
494 * 1 on Success (in the table)/ 0 on Failure (not in the table)
497 search_mca_table (const struct mca_table_entry *first,
498 const struct mca_table_entry *last,
499 unsigned long ip)
501 const struct mca_table_entry *curr;
502 u64 curr_start, curr_end;
504 curr = first;
505 while (curr <= last) {
506 curr_start = (u64) &curr->start_addr + curr->start_addr;
507 curr_end = (u64) &curr->end_addr + curr->end_addr;
509 if ((ip >= curr_start) && (ip <= curr_end)) {
510 return 1;
512 curr++;
514 return 0;
517 /* Given an address, look for it in the mca tables. */
518 int mca_recover_range(unsigned long addr)
520 extern struct mca_table_entry __start___mca_table[];
521 extern struct mca_table_entry __stop___mca_table[];
523 return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
525 EXPORT_SYMBOL_GPL(mca_recover_range);
527 #ifdef CONFIG_ACPI
529 int cpe_vector = -1;
530 int ia64_cpe_irq = -1;
532 static irqreturn_t
533 ia64_mca_cpe_int_handler (int cpe_irq, void *arg)
535 static unsigned long cpe_history[CPE_HISTORY_LENGTH];
536 static int index;
537 static DEFINE_SPINLOCK(cpe_history_lock);
539 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
540 __func__, cpe_irq, smp_processor_id());
542 /* SAL spec states this should run w/ interrupts enabled */
543 local_irq_enable();
545 spin_lock(&cpe_history_lock);
546 if (!cpe_poll_enabled && cpe_vector >= 0) {
548 int i, count = 1; /* we know 1 happened now */
549 unsigned long now = jiffies;
551 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
552 if (now - cpe_history[i] <= HZ)
553 count++;
556 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
557 if (count >= CPE_HISTORY_LENGTH) {
559 cpe_poll_enabled = 1;
560 spin_unlock(&cpe_history_lock);
561 disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
564 * Corrected errors will still be corrected, but
565 * make sure there's a log somewhere that indicates
566 * something is generating more than we can handle.
568 printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
570 mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
572 /* lock already released, get out now */
573 goto out;
574 } else {
575 cpe_history[index++] = now;
576 if (index == CPE_HISTORY_LENGTH)
577 index = 0;
580 spin_unlock(&cpe_history_lock);
581 out:
582 /* Get the CPE error record and log it */
583 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
585 return IRQ_HANDLED;
588 #endif /* CONFIG_ACPI */
590 #ifdef CONFIG_ACPI
592 * ia64_mca_register_cpev
594 * Register the corrected platform error vector with SAL.
596 * Inputs
597 * cpev Corrected Platform Error Vector number
599 * Outputs
600 * None
602 void
603 ia64_mca_register_cpev (int cpev)
605 /* Register the CPE interrupt vector with SAL */
606 struct ia64_sal_retval isrv;
608 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
609 if (isrv.status) {
610 printk(KERN_ERR "Failed to register Corrected Platform "
611 "Error interrupt vector with SAL (status %ld)\n", isrv.status);
612 return;
615 IA64_MCA_DEBUG("%s: corrected platform error "
616 "vector %#x registered\n", __func__, cpev);
618 #endif /* CONFIG_ACPI */
621 * ia64_mca_cmc_vector_setup
623 * Setup the corrected machine check vector register in the processor.
624 * (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
625 * This function is invoked on a per-processor basis.
627 * Inputs
628 * None
630 * Outputs
631 * None
633 void __cpuinit
634 ia64_mca_cmc_vector_setup (void)
636 cmcv_reg_t cmcv;
638 cmcv.cmcv_regval = 0;
639 cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */
640 cmcv.cmcv_vector = IA64_CMC_VECTOR;
641 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
643 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x registered.\n",
644 __func__, smp_processor_id(), IA64_CMC_VECTOR);
646 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
647 __func__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
651 * ia64_mca_cmc_vector_disable
653 * Mask the corrected machine check vector register in the processor.
654 * This function is invoked on a per-processor basis.
656 * Inputs
657 * dummy(unused)
659 * Outputs
660 * None
662 static void
663 ia64_mca_cmc_vector_disable (void *dummy)
665 cmcv_reg_t cmcv;
667 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
669 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
670 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
672 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x disabled.\n",
673 __func__, smp_processor_id(), cmcv.cmcv_vector);
677 * ia64_mca_cmc_vector_enable
679 * Unmask the corrected machine check vector register in the processor.
680 * This function is invoked on a per-processor basis.
682 * Inputs
683 * dummy(unused)
685 * Outputs
686 * None
688 static void
689 ia64_mca_cmc_vector_enable (void *dummy)
691 cmcv_reg_t cmcv;
693 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
695 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
696 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
698 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x enabled.\n",
699 __func__, smp_processor_id(), cmcv.cmcv_vector);
703 * ia64_mca_cmc_vector_disable_keventd
705 * Called via keventd (smp_call_function() is not safe in interrupt context) to
706 * disable the cmc interrupt vector.
708 static void
709 ia64_mca_cmc_vector_disable_keventd(struct work_struct *unused)
711 on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 0);
715 * ia64_mca_cmc_vector_enable_keventd
717 * Called via keventd (smp_call_function() is not safe in interrupt context) to
718 * enable the cmc interrupt vector.
720 static void
721 ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused)
723 on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 0);
727 * ia64_mca_wakeup
729 * Send an inter-cpu interrupt to wake-up a particular cpu.
731 * Inputs : cpuid
732 * Outputs : None
734 static void
735 ia64_mca_wakeup(int cpu)
737 platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
741 * ia64_mca_wakeup_all
743 * Wakeup all the slave cpus which have rendez'ed previously.
745 * Inputs : None
746 * Outputs : None
748 static void
749 ia64_mca_wakeup_all(void)
751 int cpu;
753 /* Clear the Rendez checkin flag for all cpus */
754 for_each_online_cpu(cpu) {
755 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
756 ia64_mca_wakeup(cpu);
762 * ia64_mca_rendez_interrupt_handler
764 * This is handler used to put slave processors into spinloop
765 * while the monarch processor does the mca handling and later
766 * wake each slave up once the monarch is done. The state
767 * IA64_MCA_RENDEZ_CHECKIN_DONE indicates the cpu is rendez'ed
768 * in SAL. The state IA64_MCA_RENDEZ_CHECKIN_NOTDONE indicates
769 * the cpu has come out of OS rendezvous.
771 * Inputs : None
772 * Outputs : None
774 static irqreturn_t
775 ia64_mca_rendez_int_handler(int rendez_irq, void *arg)
777 unsigned long flags;
778 int cpu = smp_processor_id();
779 struct ia64_mca_notify_die nd =
780 { .sos = NULL, .monarch_cpu = &monarch_cpu };
782 /* Mask all interrupts */
783 local_irq_save(flags);
785 NOTIFY_MCA(DIE_MCA_RENDZVOUS_ENTER, get_irq_regs(), (long)&nd, 1);
787 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
788 /* Register with the SAL monarch that the slave has
789 * reached SAL
791 ia64_sal_mc_rendez();
793 NOTIFY_MCA(DIE_MCA_RENDZVOUS_PROCESS, get_irq_regs(), (long)&nd, 1);
795 /* Wait for the monarch cpu to exit. */
796 while (monarch_cpu != -1)
797 cpu_relax(); /* spin until monarch leaves */
799 NOTIFY_MCA(DIE_MCA_RENDZVOUS_LEAVE, get_irq_regs(), (long)&nd, 1);
801 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
802 /* Enable all interrupts */
803 local_irq_restore(flags);
804 return IRQ_HANDLED;
808 * ia64_mca_wakeup_int_handler
810 * The interrupt handler for processing the inter-cpu interrupt to the
811 * slave cpu which was spinning in the rendez loop.
812 * Since this spinning is done by turning off the interrupts and
813 * polling on the wakeup-interrupt bit in the IRR, there is
814 * nothing useful to be done in the handler.
816 * Inputs : wakeup_irq (Wakeup-interrupt bit)
817 * arg (Interrupt handler specific argument)
818 * Outputs : None
821 static irqreturn_t
822 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg)
824 return IRQ_HANDLED;
827 /* Function pointer for extra MCA recovery */
828 int (*ia64_mca_ucmc_extension)
829 (void*,struct ia64_sal_os_state*)
830 = NULL;
833 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
835 if (ia64_mca_ucmc_extension)
836 return 1;
838 ia64_mca_ucmc_extension = fn;
839 return 0;
842 void
843 ia64_unreg_MCA_extension(void)
845 if (ia64_mca_ucmc_extension)
846 ia64_mca_ucmc_extension = NULL;
849 EXPORT_SYMBOL(ia64_reg_MCA_extension);
850 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
853 static inline void
854 copy_reg(const u64 *fr, u64 fnat, unsigned long *tr, unsigned long *tnat)
856 u64 fslot, tslot, nat;
857 *tr = *fr;
858 fslot = ((unsigned long)fr >> 3) & 63;
859 tslot = ((unsigned long)tr >> 3) & 63;
860 *tnat &= ~(1UL << tslot);
861 nat = (fnat >> fslot) & 1;
862 *tnat |= (nat << tslot);
865 /* Change the comm field on the MCA/INT task to include the pid that
866 * was interrupted, it makes for easier debugging. If that pid was 0
867 * (swapper or nested MCA/INIT) then use the start of the previous comm
868 * field suffixed with its cpu.
871 static void
872 ia64_mca_modify_comm(const struct task_struct *previous_current)
874 char *p, comm[sizeof(current->comm)];
875 if (previous_current->pid)
876 snprintf(comm, sizeof(comm), "%s %d",
877 current->comm, previous_current->pid);
878 else {
879 int l;
880 if ((p = strchr(previous_current->comm, ' ')))
881 l = p - previous_current->comm;
882 else
883 l = strlen(previous_current->comm);
884 snprintf(comm, sizeof(comm), "%s %*s %d",
885 current->comm, l, previous_current->comm,
886 task_thread_info(previous_current)->cpu);
888 memcpy(current->comm, comm, sizeof(current->comm));
891 static void
892 finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos,
893 unsigned long *nat)
895 const pal_min_state_area_t *ms = sos->pal_min_state;
896 const u64 *bank;
898 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
899 * pmsa_{xip,xpsr,xfs}
901 if (ia64_psr(regs)->ic) {
902 regs->cr_iip = ms->pmsa_iip;
903 regs->cr_ipsr = ms->pmsa_ipsr;
904 regs->cr_ifs = ms->pmsa_ifs;
905 } else {
906 regs->cr_iip = ms->pmsa_xip;
907 regs->cr_ipsr = ms->pmsa_xpsr;
908 regs->cr_ifs = ms->pmsa_xfs;
910 sos->iip = ms->pmsa_iip;
911 sos->ipsr = ms->pmsa_ipsr;
912 sos->ifs = ms->pmsa_ifs;
914 regs->pr = ms->pmsa_pr;
915 regs->b0 = ms->pmsa_br0;
916 regs->ar_rsc = ms->pmsa_rsc;
917 copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &regs->r1, nat);
918 copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &regs->r2, nat);
919 copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &regs->r3, nat);
920 copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &regs->r8, nat);
921 copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &regs->r9, nat);
922 copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &regs->r10, nat);
923 copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &regs->r11, nat);
924 copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &regs->r12, nat);
925 copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &regs->r13, nat);
926 copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &regs->r14, nat);
927 copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &regs->r15, nat);
928 if (ia64_psr(regs)->bn)
929 bank = ms->pmsa_bank1_gr;
930 else
931 bank = ms->pmsa_bank0_gr;
932 copy_reg(&bank[16-16], ms->pmsa_nat_bits, &regs->r16, nat);
933 copy_reg(&bank[17-16], ms->pmsa_nat_bits, &regs->r17, nat);
934 copy_reg(&bank[18-16], ms->pmsa_nat_bits, &regs->r18, nat);
935 copy_reg(&bank[19-16], ms->pmsa_nat_bits, &regs->r19, nat);
936 copy_reg(&bank[20-16], ms->pmsa_nat_bits, &regs->r20, nat);
937 copy_reg(&bank[21-16], ms->pmsa_nat_bits, &regs->r21, nat);
938 copy_reg(&bank[22-16], ms->pmsa_nat_bits, &regs->r22, nat);
939 copy_reg(&bank[23-16], ms->pmsa_nat_bits, &regs->r23, nat);
940 copy_reg(&bank[24-16], ms->pmsa_nat_bits, &regs->r24, nat);
941 copy_reg(&bank[25-16], ms->pmsa_nat_bits, &regs->r25, nat);
942 copy_reg(&bank[26-16], ms->pmsa_nat_bits, &regs->r26, nat);
943 copy_reg(&bank[27-16], ms->pmsa_nat_bits, &regs->r27, nat);
944 copy_reg(&bank[28-16], ms->pmsa_nat_bits, &regs->r28, nat);
945 copy_reg(&bank[29-16], ms->pmsa_nat_bits, &regs->r29, nat);
946 copy_reg(&bank[30-16], ms->pmsa_nat_bits, &regs->r30, nat);
947 copy_reg(&bank[31-16], ms->pmsa_nat_bits, &regs->r31, nat);
950 /* On entry to this routine, we are running on the per cpu stack, see
951 * mca_asm.h. The original stack has not been touched by this event. Some of
952 * the original stack's registers will be in the RBS on this stack. This stack
953 * also contains a partial pt_regs and switch_stack, the rest of the data is in
954 * PAL minstate.
956 * The first thing to do is modify the original stack to look like a blocked
957 * task so we can run backtrace on the original task. Also mark the per cpu
958 * stack as current to ensure that we use the correct task state, it also means
959 * that we can do backtrace on the MCA/INIT handler code itself.
962 static struct task_struct *
963 ia64_mca_modify_original_stack(struct pt_regs *regs,
964 const struct switch_stack *sw,
965 struct ia64_sal_os_state *sos,
966 const char *type)
968 char *p;
969 ia64_va va;
970 extern char ia64_leave_kernel[]; /* Need asm address, not function descriptor */
971 const pal_min_state_area_t *ms = sos->pal_min_state;
972 struct task_struct *previous_current;
973 struct pt_regs *old_regs;
974 struct switch_stack *old_sw;
975 unsigned size = sizeof(struct pt_regs) +
976 sizeof(struct switch_stack) + 16;
977 unsigned long *old_bspstore, *old_bsp;
978 unsigned long *new_bspstore, *new_bsp;
979 unsigned long old_unat, old_rnat, new_rnat, nat;
980 u64 slots, loadrs = regs->loadrs;
981 u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
982 u64 ar_bspstore = regs->ar_bspstore;
983 u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
984 const char *msg;
985 int cpu = smp_processor_id();
987 previous_current = curr_task(cpu);
988 set_curr_task(cpu, current);
989 if ((p = strchr(current->comm, ' ')))
990 *p = '\0';
992 /* Best effort attempt to cope with MCA/INIT delivered while in
993 * physical mode.
995 regs->cr_ipsr = ms->pmsa_ipsr;
996 if (ia64_psr(regs)->dt == 0) {
997 va.l = r12;
998 if (va.f.reg == 0) {
999 va.f.reg = 7;
1000 r12 = va.l;
1002 va.l = r13;
1003 if (va.f.reg == 0) {
1004 va.f.reg = 7;
1005 r13 = va.l;
1008 if (ia64_psr(regs)->rt == 0) {
1009 va.l = ar_bspstore;
1010 if (va.f.reg == 0) {
1011 va.f.reg = 7;
1012 ar_bspstore = va.l;
1014 va.l = ar_bsp;
1015 if (va.f.reg == 0) {
1016 va.f.reg = 7;
1017 ar_bsp = va.l;
1021 /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
1022 * have been copied to the old stack, the old stack may fail the
1023 * validation tests below. So ia64_old_stack() must restore the dirty
1024 * registers from the new stack. The old and new bspstore probably
1025 * have different alignments, so loadrs calculated on the old bsp
1026 * cannot be used to restore from the new bsp. Calculate a suitable
1027 * loadrs for the new stack and save it in the new pt_regs, where
1028 * ia64_old_stack() can get it.
1030 old_bspstore = (unsigned long *)ar_bspstore;
1031 old_bsp = (unsigned long *)ar_bsp;
1032 slots = ia64_rse_num_regs(old_bspstore, old_bsp);
1033 new_bspstore = (unsigned long *)((u64)current + IA64_RBS_OFFSET);
1034 new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
1035 regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
1037 /* Verify the previous stack state before we change it */
1038 if (user_mode(regs)) {
1039 msg = "occurred in user space";
1040 /* previous_current is guaranteed to be valid when the task was
1041 * in user space, so ...
1043 ia64_mca_modify_comm(previous_current);
1044 goto no_mod;
1047 if (r13 != sos->prev_IA64_KR_CURRENT) {
1048 msg = "inconsistent previous current and r13";
1049 goto no_mod;
1052 if (!mca_recover_range(ms->pmsa_iip)) {
1053 if ((r12 - r13) >= KERNEL_STACK_SIZE) {
1054 msg = "inconsistent r12 and r13";
1055 goto no_mod;
1057 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
1058 msg = "inconsistent ar.bspstore and r13";
1059 goto no_mod;
1061 va.p = old_bspstore;
1062 if (va.f.reg < 5) {
1063 msg = "old_bspstore is in the wrong region";
1064 goto no_mod;
1066 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
1067 msg = "inconsistent ar.bsp and r13";
1068 goto no_mod;
1070 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
1071 if (ar_bspstore + size > r12) {
1072 msg = "no room for blocked state";
1073 goto no_mod;
1077 ia64_mca_modify_comm(previous_current);
1079 /* Make the original task look blocked. First stack a struct pt_regs,
1080 * describing the state at the time of interrupt. mca_asm.S built a
1081 * partial pt_regs, copy it and fill in the blanks using minstate.
1083 p = (char *)r12 - sizeof(*regs);
1084 old_regs = (struct pt_regs *)p;
1085 memcpy(old_regs, regs, sizeof(*regs));
1086 old_regs->loadrs = loadrs;
1087 old_unat = old_regs->ar_unat;
1088 finish_pt_regs(old_regs, sos, &old_unat);
1090 /* Next stack a struct switch_stack. mca_asm.S built a partial
1091 * switch_stack, copy it and fill in the blanks using pt_regs and
1092 * minstate.
1094 * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
1095 * ar.pfs is set to 0.
1097 * unwind.c::unw_unwind() does special processing for interrupt frames.
1098 * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
1099 * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not
1100 * that this is documented, of course. Set PRED_NON_SYSCALL in the
1101 * switch_stack on the original stack so it will unwind correctly when
1102 * unwind.c reads pt_regs.
1104 * thread.ksp is updated to point to the synthesized switch_stack.
1106 p -= sizeof(struct switch_stack);
1107 old_sw = (struct switch_stack *)p;
1108 memcpy(old_sw, sw, sizeof(*sw));
1109 old_sw->caller_unat = old_unat;
1110 old_sw->ar_fpsr = old_regs->ar_fpsr;
1111 copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
1112 copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
1113 copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
1114 copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
1115 old_sw->b0 = (u64)ia64_leave_kernel;
1116 old_sw->b1 = ms->pmsa_br1;
1117 old_sw->ar_pfs = 0;
1118 old_sw->ar_unat = old_unat;
1119 old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
1120 previous_current->thread.ksp = (u64)p - 16;
1122 /* Finally copy the original stack's registers back to its RBS.
1123 * Registers from ar.bspstore through ar.bsp at the time of the event
1124 * are in the current RBS, copy them back to the original stack. The
1125 * copy must be done register by register because the original bspstore
1126 * and the current one have different alignments, so the saved RNAT
1127 * data occurs at different places.
1129 * mca_asm does cover, so the old_bsp already includes all registers at
1130 * the time of MCA/INIT. It also does flushrs, so all registers before
1131 * this function have been written to backing store on the MCA/INIT
1132 * stack.
1134 new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
1135 old_rnat = regs->ar_rnat;
1136 while (slots--) {
1137 if (ia64_rse_is_rnat_slot(new_bspstore)) {
1138 new_rnat = ia64_get_rnat(new_bspstore++);
1140 if (ia64_rse_is_rnat_slot(old_bspstore)) {
1141 *old_bspstore++ = old_rnat;
1142 old_rnat = 0;
1144 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
1145 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
1146 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
1147 *old_bspstore++ = *new_bspstore++;
1149 old_sw->ar_bspstore = (unsigned long)old_bspstore;
1150 old_sw->ar_rnat = old_rnat;
1152 sos->prev_task = previous_current;
1153 return previous_current;
1155 no_mod:
1156 mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
1157 smp_processor_id(), type, msg);
1158 old_unat = regs->ar_unat;
1159 finish_pt_regs(regs, sos, &old_unat);
1160 return previous_current;
1163 /* The monarch/slave interaction is based on monarch_cpu and requires that all
1164 * slaves have entered rendezvous before the monarch leaves. If any cpu has
1165 * not entered rendezvous yet then wait a bit. The assumption is that any
1166 * slave that has not rendezvoused after a reasonable time is never going to do
1167 * so. In this context, slave includes cpus that respond to the MCA rendezvous
1168 * interrupt, as well as cpus that receive the INIT slave event.
1171 static void
1172 ia64_wait_for_slaves(int monarch, const char *type)
1174 int c, i , wait;
1177 * wait 5 seconds total for slaves (arbitrary)
1179 for (i = 0; i < 5000; i++) {
1180 wait = 0;
1181 for_each_online_cpu(c) {
1182 if (c == monarch)
1183 continue;
1184 if (ia64_mc_info.imi_rendez_checkin[c]
1185 == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
1186 udelay(1000); /* short wait */
1187 wait = 1;
1188 break;
1191 if (!wait)
1192 goto all_in;
1196 * Maybe slave(s) dead. Print buffered messages immediately.
1198 ia64_mlogbuf_finish(0);
1199 mprintk(KERN_INFO "OS %s slave did not rendezvous on cpu", type);
1200 for_each_online_cpu(c) {
1201 if (c == monarch)
1202 continue;
1203 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
1204 mprintk(" %d", c);
1206 mprintk("\n");
1207 return;
1209 all_in:
1210 mprintk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type);
1211 return;
1214 /* mca_insert_tr
1216 * Switch rid when TR reload and needed!
1217 * iord: 1: itr, 2: itr;
1220 static void mca_insert_tr(u64 iord)
1223 int i;
1224 u64 old_rr;
1225 struct ia64_tr_entry *p;
1226 unsigned long psr;
1227 int cpu = smp_processor_id();
1229 if (!ia64_idtrs[cpu])
1230 return;
1232 psr = ia64_clear_ic();
1233 for (i = IA64_TR_ALLOC_BASE; i < IA64_TR_ALLOC_MAX; i++) {
1234 p = ia64_idtrs[cpu] + (iord - 1) * IA64_TR_ALLOC_MAX;
1235 if (p->pte & 0x1) {
1236 old_rr = ia64_get_rr(p->ifa);
1237 if (old_rr != p->rr) {
1238 ia64_set_rr(p->ifa, p->rr);
1239 ia64_srlz_d();
1241 ia64_ptr(iord, p->ifa, p->itir >> 2);
1242 ia64_srlz_i();
1243 if (iord & 0x1) {
1244 ia64_itr(0x1, i, p->ifa, p->pte, p->itir >> 2);
1245 ia64_srlz_i();
1247 if (iord & 0x2) {
1248 ia64_itr(0x2, i, p->ifa, p->pte, p->itir >> 2);
1249 ia64_srlz_i();
1251 if (old_rr != p->rr) {
1252 ia64_set_rr(p->ifa, old_rr);
1253 ia64_srlz_d();
1257 ia64_set_psr(psr);
1261 * ia64_mca_handler
1263 * This is uncorrectable machine check handler called from OS_MCA
1264 * dispatch code which is in turn called from SAL_CHECK().
1265 * This is the place where the core of OS MCA handling is done.
1266 * Right now the logs are extracted and displayed in a well-defined
1267 * format. This handler code is supposed to be run only on the
1268 * monarch processor. Once the monarch is done with MCA handling
1269 * further MCA logging is enabled by clearing logs.
1270 * Monarch also has the duty of sending wakeup-IPIs to pull the
1271 * slave processors out of rendezvous spinloop.
1273 * If multiple processors call into OS_MCA, the first will become
1274 * the monarch. Subsequent cpus will be recorded in the mca_cpu
1275 * bitmask. After the first monarch has processed its MCA, it
1276 * will wake up the next cpu in the mca_cpu bitmask and then go
1277 * into the rendezvous loop. When all processors have serviced
1278 * their MCA, the last monarch frees up the rest of the processors.
1280 void
1281 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
1282 struct ia64_sal_os_state *sos)
1284 int recover, cpu = smp_processor_id();
1285 struct task_struct *previous_current;
1286 struct ia64_mca_notify_die nd =
1287 { .sos = sos, .monarch_cpu = &monarch_cpu, .data = &recover };
1288 static atomic_t mca_count;
1289 static cpumask_t mca_cpu;
1291 if (atomic_add_return(1, &mca_count) == 1) {
1292 monarch_cpu = cpu;
1293 sos->monarch = 1;
1294 } else {
1295 cpu_set(cpu, mca_cpu);
1296 sos->monarch = 0;
1298 mprintk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d "
1299 "monarch=%ld\n", sos->proc_state_param, cpu, sos->monarch);
1301 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
1303 NOTIFY_MCA(DIE_MCA_MONARCH_ENTER, regs, (long)&nd, 1);
1305 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA;
1306 if (sos->monarch) {
1307 ia64_wait_for_slaves(cpu, "MCA");
1309 /* Wakeup all the processors which are spinning in the
1310 * rendezvous loop. They will leave SAL, then spin in the OS
1311 * with interrupts disabled until this monarch cpu leaves the
1312 * MCA handler. That gets control back to the OS so we can
1313 * backtrace the other cpus, backtrace when spinning in SAL
1314 * does not work.
1316 ia64_mca_wakeup_all();
1317 } else {
1318 while (cpu_isset(cpu, mca_cpu))
1319 cpu_relax(); /* spin until monarch wakes us */
1322 NOTIFY_MCA(DIE_MCA_MONARCH_PROCESS, regs, (long)&nd, 1);
1324 /* Get the MCA error record and log it */
1325 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1327 /* MCA error recovery */
1328 recover = (ia64_mca_ucmc_extension
1329 && ia64_mca_ucmc_extension(
1330 IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1331 sos));
1333 if (recover) {
1334 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1335 rh->severity = sal_log_severity_corrected;
1336 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1337 sos->os_status = IA64_MCA_CORRECTED;
1338 } else {
1339 /* Dump buffered message to console */
1340 ia64_mlogbuf_finish(1);
1343 if (__get_cpu_var(ia64_mca_tr_reload)) {
1344 mca_insert_tr(0x1); /*Reload dynamic itrs*/
1345 mca_insert_tr(0x2); /*Reload dynamic itrs*/
1348 NOTIFY_MCA(DIE_MCA_MONARCH_LEAVE, regs, (long)&nd, 1);
1350 if (atomic_dec_return(&mca_count) > 0) {
1351 int i;
1353 /* wake up the next monarch cpu,
1354 * and put this cpu in the rendez loop.
1356 for_each_online_cpu(i) {
1357 if (cpu_isset(i, mca_cpu)) {
1358 monarch_cpu = i;
1359 cpu_clear(i, mca_cpu); /* wake next cpu */
1360 while (monarch_cpu != -1)
1361 cpu_relax(); /* spin until last cpu leaves */
1362 set_curr_task(cpu, previous_current);
1363 ia64_mc_info.imi_rendez_checkin[cpu]
1364 = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1365 return;
1369 set_curr_task(cpu, previous_current);
1370 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1371 monarch_cpu = -1; /* This frees the slaves and previous monarchs */
1374 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd);
1375 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd);
1378 * ia64_mca_cmc_int_handler
1380 * This is corrected machine check interrupt handler.
1381 * Right now the logs are extracted and displayed in a well-defined
1382 * format.
1384 * Inputs
1385 * interrupt number
1386 * client data arg ptr
1388 * Outputs
1389 * None
1391 static irqreturn_t
1392 ia64_mca_cmc_int_handler(int cmc_irq, void *arg)
1394 static unsigned long cmc_history[CMC_HISTORY_LENGTH];
1395 static int index;
1396 static DEFINE_SPINLOCK(cmc_history_lock);
1398 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1399 __func__, cmc_irq, smp_processor_id());
1401 /* SAL spec states this should run w/ interrupts enabled */
1402 local_irq_enable();
1404 spin_lock(&cmc_history_lock);
1405 if (!cmc_polling_enabled) {
1406 int i, count = 1; /* we know 1 happened now */
1407 unsigned long now = jiffies;
1409 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1410 if (now - cmc_history[i] <= HZ)
1411 count++;
1414 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1415 if (count >= CMC_HISTORY_LENGTH) {
1417 cmc_polling_enabled = 1;
1418 spin_unlock(&cmc_history_lock);
1419 /* If we're being hit with CMC interrupts, we won't
1420 * ever execute the schedule_work() below. Need to
1421 * disable CMC interrupts on this processor now.
1423 ia64_mca_cmc_vector_disable(NULL);
1424 schedule_work(&cmc_disable_work);
1427 * Corrected errors will still be corrected, but
1428 * make sure there's a log somewhere that indicates
1429 * something is generating more than we can handle.
1431 printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1433 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1435 /* lock already released, get out now */
1436 goto out;
1437 } else {
1438 cmc_history[index++] = now;
1439 if (index == CMC_HISTORY_LENGTH)
1440 index = 0;
1443 spin_unlock(&cmc_history_lock);
1444 out:
1445 /* Get the CMC error record and log it */
1446 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1448 return IRQ_HANDLED;
1452 * ia64_mca_cmc_int_caller
1454 * Triggered by sw interrupt from CMC polling routine. Calls
1455 * real interrupt handler and either triggers a sw interrupt
1456 * on the next cpu or does cleanup at the end.
1458 * Inputs
1459 * interrupt number
1460 * client data arg ptr
1461 * Outputs
1462 * handled
1464 static irqreturn_t
1465 ia64_mca_cmc_int_caller(int cmc_irq, void *arg)
1467 static int start_count = -1;
1468 unsigned int cpuid;
1470 cpuid = smp_processor_id();
1472 /* If first cpu, update count */
1473 if (start_count == -1)
1474 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1476 ia64_mca_cmc_int_handler(cmc_irq, arg);
1478 cpuid = cpumask_next(cpuid+1, cpu_online_mask);
1480 if (cpuid < nr_cpu_ids) {
1481 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1482 } else {
1483 /* If no log record, switch out of polling mode */
1484 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1486 printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1487 schedule_work(&cmc_enable_work);
1488 cmc_polling_enabled = 0;
1490 } else {
1492 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1495 start_count = -1;
1498 return IRQ_HANDLED;
1502 * ia64_mca_cmc_poll
1504 * Poll for Corrected Machine Checks (CMCs)
1506 * Inputs : dummy(unused)
1507 * Outputs : None
1510 static void
1511 ia64_mca_cmc_poll (unsigned long dummy)
1513 /* Trigger a CMC interrupt cascade */
1514 platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1518 * ia64_mca_cpe_int_caller
1520 * Triggered by sw interrupt from CPE polling routine. Calls
1521 * real interrupt handler and either triggers a sw interrupt
1522 * on the next cpu or does cleanup at the end.
1524 * Inputs
1525 * interrupt number
1526 * client data arg ptr
1527 * Outputs
1528 * handled
1530 #ifdef CONFIG_ACPI
1532 static irqreturn_t
1533 ia64_mca_cpe_int_caller(int cpe_irq, void *arg)
1535 static int start_count = -1;
1536 static int poll_time = MIN_CPE_POLL_INTERVAL;
1537 unsigned int cpuid;
1539 cpuid = smp_processor_id();
1541 /* If first cpu, update count */
1542 if (start_count == -1)
1543 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1545 ia64_mca_cpe_int_handler(cpe_irq, arg);
1547 cpuid = cpumask_next(cpuid+1, cpu_online_mask);
1549 if (cpuid < NR_CPUS) {
1550 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1551 } else {
1553 * If a log was recorded, increase our polling frequency,
1554 * otherwise, backoff or return to interrupt mode.
1556 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1557 poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1558 } else if (cpe_vector < 0) {
1559 poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1560 } else {
1561 poll_time = MIN_CPE_POLL_INTERVAL;
1563 printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1564 enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1565 cpe_poll_enabled = 0;
1568 if (cpe_poll_enabled)
1569 mod_timer(&cpe_poll_timer, jiffies + poll_time);
1570 start_count = -1;
1573 return IRQ_HANDLED;
1577 * ia64_mca_cpe_poll
1579 * Poll for Corrected Platform Errors (CPEs), trigger interrupt
1580 * on first cpu, from there it will trickle through all the cpus.
1582 * Inputs : dummy(unused)
1583 * Outputs : None
1586 static void
1587 ia64_mca_cpe_poll (unsigned long dummy)
1589 /* Trigger a CPE interrupt cascade */
1590 platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1593 #endif /* CONFIG_ACPI */
1595 static int
1596 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1598 int c;
1599 struct task_struct *g, *t;
1600 if (val != DIE_INIT_MONARCH_PROCESS)
1601 return NOTIFY_DONE;
1602 #ifdef CONFIG_KEXEC
1603 if (atomic_read(&kdump_in_progress))
1604 return NOTIFY_DONE;
1605 #endif
1608 * FIXME: mlogbuf will brim over with INIT stack dumps.
1609 * To enable show_stack from INIT, we use oops_in_progress which should
1610 * be used in real oops. This would cause something wrong after INIT.
1612 BREAK_LOGLEVEL(console_loglevel);
1613 ia64_mlogbuf_dump_from_init();
1615 printk(KERN_ERR "Processes interrupted by INIT -");
1616 for_each_online_cpu(c) {
1617 struct ia64_sal_os_state *s;
1618 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1619 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1620 g = s->prev_task;
1621 if (g) {
1622 if (g->pid)
1623 printk(" %d", g->pid);
1624 else
1625 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1628 printk("\n\n");
1629 if (read_trylock(&tasklist_lock)) {
1630 do_each_thread (g, t) {
1631 printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1632 show_stack(t, NULL);
1633 } while_each_thread (g, t);
1634 read_unlock(&tasklist_lock);
1636 /* FIXME: This will not restore zapped printk locks. */
1637 RESTORE_LOGLEVEL(console_loglevel);
1638 return NOTIFY_DONE;
1642 * C portion of the OS INIT handler
1644 * Called from ia64_os_init_dispatch
1646 * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for
1647 * this event. This code is used for both monarch and slave INIT events, see
1648 * sos->monarch.
1650 * All INIT events switch to the INIT stack and change the previous process to
1651 * blocked status. If one of the INIT events is the monarch then we are
1652 * probably processing the nmi button/command. Use the monarch cpu to dump all
1653 * the processes. The slave INIT events all spin until the monarch cpu
1654 * returns. We can also get INIT slave events for MCA, in which case the MCA
1655 * process is the monarch.
1658 void
1659 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1660 struct ia64_sal_os_state *sos)
1662 static atomic_t slaves;
1663 static atomic_t monarchs;
1664 struct task_struct *previous_current;
1665 int cpu = smp_processor_id();
1666 struct ia64_mca_notify_die nd =
1667 { .sos = sos, .monarch_cpu = &monarch_cpu };
1669 NOTIFY_INIT(DIE_INIT_ENTER, regs, (long)&nd, 0);
1671 mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1672 sos->proc_state_param, cpu, sos->monarch);
1673 salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1675 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1676 sos->os_status = IA64_INIT_RESUME;
1678 /* FIXME: Workaround for broken proms that drive all INIT events as
1679 * slaves. The last slave that enters is promoted to be a monarch.
1680 * Remove this code in September 2006, that gives platforms a year to
1681 * fix their proms and get their customers updated.
1683 if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1684 mprintk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1685 __func__, cpu);
1686 atomic_dec(&slaves);
1687 sos->monarch = 1;
1690 /* FIXME: Workaround for broken proms that drive all INIT events as
1691 * monarchs. Second and subsequent monarchs are demoted to slaves.
1692 * Remove this code in September 2006, that gives platforms a year to
1693 * fix their proms and get their customers updated.
1695 if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1696 mprintk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1697 __func__, cpu);
1698 atomic_dec(&monarchs);
1699 sos->monarch = 0;
1702 if (!sos->monarch) {
1703 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1705 #ifdef CONFIG_KEXEC
1706 while (monarch_cpu == -1 && !atomic_read(&kdump_in_progress))
1707 udelay(1000);
1708 #else
1709 while (monarch_cpu == -1)
1710 cpu_relax(); /* spin until monarch enters */
1711 #endif
1713 NOTIFY_INIT(DIE_INIT_SLAVE_ENTER, regs, (long)&nd, 1);
1714 NOTIFY_INIT(DIE_INIT_SLAVE_PROCESS, regs, (long)&nd, 1);
1716 #ifdef CONFIG_KEXEC
1717 while (monarch_cpu != -1 && !atomic_read(&kdump_in_progress))
1718 udelay(1000);
1719 #else
1720 while (monarch_cpu != -1)
1721 cpu_relax(); /* spin until monarch leaves */
1722 #endif
1724 NOTIFY_INIT(DIE_INIT_SLAVE_LEAVE, regs, (long)&nd, 1);
1726 mprintk("Slave on cpu %d returning to normal service.\n", cpu);
1727 set_curr_task(cpu, previous_current);
1728 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1729 atomic_dec(&slaves);
1730 return;
1733 monarch_cpu = cpu;
1734 NOTIFY_INIT(DIE_INIT_MONARCH_ENTER, regs, (long)&nd, 1);
1737 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1738 * generated via the BMC's command-line interface, but since the console is on the
1739 * same serial line, the user will need some time to switch out of the BMC before
1740 * the dump begins.
1742 mprintk("Delaying for 5 seconds...\n");
1743 udelay(5*1000000);
1744 ia64_wait_for_slaves(cpu, "INIT");
1745 /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1746 * to default_monarch_init_process() above and just print all the
1747 * tasks.
1749 NOTIFY_INIT(DIE_INIT_MONARCH_PROCESS, regs, (long)&nd, 1);
1750 NOTIFY_INIT(DIE_INIT_MONARCH_LEAVE, regs, (long)&nd, 1);
1752 mprintk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu);
1753 atomic_dec(&monarchs);
1754 set_curr_task(cpu, previous_current);
1755 monarch_cpu = -1;
1756 return;
1759 static int __init
1760 ia64_mca_disable_cpe_polling(char *str)
1762 cpe_poll_enabled = 0;
1763 return 1;
1766 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1768 static struct irqaction cmci_irqaction = {
1769 .handler = ia64_mca_cmc_int_handler,
1770 .flags = IRQF_DISABLED,
1771 .name = "cmc_hndlr"
1774 static struct irqaction cmcp_irqaction = {
1775 .handler = ia64_mca_cmc_int_caller,
1776 .flags = IRQF_DISABLED,
1777 .name = "cmc_poll"
1780 static struct irqaction mca_rdzv_irqaction = {
1781 .handler = ia64_mca_rendez_int_handler,
1782 .flags = IRQF_DISABLED,
1783 .name = "mca_rdzv"
1786 static struct irqaction mca_wkup_irqaction = {
1787 .handler = ia64_mca_wakeup_int_handler,
1788 .flags = IRQF_DISABLED,
1789 .name = "mca_wkup"
1792 #ifdef CONFIG_ACPI
1793 static struct irqaction mca_cpe_irqaction = {
1794 .handler = ia64_mca_cpe_int_handler,
1795 .flags = IRQF_DISABLED,
1796 .name = "cpe_hndlr"
1799 static struct irqaction mca_cpep_irqaction = {
1800 .handler = ia64_mca_cpe_int_caller,
1801 .flags = IRQF_DISABLED,
1802 .name = "cpe_poll"
1804 #endif /* CONFIG_ACPI */
1806 /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on
1807 * these stacks can never sleep, they cannot return from the kernel to user
1808 * space, they do not appear in a normal ps listing. So there is no need to
1809 * format most of the fields.
1812 static void __cpuinit
1813 format_mca_init_stack(void *mca_data, unsigned long offset,
1814 const char *type, int cpu)
1816 struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1817 struct thread_info *ti;
1818 memset(p, 0, KERNEL_STACK_SIZE);
1819 ti = task_thread_info(p);
1820 ti->flags = _TIF_MCA_INIT;
1821 ti->preempt_count = 1;
1822 ti->task = p;
1823 ti->cpu = cpu;
1824 p->stack = ti;
1825 p->state = TASK_UNINTERRUPTIBLE;
1826 cpu_set(cpu, p->cpus_allowed);
1827 INIT_LIST_HEAD(&p->tasks);
1828 p->parent = p->real_parent = p->group_leader = p;
1829 INIT_LIST_HEAD(&p->children);
1830 INIT_LIST_HEAD(&p->sibling);
1831 strncpy(p->comm, type, sizeof(p->comm)-1);
1834 /* Caller prevents this from being called after init */
1835 static void * __init_refok mca_bootmem(void)
1837 return __alloc_bootmem(sizeof(struct ia64_mca_cpu),
1838 KERNEL_STACK_SIZE, 0);
1841 /* Do per-CPU MCA-related initialization. */
1842 void __cpuinit
1843 ia64_mca_cpu_init(void *cpu_data)
1845 void *pal_vaddr;
1846 void *data;
1847 long sz = sizeof(struct ia64_mca_cpu);
1848 int cpu = smp_processor_id();
1849 static int first_time = 1;
1852 * Structure will already be allocated if cpu has been online,
1853 * then offlined.
1855 if (__per_cpu_mca[cpu]) {
1856 data = __va(__per_cpu_mca[cpu]);
1857 } else {
1858 if (first_time) {
1859 data = mca_bootmem();
1860 first_time = 0;
1861 } else
1862 data = __get_free_pages(GFP_KERNEL, get_order(sz));
1863 if (!data)
1864 panic("Could not allocate MCA memory for cpu %d\n",
1865 cpu);
1867 format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, mca_stack),
1868 "MCA", cpu);
1869 format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, init_stack),
1870 "INIT", cpu);
1871 __get_cpu_var(ia64_mca_data) = __per_cpu_mca[cpu] = __pa(data);
1874 * Stash away a copy of the PTE needed to map the per-CPU page.
1875 * We may need it during MCA recovery.
1877 __get_cpu_var(ia64_mca_per_cpu_pte) =
1878 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1881 * Also, stash away a copy of the PAL address and the PTE
1882 * needed to map it.
1884 pal_vaddr = efi_get_pal_addr();
1885 if (!pal_vaddr)
1886 return;
1887 __get_cpu_var(ia64_mca_pal_base) =
1888 GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1889 __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1890 PAGE_KERNEL));
1893 static void __cpuinit ia64_mca_cmc_vector_adjust(void *dummy)
1895 unsigned long flags;
1897 local_irq_save(flags);
1898 if (!cmc_polling_enabled)
1899 ia64_mca_cmc_vector_enable(NULL);
1900 local_irq_restore(flags);
1903 static int __cpuinit mca_cpu_callback(struct notifier_block *nfb,
1904 unsigned long action,
1905 void *hcpu)
1907 int hotcpu = (unsigned long) hcpu;
1909 switch (action) {
1910 case CPU_ONLINE:
1911 case CPU_ONLINE_FROZEN:
1912 smp_call_function_single(hotcpu, ia64_mca_cmc_vector_adjust,
1913 NULL, 0);
1914 break;
1916 return NOTIFY_OK;
1919 static struct notifier_block mca_cpu_notifier __cpuinitdata = {
1920 .notifier_call = mca_cpu_callback
1924 * ia64_mca_init
1926 * Do all the system level mca specific initialization.
1928 * 1. Register spinloop and wakeup request interrupt vectors
1930 * 2. Register OS_MCA handler entry point
1932 * 3. Register OS_INIT handler entry point
1934 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1936 * Note that this initialization is done very early before some kernel
1937 * services are available.
1939 * Inputs : None
1941 * Outputs : None
1943 void __init
1944 ia64_mca_init(void)
1946 ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1947 ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1948 ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1949 int i;
1950 long rc;
1951 struct ia64_sal_retval isrv;
1952 unsigned long timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */
1953 static struct notifier_block default_init_monarch_nb = {
1954 .notifier_call = default_monarch_init_process,
1955 .priority = 0/* we need to notified last */
1958 IA64_MCA_DEBUG("%s: begin\n", __func__);
1960 /* Clear the Rendez checkin flag for all cpus */
1961 for(i = 0 ; i < NR_CPUS; i++)
1962 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1965 * Register the rendezvous spinloop and wakeup mechanism with SAL
1968 /* Register the rendezvous interrupt vector with SAL */
1969 while (1) {
1970 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1971 SAL_MC_PARAM_MECHANISM_INT,
1972 IA64_MCA_RENDEZ_VECTOR,
1973 timeout,
1974 SAL_MC_PARAM_RZ_ALWAYS);
1975 rc = isrv.status;
1976 if (rc == 0)
1977 break;
1978 if (rc == -2) {
1979 printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1980 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1981 timeout = isrv.v0;
1982 NOTIFY_MCA(DIE_MCA_NEW_TIMEOUT, NULL, timeout, 0);
1983 continue;
1985 printk(KERN_ERR "Failed to register rendezvous interrupt "
1986 "with SAL (status %ld)\n", rc);
1987 return;
1990 /* Register the wakeup interrupt vector with SAL */
1991 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1992 SAL_MC_PARAM_MECHANISM_INT,
1993 IA64_MCA_WAKEUP_VECTOR,
1994 0, 0);
1995 rc = isrv.status;
1996 if (rc) {
1997 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1998 "(status %ld)\n", rc);
1999 return;
2002 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __func__);
2004 ia64_mc_info.imi_mca_handler = ia64_tpa(mca_hldlr_ptr->fp);
2006 * XXX - disable SAL checksum by setting size to 0; should be
2007 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
2009 ia64_mc_info.imi_mca_handler_size = 0;
2011 /* Register the os mca handler with SAL */
2012 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
2013 ia64_mc_info.imi_mca_handler,
2014 ia64_tpa(mca_hldlr_ptr->gp),
2015 ia64_mc_info.imi_mca_handler_size,
2016 0, 0, 0)))
2018 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
2019 "(status %ld)\n", rc);
2020 return;
2023 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __func__,
2024 ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
2027 * XXX - disable SAL checksum by setting size to 0, should be
2028 * size of the actual init handler in mca_asm.S.
2030 ia64_mc_info.imi_monarch_init_handler = ia64_tpa(init_hldlr_ptr_monarch->fp);
2031 ia64_mc_info.imi_monarch_init_handler_size = 0;
2032 ia64_mc_info.imi_slave_init_handler = ia64_tpa(init_hldlr_ptr_slave->fp);
2033 ia64_mc_info.imi_slave_init_handler_size = 0;
2035 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __func__,
2036 ia64_mc_info.imi_monarch_init_handler);
2038 /* Register the os init handler with SAL */
2039 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
2040 ia64_mc_info.imi_monarch_init_handler,
2041 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
2042 ia64_mc_info.imi_monarch_init_handler_size,
2043 ia64_mc_info.imi_slave_init_handler,
2044 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
2045 ia64_mc_info.imi_slave_init_handler_size)))
2047 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
2048 "(status %ld)\n", rc);
2049 return;
2051 if (register_die_notifier(&default_init_monarch_nb)) {
2052 printk(KERN_ERR "Failed to register default monarch INIT process\n");
2053 return;
2056 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__);
2058 /* Initialize the areas set aside by the OS to buffer the
2059 * platform/processor error states for MCA/INIT/CMC
2060 * handling.
2062 ia64_log_init(SAL_INFO_TYPE_MCA);
2063 ia64_log_init(SAL_INFO_TYPE_INIT);
2064 ia64_log_init(SAL_INFO_TYPE_CMC);
2065 ia64_log_init(SAL_INFO_TYPE_CPE);
2067 mca_init = 1;
2068 printk(KERN_INFO "MCA related initialization done\n");
2072 * ia64_mca_late_init
2074 * Opportunity to setup things that require initialization later
2075 * than ia64_mca_init. Setup a timer to poll for CPEs if the
2076 * platform doesn't support an interrupt driven mechanism.
2078 * Inputs : None
2079 * Outputs : Status
2081 static int __init
2082 ia64_mca_late_init(void)
2084 if (!mca_init)
2085 return 0;
2088 * Configure the CMCI/P vector and handler. Interrupts for CMC are
2089 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
2091 register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
2092 register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
2093 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
2095 /* Setup the MCA rendezvous interrupt vector */
2096 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
2098 /* Setup the MCA wakeup interrupt vector */
2099 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
2101 #ifdef CONFIG_ACPI
2102 /* Setup the CPEI/P handler */
2103 register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
2104 #endif
2106 register_hotcpu_notifier(&mca_cpu_notifier);
2108 /* Setup the CMCI/P vector and handler */
2109 init_timer(&cmc_poll_timer);
2110 cmc_poll_timer.function = ia64_mca_cmc_poll;
2112 /* Unmask/enable the vector */
2113 cmc_polling_enabled = 0;
2114 schedule_work(&cmc_enable_work);
2116 IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __func__);
2118 #ifdef CONFIG_ACPI
2119 /* Setup the CPEI/P vector and handler */
2120 cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
2121 init_timer(&cpe_poll_timer);
2122 cpe_poll_timer.function = ia64_mca_cpe_poll;
2125 struct irq_desc *desc;
2126 unsigned int irq;
2128 if (cpe_vector >= 0) {
2129 /* If platform supports CPEI, enable the irq. */
2130 irq = local_vector_to_irq(cpe_vector);
2131 if (irq > 0) {
2132 cpe_poll_enabled = 0;
2133 desc = irq_desc + irq;
2134 desc->status |= IRQ_PER_CPU;
2135 setup_irq(irq, &mca_cpe_irqaction);
2136 ia64_cpe_irq = irq;
2137 ia64_mca_register_cpev(cpe_vector);
2138 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n",
2139 __func__);
2140 return 0;
2142 printk(KERN_ERR "%s: Failed to find irq for CPE "
2143 "interrupt handler, vector %d\n",
2144 __func__, cpe_vector);
2146 /* If platform doesn't support CPEI, get the timer going. */
2147 if (cpe_poll_enabled) {
2148 ia64_mca_cpe_poll(0UL);
2149 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __func__);
2152 #endif
2154 return 0;
2157 device_initcall(ia64_mca_late_init);