drivers/gpu/drm/radeon/radeon_asic.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_ASIC_H__
  29 #define __RADEON_ASIC_H__
  30
  31 /*
  32  * common functions
  33  */
  34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
  35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
  37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  38
  39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
  40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
  42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  44
  45 /*
  46  * r100,rv100,rs100,rv200,rs200
  47  */
  48 struct r100_mc_save {
  49         u32     GENMO_WT;
  50         u32     CRTC_EXT_CNTL;
  51         u32     CRTC_GEN_CNTL;
  52         u32     CRTC2_GEN_CNTL;
  53         u32     CUR_OFFSET;
  54         u32     CUR2_OFFSET;
  55 };
  56 int r100_init(struct radeon_device *rdev);
  57 void r100_fini(struct radeon_device *rdev);
  58 int r100_suspend(struct radeon_device *rdev);
  59 int r100_resume(struct radeon_device *rdev);
  60 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
  61 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  62 void r100_vga_set_state(struct radeon_device *rdev, bool state);
  63 bool r100_gpu_is_lockup(struct radeon_device *rdev);
  64 int r100_asic_reset(struct radeon_device *rdev);
  65 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
  66 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  67 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  68 void r100_cp_commit(struct radeon_device *rdev);
  69 void r100_ring_start(struct radeon_device *rdev);
  70 int r100_irq_set(struct radeon_device *rdev);
  71 int r100_irq_process(struct radeon_device *rdev);
  72 void r100_fence_ring_emit(struct radeon_device *rdev,
  73                           struct radeon_fence *fence);
  74 int r100_cs_parse(struct radeon_cs_parser *p);
  75 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  76 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  77 int r100_copy_blit(struct radeon_device *rdev,
  78                    uint64_t src_offset,
  79                    uint64_t dst_offset,
  80                    unsigned num_pages,
  81                    struct radeon_fence *fence);
  82 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  83                          uint32_t tiling_flags, uint32_t pitch,
  84                          uint32_t offset, uint32_t obj_size);
  85 void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
  86 void r100_bandwidth_update(struct radeon_device *rdev);
  87 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  88 int r100_ring_test(struct radeon_device *rdev);
  89 void r100_hpd_init(struct radeon_device *rdev);
  90 void r100_hpd_fini(struct radeon_device *rdev);
  91 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  92 void r100_hpd_set_polarity(struct radeon_device *rdev,
  93                            enum radeon_hpd_id hpd);
  94 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
  95 int r100_debugfs_cp_init(struct radeon_device *rdev);
  96 void r100_cp_disable(struct radeon_device *rdev);
  97 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  98 void r100_cp_fini(struct radeon_device *rdev);
  99 int r100_pci_gart_init(struct radeon_device *rdev);
 100 void r100_pci_gart_fini(struct radeon_device *rdev);
 101 int r100_pci_gart_enable(struct radeon_device *rdev);
 102 void r100_pci_gart_disable(struct radeon_device *rdev);
 103 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
 104 int r100_gui_wait_for_idle(struct radeon_device *rdev);
 105 void r100_ib_fini(struct radeon_device *rdev);
 106 int r100_ib_init(struct radeon_device *rdev);
 107 void r100_irq_disable(struct radeon_device *rdev);
 108 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
 109 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
 110 void r100_vram_init_sizes(struct radeon_device *rdev);
 111 int r100_cp_reset(struct radeon_device *rdev);
 112 void r100_vga_render_disable(struct radeon_device *rdev);
 113 void r100_restore_sanity(struct radeon_device *rdev);
 114 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
 115                                          struct radeon_cs_packet *pkt,
 116                                          struct radeon_bo *robj);
 117 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 118                           struct radeon_cs_packet *pkt,
 119                           const unsigned *auth, unsigned n,
 120                           radeon_packet0_check_t check);
 121 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 122                          struct radeon_cs_packet *pkt,
 123                          unsigned idx);
 124 void r100_enable_bm(struct radeon_device *rdev);
 125 void r100_set_common_regs(struct radeon_device *rdev);
 126 void r100_bm_disable(struct radeon_device *rdev);
 127 extern bool r100_gui_idle(struct radeon_device *rdev);
 128 extern void r100_pm_misc(struct radeon_device *rdev);
 129 extern void r100_pm_prepare(struct radeon_device *rdev);
 130 extern void r100_pm_finish(struct radeon_device *rdev);
 131 extern void r100_pm_init_profile(struct radeon_device *rdev);
 132 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
 133 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
 134 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 135 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
 136
 137 /*
 138  * r200,rv250,rs300,rv280
 139  */
 140 extern int r200_copy_dma(struct radeon_device *rdev,
 141                         uint64_t src_offset,
 142                         uint64_t dst_offset,
 143                         unsigned num_pages,
 144                          struct radeon_fence *fence);
 145
 146 /*
 147  * r300,r350,rv350,rv380
 148  */
 149 extern int r300_init(struct radeon_device *rdev);
 150 extern void r300_fini(struct radeon_device *rdev);
 151 extern int r300_suspend(struct radeon_device *rdev);
 152 extern int r300_resume(struct radeon_device *rdev);
 153 extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
 154 extern int r300_asic_reset(struct radeon_device *rdev);
 155 extern void r300_ring_start(struct radeon_device *rdev);
 156 extern void r300_fence_ring_emit(struct radeon_device *rdev,
 157                                 struct radeon_fence *fence);
 158 extern int r300_cs_parse(struct radeon_cs_parser *p);
 159 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 160 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 161 extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
 162 extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 163 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 164 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
 165
 166 /*
 167  * r420,r423,rv410
 168  */
 169 extern int r420_init(struct radeon_device *rdev);
 170 extern void r420_fini(struct radeon_device *rdev);
 171 extern int r420_suspend(struct radeon_device *rdev);
 172 extern int r420_resume(struct radeon_device *rdev);
 173 extern void r420_pm_init_profile(struct radeon_device *rdev);
 174
 175 /*
 176  * rs400,rs480
 177  */
 178 extern int rs400_init(struct radeon_device *rdev);
 179 extern void rs400_fini(struct radeon_device *rdev);
 180 extern int rs400_suspend(struct radeon_device *rdev);
 181 extern int rs400_resume(struct radeon_device *rdev);
 182 void rs400_gart_tlb_flush(struct radeon_device *rdev);
 183 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 184 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 185 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 186
 187 /*
 188  * rs600.
 189  */
 190 extern int rs600_asic_reset(struct radeon_device *rdev);
 191 extern int rs600_init(struct radeon_device *rdev);
 192 extern void rs600_fini(struct radeon_device *rdev);
 193 extern int rs600_suspend(struct radeon_device *rdev);
 194 extern int rs600_resume(struct radeon_device *rdev);
 195 int rs600_irq_set(struct radeon_device *rdev);
 196 int rs600_irq_process(struct radeon_device *rdev);
 197 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
 198 void rs600_gart_tlb_flush(struct radeon_device *rdev);
 199 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 200 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 201 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 202 void rs600_bandwidth_update(struct radeon_device *rdev);
 203 void rs600_hpd_init(struct radeon_device *rdev);
 204 void rs600_hpd_fini(struct radeon_device *rdev);
 205 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 206 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 207                             enum radeon_hpd_id hpd);
 208 extern void rs600_pm_misc(struct radeon_device *rdev);
 209 extern void rs600_pm_prepare(struct radeon_device *rdev);
 210 extern void rs600_pm_finish(struct radeon_device *rdev);
 211 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
 212 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 213 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
 214
 215 /*
 216  * rs690,rs740
 217  */
 218 int rs690_init(struct radeon_device *rdev);
 219 void rs690_fini(struct radeon_device *rdev);
 220 int rs690_resume(struct radeon_device *rdev);
 221 int rs690_suspend(struct radeon_device *rdev);
 222 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 223 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 224 void rs690_bandwidth_update(struct radeon_device *rdev);
 225
 226 /*
 227  * rv515
 228  */
 229 int rv515_init(struct radeon_device *rdev);
 230 void rv515_fini(struct radeon_device *rdev);
 231 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 232 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 233 void rv515_ring_start(struct radeon_device *rdev);
 234 uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
 235 void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 236 void rv515_bandwidth_update(struct radeon_device *rdev);
 237 int rv515_resume(struct radeon_device *rdev);
 238 int rv515_suspend(struct radeon_device *rdev);
 239
 240 /*
 241  * r520,rv530,rv560,rv570,r580
 242  */
 243 int r520_init(struct radeon_device *rdev);
 244 int r520_resume(struct radeon_device *rdev);
 245
 246 /*
 247  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
 248  */
 249 int r600_init(struct radeon_device *rdev);
 250 void r600_fini(struct radeon_device *rdev);
 251 int r600_suspend(struct radeon_device *rdev);
 252 int r600_resume(struct radeon_device *rdev);
 253 void r600_vga_set_state(struct radeon_device *rdev, bool state);
 254 int r600_wb_init(struct radeon_device *rdev);
 255 void r600_wb_fini(struct radeon_device *rdev);
 256 void r600_cp_commit(struct radeon_device *rdev);
 257 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 258 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 259 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 260 int r600_cs_parse(struct radeon_cs_parser *p);
 261 void r600_fence_ring_emit(struct radeon_device *rdev,
 262                           struct radeon_fence *fence);
 263 int r600_irq_process(struct radeon_device *rdev);
 264 int r600_irq_set(struct radeon_device *rdev);
 265 bool r600_gpu_is_lockup(struct radeon_device *rdev);
 266 int r600_asic_reset(struct radeon_device *rdev);
 267 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
 268                          uint32_t tiling_flags, uint32_t pitch,
 269                          uint32_t offset, uint32_t obj_size);
 270 void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
 271 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 272 int r600_ring_test(struct radeon_device *rdev);
 273 int r600_copy_blit(struct radeon_device *rdev,
 274                    uint64_t src_offset, uint64_t dst_offset,
 275                    unsigned num_pages, struct radeon_fence *fence);
 276 void r600_hpd_init(struct radeon_device *rdev);
 277 void r600_hpd_fini(struct radeon_device *rdev);
 278 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 279 void r600_hpd_set_polarity(struct radeon_device *rdev,
 280                            enum radeon_hpd_id hpd);
 281 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
 282 extern bool r600_gui_idle(struct radeon_device *rdev);
 283 extern void r600_pm_misc(struct radeon_device *rdev);
 284 extern void r600_pm_init_profile(struct radeon_device *rdev);
 285 extern void rs780_pm_init_profile(struct radeon_device *rdev);
 286 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
 287 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 288 extern int r600_get_pcie_lanes(struct radeon_device *rdev);
 289
 290 /*
 291  * rv770,rv730,rv710,rv740
 292  */
 293 int rv770_init(struct radeon_device *rdev);
 294 void rv770_fini(struct radeon_device *rdev);
 295 int rv770_suspend(struct radeon_device *rdev);
 296 int rv770_resume(struct radeon_device *rdev);
 297 extern void rv770_pm_misc(struct radeon_device *rdev);
 298 extern u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 299
 300 /*
 301  * evergreen
 302  */
 303 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
 304 int evergreen_init(struct radeon_device *rdev);
 305 void evergreen_fini(struct radeon_device *rdev);
 306 int evergreen_suspend(struct radeon_device *rdev);
 307 int evergreen_resume(struct radeon_device *rdev);
 308 bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
 309 int evergreen_asic_reset(struct radeon_device *rdev);
 310 void evergreen_bandwidth_update(struct radeon_device *rdev);
 311 int evergreen_copy_blit(struct radeon_device *rdev,
 312                         uint64_t src_offset, uint64_t dst_offset,
 313                         unsigned num_pages, struct radeon_fence *fence);
 314 void evergreen_hpd_init(struct radeon_device *rdev);
 315 void evergreen_hpd_fini(struct radeon_device *rdev);
 316 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 317 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 318                                 enum radeon_hpd_id hpd);
 319 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
 320 int evergreen_irq_set(struct radeon_device *rdev);
 321 int evergreen_irq_process(struct radeon_device *rdev);
 322 extern int evergreen_cs_parse(struct radeon_cs_parser *p);
 323 extern void evergreen_pm_misc(struct radeon_device *rdev);
 324 extern void evergreen_pm_prepare(struct radeon_device *rdev);
 325 extern void evergreen_pm_finish(struct radeon_device *rdev);
 326 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
 327 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
 328 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
 329
 330 #endif