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drm/radeon/kms: add pcie get/set lane support for r6xx/r7xx/evergreen
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / r300.c
blobfae5e709f270683db849c9dbce92aacca6f773fc
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include <drm/drm.h>
32 #include <drm/drm_crtc_helper.h>
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "radeon_drm.h"
37 #include "r100_track.h"
38 #include "r300d.h"
39 #include "rv350d.h"
40 #include "r300_reg_safe.h"
41
42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
43 *
44 * GPU Errata:
45 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
46 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
47 * However, scheduling such write to the ring seems harmless, i suspect
48 * the CP read collide with the flush somehow, or maybe the MC, hard to
49 * tell. (Jerome Glisse)
50 */
51
52 /*
53 * rv370,rv380 PCIE GART
54 */
55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
56
57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
58 {
59 uint32_t tmp;
60 int i;
61
62 /* Workaround HW bug do flush 2 times */
63 for (i = 0; i < 2; i++) {
64 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
65 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
66 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
67 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
68 }
69 mb();
70 }
71
72 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
73 {
74 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
75
76 if (i < 0 || i > rdev->gart.num_gpu_pages) {
77 return -EINVAL;
78 }
79 addr = (lower_32_bits(addr) >> 8) |
80 ((upper_32_bits(addr) & 0xff) << 24) |
81 0xc;
82 /* on x86 we want this to be CPU endian, on powerpc
83 * on powerpc without HW swappers, it'll get swapped on way
84 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
85 writel(addr, ((void __iomem *)ptr) + (i * 4));
86 return 0;
87 }
88
89 int rv370_pcie_gart_init(struct radeon_device *rdev)
90 {
91 int r;
92
93 if (rdev->gart.table.vram.robj) {
94 WARN(1, "RV370 PCIE GART already initialized\n");
95 return 0;
96 }
97 /* Initialize common gart structure */
98 r = radeon_gart_init(rdev);
99 if (r)
100 return r;
101 r = rv370_debugfs_pcie_gart_info_init(rdev);
102 if (r)
103 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
104 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
105 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
106 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
107 return radeon_gart_table_vram_alloc(rdev);
108 }
109
110 int rv370_pcie_gart_enable(struct radeon_device *rdev)
111 {
112 uint32_t table_addr;
113 uint32_t tmp;
114 int r;
115
116 if (rdev->gart.table.vram.robj == NULL) {
117 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
118 return -EINVAL;
119 }
120 r = radeon_gart_table_vram_pin(rdev);
121 if (r)
122 return r;
123 radeon_gart_restore(rdev);
124 /* discard memory request outside of configured range */
125 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
126 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
127 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
128 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
129 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
130 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
131 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
132 table_addr = rdev->gart.table_addr;
133 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
134 /* FIXME: setup default page */
135 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
136 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
137 /* Clear error */
138 WREG32_PCIE(0x18, 0);
139 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
140 tmp |= RADEON_PCIE_TX_GART_EN;
141 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
142 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
143 rv370_pcie_gart_tlb_flush(rdev);
144 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
145 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
146 rdev->gart.ready = true;
147 return 0;
148 }
149
150 void rv370_pcie_gart_disable(struct radeon_device *rdev)
151 {
152 u32 tmp;
153 int r;
154
155 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
156 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
157 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
158 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
159 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
160 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
161 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
162 if (rdev->gart.table.vram.robj) {
163 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
164 if (likely(r == 0)) {
165 radeon_bo_kunmap(rdev->gart.table.vram.robj);
166 radeon_bo_unpin(rdev->gart.table.vram.robj);
167 radeon_bo_unreserve(rdev->gart.table.vram.robj);
168 }
169 }
170 }
171
172 void rv370_pcie_gart_fini(struct radeon_device *rdev)
173 {
174 radeon_gart_fini(rdev);
175 rv370_pcie_gart_disable(rdev);
176 radeon_gart_table_vram_free(rdev);
177 }
178
179 void r300_fence_ring_emit(struct radeon_device *rdev,
180 struct radeon_fence *fence)
181 {
182 /* Who ever call radeon_fence_emit should call ring_lock and ask
183 * for enough space (today caller are ib schedule and buffer move) */
184 /* Write SC register so SC & US assert idle */
185 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
186 radeon_ring_write(rdev, 0);
187 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
188 radeon_ring_write(rdev, 0);
189 /* Flush 3D cache */
190 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
191 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
192 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
193 radeon_ring_write(rdev, R300_ZC_FLUSH);
194 /* Wait until IDLE & CLEAN */
195 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
196 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
197 RADEON_WAIT_2D_IDLECLEAN |
198 RADEON_WAIT_DMA_GUI_IDLE));
199 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
200 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
201 RADEON_HDP_READ_BUFFER_INVALIDATE);
202 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
203 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
204 /* Emit fence sequence & fire IRQ */
205 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
206 radeon_ring_write(rdev, fence->seq);
207 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
208 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
209 }
210
211 void r300_ring_start(struct radeon_device *rdev)
212 {
213 unsigned gb_tile_config;
214 int r;
215
216 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
217 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
218 switch(rdev->num_gb_pipes) {
219 case 2:
220 gb_tile_config |= R300_PIPE_COUNT_R300;
221 break;
222 case 3:
223 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
224 break;
225 case 4:
226 gb_tile_config |= R300_PIPE_COUNT_R420;
227 break;
228 case 1:
229 default:
230 gb_tile_config |= R300_PIPE_COUNT_RV350;
231 break;
232 }
233
234 r = radeon_ring_lock(rdev, 64);
235 if (r) {
236 return;
237 }
238 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
239 radeon_ring_write(rdev,
240 RADEON_ISYNC_ANY2D_IDLE3D |
241 RADEON_ISYNC_ANY3D_IDLE2D |
242 RADEON_ISYNC_WAIT_IDLEGUI |
243 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
244 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
245 radeon_ring_write(rdev, gb_tile_config);
246 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
247 radeon_ring_write(rdev,
248 RADEON_WAIT_2D_IDLECLEAN |
249 RADEON_WAIT_3D_IDLECLEAN);
250 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
251 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
252 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
253 radeon_ring_write(rdev, 0);
254 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
255 radeon_ring_write(rdev, 0);
256 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
257 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
258 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
259 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
260 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
261 radeon_ring_write(rdev,
262 RADEON_WAIT_2D_IDLECLEAN |
263 RADEON_WAIT_3D_IDLECLEAN);
264 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
265 radeon_ring_write(rdev, 0);
266 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
267 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
268 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
269 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
270 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
271 radeon_ring_write(rdev,
272 ((6 << R300_MS_X0_SHIFT) |
273 (6 << R300_MS_Y0_SHIFT) |
274 (6 << R300_MS_X1_SHIFT) |
275 (6 << R300_MS_Y1_SHIFT) |
276 (6 << R300_MS_X2_SHIFT) |
277 (6 << R300_MS_Y2_SHIFT) |
278 (6 << R300_MSBD0_Y_SHIFT) |
279 (6 << R300_MSBD0_X_SHIFT)));
280 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
281 radeon_ring_write(rdev,
282 ((6 << R300_MS_X3_SHIFT) |
283 (6 << R300_MS_Y3_SHIFT) |
284 (6 << R300_MS_X4_SHIFT) |
285 (6 << R300_MS_Y4_SHIFT) |
286 (6 << R300_MS_X5_SHIFT) |
287 (6 << R300_MS_Y5_SHIFT) |
288 (6 << R300_MSBD1_SHIFT)));
289 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
290 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
291 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
292 radeon_ring_write(rdev,
293 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
294 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
295 radeon_ring_write(rdev,
296 R300_GEOMETRY_ROUND_NEAREST |
297 R300_COLOR_ROUND_NEAREST);
298 radeon_ring_unlock_commit(rdev);
299 }
300
301 void r300_errata(struct radeon_device *rdev)
302 {
303 rdev->pll_errata = 0;
304
305 if (rdev->family == CHIP_R300 &&
306 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
307 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
308 }
309 }
310
311 int r300_mc_wait_for_idle(struct radeon_device *rdev)
312 {
313 unsigned i;
314 uint32_t tmp;
315
316 for (i = 0; i < rdev->usec_timeout; i++) {
317 /* read MC_STATUS */
318 tmp = RREG32(RADEON_MC_STATUS);
319 if (tmp & R300_MC_IDLE) {
320 return 0;
321 }
322 DRM_UDELAY(1);
323 }
324 return -1;
325 }
326
327 void r300_gpu_init(struct radeon_device *rdev)
328 {
329 uint32_t gb_tile_config, tmp;
330
331 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
332 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
333 /* r300,r350 */
334 rdev->num_gb_pipes = 2;
335 } else {
336 /* rv350,rv370,rv380,r300 AD, r350 AH */
337 rdev->num_gb_pipes = 1;
338 }
339 rdev->num_z_pipes = 1;
340 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
341 switch (rdev->num_gb_pipes) {
342 case 2:
343 gb_tile_config |= R300_PIPE_COUNT_R300;
344 break;
345 case 3:
346 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
347 break;
348 case 4:
349 gb_tile_config |= R300_PIPE_COUNT_R420;
350 break;
351 default:
352 case 1:
353 gb_tile_config |= R300_PIPE_COUNT_RV350;
354 break;
355 }
356 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
357
358 if (r100_gui_wait_for_idle(rdev)) {
359 printk(KERN_WARNING "Failed to wait GUI idle while "
360 "programming pipes. Bad things might happen.\n");
361 }
362
363 tmp = RREG32(R300_DST_PIPE_CONFIG);
364 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
365
366 WREG32(R300_RB2D_DSTCACHE_MODE,
367 R300_DC_AUTOFLUSH_ENABLE |
368 R300_DC_DC_DISABLE_IGNORE_PE);
369
370 if (r100_gui_wait_for_idle(rdev)) {
371 printk(KERN_WARNING "Failed to wait GUI idle while "
372 "programming pipes. Bad things might happen.\n");
373 }
374 if (r300_mc_wait_for_idle(rdev)) {
375 printk(KERN_WARNING "Failed to wait MC idle while "
376 "programming pipes. Bad things might happen.\n");
377 }
378 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
379 rdev->num_gb_pipes, rdev->num_z_pipes);
380 }
381
382 bool r300_gpu_is_lockup(struct radeon_device *rdev)
383 {
384 u32 rbbm_status;
385 int r;
386
387 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
388 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
389 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
390 return false;
391 }
392 /* force CP activities */
393 r = radeon_ring_lock(rdev, 2);
394 if (!r) {
395 /* PACKET2 NOP */
396 radeon_ring_write(rdev, 0x80000000);
397 radeon_ring_write(rdev, 0x80000000);
398 radeon_ring_unlock_commit(rdev);
399 }
400 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
401 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
402 }
403
404 int r300_asic_reset(struct radeon_device *rdev)
405 {
406 struct r100_mc_save save;
407 u32 status, tmp;
408
409 r100_mc_stop(rdev, &save);
410 status = RREG32(R_000E40_RBBM_STATUS);
411 if (!G_000E40_GUI_ACTIVE(status)) {
412 return 0;
413 }
414 status = RREG32(R_000E40_RBBM_STATUS);
415 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
416 /* stop CP */
417 WREG32(RADEON_CP_CSQ_CNTL, 0);
418 tmp = RREG32(RADEON_CP_RB_CNTL);
419 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
420 WREG32(RADEON_CP_RB_RPTR_WR, 0);
421 WREG32(RADEON_CP_RB_WPTR, 0);
422 WREG32(RADEON_CP_RB_CNTL, tmp);
423 /* save PCI state */
424 pci_save_state(rdev->pdev);
425 /* disable bus mastering */
426 r100_bm_disable(rdev);
427 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
428 S_0000F0_SOFT_RESET_GA(1));
429 RREG32(R_0000F0_RBBM_SOFT_RESET);
430 mdelay(500);
431 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
432 mdelay(1);
433 status = RREG32(R_000E40_RBBM_STATUS);
434 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
435 /* resetting the CP seems to be problematic sometimes it end up
436 * hard locking the computer, but it's necessary for successfull
437 * reset more test & playing is needed on R3XX/R4XX to find a
438 * reliable (if any solution)
439 */
440 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
441 RREG32(R_0000F0_RBBM_SOFT_RESET);
442 mdelay(500);
443 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
444 mdelay(1);
445 status = RREG32(R_000E40_RBBM_STATUS);
446 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
447 /* restore PCI & busmastering */
448 pci_restore_state(rdev->pdev);
449 r100_enable_bm(rdev);
450 /* Check if GPU is idle */
451 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
452 dev_err(rdev->dev, "failed to reset GPU\n");
453 rdev->gpu_lockup = true;
454 return -1;
455 }
456 r100_mc_resume(rdev, &save);
457 dev_info(rdev->dev, "GPU reset succeed\n");
458 return 0;
459 }
460
461 /*
462 * r300,r350,rv350,rv380 VRAM info
463 */
464 void r300_mc_init(struct radeon_device *rdev)
465 {
466 u64 base;
467 u32 tmp;
468
469 /* DDR for all card after R300 & IGP */
470 rdev->mc.vram_is_ddr = true;
471 tmp = RREG32(RADEON_MEM_CNTL);
472 tmp &= R300_MEM_NUM_CHANNELS_MASK;
473 switch (tmp) {
474 case 0: rdev->mc.vram_width = 64; break;
475 case 1: rdev->mc.vram_width = 128; break;
476 case 2: rdev->mc.vram_width = 256; break;
477 default: rdev->mc.vram_width = 128; break;
478 }
479 r100_vram_init_sizes(rdev);
480 base = rdev->mc.aper_base;
481 if (rdev->flags & RADEON_IS_IGP)
482 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
483 radeon_vram_location(rdev, &rdev->mc, base);
484 rdev->mc.gtt_base_align = 0;
485 if (!(rdev->flags & RADEON_IS_AGP))
486 radeon_gtt_location(rdev, &rdev->mc);
487 radeon_update_bandwidth_info(rdev);
488 }
489
490 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
491 {
492 uint32_t link_width_cntl, mask;
493
494 if (rdev->flags & RADEON_IS_IGP)
495 return;
496
497 if (!(rdev->flags & RADEON_IS_PCIE))
498 return;
499
500 /* FIXME wait for idle */
501
502 switch (lanes) {
503 case 0:
504 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
505 break;
506 case 1:
507 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
508 break;
509 case 2:
510 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
511 break;
512 case 4:
513 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
514 break;
515 case 8:
516 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
517 break;
518 case 12:
519 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
520 break;
521 case 16:
522 default:
523 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
524 break;
525 }
526
527 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
528
529 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
530 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
531 return;
532
533 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
534 RADEON_PCIE_LC_RECONFIG_NOW |
535 RADEON_PCIE_LC_RECONFIG_LATER |
536 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
537 link_width_cntl |= mask;
538 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
539 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
540 RADEON_PCIE_LC_RECONFIG_NOW));
541
542 /* wait for lane set to complete */
543 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
544 while (link_width_cntl == 0xffffffff)
545 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
546
547 }
548
549 int rv370_get_pcie_lanes(struct radeon_device *rdev)
550 {
551 u32 link_width_cntl;
552
553 if (rdev->flags & RADEON_IS_IGP)
554 return 0;
555
556 if (!(rdev->flags & RADEON_IS_PCIE))
557 return 0;
558
559 /* FIXME wait for idle */
560
561 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
562
563 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
564 case RADEON_PCIE_LC_LINK_WIDTH_X0:
565 return 0;
566 case RADEON_PCIE_LC_LINK_WIDTH_X1:
567 return 1;
568 case RADEON_PCIE_LC_LINK_WIDTH_X2:
569 return 2;
570 case RADEON_PCIE_LC_LINK_WIDTH_X4:
571 return 4;
572 case RADEON_PCIE_LC_LINK_WIDTH_X8:
573 return 8;
574 case RADEON_PCIE_LC_LINK_WIDTH_X16:
575 default:
576 return 16;
577 }
578 }
579
580 #if defined(CONFIG_DEBUG_FS)
581 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
582 {
583 struct drm_info_node *node = (struct drm_info_node *) m->private;
584 struct drm_device *dev = node->minor->dev;
585 struct radeon_device *rdev = dev->dev_private;
586 uint32_t tmp;
587
588 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
589 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
590 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
591 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
592 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
593 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
594 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
595 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
597 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
598 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
599 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
600 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
601 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
602 return 0;
603 }
604
605 static struct drm_info_list rv370_pcie_gart_info_list[] = {
606 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
607 };
608 #endif
609
610 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
611 {
612 #if defined(CONFIG_DEBUG_FS)
613 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
614 #else
615 return 0;
616 #endif
617 }
618
619 static int r300_packet0_check(struct radeon_cs_parser *p,
620 struct radeon_cs_packet *pkt,
621 unsigned idx, unsigned reg)
622 {
623 struct radeon_cs_reloc *reloc;
624 struct r100_cs_track *track;
625 volatile uint32_t *ib;
626 uint32_t tmp, tile_flags = 0;
627 unsigned i;
628 int r;
629 u32 idx_value;
630
631 ib = p->ib->ptr;
632 track = (struct r100_cs_track *)p->track;
633 idx_value = radeon_get_ib_value(p, idx);
634
635 switch(reg) {
636 case AVIVO_D1MODE_VLINE_START_END:
637 case RADEON_CRTC_GUI_TRIG_VLINE:
638 r = r100_cs_packet_parse_vline(p);
639 if (r) {
640 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
641 idx, reg);
642 r100_cs_dump_packet(p, pkt);
643 return r;
644 }
645 break;
646 case RADEON_DST_PITCH_OFFSET:
647 case RADEON_SRC_PITCH_OFFSET:
648 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
649 if (r)
650 return r;
651 break;
652 case R300_RB3D_COLOROFFSET0:
653 case R300_RB3D_COLOROFFSET1:
654 case R300_RB3D_COLOROFFSET2:
655 case R300_RB3D_COLOROFFSET3:
656 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
657 r = r100_cs_packet_next_reloc(p, &reloc);
658 if (r) {
659 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
660 idx, reg);
661 r100_cs_dump_packet(p, pkt);
662 return r;
663 }
664 track->cb[i].robj = reloc->robj;
665 track->cb[i].offset = idx_value;
666 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
667 break;
668 case R300_ZB_DEPTHOFFSET:
669 r = r100_cs_packet_next_reloc(p, &reloc);
670 if (r) {
671 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
672 idx, reg);
673 r100_cs_dump_packet(p, pkt);
674 return r;
675 }
676 track->zb.robj = reloc->robj;
677 track->zb.offset = idx_value;
678 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
679 break;
680 case R300_TX_OFFSET_0:
681 case R300_TX_OFFSET_0+4:
682 case R300_TX_OFFSET_0+8:
683 case R300_TX_OFFSET_0+12:
684 case R300_TX_OFFSET_0+16:
685 case R300_TX_OFFSET_0+20:
686 case R300_TX_OFFSET_0+24:
687 case R300_TX_OFFSET_0+28:
688 case R300_TX_OFFSET_0+32:
689 case R300_TX_OFFSET_0+36:
690 case R300_TX_OFFSET_0+40:
691 case R300_TX_OFFSET_0+44:
692 case R300_TX_OFFSET_0+48:
693 case R300_TX_OFFSET_0+52:
694 case R300_TX_OFFSET_0+56:
695 case R300_TX_OFFSET_0+60:
696 i = (reg - R300_TX_OFFSET_0) >> 2;
697 r = r100_cs_packet_next_reloc(p, &reloc);
698 if (r) {
699 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
700 idx, reg);
701 r100_cs_dump_packet(p, pkt);
702 return r;
703 }
704
705 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
706 tile_flags |= R300_TXO_MACRO_TILE;
707 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
708 tile_flags |= R300_TXO_MICRO_TILE;
709 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
710 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
711
712 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
713 tmp |= tile_flags;
714 ib[idx] = tmp;
715 track->textures[i].robj = reloc->robj;
716 break;
717 /* Tracked registers */
718 case 0x2084:
719 /* VAP_VF_CNTL */
720 track->vap_vf_cntl = idx_value;
721 break;
722 case 0x20B4:
723 /* VAP_VTX_SIZE */
724 track->vtx_size = idx_value & 0x7F;
725 break;
726 case 0x2134:
727 /* VAP_VF_MAX_VTX_INDX */
728 track->max_indx = idx_value & 0x00FFFFFFUL;
729 break;
730 case 0x2088:
731 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
732 if (p->rdev->family < CHIP_RV515)
733 goto fail;
734 track->vap_alt_nverts = idx_value & 0xFFFFFF;
735 break;
736 case 0x43E4:
737 /* SC_SCISSOR1 */
738 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
739 if (p->rdev->family < CHIP_RV515) {
740 track->maxy -= 1440;
741 }
742 break;
743 case 0x4E00:
744 /* RB3D_CCTL */
745 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
746 p->rdev->cmask_filp != p->filp) {
747 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
748 return -EINVAL;
749 }
750 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
751 break;
752 case 0x4E38:
753 case 0x4E3C:
754 case 0x4E40:
755 case 0x4E44:
756 /* RB3D_COLORPITCH0 */
757 /* RB3D_COLORPITCH1 */
758 /* RB3D_COLORPITCH2 */
759 /* RB3D_COLORPITCH3 */
760 r = r100_cs_packet_next_reloc(p, &reloc);
761 if (r) {
762 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
763 idx, reg);
764 r100_cs_dump_packet(p, pkt);
765 return r;
766 }
767
768 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
769 tile_flags |= R300_COLOR_TILE_ENABLE;
770 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
771 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
772 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
773 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
774
775 tmp = idx_value & ~(0x7 << 16);
776 tmp |= tile_flags;
777 ib[idx] = tmp;
778 i = (reg - 0x4E38) >> 2;
779 track->cb[i].pitch = idx_value & 0x3FFE;
780 switch (((idx_value >> 21) & 0xF)) {
781 case 9:
782 case 11:
783 case 12:
784 track->cb[i].cpp = 1;
785 break;
786 case 3:
787 case 4:
788 case 13:
789 case 15:
790 track->cb[i].cpp = 2;
791 break;
792 case 5:
793 if (p->rdev->family < CHIP_RV515) {
794 DRM_ERROR("Invalid color buffer format (%d)!\n",
795 ((idx_value >> 21) & 0xF));
796 return -EINVAL;
797 }
798 /* Pass through. */
799 case 6:
800 track->cb[i].cpp = 4;
801 break;
802 case 10:
803 track->cb[i].cpp = 8;
804 break;
805 case 7:
806 track->cb[i].cpp = 16;
807 break;
808 default:
809 DRM_ERROR("Invalid color buffer format (%d) !\n",
810 ((idx_value >> 21) & 0xF));
811 return -EINVAL;
812 }
813 break;
814 case 0x4F00:
815 /* ZB_CNTL */
816 if (idx_value & 2) {
817 track->z_enabled = true;
818 } else {
819 track->z_enabled = false;
820 }
821 break;
822 case 0x4F10:
823 /* ZB_FORMAT */
824 switch ((idx_value & 0xF)) {
825 case 0:
826 case 1:
827 track->zb.cpp = 2;
828 break;
829 case 2:
830 track->zb.cpp = 4;
831 break;
832 default:
833 DRM_ERROR("Invalid z buffer format (%d) !\n",
834 (idx_value & 0xF));
835 return -EINVAL;
836 }
837 break;
838 case 0x4F24:
839 /* ZB_DEPTHPITCH */
840 r = r100_cs_packet_next_reloc(p, &reloc);
841 if (r) {
842 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
843 idx, reg);
844 r100_cs_dump_packet(p, pkt);
845 return r;
846 }
847
848 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
849 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
850 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
851 tile_flags |= R300_DEPTHMICROTILE_TILED;
852 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
853 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
854
855 tmp = idx_value & ~(0x7 << 16);
856 tmp |= tile_flags;
857 ib[idx] = tmp;
858
859 track->zb.pitch = idx_value & 0x3FFC;
860 break;
861 case 0x4104:
862 for (i = 0; i < 16; i++) {
863 bool enabled;
864
865 enabled = !!(idx_value & (1 << i));
866 track->textures[i].enabled = enabled;
867 }
868 break;
869 case 0x44C0:
870 case 0x44C4:
871 case 0x44C8:
872 case 0x44CC:
873 case 0x44D0:
874 case 0x44D4:
875 case 0x44D8:
876 case 0x44DC:
877 case 0x44E0:
878 case 0x44E4:
879 case 0x44E8:
880 case 0x44EC:
881 case 0x44F0:
882 case 0x44F4:
883 case 0x44F8:
884 case 0x44FC:
885 /* TX_FORMAT1_[0-15] */
886 i = (reg - 0x44C0) >> 2;
887 tmp = (idx_value >> 25) & 0x3;
888 track->textures[i].tex_coord_type = tmp;
889 switch ((idx_value & 0x1F)) {
890 case R300_TX_FORMAT_X8:
891 case R300_TX_FORMAT_Y4X4:
892 case R300_TX_FORMAT_Z3Y3X2:
893 track->textures[i].cpp = 1;
894 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
895 break;
896 case R300_TX_FORMAT_X16:
897 case R300_TX_FORMAT_Y8X8:
898 case R300_TX_FORMAT_Z5Y6X5:
899 case R300_TX_FORMAT_Z6Y5X5:
900 case R300_TX_FORMAT_W4Z4Y4X4:
901 case R300_TX_FORMAT_W1Z5Y5X5:
902 case R300_TX_FORMAT_D3DMFT_CxV8U8:
903 case R300_TX_FORMAT_B8G8_B8G8:
904 case R300_TX_FORMAT_G8R8_G8B8:
905 track->textures[i].cpp = 2;
906 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
907 break;
908 case R300_TX_FORMAT_Y16X16:
909 case R300_TX_FORMAT_Z11Y11X10:
910 case R300_TX_FORMAT_Z10Y11X11:
911 case R300_TX_FORMAT_W8Z8Y8X8:
912 case R300_TX_FORMAT_W2Z10Y10X10:
913 case 0x17:
914 case R300_TX_FORMAT_FL_I32:
915 case 0x1e:
916 track->textures[i].cpp = 4;
917 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
918 break;
919 case R300_TX_FORMAT_W16Z16Y16X16:
920 case R300_TX_FORMAT_FL_R16G16B16A16:
921 case R300_TX_FORMAT_FL_I32A32:
922 track->textures[i].cpp = 8;
923 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
924 break;
925 case R300_TX_FORMAT_FL_R32G32B32A32:
926 track->textures[i].cpp = 16;
927 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
928 break;
929 case R300_TX_FORMAT_DXT1:
930 track->textures[i].cpp = 1;
931 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
932 break;
933 case R300_TX_FORMAT_ATI2N:
934 if (p->rdev->family < CHIP_R420) {
935 DRM_ERROR("Invalid texture format %u\n",
936 (idx_value & 0x1F));
937 return -EINVAL;
938 }
939 /* The same rules apply as for DXT3/5. */
940 /* Pass through. */
941 case R300_TX_FORMAT_DXT3:
942 case R300_TX_FORMAT_DXT5:
943 track->textures[i].cpp = 1;
944 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
945 break;
946 default:
947 DRM_ERROR("Invalid texture format %u\n",
948 (idx_value & 0x1F));
949 return -EINVAL;
950 break;
951 }
952 break;
953 case 0x4400:
954 case 0x4404:
955 case 0x4408:
956 case 0x440C:
957 case 0x4410:
958 case 0x4414:
959 case 0x4418:
960 case 0x441C:
961 case 0x4420:
962 case 0x4424:
963 case 0x4428:
964 case 0x442C:
965 case 0x4430:
966 case 0x4434:
967 case 0x4438:
968 case 0x443C:
969 /* TX_FILTER0_[0-15] */
970 i = (reg - 0x4400) >> 2;
971 tmp = idx_value & 0x7;
972 if (tmp == 2 || tmp == 4 || tmp == 6) {
973 track->textures[i].roundup_w = false;
974 }
975 tmp = (idx_value >> 3) & 0x7;
976 if (tmp == 2 || tmp == 4 || tmp == 6) {
977 track->textures[i].roundup_h = false;
978 }
979 break;
980 case 0x4500:
981 case 0x4504:
982 case 0x4508:
983 case 0x450C:
984 case 0x4510:
985 case 0x4514:
986 case 0x4518:
987 case 0x451C:
988 case 0x4520:
989 case 0x4524:
990 case 0x4528:
991 case 0x452C:
992 case 0x4530:
993 case 0x4534:
994 case 0x4538:
995 case 0x453C:
996 /* TX_FORMAT2_[0-15] */
997 i = (reg - 0x4500) >> 2;
998 tmp = idx_value & 0x3FFF;
999 track->textures[i].pitch = tmp + 1;
1000 if (p->rdev->family >= CHIP_RV515) {
1001 tmp = ((idx_value >> 15) & 1) << 11;
1002 track->textures[i].width_11 = tmp;
1003 tmp = ((idx_value >> 16) & 1) << 11;
1004 track->textures[i].height_11 = tmp;
1005
1006 /* ATI1N */
1007 if (idx_value & (1 << 14)) {
1008 /* The same rules apply as for DXT1. */
1009 track->textures[i].compress_format =
1010 R100_TRACK_COMP_DXT1;
1011 }
1012 } else if (idx_value & (1 << 14)) {
1013 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1014 return -EINVAL;
1015 }
1016 break;
1017 case 0x4480:
1018 case 0x4484:
1019 case 0x4488:
1020 case 0x448C:
1021 case 0x4490:
1022 case 0x4494:
1023 case 0x4498:
1024 case 0x449C:
1025 case 0x44A0:
1026 case 0x44A4:
1027 case 0x44A8:
1028 case 0x44AC:
1029 case 0x44B0:
1030 case 0x44B4:
1031 case 0x44B8:
1032 case 0x44BC:
1033 /* TX_FORMAT0_[0-15] */
1034 i = (reg - 0x4480) >> 2;
1035 tmp = idx_value & 0x7FF;
1036 track->textures[i].width = tmp + 1;
1037 tmp = (idx_value >> 11) & 0x7FF;
1038 track->textures[i].height = tmp + 1;
1039 tmp = (idx_value >> 26) & 0xF;
1040 track->textures[i].num_levels = tmp;
1041 tmp = idx_value & (1 << 31);
1042 track->textures[i].use_pitch = !!tmp;
1043 tmp = (idx_value >> 22) & 0xF;
1044 track->textures[i].txdepth = tmp;
1045 break;
1046 case R300_ZB_ZPASS_ADDR:
1047 r = r100_cs_packet_next_reloc(p, &reloc);
1048 if (r) {
1049 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1050 idx, reg);
1051 r100_cs_dump_packet(p, pkt);
1052 return r;
1053 }
1054 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1055 break;
1056 case 0x4e0c:
1057 /* RB3D_COLOR_CHANNEL_MASK */
1058 track->color_channel_mask = idx_value;
1059 break;
1060 case 0x43a4:
1061 /* SC_HYPERZ_EN */
1062 /* r300c emits this register - we need to disable hyperz for it
1063 * without complaining */
1064 if (p->rdev->hyperz_filp != p->filp) {
1065 if (idx_value & 0x1)
1066 ib[idx] = idx_value & ~1;
1067 }
1068 break;
1069 case 0x4f1c:
1070 /* ZB_BW_CNTL */
1071 track->zb_cb_clear = !!(idx_value & (1 << 5));
1072 if (p->rdev->hyperz_filp != p->filp) {
1073 if (idx_value & (R300_HIZ_ENABLE |
1074 R300_RD_COMP_ENABLE |
1075 R300_WR_COMP_ENABLE |
1076 R300_FAST_FILL_ENABLE))
1077 goto fail;
1078 }
1079 break;
1080 case 0x4e04:
1081 /* RB3D_BLENDCNTL */
1082 track->blend_read_enable = !!(idx_value & (1 << 2));
1083 break;
1084 case 0x4f28: /* ZB_DEPTHCLEARVALUE */
1085 break;
1086 case 0x4f30: /* ZB_MASK_OFFSET */
1087 case 0x4f34: /* ZB_ZMASK_PITCH */
1088 case 0x4f44: /* ZB_HIZ_OFFSET */
1089 case 0x4f54: /* ZB_HIZ_PITCH */
1090 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1091 goto fail;
1092 break;
1093 case 0x4028:
1094 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1095 goto fail;
1096 /* GB_Z_PEQ_CONFIG */
1097 if (p->rdev->family >= CHIP_RV350)
1098 break;
1099 goto fail;
1100 break;
1101 case 0x4be8:
1102 /* valid register only on RV530 */
1103 if (p->rdev->family == CHIP_RV530)
1104 break;
1105 /* fallthrough do not move */
1106 default:
1107 goto fail;
1108 }
1109 return 0;
1110 fail:
1111 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1112 reg, idx, idx_value);
1113 return -EINVAL;
1114 }
1115
1116 static int r300_packet3_check(struct radeon_cs_parser *p,
1117 struct radeon_cs_packet *pkt)
1118 {
1119 struct radeon_cs_reloc *reloc;
1120 struct r100_cs_track *track;
1121 volatile uint32_t *ib;
1122 unsigned idx;
1123 int r;
1124
1125 ib = p->ib->ptr;
1126 idx = pkt->idx + 1;
1127 track = (struct r100_cs_track *)p->track;
1128 switch(pkt->opcode) {
1129 case PACKET3_3D_LOAD_VBPNTR:
1130 r = r100_packet3_load_vbpntr(p, pkt, idx);
1131 if (r)
1132 return r;
1133 break;
1134 case PACKET3_INDX_BUFFER:
1135 r = r100_cs_packet_next_reloc(p, &reloc);
1136 if (r) {
1137 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1138 r100_cs_dump_packet(p, pkt);
1139 return r;
1140 }
1141 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1142 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1143 if (r) {
1144 return r;
1145 }
1146 break;
1147 /* Draw packet */
1148 case PACKET3_3D_DRAW_IMMD:
1149 /* Number of dwords is vtx_size * (num_vertices - 1)
1150 * PRIM_WALK must be equal to 3 vertex data in embedded
1151 * in cmd stream */
1152 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1153 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1154 return -EINVAL;
1155 }
1156 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1157 track->immd_dwords = pkt->count - 1;
1158 r = r100_cs_track_check(p->rdev, track);
1159 if (r) {
1160 return r;
1161 }
1162 break;
1163 case PACKET3_3D_DRAW_IMMD_2:
1164 /* Number of dwords is vtx_size * (num_vertices - 1)
1165 * PRIM_WALK must be equal to 3 vertex data in embedded
1166 * in cmd stream */
1167 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1168 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1169 return -EINVAL;
1170 }
1171 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1172 track->immd_dwords = pkt->count;
1173 r = r100_cs_track_check(p->rdev, track);
1174 if (r) {
1175 return r;
1176 }
1177 break;
1178 case PACKET3_3D_DRAW_VBUF:
1179 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1180 r = r100_cs_track_check(p->rdev, track);
1181 if (r) {
1182 return r;
1183 }
1184 break;
1185 case PACKET3_3D_DRAW_VBUF_2:
1186 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1187 r = r100_cs_track_check(p->rdev, track);
1188 if (r) {
1189 return r;
1190 }
1191 break;
1192 case PACKET3_3D_DRAW_INDX:
1193 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1194 r = r100_cs_track_check(p->rdev, track);
1195 if (r) {
1196 return r;
1197 }
1198 break;
1199 case PACKET3_3D_DRAW_INDX_2:
1200 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1201 r = r100_cs_track_check(p->rdev, track);
1202 if (r) {
1203 return r;
1204 }
1205 break;
1206 case PACKET3_3D_CLEAR_HIZ:
1207 case PACKET3_3D_CLEAR_ZMASK:
1208 if (p->rdev->hyperz_filp != p->filp)
1209 return -EINVAL;
1210 break;
1211 case PACKET3_3D_CLEAR_CMASK:
1212 if (p->rdev->cmask_filp != p->filp)
1213 return -EINVAL;
1214 break;
1215 case PACKET3_NOP:
1216 break;
1217 default:
1218 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1219 return -EINVAL;
1220 }
1221 return 0;
1222 }
1223
1224 int r300_cs_parse(struct radeon_cs_parser *p)
1225 {
1226 struct radeon_cs_packet pkt;
1227 struct r100_cs_track *track;
1228 int r;
1229
1230 track = kzalloc(sizeof(*track), GFP_KERNEL);
1231 if (track == NULL)
1232 return -ENOMEM;
1233 r100_cs_track_clear(p->rdev, track);
1234 p->track = track;
1235 do {
1236 r = r100_cs_packet_parse(p, &pkt, p->idx);
1237 if (r) {
1238 return r;
1239 }
1240 p->idx += pkt.count + 2;
1241 switch (pkt.type) {
1242 case PACKET_TYPE0:
1243 r = r100_cs_parse_packet0(p, &pkt,
1244 p->rdev->config.r300.reg_safe_bm,
1245 p->rdev->config.r300.reg_safe_bm_size,
1246 &r300_packet0_check);
1247 break;
1248 case PACKET_TYPE2:
1249 break;
1250 case PACKET_TYPE3:
1251 r = r300_packet3_check(p, &pkt);
1252 break;
1253 default:
1254 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1255 return -EINVAL;
1256 }
1257 if (r) {
1258 return r;
1259 }
1260 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1261 return 0;
1262 }
1263
1264 void r300_set_reg_safe(struct radeon_device *rdev)
1265 {
1266 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1267 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1268 }
1269
1270 void r300_mc_program(struct radeon_device *rdev)
1271 {
1272 struct r100_mc_save save;
1273 int r;
1274
1275 r = r100_debugfs_mc_info_init(rdev);
1276 if (r) {
1277 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1278 }
1279
1280 /* Stops all mc clients */
1281 r100_mc_stop(rdev, &save);
1282 if (rdev->flags & RADEON_IS_AGP) {
1283 WREG32(R_00014C_MC_AGP_LOCATION,
1284 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1285 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1286 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1287 WREG32(R_00015C_AGP_BASE_2,
1288 upper_32_bits(rdev->mc.agp_base) & 0xff);
1289 } else {
1290 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1291 WREG32(R_000170_AGP_BASE, 0);
1292 WREG32(R_00015C_AGP_BASE_2, 0);
1293 }
1294 /* Wait for mc idle */
1295 if (r300_mc_wait_for_idle(rdev))
1296 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1297 /* Program MC, should be a 32bits limited address space */
1298 WREG32(R_000148_MC_FB_LOCATION,
1299 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1300 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1301 r100_mc_resume(rdev, &save);
1302 }
1303
1304 void r300_clock_startup(struct radeon_device *rdev)
1305 {
1306 u32 tmp;
1307
1308 if (radeon_dynclks != -1 && radeon_dynclks)
1309 radeon_legacy_set_clock_gating(rdev, 1);
1310 /* We need to force on some of the block */
1311 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1312 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1313 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1314 tmp |= S_00000D_FORCE_VAP(1);
1315 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1316 }
1317
1318 static int r300_startup(struct radeon_device *rdev)
1319 {
1320 int r;
1321
1322 /* set common regs */
1323 r100_set_common_regs(rdev);
1324 /* program mc */
1325 r300_mc_program(rdev);
1326 /* Resume clock */
1327 r300_clock_startup(rdev);
1328 /* Initialize GPU configuration (# pipes, ...) */
1329 r300_gpu_init(rdev);
1330 /* Initialize GART (initialize after TTM so we can allocate
1331 * memory through TTM but finalize after TTM) */
1332 if (rdev->flags & RADEON_IS_PCIE) {
1333 r = rv370_pcie_gart_enable(rdev);
1334 if (r)
1335 return r;
1336 }
1337
1338 if (rdev->family == CHIP_R300 ||
1339 rdev->family == CHIP_R350 ||
1340 rdev->family == CHIP_RV350)
1341 r100_enable_bm(rdev);
1342
1343 if (rdev->flags & RADEON_IS_PCI) {
1344 r = r100_pci_gart_enable(rdev);
1345 if (r)
1346 return r;
1347 }
1348
1349 /* allocate wb buffer */
1350 r = radeon_wb_init(rdev);
1351 if (r)
1352 return r;
1353
1354 /* Enable IRQ */
1355 r100_irq_set(rdev);
1356 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1357 /* 1M ring buffer */
1358 r = r100_cp_init(rdev, 1024 * 1024);
1359 if (r) {
1360 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1361 return r;
1362 }
1363 r = r100_ib_init(rdev);
1364 if (r) {
1365 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1366 return r;
1367 }
1368 return 0;
1369 }
1370
1371 int r300_resume(struct radeon_device *rdev)
1372 {
1373 /* Make sur GART are not working */
1374 if (rdev->flags & RADEON_IS_PCIE)
1375 rv370_pcie_gart_disable(rdev);
1376 if (rdev->flags & RADEON_IS_PCI)
1377 r100_pci_gart_disable(rdev);
1378 /* Resume clock before doing reset */
1379 r300_clock_startup(rdev);
1380 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1381 if (radeon_asic_reset(rdev)) {
1382 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1383 RREG32(R_000E40_RBBM_STATUS),
1384 RREG32(R_0007C0_CP_STAT));
1385 }
1386 /* post */
1387 radeon_combios_asic_init(rdev->ddev);
1388 /* Resume clock after posting */
1389 r300_clock_startup(rdev);
1390 /* Initialize surface registers */
1391 radeon_surface_init(rdev);
1392 return r300_startup(rdev);
1393 }
1394
1395 int r300_suspend(struct radeon_device *rdev)
1396 {
1397 r100_cp_disable(rdev);
1398 radeon_wb_disable(rdev);
1399 r100_irq_disable(rdev);
1400 if (rdev->flags & RADEON_IS_PCIE)
1401 rv370_pcie_gart_disable(rdev);
1402 if (rdev->flags & RADEON_IS_PCI)
1403 r100_pci_gart_disable(rdev);
1404 return 0;
1405 }
1406
1407 void r300_fini(struct radeon_device *rdev)
1408 {
1409 r100_cp_fini(rdev);
1410 radeon_wb_fini(rdev);
1411 r100_ib_fini(rdev);
1412 radeon_gem_fini(rdev);
1413 if (rdev->flags & RADEON_IS_PCIE)
1414 rv370_pcie_gart_fini(rdev);
1415 if (rdev->flags & RADEON_IS_PCI)
1416 r100_pci_gart_fini(rdev);
1417 radeon_agp_fini(rdev);
1418 radeon_irq_kms_fini(rdev);
1419 radeon_fence_driver_fini(rdev);
1420 radeon_bo_fini(rdev);
1421 radeon_atombios_fini(rdev);
1422 kfree(rdev->bios);
1423 rdev->bios = NULL;
1424 }
1425
1426 int r300_init(struct radeon_device *rdev)
1427 {
1428 int r;
1429
1430 /* Disable VGA */
1431 r100_vga_render_disable(rdev);
1432 /* Initialize scratch registers */
1433 radeon_scratch_init(rdev);
1434 /* Initialize surface registers */
1435 radeon_surface_init(rdev);
1436 /* TODO: disable VGA need to use VGA request */
1437 /* restore some register to sane defaults */
1438 r100_restore_sanity(rdev);
1439 /* BIOS*/
1440 if (!radeon_get_bios(rdev)) {
1441 if (ASIC_IS_AVIVO(rdev))
1442 return -EINVAL;
1443 }
1444 if (rdev->is_atom_bios) {
1445 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1446 return -EINVAL;
1447 } else {
1448 r = radeon_combios_init(rdev);
1449 if (r)
1450 return r;
1451 }
1452 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1453 if (radeon_asic_reset(rdev)) {
1454 dev_warn(rdev->dev,
1455 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1456 RREG32(R_000E40_RBBM_STATUS),
1457 RREG32(R_0007C0_CP_STAT));
1458 }
1459 /* check if cards are posted or not */
1460 if (radeon_boot_test_post_card(rdev) == false)
1461 return -EINVAL;
1462 /* Set asic errata */
1463 r300_errata(rdev);
1464 /* Initialize clocks */
1465 radeon_get_clock_info(rdev->ddev);
1466 /* initialize AGP */
1467 if (rdev->flags & RADEON_IS_AGP) {
1468 r = radeon_agp_init(rdev);
1469 if (r) {
1470 radeon_agp_disable(rdev);
1471 }
1472 }
1473 /* initialize memory controller */
1474 r300_mc_init(rdev);
1475 /* Fence driver */
1476 r = radeon_fence_driver_init(rdev);
1477 if (r)
1478 return r;
1479 r = radeon_irq_kms_init(rdev);
1480 if (r)
1481 return r;
1482 /* Memory manager */
1483 r = radeon_bo_init(rdev);
1484 if (r)
1485 return r;
1486 if (rdev->flags & RADEON_IS_PCIE) {
1487 r = rv370_pcie_gart_init(rdev);
1488 if (r)
1489 return r;
1490 }
1491 if (rdev->flags & RADEON_IS_PCI) {
1492 r = r100_pci_gart_init(rdev);
1493 if (r)
1494 return r;
1495 }
1496 r300_set_reg_safe(rdev);
1497 rdev->accel_working = true;
1498 r = r300_startup(rdev);
1499 if (r) {
1500 /* Somethings want wront with the accel init stop accel */
1501 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1502 r100_cp_fini(rdev);
1503 radeon_wb_fini(rdev);
1504 r100_ib_fini(rdev);
1505 radeon_irq_kms_fini(rdev);
1506 if (rdev->flags & RADEON_IS_PCIE)
1507 rv370_pcie_gart_fini(rdev);
1508 if (rdev->flags & RADEON_IS_PCI)
1509 r100_pci_gart_fini(rdev);
1510 radeon_agp_fini(rdev);
1511 rdev->accel_working = false;
1512 }
1513 return 0;
1514 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree