include/asm-ia64/pal.h

   1 #ifndef _ASM_IA64_PAL_H
   2 #define _ASM_IA64_PAL_H
   3
   4 /*
   5  * Processor Abstraction Layer definitions.
   6  *
   7  * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
   8  * chapter 11 IA-64 Processor Abstraction Layer
   9  *
  10  * Copyright (C) 1998-2001 Hewlett-Packard Co
  11  *      David Mosberger-Tang <davidm@hpl.hp.com>
  12  *      Stephane Eranian <eranian@hpl.hp.com>
  13  * Copyright (C) 1999 VA Linux Systems
  14  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  15  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
  16  *
  17  * 99/10/01     davidm  Make sure we pass zero for reserved parameters.
  18  * 00/03/07     davidm  Updated pal_cache_flush() to be in sync with PAL v2.6.
  19  * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
  20  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
  21  * 00/05/25     eranian Support for stack calls, and static physical calls
  22  * 00/06/18     eranian Support for stacked physical calls
  23  */
  24
  25 /*
  26  * Note that some of these calls use a static-register only calling
  27  * convention which has nothing to do with the regular calling
  28  * convention.
  29  */
  30 #define PAL_CACHE_FLUSH         1       /* flush i/d cache */
  31 #define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
  32 #define PAL_CACHE_INIT          3       /* initialize i/d cache */
  33 #define PAL_CACHE_SUMMARY       4       /* get summary of cache heirarchy */
  34 #define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
  35 #define PAL_PTCE_INFO           6       /* purge TLB info */
  36 #define PAL_VM_INFO             7       /* return supported virtual memory features */
  37 #define PAL_VM_SUMMARY          8       /* return summary on supported vm features */
  38 #define PAL_BUS_GET_FEATURES    9       /* return processor bus interface features settings */
  39 #define PAL_BUS_SET_FEATURES    10      /* set processor bus features */
  40 #define PAL_DEBUG_INFO          11      /* get number of debug registers */
  41 #define PAL_FIXED_ADDR          12      /* get fixed component of processors's directed address */
  42 #define PAL_FREQ_BASE           13      /* base frequency of the platform */
  43 #define PAL_FREQ_RATIOS         14      /* ratio of processor, bus and ITC frequency */
  44 #define PAL_PERF_MON_INFO       15      /* return performance monitor info */
  45 #define PAL_PLATFORM_ADDR       16      /* set processor interrupt block and IO port space addr */
  46 #define PAL_PROC_GET_FEATURES   17      /* get configurable processor features & settings */
  47 #define PAL_PROC_SET_FEATURES   18      /* enable/disable configurable processor features */
  48 #define PAL_RSE_INFO            19      /* return rse information */
  49 #define PAL_VERSION             20      /* return version of PAL code */
  50 #define PAL_MC_CLEAR_LOG        21      /* clear all processor log info */
  51 #define PAL_MC_DRAIN            22      /* drain operations which could result in an MCA */
  52 #define PAL_MC_EXPECTED         23      /* set/reset expected MCA indicator */
  53 #define PAL_MC_DYNAMIC_STATE    24      /* get processor dynamic state */
  54 #define PAL_MC_ERROR_INFO       25      /* get processor MCA info and static state */
  55 #define PAL_MC_RESUME           26      /* Return to interrupted process */
  56 #define PAL_MC_REGISTER_MEM     27      /* Register memory for PAL to use during MCAs and inits */
  57 #define PAL_HALT                28      /* enter the low power HALT state */
  58 #define PAL_HALT_LIGHT          29      /* enter the low power light halt state*/
  59 #define PAL_COPY_INFO           30      /* returns info needed to relocate PAL */
  60 #define PAL_CACHE_LINE_INIT     31      /* init tags & data of cache line */
  61 #define PAL_PMI_ENTRYPOINT      32      /* register PMI memory entry points with the processor */
  62 #define PAL_ENTER_IA_32_ENV     33      /* enter IA-32 system environment */
  63 #define PAL_VM_PAGE_SIZE        34      /* return vm TC and page walker page sizes */
  64
  65 #define PAL_MEM_FOR_TEST        37      /* get amount of memory needed for late processor test */
  66 #define PAL_CACHE_PROT_INFO     38      /* get i/d cache protection info */
  67 #define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
  68 #define PAL_SHUTDOWN            40      /* enter processor shutdown state */
  69 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
  70 #define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
  71 #define PAL_CACHE_SHARED_INFO   43      /* returns information on caches shared by logical processor */
  72
  73 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
  74 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
  75 #define PAL_TEST_PROC           258     /* perform late processor self-test */
  76 #define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
  77 #define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
  78 #define PAL_VM_TR_READ          261     /* read contents of translation register */
  79 #define PAL_GET_PSTATE          262     /* get the current P-state */
  80 #define PAL_SET_PSTATE          263     /* set the P-state */
  81 #define PAL_BRAND_INFO          274     /* Processor branding information */
  82
  83 #ifndef __ASSEMBLY__
  84
  85 #include <linux/types.h>
  86 #include <asm/fpu.h>
  87
  88 /*
  89  * Data types needed to pass information into PAL procedures and
  90  * interpret information returned by them.
  91  */
  92
  93 /* Return status from the PAL procedure */
  94 typedef s64                             pal_status_t;
  95
  96 #define PAL_STATUS_SUCCESS              0       /* No error */
  97 #define PAL_STATUS_UNIMPLEMENTED        (-1)    /* Unimplemented procedure */
  98 #define PAL_STATUS_EINVAL               (-2)    /* Invalid argument */
  99 #define PAL_STATUS_ERROR                (-3)    /* Error */
 100 #define PAL_STATUS_CACHE_INIT_FAIL      (-4)    /* Could not initialize the
 101                                                  * specified level and type of
 102                                                  * cache without sideeffects
 103                                                  * and "restrict" was 1
 104                                                  */
 105
 106 /* Processor cache level in the heirarchy */
 107 typedef u64                             pal_cache_level_t;
 108 #define PAL_CACHE_LEVEL_L0              0       /* L0 */
 109 #define PAL_CACHE_LEVEL_L1              1       /* L1 */
 110 #define PAL_CACHE_LEVEL_L2              2       /* L2 */
 111
 112
 113 /* Processor cache type at a particular level in the heirarchy */
 114
 115 typedef u64                             pal_cache_type_t;
 116 #define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
 117 #define PAL_CACHE_TYPE_DATA             2       /* Data or unified cache */
 118 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3       /* Both Data & Instruction */
 119
 120
 121 #define PAL_CACHE_FLUSH_INVALIDATE      1       /* Invalidate clean lines */
 122 #define PAL_CACHE_FLUSH_CHK_INTRS       2       /* check for interrupts/mc while flushing */
 123
 124 /* Processor cache line size in bytes  */
 125 typedef int                             pal_cache_line_size_t;
 126
 127 /* Processor cache line state */
 128 typedef u64                             pal_cache_line_state_t;
 129 #define PAL_CACHE_LINE_STATE_INVALID    0       /* Invalid */
 130 #define PAL_CACHE_LINE_STATE_SHARED     1       /* Shared */
 131 #define PAL_CACHE_LINE_STATE_EXCLUSIVE  2       /* Exclusive */
 132 #define PAL_CACHE_LINE_STATE_MODIFIED   3       /* Modified */
 133
 134 typedef struct pal_freq_ratio {
 135         u32 den, num;           /* numerator & denominator */
 136 } itc_ratio, proc_ratio;
 137
 138 typedef union  pal_cache_config_info_1_s {
 139         struct {
 140                 u64             u               : 1,    /* 0 Unified cache ? */
 141                                 at              : 2,    /* 2-1 Cache mem attr*/
 142                                 reserved        : 5,    /* 7-3 Reserved */
 143                                 associativity   : 8,    /* 16-8 Associativity*/
 144                                 line_size       : 8,    /* 23-17 Line size */
 145                                 stride          : 8,    /* 31-24 Stride */
 146                                 store_latency   : 8,    /*39-32 Store latency*/
 147                                 load_latency    : 8,    /* 47-40 Load latency*/
 148                                 store_hints     : 8,    /* 55-48 Store hints*/
 149                                 load_hints      : 8;    /* 63-56 Load hints */
 150         } pcci1_bits;
 151         u64                     pcci1_data;
 152 } pal_cache_config_info_1_t;
 153
 154 typedef union  pal_cache_config_info_2_s {
 155         struct {
 156                 u32             cache_size;             /*cache size in bytes*/
 157
 158
 159                 u32             alias_boundary  : 8,    /* 39-32 aliased addr
 160                                                          * separation for max
 161                                                          * performance.
 162                                                          */
 163                                 tag_ls_bit      : 8,    /* 47-40 LSb of addr*/
 164                                 tag_ms_bit      : 8,    /* 55-48 MSb of addr*/
 165                                 reserved        : 8;    /* 63-56 Reserved */
 166         } pcci2_bits;
 167         u64                     pcci2_data;
 168 } pal_cache_config_info_2_t;
 169
 170
 171 typedef struct pal_cache_config_info_s {
 172         pal_status_t                    pcci_status;
 173         pal_cache_config_info_1_t       pcci_info_1;
 174         pal_cache_config_info_2_t       pcci_info_2;
 175         u64                             pcci_reserved;
 176 } pal_cache_config_info_t;
 177
 178 #define pcci_ld_hints           pcci_info_1.pcci1_bits.load_hints
 179 #define pcci_st_hints           pcci_info_1.pcci1_bits.store_hints
 180 #define pcci_ld_latency         pcci_info_1.pcci1_bits.load_latency
 181 #define pcci_st_latency         pcci_info_1.pcci1_bits.store_latency
 182 #define pcci_stride             pcci_info_1.pcci1_bits.stride
 183 #define pcci_line_size          pcci_info_1.pcci1_bits.line_size
 184 #define pcci_assoc              pcci_info_1.pcci1_bits.associativity
 185 #define pcci_cache_attr         pcci_info_1.pcci1_bits.at
 186 #define pcci_unified            pcci_info_1.pcci1_bits.u
 187 #define pcci_tag_msb            pcci_info_2.pcci2_bits.tag_ms_bit
 188 #define pcci_tag_lsb            pcci_info_2.pcci2_bits.tag_ls_bit
 189 #define pcci_alias_boundary     pcci_info_2.pcci2_bits.alias_boundary
 190 #define pcci_cache_size         pcci_info_2.pcci2_bits.cache_size
 191
 192
 193
 194 /* Possible values for cache attributes */
 195
 196 #define PAL_CACHE_ATTR_WT               0       /* Write through cache */
 197 #define PAL_CACHE_ATTR_WB               1       /* Write back cache */
 198 #define PAL_CACHE_ATTR_WT_OR_WB         2       /* Either write thru or write
 199                                                  * back depending on TLB
 200                                                  * memory attributes
 201                                                  */
 202
 203
 204 /* Possible values for cache hints */
 205
 206 #define PAL_CACHE_HINT_TEMP_1           0       /* Temporal level 1 */
 207 #define PAL_CACHE_HINT_NTEMP_1          1       /* Non-temporal level 1 */
 208 #define PAL_CACHE_HINT_NTEMP_ALL        3       /* Non-temporal all levels */
 209
 210 /* Processor cache protection  information */
 211 typedef union pal_cache_protection_element_u {
 212         u32                     pcpi_data;
 213         struct {
 214                 u32             data_bits       : 8, /* # data bits covered by
 215                                                       * each unit of protection
 216                                                       */
 217
 218                                 tagprot_lsb     : 6, /* Least -do- */
 219                                 tagprot_msb     : 6, /* Most Sig. tag address
 220                                                       * bit that this
 221                                                       * protection covers.
 222                                                       */
 223                                 prot_bits       : 6, /* # of protection bits */
 224                                 method          : 4, /* Protection method */
 225                                 t_d             : 2; /* Indicates which part
 226                                                       * of the cache this
 227                                                       * protection encoding
 228                                                       * applies.
 229                                                       */
 230         } pcp_info;
 231 } pal_cache_protection_element_t;
 232
 233 #define pcpi_cache_prot_part    pcp_info.t_d
 234 #define pcpi_prot_method        pcp_info.method
 235 #define pcpi_prot_bits          pcp_info.prot_bits
 236 #define pcpi_tagprot_msb        pcp_info.tagprot_msb
 237 #define pcpi_tagprot_lsb        pcp_info.tagprot_lsb
 238 #define pcpi_data_bits          pcp_info.data_bits
 239
 240 /* Processor cache part encodings */
 241 #define PAL_CACHE_PROT_PART_DATA        0       /* Data protection  */
 242 #define PAL_CACHE_PROT_PART_TAG         1       /* Tag  protection */
 243 #define PAL_CACHE_PROT_PART_TAG_DATA    2       /* Tag+data protection (tag is
 244                                                  * more significant )
 245                                                  */
 246 #define PAL_CACHE_PROT_PART_DATA_TAG    3       /* Data+tag protection (data is
 247                                                  * more significant )
 248                                                  */
 249 #define PAL_CACHE_PROT_PART_MAX         6
 250
 251
 252 typedef struct pal_cache_protection_info_s {
 253         pal_status_t                    pcpi_status;
 254         pal_cache_protection_element_t  pcp_info[PAL_CACHE_PROT_PART_MAX];
 255 } pal_cache_protection_info_t;
 256
 257
 258 /* Processor cache protection method encodings */
 259 #define PAL_CACHE_PROT_METHOD_NONE              0       /* No protection */
 260 #define PAL_CACHE_PROT_METHOD_ODD_PARITY        1       /* Odd parity */
 261 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY       2       /* Even parity */
 262 #define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
 263
 264
 265 /* Processor cache line identification in the heirarchy */
 266 typedef union pal_cache_line_id_u {
 267         u64                     pclid_data;
 268         struct {
 269                 u64             cache_type      : 8,    /* 7-0 cache type */
 270                                 level           : 8,    /* 15-8 level of the
 271                                                          * cache in the
 272                                                          * heirarchy.
 273                                                          */
 274                                 way             : 8,    /* 23-16 way in the set
 275                                                          */
 276                                 part            : 8,    /* 31-24 part of the
 277                                                          * cache
 278                                                          */
 279                                 reserved        : 32;   /* 63-32 is reserved*/
 280         } pclid_info_read;
 281         struct {
 282                 u64             cache_type      : 8,    /* 7-0 cache type */
 283                                 level           : 8,    /* 15-8 level of the
 284                                                          * cache in the
 285                                                          * heirarchy.
 286                                                          */
 287                                 way             : 8,    /* 23-16 way in the set
 288                                                          */
 289                                 part            : 8,    /* 31-24 part of the
 290                                                          * cache
 291                                                          */
 292                                 mesi            : 8,    /* 39-32 cache line
 293                                                          * state
 294                                                          */
 295                                 start           : 8,    /* 47-40 lsb of data to
 296                                                          * invert
 297                                                          */
 298                                 length          : 8,    /* 55-48 #bits to
 299                                                          * invert
 300                                                          */
 301                                 trigger         : 8;    /* 63-56 Trigger error
 302                                                          * by doing a load
 303                                                          * after the write
 304                                                          */
 305
 306         } pclid_info_write;
 307 } pal_cache_line_id_u_t;
 308
 309 #define pclid_read_part         pclid_info_read.part
 310 #define pclid_read_way          pclid_info_read.way
 311 #define pclid_read_level        pclid_info_read.level
 312 #define pclid_read_cache_type   pclid_info_read.cache_type
 313
 314 #define pclid_write_trigger     pclid_info_write.trigger
 315 #define pclid_write_length      pclid_info_write.length
 316 #define pclid_write_start       pclid_info_write.start
 317 #define pclid_write_mesi        pclid_info_write.mesi
 318 #define pclid_write_part        pclid_info_write.part
 319 #define pclid_write_way         pclid_info_write.way
 320 #define pclid_write_level       pclid_info_write.level
 321 #define pclid_write_cache_type  pclid_info_write.cache_type
 322
 323 /* Processor cache line part encodings */
 324 #define PAL_CACHE_LINE_ID_PART_DATA             0       /* Data */
 325 #define PAL_CACHE_LINE_ID_PART_TAG              1       /* Tag */
 326 #define PAL_CACHE_LINE_ID_PART_DATA_PROT        2       /* Data protection */
 327 #define PAL_CACHE_LINE_ID_PART_TAG_PROT         3       /* Tag protection */
 328 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT    4       /* Data+tag
 329                                                          * protection
 330                                                          */
 331 typedef struct pal_cache_line_info_s {
 332         pal_status_t            pcli_status;            /* Return status of the read cache line
 333                                                          * info call.
 334                                                          */
 335         u64                     pcli_data;              /* 64-bit data, tag, protection bits .. */
 336         u64                     pcli_data_len;          /* data length in bits */
 337         pal_cache_line_state_t  pcli_cache_line_state;  /* mesi state */
 338
 339 } pal_cache_line_info_t;
 340
 341
 342 /* Machine Check related crap */
 343
 344 /* Pending event status bits  */
 345 typedef u64                                     pal_mc_pending_events_t;
 346
 347 #define PAL_MC_PENDING_MCA                      (1 << 0)
 348 #define PAL_MC_PENDING_INIT                     (1 << 1)
 349
 350 /* Error information type */
 351 typedef u64                                     pal_mc_info_index_t;
 352
 353 #define PAL_MC_INFO_PROCESSOR                   0       /* Processor */
 354 #define PAL_MC_INFO_CACHE_CHECK                 1       /* Cache check */
 355 #define PAL_MC_INFO_TLB_CHECK                   2       /* Tlb check */
 356 #define PAL_MC_INFO_BUS_CHECK                   3       /* Bus check */
 357 #define PAL_MC_INFO_REQ_ADDR                    4       /* Requestor address */
 358 #define PAL_MC_INFO_RESP_ADDR                   5       /* Responder address */
 359 #define PAL_MC_INFO_TARGET_ADDR                 6       /* Target address */
 360 #define PAL_MC_INFO_IMPL_DEP                    7       /* Implementation
 361                                                          * dependent
 362                                                          */
 363
 364
 365 typedef struct pal_process_state_info_s {
 366         u64             reserved1       : 2,
 367                         rz              : 1,    /* PAL_CHECK processor
 368                                                  * rendezvous
 369                                                  * successful.
 370                                                  */
 371
 372                         ra              : 1,    /* PAL_CHECK attempted
 373                                                  * a rendezvous.
 374                                                  */
 375                         me              : 1,    /* Distinct multiple
 376                                                  * errors occurred
 377                                                  */
 378
 379                         mn              : 1,    /* Min. state save
 380                                                  * area has been
 381                                                  * registered with PAL
 382                                                  */
 383
 384                         sy              : 1,    /* Storage integrity
 385                                                  * synched
 386                                                  */
 387
 388
 389                         co              : 1,    /* Continuable */
 390                         ci              : 1,    /* MC isolated */
 391                         us              : 1,    /* Uncontained storage
 392                                                  * damage.
 393                                                  */
 394
 395
 396                         hd              : 1,    /* Non-essential hw
 397                                                  * lost (no loss of
 398                                                  * functionality)
 399                                                  * causing the
 400                                                  * processor to run in
 401                                                  * degraded mode.
 402                                                  */
 403
 404                         tl              : 1,    /* 1 => MC occurred
 405                                                  * after an instr was
 406                                                  * executed but before
 407                                                  * the trap that
 408                                                  * resulted from instr
 409                                                  * execution was
 410                                                  * generated.
 411                                                  * (Trap Lost )
 412                                                  */
 413                         mi              : 1,    /* More information available
 414                                                  * call PAL_MC_ERROR_INFO
 415                                                  */
 416                         pi              : 1,    /* Precise instruction pointer */
 417                         pm              : 1,    /* Precise min-state save area */
 418
 419                         dy              : 1,    /* Processor dynamic
 420                                                  * state valid
 421                                                  */
 422
 423
 424                         in              : 1,    /* 0 = MC, 1 = INIT */
 425                         rs              : 1,    /* RSE valid */
 426                         cm              : 1,    /* MC corrected */
 427                         ex              : 1,    /* MC is expected */
 428                         cr              : 1,    /* Control regs valid*/
 429                         pc              : 1,    /* Perf cntrs valid */
 430                         dr              : 1,    /* Debug regs valid */
 431                         tr              : 1,    /* Translation regs
 432                                                  * valid
 433                                                  */
 434                         rr              : 1,    /* Region regs valid */
 435                         ar              : 1,    /* App regs valid */
 436                         br              : 1,    /* Branch regs valid */
 437                         pr              : 1,    /* Predicate registers
 438                                                  * valid
 439                                                  */
 440
 441                         fp              : 1,    /* fp registers valid*/
 442                         b1              : 1,    /* Preserved bank one
 443                                                  * general registers
 444                                                  * are valid
 445                                                  */
 446                         b0              : 1,    /* Preserved bank zero
 447                                                  * general registers
 448                                                  * are valid
 449                                                  */
 450                         gr              : 1,    /* General registers
 451                                                  * are valid
 452                                                  * (excl. banked regs)
 453                                                  */
 454                         dsize           : 16,   /* size of dynamic
 455                                                  * state returned
 456                                                  * by the processor
 457                                                  */
 458
 459                         reserved2       : 11,
 460                         cc              : 1,    /* Cache check */
 461                         tc              : 1,    /* TLB check */
 462                         bc              : 1,    /* Bus check */
 463                         rc              : 1,    /* Register file check */
 464                         uc              : 1;    /* Uarch check */
 465
 466 } pal_processor_state_info_t;
 467
 468 typedef struct pal_cache_check_info_s {
 469         u64             op              : 4,    /* Type of cache
 470                                                  * operation that
 471                                                  * caused the machine
 472                                                  * check.
 473                                                  */
 474                         level           : 2,    /* Cache level */
 475                         reserved1       : 2,
 476                         dl              : 1,    /* Failure in data part
 477                                                  * of cache line
 478                                                  */
 479                         tl              : 1,    /* Failure in tag part
 480                                                  * of cache line
 481                                                  */
 482                         dc              : 1,    /* Failure in dcache */
 483                         ic              : 1,    /* Failure in icache */
 484                         mesi            : 3,    /* Cache line state */
 485                         mv              : 1,    /* mesi valid */
 486                         way             : 5,    /* Way in which the
 487                                                  * error occurred
 488                                                  */
 489                         wiv             : 1,    /* Way field valid */
 490                         reserved2       : 1,
 491                         dp              : 1,    /* Data poisoned on MBE */
 492                         reserved3       : 8,
 493
 494                         index           : 20,   /* Cache line index */
 495                         reserved4       : 2,
 496
 497                         is              : 1,    /* instruction set (1 == ia32) */
 498                         iv              : 1,    /* instruction set field valid */
 499                         pl              : 2,    /* privilege level */
 500                         pv              : 1,    /* privilege level field valid */
 501                         mcc             : 1,    /* Machine check corrected */
 502                         tv              : 1,    /* Target address
 503                                                  * structure is valid
 504                                                  */
 505                         rq              : 1,    /* Requester identifier
 506                                                  * structure is valid
 507                                                  */
 508                         rp              : 1,    /* Responder identifier
 509                                                  * structure is valid
 510                                                  */
 511                         pi              : 1;    /* Precise instruction pointer
 512                                                  * structure is valid
 513                                                  */
 514 } pal_cache_check_info_t;
 515
 516 typedef struct pal_tlb_check_info_s {
 517
 518         u64             tr_slot         : 8,    /* Slot# of TR where
 519                                                  * error occurred
 520                                                  */
 521                         trv             : 1,    /* tr_slot field is valid */
 522                         reserved1       : 1,
 523                         level           : 2,    /* TLB level where failure occurred */
 524                         reserved2       : 4,
 525                         dtr             : 1,    /* Fail in data TR */
 526                         itr             : 1,    /* Fail in inst TR */
 527                         dtc             : 1,    /* Fail in data TC */
 528                         itc             : 1,    /* Fail in inst. TC */
 529                         op              : 4,    /* Cache operation */
 530                         reserved3       : 30,
 531
 532                         is              : 1,    /* instruction set (1 == ia32) */
 533                         iv              : 1,    /* instruction set field valid */
 534                         pl              : 2,    /* privilege level */
 535                         pv              : 1,    /* privilege level field valid */
 536                         mcc             : 1,    /* Machine check corrected */
 537                         tv              : 1,    /* Target address
 538                                                  * structure is valid
 539                                                  */
 540                         rq              : 1,    /* Requester identifier
 541                                                  * structure is valid
 542                                                  */
 543                         rp              : 1,    /* Responder identifier
 544                                                  * structure is valid
 545                                                  */
 546                         pi              : 1;    /* Precise instruction pointer
 547                                                  * structure is valid
 548                                                  */
 549 } pal_tlb_check_info_t;
 550
 551 typedef struct pal_bus_check_info_s {
 552         u64             size            : 5,    /* Xaction size */
 553                         ib              : 1,    /* Internal bus error */
 554                         eb              : 1,    /* External bus error */
 555                         cc              : 1,    /* Error occurred
 556                                                  * during cache-cache
 557                                                  * transfer.
 558                                                  */
 559                         type            : 8,    /* Bus xaction type*/
 560                         sev             : 5,    /* Bus error severity*/
 561                         hier            : 2,    /* Bus hierarchy level */
 562                         dp              : 1,    /* Data poisoned on MBE */
 563                         bsi             : 8,    /* Bus error status
 564                                                  * info
 565                                                  */
 566                         reserved2       : 22,
 567
 568                         is              : 1,    /* instruction set (1 == ia32) */
 569                         iv              : 1,    /* instruction set field valid */
 570                         pl              : 2,    /* privilege level */
 571                         pv              : 1,    /* privilege level field valid */
 572                         mcc             : 1,    /* Machine check corrected */
 573                         tv              : 1,    /* Target address
 574                                                  * structure is valid
 575                                                  */
 576                         rq              : 1,    /* Requester identifier
 577                                                  * structure is valid
 578                                                  */
 579                         rp              : 1,    /* Responder identifier
 580                                                  * structure is valid
 581                                                  */
 582                         pi              : 1;    /* Precise instruction pointer
 583                                                  * structure is valid
 584                                                  */
 585 } pal_bus_check_info_t;
 586
 587 typedef struct pal_reg_file_check_info_s {
 588         u64             id              : 4,    /* Register file identifier */
 589                         op              : 4,    /* Type of register
 590                                                  * operation that
 591                                                  * caused the machine
 592                                                  * check.
 593                                                  */
 594                         reg_num         : 7,    /* Register number */
 595                         rnv             : 1,    /* reg_num valid */
 596                         reserved2       : 38,
 597
 598                         is              : 1,    /* instruction set (1 == ia32) */
 599                         iv              : 1,    /* instruction set field valid */
 600                         pl              : 2,    /* privilege level */
 601                         pv              : 1,    /* privilege level field valid */
 602                         mcc             : 1,    /* Machine check corrected */
 603                         reserved3       : 3,
 604                         pi              : 1;    /* Precise instruction pointer
 605                                                  * structure is valid
 606                                                  */
 607 } pal_reg_file_check_info_t;
 608
 609 typedef struct pal_uarch_check_info_s {
 610         u64             sid             : 5,    /* Structure identification */
 611                         level           : 3,    /* Level of failure */
 612                         array_id        : 4,    /* Array identification */
 613                         op              : 4,    /* Type of
 614                                                  * operation that
 615                                                  * caused the machine
 616                                                  * check.
 617                                                  */
 618                         way             : 6,    /* Way of structure */
 619                         wv              : 1,    /* way valid */
 620                         xv              : 1,    /* index valid */
 621                         reserved1       : 8,
 622                         index           : 8,    /* Index or set of the uarch
 623                                                  * structure that failed.
 624                                                  */
 625                         reserved2       : 24,
 626
 627                         is              : 1,    /* instruction set (1 == ia32) */
 628                         iv              : 1,    /* instruction set field valid */
 629                         pl              : 2,    /* privilege level */
 630                         pv              : 1,    /* privilege level field valid */
 631                         mcc             : 1,    /* Machine check corrected */
 632                         tv              : 1,    /* Target address
 633                                                  * structure is valid
 634                                                  */
 635                         rq              : 1,    /* Requester identifier
 636                                                  * structure is valid
 637                                                  */
 638                         rp              : 1,    /* Responder identifier
 639                                                  * structure is valid
 640                                                  */
 641                         pi              : 1;    /* Precise instruction pointer
 642                                                  * structure is valid
 643                                                  */
 644 } pal_uarch_check_info_t;
 645
 646 typedef union pal_mc_error_info_u {
 647         u64                             pmei_data;
 648         pal_processor_state_info_t      pme_processor;
 649         pal_cache_check_info_t          pme_cache;
 650         pal_tlb_check_info_t            pme_tlb;
 651         pal_bus_check_info_t            pme_bus;
 652         pal_reg_file_check_info_t       pme_reg_file;
 653         pal_uarch_check_info_t          pme_uarch;
 654 } pal_mc_error_info_t;
 655
 656 #define pmci_proc_unknown_check                 pme_processor.uc
 657 #define pmci_proc_bus_check                     pme_processor.bc
 658 #define pmci_proc_tlb_check                     pme_processor.tc
 659 #define pmci_proc_cache_check                   pme_processor.cc
 660 #define pmci_proc_dynamic_state_size            pme_processor.dsize
 661 #define pmci_proc_gpr_valid                     pme_processor.gr
 662 #define pmci_proc_preserved_bank0_gpr_valid     pme_processor.b0
 663 #define pmci_proc_preserved_bank1_gpr_valid     pme_processor.b1
 664 #define pmci_proc_fp_valid                      pme_processor.fp
 665 #define pmci_proc_predicate_regs_valid          pme_processor.pr
 666 #define pmci_proc_branch_regs_valid             pme_processor.br
 667 #define pmci_proc_app_regs_valid                pme_processor.ar
 668 #define pmci_proc_region_regs_valid             pme_processor.rr
 669 #define pmci_proc_translation_regs_valid        pme_processor.tr
 670 #define pmci_proc_debug_regs_valid              pme_processor.dr
 671 #define pmci_proc_perf_counters_valid           pme_processor.pc
 672 #define pmci_proc_control_regs_valid            pme_processor.cr
 673 #define pmci_proc_machine_check_expected        pme_processor.ex
 674 #define pmci_proc_machine_check_corrected       pme_processor.cm
 675 #define pmci_proc_rse_valid                     pme_processor.rs
 676 #define pmci_proc_machine_check_or_init         pme_processor.in
 677 #define pmci_proc_dynamic_state_valid           pme_processor.dy
 678 #define pmci_proc_operation                     pme_processor.op
 679 #define pmci_proc_trap_lost                     pme_processor.tl
 680 #define pmci_proc_hardware_damage               pme_processor.hd
 681 #define pmci_proc_uncontained_storage_damage    pme_processor.us
 682 #define pmci_proc_machine_check_isolated        pme_processor.ci
 683 #define pmci_proc_continuable                   pme_processor.co
 684 #define pmci_proc_storage_intergrity_synced     pme_processor.sy
 685 #define pmci_proc_min_state_save_area_regd      pme_processor.mn
 686 #define pmci_proc_distinct_multiple_errors      pme_processor.me
 687 #define pmci_proc_pal_attempted_rendezvous      pme_processor.ra
 688 #define pmci_proc_pal_rendezvous_complete       pme_processor.rz
 689
 690
 691 #define pmci_cache_level                        pme_cache.level
 692 #define pmci_cache_line_state                   pme_cache.mesi
 693 #define pmci_cache_line_state_valid             pme_cache.mv
 694 #define pmci_cache_line_index                   pme_cache.index
 695 #define pmci_cache_instr_cache_fail             pme_cache.ic
 696 #define pmci_cache_data_cache_fail              pme_cache.dc
 697 #define pmci_cache_line_tag_fail                pme_cache.tl
 698 #define pmci_cache_line_data_fail               pme_cache.dl
 699 #define pmci_cache_operation                    pme_cache.op
 700 #define pmci_cache_way_valid                    pme_cache.wv
 701 #define pmci_cache_target_address_valid         pme_cache.tv
 702 #define pmci_cache_way                          pme_cache.way
 703 #define pmci_cache_mc                           pme_cache.mc
 704
 705 #define pmci_tlb_instr_translation_cache_fail   pme_tlb.itc
 706 #define pmci_tlb_data_translation_cache_fail    pme_tlb.dtc
 707 #define pmci_tlb_instr_translation_reg_fail     pme_tlb.itr
 708 #define pmci_tlb_data_translation_reg_fail      pme_tlb.dtr
 709 #define pmci_tlb_translation_reg_slot           pme_tlb.tr_slot
 710 #define pmci_tlb_mc                             pme_tlb.mc
 711
 712 #define pmci_bus_status_info                    pme_bus.bsi
 713 #define pmci_bus_req_address_valid              pme_bus.rq
 714 #define pmci_bus_resp_address_valid             pme_bus.rp
 715 #define pmci_bus_target_address_valid           pme_bus.tv
 716 #define pmci_bus_error_severity                 pme_bus.sev
 717 #define pmci_bus_transaction_type               pme_bus.type
 718 #define pmci_bus_cache_cache_transfer           pme_bus.cc
 719 #define pmci_bus_transaction_size               pme_bus.size
 720 #define pmci_bus_internal_error                 pme_bus.ib
 721 #define pmci_bus_external_error                 pme_bus.eb
 722 #define pmci_bus_mc                             pme_bus.mc
 723
 724 /*
 725  * NOTE: this min_state_save area struct only includes the 1KB
 726  * architectural state save area.  The other 3 KB is scratch space
 727  * for PAL.
 728  */
 729
 730 typedef struct pal_min_state_area_s {
 731         u64     pmsa_nat_bits;          /* nat bits for saved GRs  */
 732         u64     pmsa_gr[15];            /* GR1  - GR15             */
 733         u64     pmsa_bank0_gr[16];      /* GR16 - GR31             */
 734         u64     pmsa_bank1_gr[16];      /* GR16 - GR31             */
 735         u64     pmsa_pr;                /* predicate registers     */
 736         u64     pmsa_br0;               /* branch register 0       */
 737         u64     pmsa_rsc;               /* ar.rsc                  */
 738         u64     pmsa_iip;               /* cr.iip                  */
 739         u64     pmsa_ipsr;              /* cr.ipsr                 */
 740         u64     pmsa_ifs;               /* cr.ifs                  */
 741         u64     pmsa_xip;               /* previous iip            */
 742         u64     pmsa_xpsr;              /* previous psr            */
 743         u64     pmsa_xfs;               /* previous ifs            */
 744         u64     pmsa_br1;               /* branch register 1       */
 745         u64     pmsa_reserved[70];      /* pal_min_state_area should total to 1KB */
 746 } pal_min_state_area_t;
 747
 748
 749 struct ia64_pal_retval {
 750         /*
 751          * A zero status value indicates call completed without error.
 752          * A negative status value indicates reason of call failure.
 753          * A positive status value indicates success but an
 754          * informational value should be printed (e.g., "reboot for
 755          * change to take effect").
 756          */
 757         s64 status;
 758         u64 v0;
 759         u64 v1;
 760         u64 v2;
 761 };
 762
 763 /*
 764  * Note: Currently unused PAL arguments are generally labeled
 765  * "reserved" so the value specified in the PAL documentation
 766  * (generally 0) MUST be passed.  Reserved parameters are not optional
 767  * parameters.
 768  */
 769 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
 770 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
 771 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
 772 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
 773 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
 774 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
 775
 776 #define PAL_CALL(iprv,a0,a1,a2,a3) do {                 \
 777         struct ia64_fpreg fr[6];                        \
 778         ia64_save_scratch_fpregs(fr);                   \
 779         iprv = ia64_pal_call_static(a0, a1, a2, a3);    \
 780         ia64_load_scratch_fpregs(fr);                   \
 781 } while (0)
 782
 783 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {             \
 784         struct ia64_fpreg fr[6];                        \
 785         ia64_save_scratch_fpregs(fr);                   \
 786         iprv = ia64_pal_call_stacked(a0, a1, a2, a3);   \
 787         ia64_load_scratch_fpregs(fr);                   \
 788 } while (0)
 789
 790 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {                    \
 791         struct ia64_fpreg fr[6];                                \
 792         ia64_save_scratch_fpregs(fr);                           \
 793         iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);       \
 794         ia64_load_scratch_fpregs(fr);                           \
 795 } while (0)
 796
 797 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {                \
 798         struct ia64_fpreg fr[6];                                \
 799         ia64_save_scratch_fpregs(fr);                           \
 800         iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);      \
 801         ia64_load_scratch_fpregs(fr);                           \
 802 } while (0)
 803
 804 typedef int (*ia64_pal_handler) (u64, ...);
 805 extern ia64_pal_handler ia64_pal;
 806 extern void ia64_pal_handler_init (void *);
 807
 808 extern ia64_pal_handler ia64_pal;
 809
 810 extern pal_cache_config_info_t          l0d_cache_config_info;
 811 extern pal_cache_config_info_t          l0i_cache_config_info;
 812 extern pal_cache_config_info_t          l1_cache_config_info;
 813 extern pal_cache_config_info_t          l2_cache_config_info;
 814
 815 extern pal_cache_protection_info_t      l0d_cache_protection_info;
 816 extern pal_cache_protection_info_t      l0i_cache_protection_info;
 817 extern pal_cache_protection_info_t      l1_cache_protection_info;
 818 extern pal_cache_protection_info_t      l2_cache_protection_info;
 819
 820 extern pal_cache_config_info_t          pal_cache_config_info_get(pal_cache_level_t,
 821                                                                   pal_cache_type_t);
 822
 823 extern pal_cache_protection_info_t      pal_cache_protection_info_get(pal_cache_level_t,
 824                                                                       pal_cache_type_t);
 825
 826
 827 extern void                             pal_error(int);
 828
 829
 830 /* Useful wrappers for the current list of pal procedures */
 831
 832 typedef union pal_bus_features_u {
 833         u64     pal_bus_features_val;
 834         struct {
 835                 u64     pbf_reserved1                           :       29;
 836                 u64     pbf_req_bus_parking                     :       1;
 837                 u64     pbf_bus_lock_mask                       :       1;
 838                 u64     pbf_enable_half_xfer_rate               :       1;
 839                 u64     pbf_reserved2                           :       22;
 840                 u64     pbf_disable_xaction_queueing            :       1;
 841                 u64     pbf_disable_resp_err_check              :       1;
 842                 u64     pbf_disable_berr_check                  :       1;
 843                 u64     pbf_disable_bus_req_internal_err_signal :       1;
 844                 u64     pbf_disable_bus_req_berr_signal         :       1;
 845                 u64     pbf_disable_bus_init_event_check        :       1;
 846                 u64     pbf_disable_bus_init_event_signal       :       1;
 847                 u64     pbf_disable_bus_addr_err_check          :       1;
 848                 u64     pbf_disable_bus_addr_err_signal         :       1;
 849                 u64     pbf_disable_bus_data_err_check          :       1;
 850         } pal_bus_features_s;
 851 } pal_bus_features_u_t;
 852
 853 extern void pal_bus_features_print (u64);
 854
 855 /* Provide information about configurable processor bus features */
 856 static inline s64
 857 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
 858                            pal_bus_features_u_t *features_status,
 859                            pal_bus_features_u_t *features_control)
 860 {
 861         struct ia64_pal_retval iprv;
 862         PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
 863         if (features_avail)
 864                 features_avail->pal_bus_features_val = iprv.v0;
 865         if (features_status)
 866                 features_status->pal_bus_features_val = iprv.v1;
 867         if (features_control)
 868                 features_control->pal_bus_features_val = iprv.v2;
 869         return iprv.status;
 870 }
 871
 872 /* Enables/disables specific processor bus features */
 873 static inline s64
 874 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
 875 {
 876         struct ia64_pal_retval iprv;
 877         PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
 878         return iprv.status;
 879 }
 880
 881 /* Get detailed cache information */
 882 static inline s64
 883 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
 884 {
 885         struct ia64_pal_retval iprv;
 886
 887         PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
 888
 889         if (iprv.status == 0) {
 890                 conf->pcci_status                 = iprv.status;
 891                 conf->pcci_info_1.pcci1_data      = iprv.v0;
 892                 conf->pcci_info_2.pcci2_data      = iprv.v1;
 893                 conf->pcci_reserved               = iprv.v2;
 894         }
 895         return iprv.status;
 896
 897 }
 898
 899 /* Get detailed cche protection information */
 900 static inline s64
 901 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
 902 {
 903         struct ia64_pal_retval iprv;
 904
 905         PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
 906
 907         if (iprv.status == 0) {
 908                 prot->pcpi_status           = iprv.status;
 909                 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
 910                 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
 911                 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
 912                 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
 913                 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
 914                 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
 915         }
 916         return iprv.status;
 917 }
 918
 919 /*
 920  * Flush the processor instruction or data caches.  *PROGRESS must be
 921  * initialized to zero before calling this for the first time..
 922  */
 923 static inline s64
 924 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
 925 {
 926         struct ia64_pal_retval iprv;
 927         PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
 928         if (vector)
 929                 *vector = iprv.v0;
 930         *progress = iprv.v1;
 931         return iprv.status;
 932 }
 933
 934
 935 /* Initialize the processor controlled caches */
 936 static inline s64
 937 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
 938 {
 939         struct ia64_pal_retval iprv;
 940         PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
 941         return iprv.status;
 942 }
 943
 944 /* Initialize the tags and data of a data or unified cache line of
 945  * processor controlled cache to known values without the availability
 946  * of backing memory.
 947  */
 948 static inline s64
 949 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
 950 {
 951         struct ia64_pal_retval iprv;
 952         PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
 953         return iprv.status;
 954 }
 955
 956
 957 /* Read the data and tag of a processor controlled cache line for diags */
 958 static inline s64
 959 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
 960 {
 961         struct ia64_pal_retval iprv;
 962         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
 963                                 physical_addr, 0);
 964         return iprv.status;
 965 }
 966
 967 /* Return summary information about the heirarchy of caches controlled by the processor */
 968 static inline s64
 969 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
 970 {
 971         struct ia64_pal_retval iprv;
 972         PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
 973         if (cache_levels)
 974                 *cache_levels = iprv.v0;
 975         if (unique_caches)
 976                 *unique_caches = iprv.v1;
 977         return iprv.status;
 978 }
 979
 980 /* Write the data and tag of a processor-controlled cache line for diags */
 981 static inline s64
 982 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
 983 {
 984         struct ia64_pal_retval iprv;
 985         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
 986                                 physical_addr, data);
 987         return iprv.status;
 988 }
 989
 990
 991 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
 992 static inline s64
 993 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
 994                     u64 *buffer_size, u64 *buffer_align)
 995 {
 996         struct ia64_pal_retval iprv;
 997         PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
 998         if (buffer_size)
 999                 *buffer_size = iprv.v0;
1000         if (buffer_align)
1001                 *buffer_align = iprv.v1;
1002         return iprv.status;
1003 }
1004
1005 /* Copy relocatable PAL procedures from ROM to memory */
1006 static inline s64
1007 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1008 {
1009         struct ia64_pal_retval iprv;
1010         PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1011         if (pal_proc_offset)
1012                 *pal_proc_offset = iprv.v0;
1013         return iprv.status;
1014 }
1015
1016 /* Return the number of instruction and data debug register pairs */
1017 static inline s64
1018 ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs)
1019 {
1020         struct ia64_pal_retval iprv;
1021         PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1022         if (inst_regs)
1023                 *inst_regs = iprv.v0;
1024         if (data_regs)
1025                 *data_regs = iprv.v1;
1026
1027         return iprv.status;
1028 }
1029
1030 #ifdef TBD
1031 /* Switch from IA64-system environment to IA-32 system environment */
1032 static inline s64
1033 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1034 {
1035         struct ia64_pal_retval iprv;
1036         PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1037         return iprv.status;
1038 }
1039 #endif
1040
1041 /* Get unique geographical address of this processor on its bus */
1042 static inline s64
1043 ia64_pal_fixed_addr (u64 *global_unique_addr)
1044 {
1045         struct ia64_pal_retval iprv;
1046         PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1047         if (global_unique_addr)
1048                 *global_unique_addr = iprv.v0;
1049         return iprv.status;
1050 }
1051
1052 /* Get base frequency of the platform if generated by the processor */
1053 static inline s64
1054 ia64_pal_freq_base (u64 *platform_base_freq)
1055 {
1056         struct ia64_pal_retval iprv;
1057         PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1058         if (platform_base_freq)
1059                 *platform_base_freq = iprv.v0;
1060         return iprv.status;
1061 }
1062
1063 /*
1064  * Get the ratios for processor frequency, bus frequency and interval timer to
1065  * to base frequency of the platform
1066  */
1067 static inline s64
1068 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1069                       struct pal_freq_ratio *itc_ratio)
1070 {
1071         struct ia64_pal_retval iprv;
1072         PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1073         if (proc_ratio)
1074                 *(u64 *)proc_ratio = iprv.v0;
1075         if (bus_ratio)
1076                 *(u64 *)bus_ratio = iprv.v1;
1077         if (itc_ratio)
1078                 *(u64 *)itc_ratio = iprv.v2;
1079         return iprv.status;
1080 }
1081
1082 /* Make the processor enter HALT or one of the implementation dependent low
1083  * power states where prefetching and execution are suspended and cache and
1084  * TLB coherency is not maintained.
1085  */
1086 static inline s64
1087 ia64_pal_halt (u64 halt_state)
1088 {
1089         struct ia64_pal_retval iprv;
1090         PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1091         return iprv.status;
1092 }
1093
1094 typedef union pal_power_mgmt_info_u {
1095         u64                     ppmi_data;
1096         struct {
1097                u64              exit_latency            : 16,
1098                                 entry_latency           : 16,
1099                                 power_consumption       : 28,
1100                                 im                      : 1,
1101                                 co                      : 1,
1102                                 reserved                : 2;
1103         } pal_power_mgmt_info_s;
1104 } pal_power_mgmt_info_u_t;
1105
1106 /* Return information about processor's optional power management capabilities. */
1107 static inline s64
1108 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1109 {
1110         struct ia64_pal_retval iprv;
1111         PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1112         return iprv.status;
1113 }
1114
1115 /* Get the current P-state information */
1116 static inline s64
1117 ia64_pal_get_pstate (u64 *pstate_index)
1118 {
1119         struct ia64_pal_retval iprv;
1120         PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
1121         *pstate_index = iprv.v0;
1122         return iprv.status;
1123 }
1124
1125 /* Set the P-state */
1126 static inline s64
1127 ia64_pal_set_pstate (u64 pstate_index)
1128 {
1129         struct ia64_pal_retval iprv;
1130         PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1131         return iprv.status;
1132 }
1133
1134 /* Processor branding information*/
1135 static inline s64
1136 ia64_pal_get_brand_info (char *brand_info)
1137 {
1138         struct ia64_pal_retval iprv;
1139         PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1140         return iprv.status;
1141 }
1142
1143 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1144  * suspended, but cache and TLB coherency is maintained.
1145  */
1146 static inline s64
1147 ia64_pal_halt_light (void)
1148 {
1149         struct ia64_pal_retval iprv;
1150         PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1151         return iprv.status;
1152 }
1153
1154 /* Clear all the processor error logging   registers and reset the indicator that allows
1155  * the error logging registers to be written. This procedure also checks the pending
1156  * machine check bit and pending INIT bit and reports their states.
1157  */
1158 static inline s64
1159 ia64_pal_mc_clear_log (u64 *pending_vector)
1160 {
1161         struct ia64_pal_retval iprv;
1162         PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1163         if (pending_vector)
1164                 *pending_vector = iprv.v0;
1165         return iprv.status;
1166 }
1167
1168 /* Ensure that all outstanding transactions in a processor are completed or that any
1169  * MCA due to thes outstanding transaction is taken.
1170  */
1171 static inline s64
1172 ia64_pal_mc_drain (void)
1173 {
1174         struct ia64_pal_retval iprv;
1175         PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1176         return iprv.status;
1177 }
1178
1179 /* Return the machine check dynamic processor state */
1180 static inline s64
1181 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1182 {
1183         struct ia64_pal_retval iprv;
1184         PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1185         if (size)
1186                 *size = iprv.v0;
1187         if (pds)
1188                 *pds = iprv.v1;
1189         return iprv.status;
1190 }
1191
1192 /* Return processor machine check information */
1193 static inline s64
1194 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1195 {
1196         struct ia64_pal_retval iprv;
1197         PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1198         if (size)
1199                 *size = iprv.v0;
1200         if (error_info)
1201                 *error_info = iprv.v1;
1202         return iprv.status;
1203 }
1204
1205 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1206  * attempt to correct any expected machine checks.
1207  */
1208 static inline s64
1209 ia64_pal_mc_expected (u64 expected, u64 *previous)
1210 {
1211         struct ia64_pal_retval iprv;
1212         PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1213         if (previous)
1214                 *previous = iprv.v0;
1215         return iprv.status;
1216 }
1217
1218 /* Register a platform dependent location with PAL to which it can save
1219  * minimal processor state in the event of a machine check or initialization
1220  * event.
1221  */
1222 static inline s64
1223 ia64_pal_mc_register_mem (u64 physical_addr)
1224 {
1225         struct ia64_pal_retval iprv;
1226         PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1227         return iprv.status;
1228 }
1229
1230 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1231  * and resume execution
1232  */
1233 static inline s64
1234 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1235 {
1236         struct ia64_pal_retval iprv;
1237         PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1238         return iprv.status;
1239 }
1240
1241 /* Return the memory attributes implemented by the processor */
1242 static inline s64
1243 ia64_pal_mem_attrib (u64 *mem_attrib)
1244 {
1245         struct ia64_pal_retval iprv;
1246         PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1247         if (mem_attrib)
1248                 *mem_attrib = iprv.v0 & 0xff;
1249         return iprv.status;
1250 }
1251
1252 /* Return the amount of memory needed for second phase of processor
1253  * self-test and the required alignment of memory.
1254  */
1255 static inline s64
1256 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1257 {
1258         struct ia64_pal_retval iprv;
1259         PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1260         if (bytes_needed)
1261                 *bytes_needed = iprv.v0;
1262         if (alignment)
1263                 *alignment = iprv.v1;
1264         return iprv.status;
1265 }
1266
1267 typedef union pal_perf_mon_info_u {
1268         u64                       ppmi_data;
1269         struct {
1270                u64              generic         : 8,
1271                                 width           : 8,
1272                                 cycles          : 8,
1273                                 retired         : 8,
1274                                 reserved        : 32;
1275         } pal_perf_mon_info_s;
1276 } pal_perf_mon_info_u_t;
1277
1278 /* Return the performance monitor information about what can be counted
1279  * and how to configure the monitors to count the desired events.
1280  */
1281 static inline s64
1282 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1283 {
1284         struct ia64_pal_retval iprv;
1285         PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1286         if (pm_info)
1287                 pm_info->ppmi_data = iprv.v0;
1288         return iprv.status;
1289 }
1290
1291 /* Specifies the physical address of the processor interrupt block
1292  * and I/O port space.
1293  */
1294 static inline s64
1295 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1296 {
1297         struct ia64_pal_retval iprv;
1298         PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1299         return iprv.status;
1300 }
1301
1302 /* Set the SAL PMI entrypoint in memory */
1303 static inline s64
1304 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1305 {
1306         struct ia64_pal_retval iprv;
1307         PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1308         return iprv.status;
1309 }
1310
1311 struct pal_features_s;
1312 /* Provide information about configurable processor features */
1313 static inline s64
1314 ia64_pal_proc_get_features (u64 *features_avail,
1315                             u64 *features_status,
1316                             u64 *features_control)
1317 {
1318         struct ia64_pal_retval iprv;
1319         PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1320         if (iprv.status == 0) {
1321                 *features_avail   = iprv.v0;
1322                 *features_status  = iprv.v1;
1323                 *features_control = iprv.v2;
1324         }
1325         return iprv.status;
1326 }
1327
1328 /* Enable/disable processor dependent features */
1329 static inline s64
1330 ia64_pal_proc_set_features (u64 feature_select)
1331 {
1332         struct ia64_pal_retval iprv;
1333         PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1334         return iprv.status;
1335 }
1336
1337 /*
1338  * Put everything in a struct so we avoid the global offset table whenever
1339  * possible.
1340  */
1341 typedef struct ia64_ptce_info_s {
1342         u64             base;
1343         u32             count[2];
1344         u32             stride[2];
1345 } ia64_ptce_info_t;
1346
1347 /* Return the information required for the architected loop used to purge
1348  * (initialize) the entire TC
1349  */
1350 static inline s64
1351 ia64_get_ptce (ia64_ptce_info_t *ptce)
1352 {
1353         struct ia64_pal_retval iprv;
1354
1355         if (!ptce)
1356                 return -1;
1357
1358         PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1359         if (iprv.status == 0) {
1360                 ptce->base = iprv.v0;
1361                 ptce->count[0] = iprv.v1 >> 32;
1362                 ptce->count[1] = iprv.v1 & 0xffffffff;
1363                 ptce->stride[0] = iprv.v2 >> 32;
1364                 ptce->stride[1] = iprv.v2 & 0xffffffff;
1365         }
1366         return iprv.status;
1367 }
1368
1369 /* Return info about implemented application and control registers. */
1370 static inline s64
1371 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1372 {
1373         struct ia64_pal_retval iprv;
1374         PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1375         if (reg_info_1)
1376                 *reg_info_1 = iprv.v0;
1377         if (reg_info_2)
1378                 *reg_info_2 = iprv.v1;
1379         return iprv.status;
1380 }
1381
1382 typedef union pal_hints_u {
1383         u64                     ph_data;
1384         struct {
1385                u64              si              : 1,
1386                                 li              : 1,
1387                                 reserved        : 62;
1388         } pal_hints_s;
1389 } pal_hints_u_t;
1390
1391 /* Return information about the register stack and RSE for this processor
1392  * implementation.
1393  */
1394 static inline s64
1395 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1396 {
1397         struct ia64_pal_retval iprv;
1398         PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1399         if (num_phys_stacked)
1400                 *num_phys_stacked = iprv.v0;
1401         if (hints)
1402                 hints->ph_data = iprv.v1;
1403         return iprv.status;
1404 }
1405
1406 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1407  * suspended, but cause cache and TLB coherency to be maintained.
1408  * This is usually called in IA-32 mode.
1409  */
1410 static inline s64
1411 ia64_pal_shutdown (void)
1412 {
1413         struct ia64_pal_retval iprv;
1414         PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1415         return iprv.status;
1416 }
1417
1418 /* Perform the second phase of processor self-test. */
1419 static inline s64
1420 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1421 {
1422         struct ia64_pal_retval iprv;
1423         PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1424         if (self_test_state)
1425                 *self_test_state = iprv.v0;
1426         return iprv.status;
1427 }
1428
1429 typedef union  pal_version_u {
1430         u64     pal_version_val;
1431         struct {
1432                 u64     pv_pal_b_rev            :       8;
1433                 u64     pv_pal_b_model          :       8;
1434                 u64     pv_reserved1            :       8;
1435                 u64     pv_pal_vendor           :       8;
1436                 u64     pv_pal_a_rev            :       8;
1437                 u64     pv_pal_a_model          :       8;
1438                 u64     pv_reserved2            :       16;
1439         } pal_version_s;
1440 } pal_version_u_t;
1441
1442
1443 /*
1444  * Return PAL version information.  While the documentation states that
1445  * PAL_VERSION can be called in either physical or virtual mode, some
1446  * implementations only allow physical calls.  We don't call it very often,
1447  * so the overhead isn't worth eliminating.
1448  */
1449 static inline s64
1450 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1451 {
1452         struct ia64_pal_retval iprv;
1453         PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1454         if (pal_min_version)
1455                 pal_min_version->pal_version_val = iprv.v0;
1456
1457         if (pal_cur_version)
1458                 pal_cur_version->pal_version_val = iprv.v1;
1459
1460         return iprv.status;
1461 }
1462
1463 typedef union pal_tc_info_u {
1464         u64                     pti_val;
1465         struct {
1466                u64              num_sets        :       8,
1467                                 associativity   :       8,
1468                                 num_entries     :       16,
1469                                 pf              :       1,
1470                                 unified         :       1,
1471                                 reduce_tr       :       1,
1472                                 reserved        :       29;
1473         } pal_tc_info_s;
1474 } pal_tc_info_u_t;
1475
1476 #define tc_reduce_tr            pal_tc_info_s.reduce_tr
1477 #define tc_unified              pal_tc_info_s.unified
1478 #define tc_pf                   pal_tc_info_s.pf
1479 #define tc_num_entries          pal_tc_info_s.num_entries
1480 #define tc_associativity        pal_tc_info_s.associativity
1481 #define tc_num_sets             pal_tc_info_s.num_sets
1482
1483
1484 /* Return information about the virtual memory characteristics of the processor
1485  * implementation.
1486  */
1487 static inline s64
1488 ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
1489 {
1490         struct ia64_pal_retval iprv;
1491         PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1492         if (tc_info)
1493                 tc_info->pti_val = iprv.v0;
1494         if (tc_pages)
1495                 *tc_pages = iprv.v1;
1496         return iprv.status;
1497 }
1498
1499 /* Get page size information about the virtual memory characteristics of the processor
1500  * implementation.
1501  */
1502 static inline s64
1503 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1504 {
1505         struct ia64_pal_retval iprv;
1506         PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1507         if (tr_pages)
1508                 *tr_pages = iprv.v0;
1509         if (vw_pages)
1510                 *vw_pages = iprv.v1;
1511         return iprv.status;
1512 }
1513
1514 typedef union pal_vm_info_1_u {
1515         u64                     pvi1_val;
1516         struct {
1517                 u64             vw              : 1,
1518                                 phys_add_size   : 7,
1519                                 key_size        : 8,
1520                                 max_pkr         : 8,
1521                                 hash_tag_id     : 8,
1522                                 max_dtr_entry   : 8,
1523                                 max_itr_entry   : 8,
1524                                 max_unique_tcs  : 8,
1525                                 num_tc_levels   : 8;
1526         } pal_vm_info_1_s;
1527 } pal_vm_info_1_u_t;
1528
1529 typedef union pal_vm_info_2_u {
1530         u64                     pvi2_val;
1531         struct {
1532                 u64             impl_va_msb     : 8,
1533                                 rid_size        : 8,
1534                                 reserved        : 48;
1535         } pal_vm_info_2_s;
1536 } pal_vm_info_2_u_t;
1537
1538 /* Get summary information about the virtual memory characteristics of the processor
1539  * implementation.
1540  */
1541 static inline s64
1542 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1543 {
1544         struct ia64_pal_retval iprv;
1545         PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1546         if (vm_info_1)
1547                 vm_info_1->pvi1_val = iprv.v0;
1548         if (vm_info_2)
1549                 vm_info_2->pvi2_val = iprv.v1;
1550         return iprv.status;
1551 }
1552
1553 typedef union pal_itr_valid_u {
1554         u64                     piv_val;
1555         struct {
1556                u64              access_rights_valid     : 1,
1557                                 priv_level_valid        : 1,
1558                                 dirty_bit_valid         : 1,
1559                                 mem_attr_valid          : 1,
1560                                 reserved                : 60;
1561         } pal_tr_valid_s;
1562 } pal_tr_valid_u_t;
1563
1564 /* Read a translation register */
1565 static inline s64
1566 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1567 {
1568         struct ia64_pal_retval iprv;
1569         PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1570         if (tr_valid)
1571                 tr_valid->piv_val = iprv.v0;
1572         return iprv.status;
1573 }
1574
1575 /*
1576  * PAL_PREFETCH_VISIBILITY transaction types
1577  */
1578 #define PAL_VISIBILITY_VIRTUAL          0
1579 #define PAL_VISIBILITY_PHYSICAL         1
1580
1581 /*
1582  * PAL_PREFETCH_VISIBILITY return codes
1583  */
1584 #define PAL_VISIBILITY_OK               1
1585 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1586 #define PAL_VISIBILITY_INVAL_ARG        -2
1587 #define PAL_VISIBILITY_ERROR            -3
1588
1589 static inline s64
1590 ia64_pal_prefetch_visibility (s64 trans_type)
1591 {
1592         struct ia64_pal_retval iprv;
1593         PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1594         return iprv.status;
1595 }
1596
1597 /* data structure for getting information on logical to physical mappings */
1598 typedef union pal_log_overview_u {
1599         struct {
1600                 u64     num_log         :16,    /* Total number of logical
1601                                                  * processors on this die
1602                                                  */
1603                         tpc             :8,     /* Threads per core */
1604                         reserved3       :8,     /* Reserved */
1605                         cpp             :8,     /* Cores per processor */
1606                         reserved2       :8,     /* Reserved */
1607                         ppid            :8,     /* Physical processor ID */
1608                         reserved1       :8;     /* Reserved */
1609         } overview_bits;
1610         u64 overview_data;
1611 } pal_log_overview_t;
1612
1613 typedef union pal_proc_n_log_info1_u{
1614         struct {
1615                 u64     tid             :16,    /* Thread id */
1616                         reserved2       :16,    /* Reserved */
1617                         cid             :16,    /* Core id */
1618                         reserved1       :16;    /* Reserved */
1619         } ppli1_bits;
1620         u64     ppli1_data;
1621 } pal_proc_n_log_info1_t;
1622
1623 typedef union pal_proc_n_log_info2_u {
1624         struct {
1625                 u64     la              :16,    /* Logical address */
1626                         reserved        :48;    /* Reserved */
1627         } ppli2_bits;
1628         u64     ppli2_data;
1629 } pal_proc_n_log_info2_t;
1630
1631 typedef struct pal_logical_to_physical_s
1632 {
1633         pal_log_overview_t overview;
1634         pal_proc_n_log_info1_t ppli1;
1635         pal_proc_n_log_info2_t ppli2;
1636 } pal_logical_to_physical_t;
1637
1638 #define overview_num_log        overview.overview_bits.num_log
1639 #define overview_tpc            overview.overview_bits.tpc
1640 #define overview_cpp            overview.overview_bits.cpp
1641 #define overview_ppid           overview.overview_bits.ppid
1642 #define log1_tid                ppli1.ppli1_bits.tid
1643 #define log1_cid                ppli1.ppli1_bits.cid
1644 #define log2_la                 ppli2.ppli2_bits.la
1645
1646 /* Get information on logical to physical processor mappings. */
1647 static inline s64
1648 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1649 {
1650         struct ia64_pal_retval iprv;
1651
1652         PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1653
1654         if (iprv.status == PAL_STATUS_SUCCESS)
1655         {
1656                 mapping->overview.overview_data = iprv.v0;
1657                 mapping->ppli1.ppli1_data = iprv.v1;
1658                 mapping->ppli2.ppli2_data = iprv.v2;
1659         }
1660
1661         return iprv.status;
1662 }
1663
1664 typedef struct pal_cache_shared_info_s
1665 {
1666         u64 num_shared;
1667         pal_proc_n_log_info1_t ppli1;
1668         pal_proc_n_log_info2_t ppli2;
1669 } pal_cache_shared_info_t;
1670
1671 /* Get information on logical to physical processor mappings. */
1672 static inline s64
1673 ia64_pal_cache_shared_info(u64 level,
1674                 u64 type,
1675                 u64 proc_number,
1676                 pal_cache_shared_info_t *info)
1677 {
1678         struct ia64_pal_retval iprv;
1679
1680         PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1681
1682         if (iprv.status == PAL_STATUS_SUCCESS) {
1683                 info->num_shared = iprv.v0;
1684                 info->ppli1.ppli1_data = iprv.v1;
1685                 info->ppli2.ppli2_data = iprv.v2;
1686         }
1687
1688         return iprv.status;
1689 }
1690 #endif /* __ASSEMBLY__ */
1691
1692 #endif /* _ASM_IA64_PAL_H */