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Staging: merge 2.6.39-rc3 into staging-next
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / gma500 / psb_drv.c
blob711e5a997c957bab8070cda9c722db544ce4dd0c
1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
3 * All Rights Reserved.
4 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
5 * All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 **************************************************************************/
21
22 #include <drm/drmP.h>
23 #include <drm/drm.h>
24 #include "psb_drm.h"
25 #include "psb_drv.h"
26 #include "psb_fb.h"
27 #include "psb_reg.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_bios.h"
30 #include <drm/drm_pciids.h>
31 #include "psb_powermgmt.h"
32 #include <linux/cpu.h>
33 #include <linux/notifier.h>
34 #include <linux/spinlock.h>
35 #include <linux/pm_runtime.h>
36 #include <acpi/video.h>
37
38 int drm_psb_debug;
39 static int drm_psb_trap_pagefaults;
40
41 int drm_psb_no_fb;
42
43 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
44
45 MODULE_PARM_DESC(debug, "Enable debug output");
46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
48 module_param_named(debug, drm_psb_debug, int, 0600);
49 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
50 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
51
52
53 static struct pci_device_id pciidlist[] = {
54 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
55 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
56 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
57 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
58 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
59 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
60 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
61 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
62 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
63 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
64 { 0, 0, 0}
65 };
66 MODULE_DEVICE_TABLE(pci, pciidlist);
67
68 /*
69 * Standard IOCTLs.
70 */
71
72 #define DRM_IOCTL_PSB_KMS_OFF \
73 DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
74 #define DRM_IOCTL_PSB_KMS_ON \
75 DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
76 #define DRM_IOCTL_PSB_VT_LEAVE \
77 DRM_IO(DRM_PSB_VT_LEAVE + DRM_COMMAND_BASE)
78 #define DRM_IOCTL_PSB_VT_ENTER \
79 DRM_IO(DRM_PSB_VT_ENTER + DRM_COMMAND_BASE)
80 #define DRM_IOCTL_PSB_SIZES \
81 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
82 struct drm_psb_sizes_arg)
83 #define DRM_IOCTL_PSB_FUSE_REG \
84 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
85 #define DRM_IOCTL_PSB_DC_STATE \
86 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
87 struct drm_psb_dc_state_arg)
88 #define DRM_IOCTL_PSB_ADB \
89 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
90 #define DRM_IOCTL_PSB_MODE_OPERATION \
91 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
92 struct drm_psb_mode_operation_arg)
93 #define DRM_IOCTL_PSB_STOLEN_MEMORY \
94 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
95 struct drm_psb_stolen_memory_arg)
96 #define DRM_IOCTL_PSB_REGISTER_RW \
97 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
98 struct drm_psb_register_rw_arg)
99 #define DRM_IOCTL_PSB_GTT_MAP \
100 DRM_IOWR(DRM_PSB_GTT_MAP + DRM_COMMAND_BASE, \
101 struct psb_gtt_mapping_arg)
102 #define DRM_IOCTL_PSB_GTT_UNMAP \
103 DRM_IOW(DRM_PSB_GTT_UNMAP + DRM_COMMAND_BASE, \
104 struct psb_gtt_mapping_arg)
105 #define DRM_IOCTL_PSB_UPDATE_GUARD \
106 DRM_IOWR(DRM_PSB_UPDATE_GUARD + DRM_COMMAND_BASE, \
107 uint32_t)
108 #define DRM_IOCTL_PSB_DPST \
109 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
110 uint32_t)
111 #define DRM_IOCTL_PSB_GAMMA \
112 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
113 struct drm_psb_dpst_lut_arg)
114 #define DRM_IOCTL_PSB_DPST_BL \
115 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
116 uint32_t)
117 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID \
118 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
119 struct drm_psb_get_pipe_from_crtc_id_arg)
120
121 #define DRM_IOCTL_PSB_KMS_OFF DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
122 #define DRM_IOCTL_PSB_KMS_ON DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
123
124 static int psb_vt_leave_ioctl(struct drm_device *dev, void *data,
125 struct drm_file *file_priv);
126 static int psb_vt_enter_ioctl(struct drm_device *dev, void *data,
127 struct drm_file *file_priv);
128 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
129 struct drm_file *file_priv);
130 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
131 struct drm_file *file_priv);
132 static int psb_adb_ioctl(struct drm_device *dev, void *data,
133 struct drm_file *file_priv);
134 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
135 struct drm_file *file_priv);
136 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
137 struct drm_file *file_priv);
138 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
139 struct drm_file *file_priv);
140 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
141 struct drm_file *file_priv);
142 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
143 struct drm_file *file_priv);
144 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
145 struct drm_file *file_priv);
146
147 #define PSB_IOCTL_DEF(ioctl, func, flags) \
148 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
149
150 static struct drm_ioctl_desc psb_ioctls[] = {
151 PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_OFF, psbfb_kms_off_ioctl,
152 DRM_ROOT_ONLY),
153 PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_ON,
154 psbfb_kms_on_ioctl,
155 DRM_ROOT_ONLY),
156 PSB_IOCTL_DEF(DRM_IOCTL_PSB_VT_LEAVE, psb_vt_leave_ioctl,
157 DRM_ROOT_ONLY),
158 PSB_IOCTL_DEF(DRM_IOCTL_PSB_VT_ENTER,
159 psb_vt_enter_ioctl,
160 DRM_ROOT_ONLY),
161 PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
162 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
163 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
164 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
165 DRM_AUTH),
166 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
167 DRM_AUTH),
168 PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
169 DRM_AUTH),
170 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GTT_MAP,
171 psb_gtt_map_meminfo_ioctl,
172 DRM_AUTH),
173 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GTT_UNMAP,
174 psb_gtt_unmap_meminfo_ioctl,
175 DRM_AUTH),
176 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
177 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
178 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
179 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
180 psb_intel_get_pipe_from_crtc_id, 0),
181
182 };
183
184 static void psb_lastclose(struct drm_device *dev)
185 {
186 return;
187 }
188
189 static void psb_do_takedown(struct drm_device *dev)
190 {
191 /* FIXME: do we need to clean up the gtt here ? */
192 }
193
194 void mrst_get_fuse_settings(struct drm_device *dev)
195 {
196 struct drm_psb_private *dev_priv = dev->dev_private;
197 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
198 uint32_t fuse_value = 0;
199 uint32_t fuse_value_tmp = 0;
200
201 #define FB_REG06 0xD0810600
202 #define FB_MIPI_DISABLE (1 << 11)
203 #define FB_REG09 0xD0810900
204 #define FB_REG09 0xD0810900
205 #define FB_SKU_MASK 0x7000
206 #define FB_SKU_SHIFT 12
207 #define FB_SKU_100 0
208 #define FB_SKU_100L 1
209 #define FB_SKU_83 2
210 pci_write_config_dword(pci_root, 0xD0, FB_REG06);
211 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
212
213 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
214
215 DRM_INFO("internal display is %s\n",
216 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
217
218 /*prevent Runtime suspend at start*/
219 if (dev_priv->iLVDS_enable) {
220 dev_priv->is_lvds_on = true;
221 dev_priv->is_mipi_on = false;
222 }
223 else {
224 dev_priv->is_mipi_on = true;
225 dev_priv->is_lvds_on = false;
226 }
227
228 dev_priv->video_device_fuse = fuse_value;
229
230 pci_write_config_dword(pci_root, 0xD0, FB_REG09);
231 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
232
233 DRM_INFO("SKU values is 0x%x. \n", fuse_value);
234 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
235
236 dev_priv->fuse_reg_value = fuse_value;
237
238 switch (fuse_value_tmp) {
239 case FB_SKU_100:
240 dev_priv->core_freq = 200;
241 break;
242 case FB_SKU_100L:
243 dev_priv->core_freq = 100;
244 break;
245 case FB_SKU_83:
246 dev_priv->core_freq = 166;
247 break;
248 default:
249 DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp);
250 dev_priv->core_freq = 0;
251 }
252 DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
253 pci_dev_put(pci_root);
254 }
255
256 void mid_get_pci_revID (struct drm_psb_private *dev_priv)
257 {
258 uint32_t platform_rev_id = 0;
259 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
260
261 /*get the revison ID, B0:D2:F0;0x08 */
262 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
263 dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
264 pci_dev_put(pci_gfx_root);
265 PSB_DEBUG_ENTRY("platform_rev_id is %x\n", dev_priv->platform_rev_id);
266 }
267
268 void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
269 {
270 struct mrst_vbt *vbt = &dev_priv->vbt_data;
271 u32 platform_config_address;
272 u16 new_size;
273 u8 *vbt_virtual;
274 u8 bpi;
275 u8 number_desc = 0;
276 struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
277 struct gct_r10_timing_info ti;
278 void *pGCT;
279 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
280
281 /*get the address of the platform config vbt, B0:D2:F0;0xFC */
282 pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
283 pci_dev_put(pci_gfx_root);
284 DRM_INFO("drm platform config address is %x\n",
285 platform_config_address);
286
287 /* check for platform config address == 0. */
288 /* this means fw doesn't support vbt */
289
290 if (platform_config_address == 0) {
291 vbt->size = 0;
292 return;
293 }
294
295 /* get the virtual address of the vbt */
296 vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
297
298 memcpy(vbt, vbt_virtual, sizeof(*vbt));
299 iounmap(vbt_virtual); /* Free virtual address space */
300
301 printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
302
303 switch (vbt->revision) {
304 case 0:
305 vbt->mrst_gct = NULL;
306 vbt->mrst_gct = \
307 ioremap(platform_config_address + sizeof(*vbt) - 4,
308 vbt->size - sizeof(*vbt) + 4);
309 pGCT = vbt->mrst_gct;
310 bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
311 dev_priv->gct_data.bpi = bpi;
312 dev_priv->gct_data.pt =
313 ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
314 memcpy(&dev_priv->gct_data.DTD,
315 &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
316 sizeof(struct mrst_timing_info));
317 dev_priv->gct_data.Panel_Port_Control =
318 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
319 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
320 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
321 break;
322 case 1:
323 vbt->mrst_gct = NULL;
324 vbt->mrst_gct = \
325 ioremap(platform_config_address + sizeof(*vbt) - 4,
326 vbt->size - sizeof(*vbt) + 4);
327 pGCT = vbt->mrst_gct;
328 bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
329 dev_priv->gct_data.bpi = bpi;
330 dev_priv->gct_data.pt =
331 ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
332 memcpy(&dev_priv->gct_data.DTD,
333 &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
334 sizeof(struct mrst_timing_info));
335 dev_priv->gct_data.Panel_Port_Control =
336 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
337 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
338 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
339 break;
340 case 0x10:
341 /*header definition changed from rev 01 (v2) to rev 10h. */
342 /*so, some values have changed location*/
343 new_size = vbt->checksum; /*checksum contains lo size byte*/
344 /*LSB of mrst_gct contains hi size byte*/
345 new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
346
347 vbt->checksum = vbt->size; /*size contains the checksum*/
348 if (new_size > 0xff)
349 vbt->size = 0xff; /*restrict size to 255*/
350 else
351 vbt->size = new_size;
352
353 /* number of descriptors defined in the GCT */
354 number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
355 bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
356 vbt->mrst_gct = NULL;
357 vbt->mrst_gct = \
358 ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
359 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
360 pGCT = vbt->mrst_gct;
361 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
362 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
363
364 /*copy the GCT display timings into a temp structure*/
365 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
366
367 /*now copy the temp struct into the dev_priv->gct_data*/
368 dp_ti->pixel_clock = ti.pixel_clock;
369 dp_ti->hactive_hi = ti.hactive_hi;
370 dp_ti->hactive_lo = ti.hactive_lo;
371 dp_ti->hblank_hi = ti.hblank_hi;
372 dp_ti->hblank_lo = ti.hblank_lo;
373 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
374 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
375 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
376 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
377 dp_ti->vactive_hi = ti.vactive_hi;
378 dp_ti->vactive_lo = ti.vactive_lo;
379 dp_ti->vblank_hi = ti.vblank_hi;
380 dp_ti->vblank_lo = ti.vblank_lo;
381 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
382 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
383 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
384 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
385
386 /*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
387 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
388 *((u8 *)pGCT + 0x0d);
389 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
390 (*((u8 *)pGCT + 0x0e)) << 8;
391 break;
392 default:
393 printk(KERN_ERR "Unknown revision of GCT!\n");
394 vbt->size = 0;
395 }
396 }
397
398 static void psb_get_core_freq(struct drm_device *dev)
399 {
400 uint32_t clock;
401 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
402 struct drm_psb_private *dev_priv = dev->dev_private;
403
404 /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
405 /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
406
407 pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
408 pci_read_config_dword(pci_root, 0xD4, &clock);
409 pci_dev_put(pci_root);
410
411 switch (clock & 0x07) {
412 case 0:
413 dev_priv->core_freq = 100;
414 break;
415 case 1:
416 dev_priv->core_freq = 133;
417 break;
418 case 2:
419 dev_priv->core_freq = 150;
420 break;
421 case 3:
422 dev_priv->core_freq = 178;
423 break;
424 case 4:
425 dev_priv->core_freq = 200;
426 break;
427 case 5:
428 case 6:
429 case 7:
430 dev_priv->core_freq = 266;
431 default:
432 dev_priv->core_freq = 0;
433 }
434 }
435
436 static int psb_do_init(struct drm_device *dev)
437 {
438 struct drm_psb_private *dev_priv =
439 (struct drm_psb_private *) dev->dev_private;
440 struct psb_gtt *pg = dev_priv->pg;
441
442 uint32_t stolen_gtt;
443 uint32_t tt_start;
444 uint32_t tt_pages;
445
446 int ret = -ENOMEM;
447
448 if (pg->mmu_gatt_start & 0x0FFFFFFF) {
449 DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n");
450 ret = -EINVAL;
451 goto out_err;
452 }
453
454
455 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
456 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
457 stolen_gtt =
458 (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
459
460 dev_priv->gatt_free_offset = pg->mmu_gatt_start +
461 (stolen_gtt << PAGE_SHIFT) * 1024;
462
463 if (1 || drm_debug) {
464 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
465 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
466 DRM_INFO("SGX core id = 0x%08x\n", core_id);
467 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
468 (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
469 _PSB_CC_REVISION_MAJOR_SHIFT,
470 (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
471 _PSB_CC_REVISION_MINOR_SHIFT);
472 DRM_INFO
473 ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
474 (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
475 _PSB_CC_REVISION_MAINTENANCE_SHIFT,
476 (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
477 _PSB_CC_REVISION_DESIGNER_SHIFT);
478 }
479
480
481 spin_lock_init(&dev_priv->irqmask_lock);
482
483 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
484 pg->gatt_pages : PSB_TT_PRIV0_PLIMIT;
485 tt_start = dev_priv->gatt_free_offset - pg->mmu_gatt_start;
486 tt_pages -= tt_start >> PAGE_SHIFT;
487 /* FIXME: can we kill ta_mem_size ? */
488 dev_priv->sizes.ta_mem_size = 0;
489
490 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
491 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
492 PSB_RSGX32(PSB_CR_BIF_BANK1);
493 PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
494 PSB_CR_BIF_CTRL);
495 psb_spank(dev_priv);
496
497 /* mmu_gatt ?? */
498 printk(KERN_INFO "TWOD base %08lX\n", (u32) pg->gatt_start);
499 PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
500
501 return 0;
502 out_err:
503 psb_do_takedown(dev);
504 return ret;
505 }
506
507 static int psb_driver_unload(struct drm_device *dev)
508 {
509 struct drm_psb_private *dev_priv =
510 (struct drm_psb_private *) dev->dev_private;
511
512 /* Kill vblank etc here */
513
514 psb_backlight_exit(); /*writes minimum value to backlight HW reg */
515
516 if (drm_psb_no_fb == 0)
517 psb_modeset_cleanup(dev);
518
519 if (dev_priv) {
520 psb_lid_timer_takedown(dev_priv);
521
522 psb_do_takedown(dev);
523
524
525 if (dev_priv->pf_pd) {
526 psb_mmu_free_pagedir(dev_priv->pf_pd);
527 dev_priv->pf_pd = NULL;
528 }
529 if (dev_priv->mmu) {
530 struct psb_gtt *pg = dev_priv->pg;
531
532 down_read(&pg->sem);
533 psb_mmu_remove_pfn_sequence(
534 psb_mmu_get_default_pd
535 (dev_priv->mmu),
536 pg->mmu_gatt_start,
537 pg->vram_stolen_size >> PAGE_SHIFT);
538 up_read(&pg->sem);
539 psb_mmu_driver_takedown(dev_priv->mmu);
540 dev_priv->mmu = NULL;
541 }
542 psb_gtt_takedown(dev_priv->pg, 1);
543 if (dev_priv->scratch_page) {
544 __free_page(dev_priv->scratch_page);
545 dev_priv->scratch_page = NULL;
546 }
547 if (dev_priv->vdc_reg) {
548 iounmap(dev_priv->vdc_reg);
549 dev_priv->vdc_reg = NULL;
550 }
551 if (dev_priv->sgx_reg) {
552 iounmap(dev_priv->sgx_reg);
553 dev_priv->sgx_reg = NULL;
554 }
555
556 kfree(dev_priv);
557 dev->dev_private = NULL;
558
559 /*destroy VBT data*/
560 psb_intel_destroy_bios(dev);
561 }
562
563 gma_power_uninit(dev);
564
565 return 0;
566 }
567
568
569 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
570 {
571 struct drm_psb_private *dev_priv;
572 unsigned long resource_start;
573 struct psb_gtt *pg;
574 unsigned long irqflags;
575 int ret = -ENOMEM;
576 uint32_t tt_pages;
577
578 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
579 if (dev_priv == NULL)
580 return -ENOMEM;
581
582 if (IS_MRST(dev))
583 dev_priv->num_pipe = 1;
584 else
585 dev_priv->num_pipe = 2;
586
587 dev_priv->dev = dev;
588
589 dev->dev_private = (void *) dev_priv;
590 dev_priv->chipset = chipset;
591
592 PSB_DEBUG_INIT("Mapping MMIO\n");
593 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
594
595 dev_priv->vdc_reg =
596 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
597 if (!dev_priv->vdc_reg)
598 goto out_err;
599
600 dev_priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET,
601 PSB_SGX_SIZE);
602
603 if (!dev_priv->sgx_reg)
604 goto out_err;
605
606 if (IS_MRST(dev)) {
607 mrst_get_fuse_settings(dev);
608 mrst_get_vbt_data(dev_priv);
609 mid_get_pci_revID(dev_priv);
610 } else {
611 psb_get_core_freq(dev);
612 psb_intel_opregion_init(dev);
613 psb_intel_init_bios(dev);
614 }
615
616 /* Init OSPM support */
617 gma_power_init(dev);
618
619 ret = -ENOMEM;
620
621 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
622 if (!dev_priv->scratch_page)
623 goto out_err;
624
625 set_pages_uc(dev_priv->scratch_page, 1);
626
627 dev_priv->pg = psb_gtt_alloc(dev);
628 if (!dev_priv->pg)
629 goto out_err;
630
631 ret = psb_gtt_init(dev_priv->pg, 0);
632 if (ret)
633 goto out_err;
634
635 ret = psb_gtt_mm_init(dev_priv->pg);
636 if (ret)
637 goto out_err;
638
639 dev_priv->mmu = psb_mmu_driver_init((void *)0,
640 drm_psb_trap_pagefaults, 0,
641 dev_priv);
642 if (!dev_priv->mmu)
643 goto out_err;
644
645 pg = dev_priv->pg;
646
647 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
648 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
649
650
651 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
652 if (!dev_priv->pf_pd)
653 goto out_err;
654
655 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
656 psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
657
658 ret = psb_do_init(dev);
659 if (ret)
660 return ret;
661
662 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
663 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
664
665 /* igd_opregion_init(&dev_priv->opregion_dev); */
666 acpi_video_register();
667 if (dev_priv->lid_state)
668 psb_lid_timer_init(dev_priv);
669
670 ret = drm_vblank_init(dev, dev_priv->num_pipe);
671 if (ret)
672 goto out_err;
673
674 /*
675 * Install interrupt handlers prior to powering off SGX or else we will
676 * crash.
677 */
678 dev_priv->vdc_irq_mask = 0;
679 dev_priv->pipestat[0] = 0;
680 dev_priv->pipestat[1] = 0;
681 dev_priv->pipestat[2] = 0;
682 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
683 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
684 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
685 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
686 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
687 if (drm_core_check_feature(dev, DRIVER_MODESET))
688 drm_irq_install(dev);
689
690 dev->vblank_disable_allowed = 1;
691
692 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
693
694 dev->driver->get_vblank_counter = psb_get_vblank_counter;
695
696 if (drm_psb_no_fb == 0) {
697 psb_modeset_init(dev);
698 psb_fbdev_init(dev);
699 drm_kms_helper_poll_init(dev);
700 }
701
702 ret = psb_backlight_init(dev);
703 if (ret)
704 return ret;
705 #if 0
706 /*enable runtime pm at last*/
707 pm_runtime_enable(&dev->pdev->dev);
708 pm_runtime_set_active(&dev->pdev->dev);
709 #endif
710 /*Intel drm driver load is done, continue doing pvr load*/
711 DRM_DEBUG("Pvr driver load\n");
712 return 0;
713 out_err:
714 psb_driver_unload(dev);
715 return ret;
716 }
717
718 int psb_driver_device_is_agp(struct drm_device *dev)
719 {
720 return 0;
721 }
722
723
724 static int psb_vt_leave_ioctl(struct drm_device *dev, void *data,
725 struct drm_file *file_priv)
726 {
727 return 0;
728 }
729
730 static int psb_vt_enter_ioctl(struct drm_device *dev, void *data,
731 struct drm_file *file_priv)
732 {
733 return 0;
734 }
735
736 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
737 struct drm_file *file_priv)
738 {
739 struct drm_psb_private *dev_priv = psb_priv(dev);
740 struct drm_psb_sizes_arg *arg =
741 (struct drm_psb_sizes_arg *) data;
742
743 *arg = dev_priv->sizes;
744 return 0;
745 }
746
747 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
748 struct drm_file *file_priv)
749 {
750 uint32_t flags;
751 uint32_t obj_id;
752 struct drm_mode_object *obj;
753 struct drm_connector *connector;
754 struct drm_crtc *crtc;
755 struct drm_psb_dc_state_arg *arg =
756 (struct drm_psb_dc_state_arg *)data;
757
758 flags = arg->flags;
759 obj_id = arg->obj_id;
760
761 if (flags & PSB_DC_CRTC_MASK) {
762 obj = drm_mode_object_find(dev, obj_id,
763 DRM_MODE_OBJECT_CRTC);
764 if (!obj) {
765 DRM_DEBUG("Invalid CRTC object.\n");
766 return -EINVAL;
767 }
768
769 crtc = obj_to_crtc(obj);
770
771 mutex_lock(&dev->mode_config.mutex);
772 if (drm_helper_crtc_in_use(crtc)) {
773 if (flags & PSB_DC_CRTC_SAVE)
774 crtc->funcs->save(crtc);
775 else
776 crtc->funcs->restore(crtc);
777 }
778 mutex_unlock(&dev->mode_config.mutex);
779
780 return 0;
781 } else if (flags & PSB_DC_OUTPUT_MASK) {
782 obj = drm_mode_object_find(dev, obj_id,
783 DRM_MODE_OBJECT_CONNECTOR);
784 if (!obj) {
785 DRM_DEBUG("Invalid connector id.\n");
786 return -EINVAL;
787 }
788
789 connector = obj_to_connector(obj);
790 if (flags & PSB_DC_OUTPUT_SAVE)
791 connector->funcs->save(connector);
792 else
793 connector->funcs->restore(connector);
794
795 return 0;
796 }
797
798 DRM_DEBUG("Bad flags 0x%x\n", flags);
799 return -EINVAL;
800 }
801
802 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
803 struct drm_file *file_priv)
804 {
805 struct drm_psb_private *dev_priv = psb_priv(dev);
806 uint32_t *arg = data;
807 struct backlight_device bd;
808 dev_priv->blc_adj2 = *arg;
809
810 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
811 bd.props.brightness = psb_get_brightness(&bd);
812 psb_set_brightness(&bd);
813 #endif
814 return 0;
815 }
816
817 static int psb_adb_ioctl(struct drm_device *dev, void *data,
818 struct drm_file *file_priv)
819 {
820 struct drm_psb_private *dev_priv = psb_priv(dev);
821 uint32_t *arg = data;
822 struct backlight_device bd;
823 dev_priv->blc_adj1 = *arg;
824
825 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
826 bd.props.brightness = psb_get_brightness(&bd);
827 psb_set_brightness(&bd);
828 #endif
829 return 0;
830 }
831
832 /* return the current mode to the dpst module */
833 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
834 struct drm_file *file_priv)
835 {
836 struct drm_psb_private *dev_priv = psb_priv(dev);
837 uint32_t *arg = data;
838 uint32_t x;
839 uint32_t y;
840 uint32_t reg;
841
842 if (!gma_power_begin(dev, 0))
843 return 0;
844
845 reg = PSB_RVDC32(PIPEASRC);
846
847 gma_power_end(dev);
848
849 /* horizontal is the left 16 bits */
850 x = reg >> 16;
851 /* vertical is the right 16 bits */
852 y = reg & 0x0000ffff;
853
854 /* the values are the image size minus one */
855 x++;
856 y++;
857
858 *arg = (x << 16) | y;
859
860 return 0;
861 }
862 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
863 struct drm_file *file_priv)
864 {
865 struct drm_psb_dpst_lut_arg *lut_arg = data;
866 struct drm_mode_object *obj;
867 struct drm_crtc *crtc;
868 struct drm_connector *connector;
869 struct psb_intel_crtc *psb_intel_crtc;
870 int i = 0;
871 int32_t obj_id;
872
873 obj_id = lut_arg->output_id;
874 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
875 if (!obj) {
876 DRM_DEBUG("Invalid Connector object.\n");
877 return -EINVAL;
878 }
879
880 connector = obj_to_connector(obj);
881 crtc = connector->encoder->crtc;
882 psb_intel_crtc = to_psb_intel_crtc(crtc);
883
884 for (i = 0; i < 256; i++)
885 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
886
887 psb_intel_crtc_load_lut(crtc);
888
889 return 0;
890 }
891
892 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
893 struct drm_file *file_priv)
894 {
895 uint32_t obj_id;
896 uint16_t op;
897 struct drm_mode_modeinfo *umode;
898 struct drm_display_mode *mode = NULL;
899 struct drm_psb_mode_operation_arg *arg;
900 struct drm_mode_object *obj;
901 struct drm_connector *connector;
902 struct drm_framebuffer *drm_fb;
903 struct psb_framebuffer *psb_fb;
904 struct drm_connector_helper_funcs *connector_funcs;
905 int ret = 0;
906 int resp = MODE_OK;
907 struct drm_psb_private *dev_priv = psb_priv(dev);
908
909 arg = (struct drm_psb_mode_operation_arg *)data;
910 obj_id = arg->obj_id;
911 op = arg->operation;
912
913 switch (op) {
914 case PSB_MODE_OPERATION_SET_DC_BASE:
915 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
916 if (!obj) {
917 DRM_ERROR("Invalid FB id %d\n", obj_id);
918 return -EINVAL;
919 }
920
921 drm_fb = obj_to_fb(obj);
922 psb_fb = to_psb_fb(drm_fb);
923
924 if (gma_power_begin(dev, 0)) {
925 REG_WRITE(DSPASURF, psb_fb->offset);
926 REG_READ(DSPASURF);
927 gma_power_end(dev);
928 } else {
929 dev_priv->saveDSPASURF = psb_fb->offset;
930 }
931
932 return 0;
933 case PSB_MODE_OPERATION_MODE_VALID:
934 umode = &arg->mode;
935
936 mutex_lock(&dev->mode_config.mutex);
937
938 obj = drm_mode_object_find(dev, obj_id,
939 DRM_MODE_OBJECT_CONNECTOR);
940 if (!obj) {
941 ret = -EINVAL;
942 goto mode_op_out;
943 }
944
945 connector = obj_to_connector(obj);
946
947 mode = drm_mode_create(dev);
948 if (!mode) {
949 ret = -ENOMEM;
950 goto mode_op_out;
951 }
952
953 /* drm_crtc_convert_umode(mode, umode); */
954 {
955 mode->clock = umode->clock;
956 mode->hdisplay = umode->hdisplay;
957 mode->hsync_start = umode->hsync_start;
958 mode->hsync_end = umode->hsync_end;
959 mode->htotal = umode->htotal;
960 mode->hskew = umode->hskew;
961 mode->vdisplay = umode->vdisplay;
962 mode->vsync_start = umode->vsync_start;
963 mode->vsync_end = umode->vsync_end;
964 mode->vtotal = umode->vtotal;
965 mode->vscan = umode->vscan;
966 mode->vrefresh = umode->vrefresh;
967 mode->flags = umode->flags;
968 mode->type = umode->type;
969 strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
970 mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
971 }
972
973 connector_funcs = (struct drm_connector_helper_funcs *)
974 connector->helper_private;
975
976 if (connector_funcs->mode_valid) {
977 resp = connector_funcs->mode_valid(connector, mode);
978 arg->data = (void *)resp;
979 }
980
981 /*do some clean up work*/
982 if (mode)
983 drm_mode_destroy(dev, mode);
984 mode_op_out:
985 mutex_unlock(&dev->mode_config.mutex);
986 return ret;
987
988 default:
989 DRM_DEBUG("Unsupported psb mode operation");
990 return -EOPNOTSUPP;
991 }
992
993 return 0;
994 }
995
996 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
997 struct drm_file *file_priv)
998 {
999 struct drm_psb_private *dev_priv = psb_priv(dev);
1000 struct drm_psb_stolen_memory_arg *arg = data;
1001
1002 arg->base = dev_priv->pg->stolen_base;
1003 arg->size = dev_priv->pg->vram_stolen_size;
1004
1005 return 0;
1006 }
1007
1008 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv)
1010 {
1011 struct drm_psb_private *dev_priv = psb_priv(dev);
1012 struct drm_psb_register_rw_arg *arg = data;
1013 bool usage = arg->b_force_hw_on ? true : false;
1014
1015 if (arg->display_write_mask != 0) {
1016 if (gma_power_begin(dev, usage)) {
1017 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
1018 PSB_WVDC32(arg->display.pfit_controls,
1019 PFIT_CONTROL);
1020 if (arg->display_write_mask &
1021 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1022 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
1023 PFIT_AUTO_RATIOS);
1024 if (arg->display_write_mask &
1025 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1026 PSB_WVDC32(
1027 arg->display.pfit_programmed_scale_ratios,
1028 PFIT_PGM_RATIOS);
1029 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1030 PSB_WVDC32(arg->display.pipeasrc,
1031 PIPEASRC);
1032 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1033 PSB_WVDC32(arg->display.pipebsrc,
1034 PIPEBSRC);
1035 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1036 PSB_WVDC32(arg->display.vtotal_a,
1037 VTOTAL_A);
1038 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1039 PSB_WVDC32(arg->display.vtotal_b,
1040 VTOTAL_B);
1041 gma_power_end(dev);
1042 } else {
1043 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
1044 dev_priv->savePFIT_CONTROL =
1045 arg->display.pfit_controls;
1046 if (arg->display_write_mask &
1047 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1048 dev_priv->savePFIT_AUTO_RATIOS =
1049 arg->display.pfit_autoscale_ratios;
1050 if (arg->display_write_mask &
1051 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1052 dev_priv->savePFIT_PGM_RATIOS =
1053 arg->display.pfit_programmed_scale_ratios;
1054 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1055 dev_priv->savePIPEASRC = arg->display.pipeasrc;
1056 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1057 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
1058 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1059 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
1060 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1061 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
1062 }
1063 }
1064
1065 if (arg->display_read_mask != 0) {
1066 if (gma_power_begin(dev, usage)) {
1067 if (arg->display_read_mask &
1068 REGRWBITS_PFIT_CONTROLS)
1069 arg->display.pfit_controls =
1070 PSB_RVDC32(PFIT_CONTROL);
1071 if (arg->display_read_mask &
1072 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1073 arg->display.pfit_autoscale_ratios =
1074 PSB_RVDC32(PFIT_AUTO_RATIOS);
1075 if (arg->display_read_mask &
1076 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1077 arg->display.pfit_programmed_scale_ratios =
1078 PSB_RVDC32(PFIT_PGM_RATIOS);
1079 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1080 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
1081 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1082 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
1083 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1084 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
1085 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1086 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
1087 gma_power_end(dev);
1088 } else {
1089 if (arg->display_read_mask &
1090 REGRWBITS_PFIT_CONTROLS)
1091 arg->display.pfit_controls =
1092 dev_priv->savePFIT_CONTROL;
1093 if (arg->display_read_mask &
1094 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1095 arg->display.pfit_autoscale_ratios =
1096 dev_priv->savePFIT_AUTO_RATIOS;
1097 if (arg->display_read_mask &
1098 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1099 arg->display.pfit_programmed_scale_ratios =
1100 dev_priv->savePFIT_PGM_RATIOS;
1101 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1102 arg->display.pipeasrc = dev_priv->savePIPEASRC;
1103 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1104 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
1105 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1106 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
1107 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1108 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
1109 }
1110 }
1111
1112 if (arg->overlay_write_mask != 0) {
1113 if (gma_power_begin(dev, usage)) {
1114 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1115 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
1116 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
1117 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
1118 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
1119 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
1120 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
1121 }
1122 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1123 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
1124 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
1125 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
1126 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
1127 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
1128 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
1129 }
1130
1131 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
1132 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
1133
1134 if (arg->overlay.b_wait_vblank) {
1135 /* Wait for 20ms.*/
1136 unsigned long vblank_timeout = jiffies
1137 + HZ/50;
1138 uint32_t temp;
1139 while (time_before_eq(jiffies,
1140 vblank_timeout)) {
1141 temp = PSB_RVDC32(OV_DOVASTA);
1142 if ((temp & (0x1 << 31)) != 0)
1143 break;
1144 cpu_relax();
1145 }
1146 }
1147 }
1148 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
1149 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
1150 if (arg->overlay.b_wait_vblank) {
1151 /* Wait for 20ms.*/
1152 unsigned long vblank_timeout =
1153 jiffies + HZ/50;
1154 uint32_t temp;
1155 while (time_before_eq(jiffies,
1156 vblank_timeout)) {
1157 temp = PSB_RVDC32(OVC_DOVCSTA);
1158 if ((temp & (0x1 << 31)) != 0)
1159 break;
1160 cpu_relax();
1161 }
1162 }
1163 }
1164 gma_power_end(dev);
1165 } else {
1166 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1167 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
1168 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
1169 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
1170 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
1171 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
1172 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
1173 }
1174 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1175 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
1176 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
1177 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
1178 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
1179 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
1180 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
1181 }
1182 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
1183 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
1184 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
1185 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
1186 }
1187 }
1188
1189 if (arg->overlay_read_mask != 0) {
1190 if (gma_power_begin(dev, usage)) {
1191 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1192 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1193 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
1194 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
1195 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
1196 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
1197 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
1198 }
1199 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1200 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
1201 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
1202 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
1203 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
1204 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
1205 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
1206 }
1207 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1208 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
1209 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1210 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
1211 gma_power_end(dev);
1212 } else {
1213 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1214 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
1215 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
1216 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
1217 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
1218 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
1219 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
1220 }
1221 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1222 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
1223 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
1224 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
1225 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
1226 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
1227 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
1228 }
1229 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1230 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
1231 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1232 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
1233 }
1234 }
1235
1236 if (arg->sprite_enable_mask != 0) {
1237 if (gma_power_begin(dev, usage)) {
1238 PSB_WVDC32(0x1F3E, DSPARB);
1239 PSB_WVDC32(arg->sprite.dspa_control
1240 | PSB_RVDC32(DSPACNTR), DSPACNTR);
1241 PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
1242 PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
1243 PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
1244 PSB_RVDC32(DSPASURF);
1245 PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
1246 PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
1247 PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
1248 PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
1249 PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
1250 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1251 PSB_RVDC32(DSPCSURF);
1252 gma_power_end(dev);
1253 }
1254 }
1255
1256 if (arg->sprite_disable_mask != 0) {
1257 if (gma_power_begin(dev, usage)) {
1258 PSB_WVDC32(0x3F3E, DSPARB);
1259 PSB_WVDC32(0x0, DSPCCNTR);
1260 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1261 PSB_RVDC32(DSPCSURF);
1262 gma_power_end(dev);
1263 }
1264 }
1265
1266 if (arg->subpicture_enable_mask != 0) {
1267 if (gma_power_begin(dev, usage)) {
1268 uint32_t temp;
1269 if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
1270 temp = PSB_RVDC32(DSPACNTR);
1271 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1272 temp &= ~DISPPLANE_BOTTOM;
1273 temp |= DISPPLANE_32BPP;
1274 PSB_WVDC32(temp, DSPACNTR);
1275
1276 temp = PSB_RVDC32(DSPABASE);
1277 PSB_WVDC32(temp, DSPABASE);
1278 PSB_RVDC32(DSPABASE);
1279 temp = PSB_RVDC32(DSPASURF);
1280 PSB_WVDC32(temp, DSPASURF);
1281 PSB_RVDC32(DSPASURF);
1282 }
1283 if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1284 temp = PSB_RVDC32(DSPBCNTR);
1285 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1286 temp &= ~DISPPLANE_BOTTOM;
1287 temp |= DISPPLANE_32BPP;
1288 PSB_WVDC32(temp, DSPBCNTR);
1289
1290 temp = PSB_RVDC32(DSPBBASE);
1291 PSB_WVDC32(temp, DSPBBASE);
1292 PSB_RVDC32(DSPBBASE);
1293 temp = PSB_RVDC32(DSPBSURF);
1294 PSB_WVDC32(temp, DSPBSURF);
1295 PSB_RVDC32(DSPBSURF);
1296 }
1297 if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1298 temp = PSB_RVDC32(DSPCCNTR);
1299 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1300 temp &= ~DISPPLANE_BOTTOM;
1301 temp |= DISPPLANE_32BPP;
1302 PSB_WVDC32(temp, DSPCCNTR);
1303
1304 temp = PSB_RVDC32(DSPCBASE);
1305 PSB_WVDC32(temp, DSPCBASE);
1306 PSB_RVDC32(DSPCBASE);
1307 temp = PSB_RVDC32(DSPCSURF);
1308 PSB_WVDC32(temp, DSPCSURF);
1309 PSB_RVDC32(DSPCSURF);
1310 }
1311 gma_power_end(dev);
1312 }
1313 }
1314
1315 if (arg->subpicture_disable_mask != 0) {
1316 if (gma_power_begin(dev, usage)) {
1317 uint32_t temp;
1318 if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1319 temp = PSB_RVDC32(DSPACNTR);
1320 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1321 temp |= DISPPLANE_32BPP_NO_ALPHA;
1322 PSB_WVDC32(temp, DSPACNTR);
1323
1324 temp = PSB_RVDC32(DSPABASE);
1325 PSB_WVDC32(temp, DSPABASE);
1326 PSB_RVDC32(DSPABASE);
1327 temp = PSB_RVDC32(DSPASURF);
1328 PSB_WVDC32(temp, DSPASURF);
1329 PSB_RVDC32(DSPASURF);
1330 }
1331 if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1332 temp = PSB_RVDC32(DSPBCNTR);
1333 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1334 temp |= DISPPLANE_32BPP_NO_ALPHA;
1335 PSB_WVDC32(temp, DSPBCNTR);
1336
1337 temp = PSB_RVDC32(DSPBBASE);
1338 PSB_WVDC32(temp, DSPBBASE);
1339 PSB_RVDC32(DSPBBASE);
1340 temp = PSB_RVDC32(DSPBSURF);
1341 PSB_WVDC32(temp, DSPBSURF);
1342 PSB_RVDC32(DSPBSURF);
1343 }
1344 if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1345 temp = PSB_RVDC32(DSPCCNTR);
1346 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1347 temp |= DISPPLANE_32BPP_NO_ALPHA;
1348 PSB_WVDC32(temp, DSPCCNTR);
1349
1350 temp = PSB_RVDC32(DSPCBASE);
1351 PSB_WVDC32(temp, DSPCBASE);
1352 PSB_RVDC32(DSPCBASE);
1353 temp = PSB_RVDC32(DSPCSURF);
1354 PSB_WVDC32(temp, DSPCSURF);
1355 PSB_RVDC32(DSPCSURF);
1356 }
1357 gma_power_end(dev);
1358 }
1359 }
1360
1361 return 0;
1362 }
1363
1364 /* always available as we are SIGIO'd */
1365 static unsigned int psb_poll(struct file *filp,
1366 struct poll_table_struct *wait)
1367 {
1368 return POLLIN | POLLRDNORM;
1369 }
1370
1371 /* Not sure what we will need yet - in the PVR driver this disappears into
1372 a tangle of abstracted handlers and per process crap */
1373
1374 struct psb_priv {
1375 int dummy;
1376 };
1377
1378 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1379 {
1380 struct psb_priv *psb = kzalloc(sizeof(struct psb_priv), GFP_KERNEL);
1381 if (psb == NULL)
1382 return -ENOMEM;
1383 priv->driver_priv = psb;
1384 DRM_DEBUG("\n");
1385 /*return PVRSRVOpen(dev, priv);*/
1386 return 0;
1387 }
1388
1389 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1390 {
1391 kfree(priv->driver_priv);
1392 priv->driver_priv = NULL;
1393 }
1394
1395 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1396 unsigned long arg)
1397 {
1398 struct drm_file *file_priv = filp->private_data;
1399 struct drm_device *dev = file_priv->minor->dev;
1400 struct drm_psb_private *dev_priv = dev->dev_private;
1401 static unsigned int runtime_allowed;
1402 unsigned int nr = DRM_IOCTL_NR(cmd);
1403
1404 DRM_DEBUG("cmd = %x, nr = %x\n", cmd, nr);
1405
1406 if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1407 runtime_allowed++;
1408 pm_runtime_allow(&dev->pdev->dev);
1409 dev_priv->rpm_enabled = 1;
1410 }
1411 /*
1412 * The driver private ioctls should be thread-safe.
1413 */
1414
1415 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1416 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1417 struct drm_ioctl_desc *ioctl =
1418 &psb_ioctls[nr - DRM_COMMAND_BASE];
1419
1420 if (unlikely(ioctl->cmd != cmd)) {
1421 DRM_ERROR(
1422 "Invalid drm cmnd %d ioctl->cmd %x, cmd %x\n",
1423 nr - DRM_COMMAND_BASE, ioctl->cmd, cmd);
1424 return -EINVAL;
1425 }
1426
1427 return drm_ioctl(filp, cmd, arg);
1428 }
1429 /*
1430 * Not all old drm ioctls are thread-safe.
1431 */
1432
1433 return drm_ioctl(filp, cmd, arg);
1434 }
1435
1436
1437 /* When a client dies:
1438 * - Check for and clean up flipped page state
1439 */
1440 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1441 {
1442 }
1443
1444 static void psb_remove(struct pci_dev *pdev)
1445 {
1446 struct drm_device *dev = pci_get_drvdata(pdev);
1447 drm_put_dev(dev);
1448 }
1449
1450 static int psb_open(struct inode *inode, struct file *filp)
1451 {
1452 return 0;
1453 }
1454
1455 static int psb_release(struct inode *inode, struct file *filp)
1456 {
1457 return 0;
1458 }
1459
1460
1461 static const struct dev_pm_ops psb_pm_ops = {
1462 .runtime_suspend = psb_runtime_suspend,
1463 .runtime_resume = psb_runtime_resume,
1464 .runtime_idle = psb_runtime_idle,
1465 };
1466
1467 static struct drm_driver driver = {
1468 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1469 DRIVER_IRQ_VBL | DRIVER_MODESET,
1470 .load = psb_driver_load,
1471 .unload = psb_driver_unload,
1472
1473 .ioctls = psb_ioctls,
1474 .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1475 .device_is_agp = psb_driver_device_is_agp,
1476 .irq_preinstall = psb_irq_preinstall,
1477 .irq_postinstall = psb_irq_postinstall,
1478 .irq_uninstall = psb_irq_uninstall,
1479 .irq_handler = psb_irq_handler,
1480 .enable_vblank = psb_enable_vblank,
1481 .disable_vblank = psb_disable_vblank,
1482 .get_vblank_counter = psb_get_vblank_counter,
1483 .firstopen = NULL,
1484 .lastclose = psb_lastclose,
1485 .open = psb_driver_open,
1486 .postclose = psb_driver_close,
1487 #if 0 /* ACFIXME */
1488 .get_map_ofs = drm_core_get_map_ofs,
1489 .get_reg_ofs = drm_core_get_reg_ofs,
1490 .proc_init = psb_proc_init,
1491 .proc_cleanup = psb_proc_cleanup,
1492 #endif
1493 .preclose = psb_driver_preclose,
1494 .fops = {
1495 .owner = THIS_MODULE,
1496 .open = psb_open,
1497 .release = psb_release,
1498 .unlocked_ioctl = psb_unlocked_ioctl,
1499 /* .mmap = psb_mmap, */
1500 .poll = psb_poll,
1501 .fasync = drm_fasync,
1502 .read = drm_read,
1503 },
1504 .name = DRIVER_NAME,
1505 .desc = DRIVER_DESC,
1506 .date = PSB_DRM_DRIVER_DATE,
1507 .major = PSB_DRM_DRIVER_MAJOR,
1508 .minor = PSB_DRM_DRIVER_MINOR,
1509 .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1510 };
1511
1512 static struct pci_driver psb_pci_driver = {
1513 .name = DRIVER_NAME,
1514 .id_table = pciidlist,
1515 .resume = gma_power_resume,
1516 .suspend = gma_power_suspend,
1517 .probe = psb_probe,
1518 .remove = psb_remove,
1519 #ifdef CONFIG_PM
1520 .driver.pm = &psb_pm_ops,
1521 #endif
1522 };
1523
1524 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1525 {
1526 /* MLD Added this from Inaky's patch */
1527 if (pci_enable_msi(pdev))
1528 DRM_ERROR("Enable MSI failed!\n");
1529 return drm_get_pci_dev(pdev, ent, &driver);
1530 }
1531
1532 static int __init psb_init(void)
1533 {
1534 return drm_pci_init(&driver, &psb_pci_driver);
1535 }
1536
1537 static void __exit psb_exit(void)
1538 {
1539 drm_pci_exit(&driver, &psb_pci_driver);
1540 }
1541
1542 late_initcall(psb_init);
1543 module_exit(psb_exit);
1544
1545 MODULE_AUTHOR(DRIVER_AUTHOR);
1546 MODULE_DESCRIPTION(DRIVER_DESC);
1547 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree