2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/pci_ids.h>
20 #include <linux/netdevice.h>
24 #include BCMEMBEDIMAGE
25 #endif /* BCMEMBEDIMAGE */
35 #include <hndrte_armtrap.h>
36 #include <hndrte_cons.h>
37 #endif /* DHD_DEBUG */
43 #include <sbsdpcmdev.h>
46 #include <proto/802.11.h>
48 #include <dngl_stats.h>
51 #include <dhd_proto.h>
55 #include <siutils_priv.h>
57 #ifndef DHDSDIO_MEM_DUMP_FNAME
58 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
61 #define TXQLEN 2048 /* bulk tx queue length */
62 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
63 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
66 #define TXRETRIES 2 /* # of retries for tx frames */
68 #if defined(CONFIG_MACH_SANDGATE2G)
69 #define DHD_RXBOUND 250 /* Default for max rx frames in
72 #define DHD_RXBOUND 50 /* Default for max rx frames in
74 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
76 #define DHD_TXBOUND 20 /* Default for max tx frames in
79 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
81 #define MEMBLOCK 2048 /* Block size used for downloading
83 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
84 biggest possible glom */
86 /* Packet alignment for most efficient SDIO (can change based on platform) */
88 #define DHD_SDALIGN 32
90 #if !ISPOWEROF2(DHD_SDALIGN)
91 #error DHD_SDALIGN is not a power of 2!
95 #define DHD_FIRSTREAD 32
97 #if !ISPOWEROF2(DHD_FIRSTREAD)
98 #error DHD_FIRSTREAD is not a power of 2!
101 /* Total length of frame header for dongle protocol */
102 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
104 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
106 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
109 /* Space for header read, limit for data packets */
111 #define MAX_HDR_READ 32
113 #if !ISPOWEROF2(MAX_HDR_READ)
114 #error MAX_HDR_READ is not a power of 2!
117 #define MAX_RX_DATASZ 2048
119 /* Maximum milliseconds to wait for F2 to come up */
120 #define DHD_WAIT_F2RDY 3000
122 /* Bump up limit on waiting for HT to account for first startup;
123 * if the image is doing a CRC calculation before programming the PMU
124 * for HT availability, it could take a couple hundred ms more, so
125 * max out at a 1 second (1000000us).
127 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
128 #undef PMU_MAX_TRANSITION_DLY
129 #define PMU_MAX_TRANSITION_DLY 1000000
132 /* Value for ChipClockCSR during initial setup */
133 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
134 SBSDIO_ALP_AVAIL_REQ)
135 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
137 /* Flags for SDH calls */
138 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
140 /* Packet free applicable unconditionally for sdio and sdspi. Conditional if
141 * bufpool was present for gspi bus.
143 #define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
144 pkt_buf_free_skb(pkt);
147 * Conversion of 802.1D priority to precedence level
149 #define PRIO2PREC(prio) \
150 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
153 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep
);
154 extern int dhdcdc_set_ioctl(dhd_pub_t
*dhd
, int ifidx
, uint cmd
, void *buf
,
158 /* Device console log buffer state */
159 typedef struct dhd_console
{
160 uint count
; /* Poll interval msec counter */
161 uint log_addr
; /* Log struct address (fixed) */
162 hndrte_log_t log
; /* Log struct (host copy) */
163 uint bufsize
; /* Size of log buffer */
164 u8
*buf
; /* Log buffer (host copy) */
165 uint last
; /* Last buffer read index */
167 #endif /* DHD_DEBUG */
169 /* Private data for SDIO bus interaction */
170 typedef struct dhd_bus
{
173 bcmsdh_info_t
*sdh
; /* Handle for BCMSDH calls */
174 si_t
*sih
; /* Handle for SI calls */
175 char *vars
; /* Variables (from CIS and/or other) */
176 uint varsz
; /* Size of variables buffer */
177 u32 sbaddr
; /* Current SB window pointer (-1, invalid) */
179 sdpcmd_regs_t
*regs
; /* Registers for SDIO core */
180 uint sdpcmrev
; /* SDIO core revision */
181 uint armrev
; /* CPU core revision */
182 uint ramrev
; /* SOCRAM core revision */
183 u32 ramsize
; /* Size of RAM in SOCRAM (bytes) */
184 u32 orig_ramsize
; /* Size of RAM in SOCRAM (bytes) */
186 u32 bus
; /* gSPI or SDIO bus */
187 u32 hostintmask
; /* Copy of Host Interrupt Mask */
188 u32 intstatus
; /* Intstatus bits (events) pending */
189 bool dpc_sched
; /* Indicates DPC schedule (intrpt rcvd) */
190 bool fcstate
; /* State of dongle flow-control */
192 u16 cl_devid
; /* cached devid for dhdsdio_probe_attach() */
193 char *fw_path
; /* module_param: path to firmware image */
194 char *nv_path
; /* module_param: path to nvram vars file */
195 const char *nvram_params
; /* user specified nvram params. */
197 uint blocksize
; /* Block size of SDIO transfers */
198 uint roundup
; /* Max roundup limit */
200 struct pktq txq
; /* Queue length used for flow-control */
201 u8 flowcontrol
; /* per prio flow control bitmask */
202 u8 tx_seq
; /* Transmit sequence number (next) */
203 u8 tx_max
; /* Maximum transmit sequence allowed */
205 u8 hdrbuf
[MAX_HDR_READ
+ DHD_SDALIGN
];
206 u8
*rxhdr
; /* Header of current rx frame (in hdrbuf) */
207 u16 nextlen
; /* Next Read Len from last header */
208 u8 rx_seq
; /* Receive sequence number (expected) */
209 bool rxskip
; /* Skip receive (awaiting NAK ACK) */
211 struct sk_buff
*glomd
; /* Packet containing glomming descriptor */
212 struct sk_buff
*glom
; /* Packet chain for glommed superframe */
213 uint glomerr
; /* Glom packet read errors */
215 u8
*rxbuf
; /* Buffer for receiving control packets */
216 uint rxblen
; /* Allocated length of rxbuf */
217 u8
*rxctl
; /* Aligned pointer into rxbuf */
218 u8
*databuf
; /* Buffer for receiving big glom packet */
219 u8
*dataptr
; /* Aligned pointer into databuf */
220 uint rxlen
; /* Length of valid data in buffer */
222 u8 sdpcm_ver
; /* Bus protocol reported by dongle */
224 bool intr
; /* Use interrupts */
225 bool poll
; /* Use polling */
226 bool ipend
; /* Device interrupt is pending */
227 bool intdis
; /* Interrupts disabled by isr */
228 uint intrcount
; /* Count of device interrupt callbacks */
229 uint lastintrs
; /* Count as of last watchdog timer */
230 uint spurious
; /* Count of spurious interrupts */
231 uint pollrate
; /* Ticks between device polls */
232 uint polltick
; /* Tick counter */
233 uint pollcnt
; /* Count of active polls */
236 dhd_console_t console
; /* Console output polling support */
237 uint console_addr
; /* Console address from shared struct */
238 #endif /* DHD_DEBUG */
240 uint regfails
; /* Count of R_REG/W_REG failures */
242 uint clkstate
; /* State of sd and backplane clock(s) */
243 bool activity
; /* Activity flag for clock down */
244 s32 idletime
; /* Control for activity timeout */
245 s32 idlecount
; /* Activity timeout counter */
246 s32 idleclock
; /* How to set bus driver when idle */
247 s32 sd_divisor
; /* Speed control to bus driver */
248 s32 sd_mode
; /* Mode control to bus driver */
249 s32 sd_rxchain
; /* If bcmsdh api accepts PKT chains */
250 bool use_rxchain
; /* If dhd should use PKT chains */
251 bool sleeping
; /* Is SDIO bus sleeping? */
252 bool rxflow_mode
; /* Rx flow control mode */
253 bool rxflow
; /* Is rx flow control on */
254 uint prev_rxlim_hit
; /* Is prev rx limit exceeded
255 (per dpc schedule) */
256 bool alp_only
; /* Don't use HT clock (ALP only) */
257 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
261 /* external loopback */
265 /* pktgen configuration */
266 uint pktgen_freq
; /* Ticks between bursts */
267 uint pktgen_count
; /* Packets to send each burst */
268 uint pktgen_print
; /* Bursts between count displays */
269 uint pktgen_total
; /* Stop after this many */
270 uint pktgen_minlen
; /* Minimum packet data len */
271 uint pktgen_maxlen
; /* Maximum packet data len */
272 uint pktgen_mode
; /* Configured mode: tx, rx, or echo */
273 uint pktgen_stop
; /* Number of tx failures causing stop */
275 /* active pktgen fields */
276 uint pktgen_tick
; /* Tick counter for bursts */
277 uint pktgen_ptick
; /* Burst counter for printing */
278 uint pktgen_sent
; /* Number of test packets generated */
279 uint pktgen_rcvd
; /* Number of test packets received */
280 uint pktgen_fail
; /* Number of failed send attempts */
281 u16 pktgen_len
; /* Length of next packet to send */
284 /* Some additional counters */
285 uint tx_sderrs
; /* Count of tx attempts with sd errors */
286 uint fcqueued
; /* Tx packets that got queued */
287 uint rxrtx
; /* Count of rtx requests (NAK to dongle) */
288 uint rx_toolong
; /* Receive frames too long to receive */
289 uint rxc_errors
; /* SDIO errors when reading control frames */
290 uint rx_hdrfail
; /* SDIO errors on header reads */
291 uint rx_badhdr
; /* Bad received headers (roosync?) */
292 uint rx_badseq
; /* Mismatched rx sequence number */
293 uint fc_rcvd
; /* Number of flow-control events received */
294 uint fc_xoff
; /* Number which turned on flow-control */
295 uint fc_xon
; /* Number which turned off flow-control */
296 uint rxglomfail
; /* Failed deglom attempts */
297 uint rxglomframes
; /* Number of glom frames (superframes) */
298 uint rxglompkts
; /* Number of packets from glom frames */
299 uint f2rxhdrs
; /* Number of header reads */
300 uint f2rxdata
; /* Number of frame data reads */
301 uint f2txdata
; /* Number of f2 frame writes */
302 uint f1regdata
; /* Number of f1 register accesses */
306 bool ctrl_frame_stat
;
312 #define CLK_PENDING 2 /* Not used yet */
315 #define DHD_NOPMU(dhd) (false)
318 static int qcount
[NUMPRIO
];
319 static int tx_packets
[NUMPRIO
];
320 #endif /* DHD_DEBUG */
322 /* Deferred transmit */
323 const uint dhd_deferred_tx
= 1;
325 extern uint dhd_watchdog_ms
;
326 extern void dhd_os_wd_timer(void *bus
, uint wdtick
);
333 /* override the RAM size if possible */
334 #define DONGLE_MIN_MEMSIZE (128 * 1024)
335 int dhd_dongle_memsize
;
337 static bool dhd_alignctl
;
341 static bool retrydata
;
342 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
344 static const uint watermark
= 8;
345 static const uint firstread
= DHD_FIRSTREAD
;
347 #define HDATLEN (firstread - (SDPCM_HDRLEN))
349 /* Retry count for register access failures */
350 static const uint retry_limit
= 2;
352 /* Force even SD lengths (some host controllers mess up on odd bytes) */
353 static bool forcealign
;
357 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
358 extern void bcmsdh_enable_hw_oob_intr(void *sdh
, bool enable
);
361 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
362 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
363 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
364 #define PKTALIGN(_p, _len, _align) \
367 datalign = (unsigned long)((_p)->data); \
368 datalign = roundup(datalign, (_align)) - datalign; \
369 ASSERT(datalign < (_align)); \
370 ASSERT((_p)->len >= ((_len) + datalign)); \
372 skb_pull((_p), datalign); \
373 __skb_trim((_p), (_len)); \
376 /* Limit on rounding up frames */
377 static const uint max_roundup
= 512;
379 /* Try doing readahead */
380 static bool dhd_readahead
;
382 /* To check if there's window offered */
383 #define DATAOK(bus) \
384 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
385 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
387 /* Macros to get register read/write status */
388 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
389 #define R_SDREG(regvar, regaddr, retryvar) \
393 regvar = R_REG(regaddr); \
394 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
396 bus->regfails += (retryvar-1); \
397 if (retryvar > retry_limit) { \
398 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
399 __func__, __LINE__)); \
405 #define W_SDREG(regval, regaddr, retryvar) \
409 W_REG(regaddr, regval); \
410 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
412 bus->regfails += (retryvar-1); \
413 if (retryvar > retry_limit) \
414 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
415 __func__, __LINE__)); \
419 #define DHD_BUS SDIO_BUS
421 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
423 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
425 #define GSPI_PR55150_BAILOUT
428 static void dhdsdio_testrcv(dhd_bus_t
*bus
, void *pkt
, uint seq
);
429 static void dhdsdio_sdtest_set(dhd_bus_t
*bus
, bool start
);
433 static int dhdsdio_checkdied(dhd_bus_t
*bus
, u8
*data
, uint size
);
434 static int dhdsdio_mem_dump(dhd_bus_t
*bus
);
435 #endif /* DHD_DEBUG */
436 static int dhdsdio_download_state(dhd_bus_t
*bus
, bool enter
);
438 static void dhdsdio_release(dhd_bus_t
*bus
);
439 static void dhdsdio_release_malloc(dhd_bus_t
*bus
);
440 static void dhdsdio_disconnect(void *ptr
);
441 static bool dhdsdio_chipmatch(u16 chipid
);
442 static bool dhdsdio_probe_attach(dhd_bus_t
*bus
, void *sdh
,
443 void *regsva
, u16 devid
);
444 static bool dhdsdio_probe_malloc(dhd_bus_t
*bus
, void *sdh
);
445 static bool dhdsdio_probe_init(dhd_bus_t
*bus
, void *sdh
);
446 static void dhdsdio_release_dongle(dhd_bus_t
*bus
);
448 static uint
process_nvram_vars(char *varbuf
, uint len
);
450 static void dhd_dongle_setmemsize(struct dhd_bus
*bus
, int mem_size
);
451 static int dhd_bcmsdh_recv_buf(dhd_bus_t
*bus
, u32 addr
, uint fn
,
452 uint flags
, u8
*buf
, uint nbytes
,
453 struct sk_buff
*pkt
, bcmsdh_cmplt_fn_t complete
,
455 static int dhd_bcmsdh_send_buf(dhd_bus_t
*bus
, u32 addr
, uint fn
,
456 uint flags
, u8
*buf
, uint nbytes
,
457 struct sk_buff
*pkt
, bcmsdh_cmplt_fn_t complete
,
460 static bool dhdsdio_download_firmware(struct dhd_bus
*bus
, void *sdh
);
461 static int _dhdsdio_download_firmware(struct dhd_bus
*bus
);
463 static int dhdsdio_download_code_file(struct dhd_bus
*bus
, char *image_path
);
464 static int dhdsdio_download_nvram(struct dhd_bus
*bus
);
466 static int dhdsdio_download_code_array(struct dhd_bus
*bus
);
469 static void dhd_dongle_setmemsize(struct dhd_bus
*bus
, int mem_size
)
471 s32 min_size
= DONGLE_MIN_MEMSIZE
;
472 /* Restrict the memsize to user specified limit */
473 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
474 dhd_dongle_memsize
, min_size
));
475 if ((dhd_dongle_memsize
> min_size
) &&
476 (dhd_dongle_memsize
< (s32
) bus
->orig_ramsize
))
477 bus
->ramsize
= dhd_dongle_memsize
;
480 static int dhdsdio_set_siaddr_window(dhd_bus_t
*bus
, u32 address
)
483 bcmsdh_cfg_write(bus
->sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_SBADDRLOW
,
484 (address
>> 8) & SBSDIO_SBADDRLOW_MASK
, &err
);
486 bcmsdh_cfg_write(bus
->sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_SBADDRMID
,
487 (address
>> 16) & SBSDIO_SBADDRMID_MASK
, &err
);
489 bcmsdh_cfg_write(bus
->sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_SBADDRHIGH
,
490 (address
>> 24) & SBSDIO_SBADDRHIGH_MASK
,
495 /* Turn backplane clock on or off */
496 static int dhdsdio_htclk(dhd_bus_t
*bus
, bool on
, bool pendok
)
499 u8 clkctl
, clkreq
, devctl
;
502 DHD_TRACE(("%s: Enter\n", __func__
));
504 #if defined(OOB_INTR_ONLY)
511 /* Request HT Avail */
513 bus
->alp_only
? SBSDIO_ALP_AVAIL_REQ
: SBSDIO_HT_AVAIL_REQ
;
515 if ((bus
->sih
->chip
== BCM4329_CHIP_ID
)
516 && (bus
->sih
->chiprev
== 0))
517 clkreq
|= SBSDIO_FORCE_ALP
;
519 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
522 DHD_ERROR(("%s: HT Avail request error: %d\n",
527 if (pendok
&& ((bus
->sih
->buscoretype
== PCMCIA_CORE_ID
)
528 && (bus
->sih
->buscorerev
== 9))) {
530 R_SDREG(dummy
, &bus
->regs
->clockctlstatus
, retries
);
533 /* Check current status */
535 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
538 DHD_ERROR(("%s: HT Avail read error: %d\n",
543 /* Go to pending and await interrupt if appropriate */
544 if (!SBSDIO_CLKAV(clkctl
, bus
->alp_only
) && pendok
) {
545 /* Allow only clock-available interrupt */
547 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
,
550 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
555 devctl
|= SBSDIO_DEVCTL_CA_INT_ONLY
;
556 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
,
558 DHD_INFO(("CLKCTL: set PENDING\n"));
559 bus
->clkstate
= CLK_PENDING
;
562 } else if (bus
->clkstate
== CLK_PENDING
) {
563 /* Cancel CA-only interrupt filter */
565 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
,
567 devctl
&= ~SBSDIO_DEVCTL_CA_INT_ONLY
;
568 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
,
572 /* Otherwise, wait here (polling) for HT Avail */
573 if (!SBSDIO_CLKAV(clkctl
, bus
->alp_only
)) {
574 SPINWAIT_SLEEP(sdioh_spinwait_sleep
,
576 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
,
577 SBSDIO_FUNC1_CHIPCLKCSR
,
579 !SBSDIO_CLKAV(clkctl
, bus
->alp_only
)),
580 PMU_MAX_TRANSITION_DLY
);
583 DHD_ERROR(("%s: HT Avail request error: %d\n",
587 if (!SBSDIO_CLKAV(clkctl
, bus
->alp_only
)) {
588 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
589 __func__
, PMU_MAX_TRANSITION_DLY
, clkctl
));
593 /* Mark clock available */
594 bus
->clkstate
= CLK_AVAIL
;
595 DHD_INFO(("CLKCTL: turned ON\n"));
597 #if defined(DHD_DEBUG)
598 if (bus
->alp_only
== true) {
599 #if !defined(BCMLXSDMMC)
600 if (!SBSDIO_ALPONLY(clkctl
)) {
601 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
604 #endif /* !defined(BCMLXSDMMC) */
606 if (SBSDIO_ALPONLY(clkctl
)) {
607 DHD_ERROR(("%s: HT Clock should be on.\n",
611 #endif /* defined (DHD_DEBUG) */
613 bus
->activity
= true;
617 if (bus
->clkstate
== CLK_PENDING
) {
618 /* Cancel CA-only interrupt filter */
620 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
,
622 devctl
&= ~SBSDIO_DEVCTL_CA_INT_ONLY
;
623 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
,
627 bus
->clkstate
= CLK_SDONLY
;
628 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
630 DHD_INFO(("CLKCTL: turned OFF\n"));
632 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
640 /* Change idle/active SD state */
641 static int dhdsdio_sdclk(dhd_bus_t
*bus
, bool on
)
646 DHD_TRACE(("%s: Enter\n", __func__
));
649 if (bus
->idleclock
== DHD_IDLE_STOP
) {
650 /* Turn on clock and restore mode */
652 err
= bcmsdh_iovar_op(bus
->sdh
, "sd_clock", NULL
, 0,
653 &iovalue
, sizeof(iovalue
), true);
655 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
660 iovalue
= bus
->sd_mode
;
661 err
= bcmsdh_iovar_op(bus
->sdh
, "sd_mode", NULL
, 0,
662 &iovalue
, sizeof(iovalue
), true);
664 DHD_ERROR(("%s: error changing sd_mode: %d\n",
668 } else if (bus
->idleclock
!= DHD_IDLE_ACTIVE
) {
669 /* Restore clock speed */
670 iovalue
= bus
->sd_divisor
;
671 err
= bcmsdh_iovar_op(bus
->sdh
, "sd_divisor", NULL
, 0,
672 &iovalue
, sizeof(iovalue
), true);
674 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
679 bus
->clkstate
= CLK_SDONLY
;
681 /* Stop or slow the SD clock itself */
682 if ((bus
->sd_divisor
== -1) || (bus
->sd_mode
== -1)) {
683 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
684 __func__
, bus
->sd_divisor
, bus
->sd_mode
));
687 if (bus
->idleclock
== DHD_IDLE_STOP
) {
689 /* Change to SD1 mode and turn off clock */
692 bcmsdh_iovar_op(bus
->sdh
, "sd_mode", NULL
,
694 sizeof(iovalue
), true);
696 DHD_ERROR(("%s: error changing sd_clock: %d\n",
703 err
= bcmsdh_iovar_op(bus
->sdh
, "sd_clock", NULL
, 0,
704 &iovalue
, sizeof(iovalue
), true);
706 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
710 } else if (bus
->idleclock
!= DHD_IDLE_ACTIVE
) {
711 /* Set divisor to idle value */
712 iovalue
= bus
->idleclock
;
713 err
= bcmsdh_iovar_op(bus
->sdh
, "sd_divisor", NULL
, 0,
714 &iovalue
, sizeof(iovalue
), true);
716 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
721 bus
->clkstate
= CLK_NONE
;
727 /* Transition SD and backplane clock readiness */
728 static int dhdsdio_clkctl(dhd_bus_t
*bus
, uint target
, bool pendok
)
731 uint oldstate
= bus
->clkstate
;
732 #endif /* DHD_DEBUG */
734 DHD_TRACE(("%s: Enter\n", __func__
));
736 /* Early exit if we're already there */
737 if (bus
->clkstate
== target
) {
738 if (target
== CLK_AVAIL
) {
739 dhd_os_wd_timer(bus
->dhd
, dhd_watchdog_ms
);
740 bus
->activity
= true;
747 /* Make sure SD clock is available */
748 if (bus
->clkstate
== CLK_NONE
)
749 dhdsdio_sdclk(bus
, true);
750 /* Now request HT Avail on the backplane */
751 dhdsdio_htclk(bus
, true, pendok
);
752 dhd_os_wd_timer(bus
->dhd
, dhd_watchdog_ms
);
753 bus
->activity
= true;
757 /* Remove HT request, or bring up SD clock */
758 if (bus
->clkstate
== CLK_NONE
)
759 dhdsdio_sdclk(bus
, true);
760 else if (bus
->clkstate
== CLK_AVAIL
)
761 dhdsdio_htclk(bus
, false, false);
763 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
764 bus
->clkstate
, target
));
765 dhd_os_wd_timer(bus
->dhd
, dhd_watchdog_ms
);
769 /* Make sure to remove HT request */
770 if (bus
->clkstate
== CLK_AVAIL
)
771 dhdsdio_htclk(bus
, false, false);
772 /* Now remove the SD clock */
773 dhdsdio_sdclk(bus
, false);
774 dhd_os_wd_timer(bus
->dhd
, 0);
778 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate
, bus
->clkstate
));
779 #endif /* DHD_DEBUG */
784 int dhdsdio_bussleep(dhd_bus_t
*bus
, bool sleep
)
786 bcmsdh_info_t
*sdh
= bus
->sdh
;
787 sdpcmd_regs_t
*regs
= bus
->regs
;
790 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
791 (sleep
? "SLEEP" : "WAKE"),
792 (bus
->sleeping
? "SLEEP" : "WAKE")));
794 /* Done if we're already in the requested state */
795 if (sleep
== bus
->sleeping
)
798 /* Going to sleep: set the alarm and turn off the lights... */
800 /* Don't sleep if something is pending */
801 if (bus
->dpc_sched
|| bus
->rxskip
|| pktq_len(&bus
->txq
))
804 /* Disable SDIO interrupts (no longer interested) */
805 bcmsdh_intr_disable(bus
->sdh
);
807 /* Make sure the controller has the bus up */
808 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
810 /* Tell device to start using OOB wakeup */
811 W_SDREG(SMB_USE_OOB
, ®s
->tosbmailbox
, retries
);
812 if (retries
> retry_limit
)
813 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
815 /* Turn off our contribution to the HT clock request */
816 dhdsdio_clkctl(bus
, CLK_SDONLY
, false);
818 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
819 SBSDIO_FORCE_HW_CLKREQ_OFF
, NULL
);
821 /* Isolate the bus */
822 if (bus
->sih
->chip
!= BCM4329_CHIP_ID
823 && bus
->sih
->chip
!= BCM4319_CHIP_ID
) {
824 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
,
825 SBSDIO_DEVCTL_PADS_ISO
, NULL
);
829 bus
->sleeping
= true;
832 /* Waking up: bus power up is ok, set local state */
834 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
837 /* Force pad isolation off if possible
838 (in case power never toggled) */
839 if ((bus
->sih
->buscoretype
== PCMCIA_CORE_ID
)
840 && (bus
->sih
->buscorerev
>= 10))
841 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
, 0,
844 /* Make sure the controller has the bus up */
845 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
847 /* Send misc interrupt to indicate OOB not needed */
848 W_SDREG(0, ®s
->tosbmailboxdata
, retries
);
849 if (retries
<= retry_limit
)
850 W_SDREG(SMB_DEV_INT
, ®s
->tosbmailbox
, retries
);
852 if (retries
> retry_limit
)
853 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
855 /* Make sure we have SD bus access */
856 dhdsdio_clkctl(bus
, CLK_SDONLY
, false);
859 bus
->sleeping
= false;
861 /* Enable interrupts again */
862 if (bus
->intr
&& (bus
->dhd
->busstate
== DHD_BUS_DATA
)) {
864 bcmsdh_intr_enable(bus
->sdh
);
871 #if defined(OOB_INTR_ONLY)
872 void dhd_enable_oob_intr(struct dhd_bus
*bus
, bool enable
)
875 bcmsdh_enable_hw_oob_intr(bus
->sdh
, enable
);
877 sdpcmd_regs_t
*regs
= bus
->regs
;
880 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
881 if (enable
== true) {
883 /* Tell device to start using OOB wakeup */
884 W_SDREG(SMB_USE_OOB
, ®s
->tosbmailbox
, retries
);
885 if (retries
> retry_limit
)
886 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
889 /* Send misc interrupt to indicate OOB not needed */
890 W_SDREG(0, ®s
->tosbmailboxdata
, retries
);
891 if (retries
<= retry_limit
)
892 W_SDREG(SMB_DEV_INT
, ®s
->tosbmailbox
, retries
);
895 /* Turn off our contribution to the HT clock request */
896 dhdsdio_clkctl(bus
, CLK_SDONLY
, false);
897 #endif /* !defined(HW_OOB) */
899 #endif /* defined(OOB_INTR_ONLY) */
901 #define BUS_WAKE(bus) \
903 if ((bus)->sleeping) \
904 dhdsdio_bussleep((bus), false); \
907 /* Writes a HW/SW header into the packet and sends it. */
908 /* Assumes: (a) header space already there, (b) caller holds lock */
909 static int dhdsdio_txpkt(dhd_bus_t
*bus
, struct sk_buff
*pkt
, uint chan
,
921 DHD_TRACE(("%s: Enter\n", __func__
));
925 if (bus
->dhd
->dongle_reset
) {
930 frame
= (u8
*) (pkt
->data
);
932 /* Add alignment padding, allocate new packet if needed */
933 pad
= ((unsigned long)frame
% DHD_SDALIGN
);
935 if (skb_headroom(pkt
) < pad
) {
936 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
937 __func__
, skb_headroom(pkt
), pad
));
938 bus
->dhd
->tx_realloc
++;
939 new = pkt_buf_get_skb(pkt
->len
+ DHD_SDALIGN
);
941 DHD_ERROR(("%s: couldn't allocate new %d-byte "
943 __func__
, pkt
->len
+ DHD_SDALIGN
));
948 PKTALIGN(new, pkt
->len
, DHD_SDALIGN
);
949 memcpy(new->data
, pkt
->data
, pkt
->len
);
951 pkt_buf_free_skb(pkt
);
952 /* free the pkt if canned one is not used */
955 frame
= (u8
*) (pkt
->data
);
956 ASSERT(((unsigned long)frame
% DHD_SDALIGN
) == 0);
960 frame
= (u8
*) (pkt
->data
);
962 ASSERT((pad
+ SDPCM_HDRLEN
) <= (int)(pkt
->len
));
963 memset(frame
, 0, pad
+ SDPCM_HDRLEN
);
966 ASSERT(pad
< DHD_SDALIGN
);
968 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
969 len
= (u16
) (pkt
->len
);
970 *(u16
*) frame
= cpu_to_le16(len
);
971 *(((u16
*) frame
) + 1) = cpu_to_le16(~len
);
973 /* Software tag: channel, sequence number, data offset */
975 ((chan
<< SDPCM_CHANNEL_SHIFT
) & SDPCM_CHANNEL_MASK
) | bus
->tx_seq
|
977 SDPCM_HDRLEN
) << SDPCM_DOFFSET_SHIFT
) & SDPCM_DOFFSET_MASK
);
979 put_unaligned_le32(swheader
, frame
+ SDPCM_FRAMETAG_LEN
);
980 put_unaligned_le32(0, frame
+ SDPCM_FRAMETAG_LEN
+ sizeof(swheader
));
983 tx_packets
[pkt
->priority
]++;
984 if (DHD_BYTES_ON() &&
985 (((DHD_CTL_ON() && (chan
== SDPCM_CONTROL_CHANNEL
)) ||
986 (DHD_DATA_ON() && (chan
!= SDPCM_CONTROL_CHANNEL
))))) {
987 prhex("Tx Frame", frame
, len
);
988 } else if (DHD_HDRS_ON()) {
989 prhex("TxHdr", frame
, min_t(u16
, len
, 16));
993 /* Raise len to next SDIO block to eliminate tail command */
994 if (bus
->roundup
&& bus
->blocksize
&& (len
> bus
->blocksize
)) {
995 u16 pad
= bus
->blocksize
- (len
% bus
->blocksize
);
996 if ((pad
<= bus
->roundup
) && (pad
< bus
->blocksize
))
998 if (pad
<= skb_tailroom(pkt
))
1001 } else if (len
% DHD_SDALIGN
) {
1002 len
+= DHD_SDALIGN
- (len
% DHD_SDALIGN
);
1005 /* Some controllers have trouble with odd bytes -- round to even */
1006 if (forcealign
&& (len
& (ALIGNMENT
- 1))) {
1008 if (skb_tailroom(pkt
))
1010 len
= roundup(len
, ALIGNMENT
);
1013 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1020 dhd_bcmsdh_send_buf(bus
, bcmsdh_cur_sbwad(sdh
), SDIO_FUNC_2
,
1021 F2SYNC
, frame
, len
, pkt
, NULL
, NULL
);
1023 ASSERT(ret
!= BCME_PENDING
);
1026 /* On failure, abort the command
1027 and terminate the frame */
1028 DHD_INFO(("%s: sdio error %d, abort command and "
1029 "terminate frame.\n", __func__
, ret
));
1032 bcmsdh_abort(sdh
, SDIO_FUNC_2
);
1033 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
,
1034 SBSDIO_FUNC1_FRAMECTRL
, SFC_WF_TERM
,
1038 for (i
= 0; i
< 3; i
++) {
1040 hi
= bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
,
1041 SBSDIO_FUNC1_WFRAMEBCHI
,
1043 lo
= bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
,
1044 SBSDIO_FUNC1_WFRAMEBCLO
,
1046 bus
->f1regdata
+= 2;
1047 if ((hi
== 0) && (lo
== 0))
1053 bus
->tx_seq
= (bus
->tx_seq
+ 1) % SDPCM_SEQUENCE_WRAP
;
1055 } while ((ret
< 0) && retrydata
&& retries
++ < TXRETRIES
);
1058 /* restore pkt buffer pointer before calling tx complete routine */
1059 skb_pull(pkt
, SDPCM_HDRLEN
+ pad
);
1060 dhd_os_sdunlock(bus
->dhd
);
1061 dhd_txcomplete(bus
->dhd
, pkt
, ret
!= 0);
1062 dhd_os_sdlock(bus
->dhd
);
1065 pkt_buf_free_skb(pkt
);
1070 int dhd_bus_txdata(struct dhd_bus
*bus
, struct sk_buff
*pkt
)
1072 int ret
= BCME_ERROR
;
1075 DHD_TRACE(("%s: Enter\n", __func__
));
1080 /* Push the test header if doing loopback */
1081 if (bus
->ext_loop
) {
1083 skb_push(pkt
, SDPCM_TEST_HDRLEN
);
1085 *data
++ = SDPCM_TEST_ECHOREQ
;
1086 *data
++ = (u8
) bus
->loopid
++;
1087 *data
++ = (datalen
>> 0);
1088 *data
++ = (datalen
>> 8);
1089 datalen
+= SDPCM_TEST_HDRLEN
;
1093 /* Add space for the header */
1094 skb_push(pkt
, SDPCM_HDRLEN
);
1095 ASSERT(IS_ALIGNED((unsigned long)(pkt
->data
), 2));
1097 prec
= PRIO2PREC((pkt
->priority
& PRIOMASK
));
1099 /* Check for existing queue, current flow-control,
1100 pending event, or pending clock */
1101 if (dhd_deferred_tx
|| bus
->fcstate
|| pktq_len(&bus
->txq
)
1102 || bus
->dpc_sched
|| (!DATAOK(bus
))
1103 || (bus
->flowcontrol
& NBITVAL(prec
))
1104 || (bus
->clkstate
!= CLK_AVAIL
)) {
1105 DHD_TRACE(("%s: deferring pktq len %d\n", __func__
,
1106 pktq_len(&bus
->txq
)));
1109 /* Priority based enq */
1110 dhd_os_sdlock_txq(bus
->dhd
);
1111 if (dhd_prec_enq(bus
->dhd
, &bus
->txq
, pkt
, prec
) == false) {
1112 skb_pull(pkt
, SDPCM_HDRLEN
);
1113 dhd_txcomplete(bus
->dhd
, pkt
, false);
1114 pkt_buf_free_skb(pkt
);
1115 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__
));
1116 ret
= BCME_NORESOURCE
;
1120 dhd_os_sdunlock_txq(bus
->dhd
);
1122 if (pktq_len(&bus
->txq
) >= TXHI
)
1123 dhd_txflowcontrol(bus
->dhd
, 0, ON
);
1126 if (pktq_plen(&bus
->txq
, prec
) > qcount
[prec
])
1127 qcount
[prec
] = pktq_plen(&bus
->txq
, prec
);
1129 /* Schedule DPC if needed to send queued packet(s) */
1130 if (dhd_deferred_tx
&& !bus
->dpc_sched
) {
1131 bus
->dpc_sched
= true;
1132 dhd_sched_dpc(bus
->dhd
);
1135 /* Lock: we're about to use shared data/code (and SDIO) */
1136 dhd_os_sdlock(bus
->dhd
);
1138 /* Otherwise, send it now */
1140 /* Make sure back plane ht clk is on, no pending allowed */
1141 dhdsdio_clkctl(bus
, CLK_AVAIL
, true);
1144 DHD_TRACE(("%s: calling txpkt\n", __func__
));
1145 ret
= dhdsdio_txpkt(bus
, pkt
, SDPCM_DATA_CHANNEL
, true);
1147 ret
= dhdsdio_txpkt(bus
, pkt
,
1148 (bus
->ext_loop
? SDPCM_TEST_CHANNEL
:
1149 SDPCM_DATA_CHANNEL
), true);
1152 bus
->dhd
->tx_errors
++;
1154 bus
->dhd
->dstats
.tx_bytes
+= datalen
;
1156 if ((bus
->idletime
== DHD_IDLE_IMMEDIATE
) && !bus
->dpc_sched
) {
1157 bus
->activity
= false;
1158 dhdsdio_clkctl(bus
, CLK_NONE
, true);
1161 dhd_os_sdunlock(bus
->dhd
);
1167 static uint
dhdsdio_sendfromq(dhd_bus_t
*bus
, uint maxframes
)
1169 struct sk_buff
*pkt
;
1172 int ret
= 0, prec_out
;
1177 dhd_pub_t
*dhd
= bus
->dhd
;
1178 sdpcmd_regs_t
*regs
= bus
->regs
;
1180 DHD_TRACE(("%s: Enter\n", __func__
));
1182 tx_prec_map
= ~bus
->flowcontrol
;
1184 /* Send frames until the limit or some other event */
1185 for (cnt
= 0; (cnt
< maxframes
) && DATAOK(bus
); cnt
++) {
1186 dhd_os_sdlock_txq(bus
->dhd
);
1187 pkt
= pktq_mdeq(&bus
->txq
, tx_prec_map
, &prec_out
);
1189 dhd_os_sdunlock_txq(bus
->dhd
);
1192 dhd_os_sdunlock_txq(bus
->dhd
);
1193 datalen
= pkt
->len
- SDPCM_HDRLEN
;
1196 ret
= dhdsdio_txpkt(bus
, pkt
, SDPCM_DATA_CHANNEL
, true);
1198 ret
= dhdsdio_txpkt(bus
, pkt
,
1199 (bus
->ext_loop
? SDPCM_TEST_CHANNEL
:
1200 SDPCM_DATA_CHANNEL
), true);
1203 bus
->dhd
->tx_errors
++;
1205 bus
->dhd
->dstats
.tx_bytes
+= datalen
;
1207 /* In poll mode, need to check for other events */
1208 if (!bus
->intr
&& cnt
) {
1209 /* Check device status, signal pending interrupt */
1210 R_SDREG(intstatus
, ®s
->intstatus
, retries
);
1212 if (bcmsdh_regfail(bus
->sdh
))
1214 if (intstatus
& bus
->hostintmask
)
1219 /* Deflow-control stack if needed */
1220 if (dhd
->up
&& (dhd
->busstate
== DHD_BUS_DATA
) &&
1221 dhd
->txoff
&& (pktq_len(&bus
->txq
) < TXLOW
))
1222 dhd_txflowcontrol(dhd
, 0, OFF
);
1227 int dhd_bus_txctl(struct dhd_bus
*bus
, unsigned char *msg
, uint msglen
)
1233 bcmsdh_info_t
*sdh
= bus
->sdh
;
1238 DHD_TRACE(("%s: Enter\n", __func__
));
1240 if (bus
->dhd
->dongle_reset
)
1243 /* Back the pointer to make a room for bus header */
1244 frame
= msg
- SDPCM_HDRLEN
;
1245 len
= (msglen
+= SDPCM_HDRLEN
);
1247 /* Add alignment padding (optional for ctl frames) */
1249 doff
= ((unsigned long)frame
% DHD_SDALIGN
);
1254 memset(frame
, 0, doff
+ SDPCM_HDRLEN
);
1256 ASSERT(doff
< DHD_SDALIGN
);
1258 doff
+= SDPCM_HDRLEN
;
1260 /* Round send length to next SDIO block */
1261 if (bus
->roundup
&& bus
->blocksize
&& (len
> bus
->blocksize
)) {
1262 u16 pad
= bus
->blocksize
- (len
% bus
->blocksize
);
1263 if ((pad
<= bus
->roundup
) && (pad
< bus
->blocksize
))
1265 } else if (len
% DHD_SDALIGN
) {
1266 len
+= DHD_SDALIGN
- (len
% DHD_SDALIGN
);
1269 /* Satisfy length-alignment requirements */
1270 if (forcealign
&& (len
& (ALIGNMENT
- 1)))
1271 len
= roundup(len
, ALIGNMENT
);
1273 ASSERT(IS_ALIGNED((unsigned long)frame
, 2));
1275 /* Need to lock here to protect txseq and SDIO tx calls */
1276 dhd_os_sdlock(bus
->dhd
);
1280 /* Make sure backplane clock is on */
1281 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
1283 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1284 *(u16
*) frame
= cpu_to_le16((u16
) msglen
);
1285 *(((u16
*) frame
) + 1) = cpu_to_le16(~msglen
);
1287 /* Software tag: channel, sequence number, data offset */
1289 ((SDPCM_CONTROL_CHANNEL
<< SDPCM_CHANNEL_SHIFT
) &
1291 | bus
->tx_seq
| ((doff
<< SDPCM_DOFFSET_SHIFT
) &
1292 SDPCM_DOFFSET_MASK
);
1293 put_unaligned_le32(swheader
, frame
+ SDPCM_FRAMETAG_LEN
);
1294 put_unaligned_le32(0, frame
+ SDPCM_FRAMETAG_LEN
+ sizeof(swheader
));
1297 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1298 __func__
, bus
->tx_max
, bus
->tx_seq
));
1299 bus
->ctrl_frame_stat
= true;
1301 bus
->ctrl_frame_buf
= frame
;
1302 bus
->ctrl_frame_len
= len
;
1304 dhd_wait_for_event(bus
->dhd
, &bus
->ctrl_frame_stat
);
1306 if (bus
->ctrl_frame_stat
== false) {
1307 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__
));
1310 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__
));
1317 if (DHD_BYTES_ON() && DHD_CTL_ON())
1318 prhex("Tx Frame", frame
, len
);
1319 else if (DHD_HDRS_ON())
1320 prhex("TxHdr", frame
, min_t(u16
, len
, 16));
1324 bus
->ctrl_frame_stat
= false;
1326 dhd_bcmsdh_send_buf(bus
, bcmsdh_cur_sbwad(sdh
),
1327 SDIO_FUNC_2
, F2SYNC
, frame
, len
,
1330 ASSERT(ret
!= BCME_PENDING
);
1333 /* On failure, abort the command and
1334 terminate the frame */
1335 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1339 bcmsdh_abort(sdh
, SDIO_FUNC_2
);
1341 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
,
1342 SBSDIO_FUNC1_FRAMECTRL
,
1346 for (i
= 0; i
< 3; i
++) {
1348 hi
= bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
,
1349 SBSDIO_FUNC1_WFRAMEBCHI
,
1351 lo
= bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
,
1352 SBSDIO_FUNC1_WFRAMEBCLO
,
1354 bus
->f1regdata
+= 2;
1355 if ((hi
== 0) && (lo
== 0))
1362 (bus
->tx_seq
+ 1) % SDPCM_SEQUENCE_WRAP
;
1364 } while ((ret
< 0) && retries
++ < TXRETRIES
);
1367 if ((bus
->idletime
== DHD_IDLE_IMMEDIATE
) && !bus
->dpc_sched
) {
1368 bus
->activity
= false;
1369 dhdsdio_clkctl(bus
, CLK_NONE
, true);
1372 dhd_os_sdunlock(bus
->dhd
);
1375 bus
->dhd
->tx_ctlerrs
++;
1377 bus
->dhd
->tx_ctlpkts
++;
1379 return ret
? -EIO
: 0;
1382 int dhd_bus_rxctl(struct dhd_bus
*bus
, unsigned char *msg
, uint msglen
)
1388 DHD_TRACE(("%s: Enter\n", __func__
));
1390 if (bus
->dhd
->dongle_reset
)
1393 /* Wait until control frame is available */
1394 timeleft
= dhd_os_ioctl_resp_wait(bus
->dhd
, &bus
->rxlen
, &pending
);
1396 dhd_os_sdlock(bus
->dhd
);
1398 memcpy(msg
, bus
->rxctl
, min(msglen
, rxlen
));
1400 dhd_os_sdunlock(bus
->dhd
);
1403 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1404 __func__
, rxlen
, msglen
));
1405 } else if (timeleft
== 0) {
1406 DHD_ERROR(("%s: resumed on timeout\n", __func__
));
1408 dhd_os_sdlock(bus
->dhd
);
1409 dhdsdio_checkdied(bus
, NULL
, 0);
1410 dhd_os_sdunlock(bus
->dhd
);
1411 #endif /* DHD_DEBUG */
1412 } else if (pending
== true) {
1413 DHD_CTL(("%s: cancelled\n", __func__
));
1414 return -ERESTARTSYS
;
1416 DHD_CTL(("%s: resumed for unknown reason?\n", __func__
));
1418 dhd_os_sdlock(bus
->dhd
);
1419 dhdsdio_checkdied(bus
, NULL
, 0);
1420 dhd_os_sdunlock(bus
->dhd
);
1421 #endif /* DHD_DEBUG */
1425 bus
->dhd
->rx_ctlpkts
++;
1427 bus
->dhd
->rx_ctlerrs
++;
1429 return rxlen
? (int)rxlen
: -ETIMEDOUT
;
1468 const bcm_iovar_t dhdsdio_iovars
[] = {
1469 {"intr", IOV_INTR
, 0, IOVT_BOOL
, 0},
1470 {"sleep", IOV_SLEEP
, 0, IOVT_BOOL
, 0},
1471 {"pollrate", IOV_POLLRATE
, 0, IOVT_UINT32
, 0},
1472 {"idletime", IOV_IDLETIME
, 0, IOVT_INT32
, 0},
1473 {"idleclock", IOV_IDLECLOCK
, 0, IOVT_INT32
, 0},
1474 {"sd1idle", IOV_SD1IDLE
, 0, IOVT_BOOL
, 0},
1475 {"membytes", IOV_MEMBYTES
, 0, IOVT_BUFFER
, 2 * sizeof(int)},
1476 {"memsize", IOV_MEMSIZE
, 0, IOVT_UINT32
, 0},
1477 {"download", IOV_DOWNLOAD
, 0, IOVT_BOOL
, 0},
1478 {"vars", IOV_VARS
, 0, IOVT_BUFFER
, 0},
1479 {"sdiod_drive", IOV_SDIOD_DRIVE
, 0, IOVT_UINT32
, 0},
1480 {"readahead", IOV_READAHEAD
, 0, IOVT_BOOL
, 0},
1481 {"sdrxchain", IOV_SDRXCHAIN
, 0, IOVT_BOOL
, 0},
1482 {"alignctl", IOV_ALIGNCTL
, 0, IOVT_BOOL
, 0},
1483 {"sdalign", IOV_SDALIGN
, 0, IOVT_BOOL
, 0},
1484 {"devreset", IOV_DEVRESET
, 0, IOVT_BOOL
, 0},
1486 {"sdreg", IOV_SDREG
, 0, IOVT_BUFFER
, sizeof(sdreg_t
)}
1488 {"sbreg", IOV_SBREG
, 0, IOVT_BUFFER
, sizeof(sdreg_t
)}
1490 {"sd_cis", IOV_SDCIS
, 0, IOVT_BUFFER
, DHD_IOCTL_MAXLEN
}
1492 {"forcealign", IOV_FORCEEVEN
, 0, IOVT_BOOL
, 0}
1494 {"txbound", IOV_TXBOUND
, 0, IOVT_UINT32
, 0}
1496 {"rxbound", IOV_RXBOUND
, 0, IOVT_UINT32
, 0}
1498 {"txminmax", IOV_TXMINMAX
, 0, IOVT_UINT32
, 0}
1500 {"cpu", IOV_CPU
, 0, IOVT_BOOL
, 0}
1503 {"checkdied", IOV_CHECKDIED
, 0, IOVT_BUFFER
, 0}
1505 #endif /* DHD_DEBUG */
1506 #endif /* DHD_DEBUG */
1508 {"extloop", IOV_EXTLOOP
, 0, IOVT_BOOL
, 0}
1510 {"pktgen", IOV_PKTGEN
, 0, IOVT_BUFFER
, sizeof(dhd_pktgen_t
)}
1518 dhd_dump_pct(struct bcmstrbuf
*strbuf
, char *desc
, uint num
, uint div
)
1523 bcm_bprintf(strbuf
, "%s N/A", desc
);
1526 q2
= (100 * (num
- (q1
* div
))) / div
;
1527 bcm_bprintf(strbuf
, "%s %d.%02d", desc
, q1
, q2
);
1531 void dhd_bus_dump(dhd_pub_t
*dhdp
, struct bcmstrbuf
*strbuf
)
1533 dhd_bus_t
*bus
= dhdp
->bus
;
1535 bcm_bprintf(strbuf
, "Bus SDIO structure:\n");
1537 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1538 bus
->hostintmask
, bus
->intstatus
, bus
->sdpcm_ver
);
1540 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1541 bus
->fcstate
, pktq_len(&bus
->txq
), bus
->tx_seq
, bus
->tx_max
,
1542 bus
->rxskip
, bus
->rxlen
, bus
->rx_seq
);
1543 bcm_bprintf(strbuf
, "intr %d intrcount %d lastintrs %d spurious %d\n",
1544 bus
->intr
, bus
->intrcount
, bus
->lastintrs
, bus
->spurious
);
1545 bcm_bprintf(strbuf
, "pollrate %d pollcnt %d regfails %d\n",
1546 bus
->pollrate
, bus
->pollcnt
, bus
->regfails
);
1548 bcm_bprintf(strbuf
, "\nAdditional counters:\n");
1550 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1551 bus
->tx_sderrs
, bus
->fcqueued
, bus
->rxrtx
, bus
->rx_toolong
,
1553 bcm_bprintf(strbuf
, "rx_hdrfail %d badhdr %d badseq %d\n",
1554 bus
->rx_hdrfail
, bus
->rx_badhdr
, bus
->rx_badseq
);
1555 bcm_bprintf(strbuf
, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus
->fc_rcvd
,
1556 bus
->fc_xoff
, bus
->fc_xon
);
1557 bcm_bprintf(strbuf
, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1558 bus
->rxglomfail
, bus
->rxglomframes
, bus
->rxglompkts
);
1559 bcm_bprintf(strbuf
, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1560 (bus
->f2rxhdrs
+ bus
->f2rxdata
), bus
->f2rxhdrs
,
1561 bus
->f2rxdata
, bus
->f2txdata
, bus
->f1regdata
);
1563 dhd_dump_pct(strbuf
, "\nRx: pkts/f2rd", bus
->dhd
->rx_packets
,
1564 (bus
->f2rxhdrs
+ bus
->f2rxdata
));
1565 dhd_dump_pct(strbuf
, ", pkts/f1sd", bus
->dhd
->rx_packets
,
1567 dhd_dump_pct(strbuf
, ", pkts/sd", bus
->dhd
->rx_packets
,
1568 (bus
->f2rxhdrs
+ bus
->f2rxdata
+ bus
->f1regdata
));
1569 dhd_dump_pct(strbuf
, ", pkts/int", bus
->dhd
->rx_packets
,
1571 bcm_bprintf(strbuf
, "\n");
1573 dhd_dump_pct(strbuf
, "Rx: glom pct", (100 * bus
->rxglompkts
),
1574 bus
->dhd
->rx_packets
);
1575 dhd_dump_pct(strbuf
, ", pkts/glom", bus
->rxglompkts
,
1577 bcm_bprintf(strbuf
, "\n");
1579 dhd_dump_pct(strbuf
, "Tx: pkts/f2wr", bus
->dhd
->tx_packets
,
1581 dhd_dump_pct(strbuf
, ", pkts/f1sd", bus
->dhd
->tx_packets
,
1583 dhd_dump_pct(strbuf
, ", pkts/sd", bus
->dhd
->tx_packets
,
1584 (bus
->f2txdata
+ bus
->f1regdata
));
1585 dhd_dump_pct(strbuf
, ", pkts/int", bus
->dhd
->tx_packets
,
1587 bcm_bprintf(strbuf
, "\n");
1589 dhd_dump_pct(strbuf
, "Total: pkts/f2rw",
1590 (bus
->dhd
->tx_packets
+ bus
->dhd
->rx_packets
),
1591 (bus
->f2txdata
+ bus
->f2rxhdrs
+ bus
->f2rxdata
));
1592 dhd_dump_pct(strbuf
, ", pkts/f1sd",
1593 (bus
->dhd
->tx_packets
+ bus
->dhd
->rx_packets
),
1595 dhd_dump_pct(strbuf
, ", pkts/sd",
1596 (bus
->dhd
->tx_packets
+ bus
->dhd
->rx_packets
),
1597 (bus
->f2txdata
+ bus
->f2rxhdrs
+ bus
->f2rxdata
+
1599 dhd_dump_pct(strbuf
, ", pkts/int",
1600 (bus
->dhd
->tx_packets
+ bus
->dhd
->rx_packets
),
1602 bcm_bprintf(strbuf
, "\n\n");
1606 if (bus
->pktgen_count
) {
1607 bcm_bprintf(strbuf
, "pktgen config and count:\n");
1609 "freq %d count %d print %d total %d min %d len %d\n",
1610 bus
->pktgen_freq
, bus
->pktgen_count
,
1611 bus
->pktgen_print
, bus
->pktgen_total
,
1612 bus
->pktgen_minlen
, bus
->pktgen_maxlen
);
1613 bcm_bprintf(strbuf
, "send attempts %d rcvd %d fail %d\n",
1614 bus
->pktgen_sent
, bus
->pktgen_rcvd
,
1619 bcm_bprintf(strbuf
, "dpc_sched %d host interrupt%spending\n",
1621 (bcmsdh_intr_pending(bus
->sdh
) ? " " : " not "));
1622 bcm_bprintf(strbuf
, "blocksize %d roundup %d\n", bus
->blocksize
,
1624 #endif /* DHD_DEBUG */
1626 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1627 bus
->clkstate
, bus
->activity
, bus
->idletime
, bus
->idlecount
,
1631 void dhd_bus_clearcounts(dhd_pub_t
*dhdp
)
1633 dhd_bus_t
*bus
= (dhd_bus_t
*) dhdp
->bus
;
1635 bus
->intrcount
= bus
->lastintrs
= bus
->spurious
= bus
->regfails
= 0;
1636 bus
->rxrtx
= bus
->rx_toolong
= bus
->rxc_errors
= 0;
1637 bus
->rx_hdrfail
= bus
->rx_badhdr
= bus
->rx_badseq
= 0;
1638 bus
->tx_sderrs
= bus
->fc_rcvd
= bus
->fc_xoff
= bus
->fc_xon
= 0;
1639 bus
->rxglomfail
= bus
->rxglomframes
= bus
->rxglompkts
= 0;
1640 bus
->f2rxhdrs
= bus
->f2rxdata
= bus
->f2txdata
= bus
->f1regdata
= 0;
1644 static int dhdsdio_pktgen_get(dhd_bus_t
*bus
, u8
*arg
)
1646 dhd_pktgen_t pktgen
;
1648 pktgen
.version
= DHD_PKTGEN_VERSION
;
1649 pktgen
.freq
= bus
->pktgen_freq
;
1650 pktgen
.count
= bus
->pktgen_count
;
1651 pktgen
.print
= bus
->pktgen_print
;
1652 pktgen
.total
= bus
->pktgen_total
;
1653 pktgen
.minlen
= bus
->pktgen_minlen
;
1654 pktgen
.maxlen
= bus
->pktgen_maxlen
;
1655 pktgen
.numsent
= bus
->pktgen_sent
;
1656 pktgen
.numrcvd
= bus
->pktgen_rcvd
;
1657 pktgen
.numfail
= bus
->pktgen_fail
;
1658 pktgen
.mode
= bus
->pktgen_mode
;
1659 pktgen
.stop
= bus
->pktgen_stop
;
1661 memcpy(arg
, &pktgen
, sizeof(pktgen
));
1666 static int dhdsdio_pktgen_set(dhd_bus_t
*bus
, u8
*arg
)
1668 dhd_pktgen_t pktgen
;
1669 uint oldcnt
, oldmode
;
1671 memcpy(&pktgen
, arg
, sizeof(pktgen
));
1672 if (pktgen
.version
!= DHD_PKTGEN_VERSION
)
1675 oldcnt
= bus
->pktgen_count
;
1676 oldmode
= bus
->pktgen_mode
;
1678 bus
->pktgen_freq
= pktgen
.freq
;
1679 bus
->pktgen_count
= pktgen
.count
;
1680 bus
->pktgen_print
= pktgen
.print
;
1681 bus
->pktgen_total
= pktgen
.total
;
1682 bus
->pktgen_minlen
= pktgen
.minlen
;
1683 bus
->pktgen_maxlen
= pktgen
.maxlen
;
1684 bus
->pktgen_mode
= pktgen
.mode
;
1685 bus
->pktgen_stop
= pktgen
.stop
;
1687 bus
->pktgen_tick
= bus
->pktgen_ptick
= 0;
1688 bus
->pktgen_len
= max(bus
->pktgen_len
, bus
->pktgen_minlen
);
1689 bus
->pktgen_len
= min(bus
->pktgen_len
, bus
->pktgen_maxlen
);
1691 /* Clear counts for a new pktgen (mode change, or was stopped) */
1692 if (bus
->pktgen_count
&& (!oldcnt
|| oldmode
!= bus
->pktgen_mode
))
1693 bus
->pktgen_sent
= bus
->pktgen_rcvd
= bus
->pktgen_fail
= 0;
1700 dhdsdio_membytes(dhd_bus_t
*bus
, bool write
, u32 address
, u8
*data
,
1707 /* Determine initial transfer parameters */
1708 sdaddr
= address
& SBSDIO_SB_OFT_ADDR_MASK
;
1709 if ((sdaddr
+ size
) & SBSDIO_SBWINDOW_MASK
)
1710 dsize
= (SBSDIO_SB_OFT_ADDR_LIMIT
- sdaddr
);
1714 /* Set the backplane window to include the start address */
1715 bcmerror
= dhdsdio_set_siaddr_window(bus
, address
);
1717 DHD_ERROR(("%s: window change failed\n", __func__
));
1721 /* Do the transfer(s) */
1723 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1724 __func__
, (write
? "write" : "read"), dsize
,
1725 sdaddr
, (address
& SBSDIO_SBWINDOW_MASK
)));
1727 bcmsdh_rwdata(bus
->sdh
, write
, sdaddr
, data
, dsize
);
1729 DHD_ERROR(("%s: membytes transfer failed\n", __func__
));
1733 /* Adjust for next transfer (if any) */
1738 bcmerror
= dhdsdio_set_siaddr_window(bus
, address
);
1740 DHD_ERROR(("%s: window change failed\n",
1745 dsize
= min_t(uint
, SBSDIO_SB_OFT_ADDR_LIMIT
, size
);
1750 /* Return the window to backplane enumeration space for core access */
1751 if (dhdsdio_set_siaddr_window(bus
, bcmsdh_cur_sbwad(bus
->sdh
))) {
1752 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1753 __func__
, bcmsdh_cur_sbwad(bus
->sdh
)));
1760 static int dhdsdio_readshared(dhd_bus_t
*bus
, sdpcm_shared_t
*sh
)
1765 /* Read last word in memory to determine address of
1766 sdpcm_shared structure */
1767 rv
= dhdsdio_membytes(bus
, false, bus
->ramsize
- 4, (u8
*)&addr
, 4);
1771 addr
= le32_to_cpu(addr
);
1773 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr
));
1776 * Check if addr is valid.
1777 * NVRAM length at the end of memory should have been overwritten.
1779 if (addr
== 0 || ((~addr
>> 16) & 0xffff) == (addr
& 0xffff)) {
1780 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1785 /* Read hndrte_shared structure */
1786 rv
= dhdsdio_membytes(bus
, false, addr
, (u8
*) sh
,
1787 sizeof(sdpcm_shared_t
));
1792 sh
->flags
= le32_to_cpu(sh
->flags
);
1793 sh
->trap_addr
= le32_to_cpu(sh
->trap_addr
);
1794 sh
->assert_exp_addr
= le32_to_cpu(sh
->assert_exp_addr
);
1795 sh
->assert_file_addr
= le32_to_cpu(sh
->assert_file_addr
);
1796 sh
->assert_line
= le32_to_cpu(sh
->assert_line
);
1797 sh
->console_addr
= le32_to_cpu(sh
->console_addr
);
1798 sh
->msgtrace_addr
= le32_to_cpu(sh
->msgtrace_addr
);
1800 if ((sh
->flags
& SDPCM_SHARED_VERSION_MASK
) != SDPCM_SHARED_VERSION
) {
1801 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1802 "is different than sdpcm_shared version %d in dongle\n",
1803 __func__
, SDPCM_SHARED_VERSION
,
1804 sh
->flags
& SDPCM_SHARED_VERSION_MASK
));
1811 static int dhdsdio_checkdied(dhd_bus_t
*bus
, u8
*data
, uint size
)
1815 char *mbuffer
= NULL
;
1816 uint maxstrlen
= 256;
1819 sdpcm_shared_t sdpcm_shared
;
1820 struct bcmstrbuf strbuf
;
1822 DHD_TRACE(("%s: Enter\n", __func__
));
1826 * Called after a rx ctrl timeout. "data" is NULL.
1827 * allocate memory to trace the trap or assert.
1830 mbuffer
= data
= kmalloc(msize
, GFP_ATOMIC
);
1831 if (mbuffer
== NULL
) {
1832 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__
,
1834 bcmerror
= BCME_NOMEM
;
1839 str
= kmalloc(maxstrlen
, GFP_ATOMIC
);
1841 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__
, maxstrlen
));
1842 bcmerror
= BCME_NOMEM
;
1846 bcmerror
= dhdsdio_readshared(bus
, &sdpcm_shared
);
1850 bcm_binit(&strbuf
, data
, size
);
1852 bcm_bprintf(&strbuf
,
1853 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1854 sdpcm_shared
.msgtrace_addr
, sdpcm_shared
.console_addr
);
1856 if ((sdpcm_shared
.flags
& SDPCM_SHARED_ASSERT_BUILT
) == 0) {
1857 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1858 * (Avoids conflict with real asserts for programmatic
1859 * parsing of output.)
1861 bcm_bprintf(&strbuf
, "Assrt not built in dongle\n");
1864 if ((sdpcm_shared
.flags
& (SDPCM_SHARED_ASSERT
| SDPCM_SHARED_TRAP
)) ==
1866 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1867 * (Avoids conflict with real asserts for programmatic
1868 * parsing of output.)
1870 bcm_bprintf(&strbuf
, "No trap%s in dongle",
1871 (sdpcm_shared
.flags
& SDPCM_SHARED_ASSERT_BUILT
)
1874 if (sdpcm_shared
.flags
& SDPCM_SHARED_ASSERT
) {
1875 /* Download assert */
1876 bcm_bprintf(&strbuf
, "Dongle assert");
1877 if (sdpcm_shared
.assert_exp_addr
!= 0) {
1879 bcmerror
= dhdsdio_membytes(bus
, false,
1880 sdpcm_shared
.assert_exp_addr
,
1881 (u8
*) str
, maxstrlen
);
1885 str
[maxstrlen
- 1] = '\0';
1886 bcm_bprintf(&strbuf
, " expr \"%s\"", str
);
1889 if (sdpcm_shared
.assert_file_addr
!= 0) {
1891 bcmerror
= dhdsdio_membytes(bus
, false,
1892 sdpcm_shared
.assert_file_addr
,
1893 (u8
*) str
, maxstrlen
);
1897 str
[maxstrlen
- 1] = '\0';
1898 bcm_bprintf(&strbuf
, " file \"%s\"", str
);
1901 bcm_bprintf(&strbuf
, " line %d ",
1902 sdpcm_shared
.assert_line
);
1905 if (sdpcm_shared
.flags
& SDPCM_SHARED_TRAP
) {
1906 bcmerror
= dhdsdio_membytes(bus
, false,
1907 sdpcm_shared
.trap_addr
, (u8
*)&tr
,
1912 bcm_bprintf(&strbuf
,
1913 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
1914 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
1915 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
1916 tr
.type
, tr
.epc
, tr
.cpsr
, tr
.spsr
, tr
.r13
,
1917 tr
.r14
, tr
.pc
, sdpcm_shared
.trap_addr
,
1918 tr
.r0
, tr
.r1
, tr
.r2
, tr
.r3
, tr
.r4
, tr
.r5
,
1923 if (sdpcm_shared
.flags
& (SDPCM_SHARED_ASSERT
| SDPCM_SHARED_TRAP
))
1924 DHD_ERROR(("%s: %s\n", __func__
, strbuf
.origbuf
));
1927 if (sdpcm_shared
.flags
& SDPCM_SHARED_TRAP
) {
1928 /* Mem dump to a file on device */
1929 dhdsdio_mem_dump(bus
);
1931 #endif /* DHD_DEBUG */
1940 static int dhdsdio_mem_dump(dhd_bus_t
*bus
)
1943 int size
; /* Full mem size */
1944 int start
= 0; /* Start address */
1945 int read_size
= 0; /* Read size of each iteration */
1946 u8
*buf
= NULL
, *databuf
= NULL
;
1948 /* Get full mem size */
1949 size
= bus
->ramsize
;
1950 buf
= kmalloc(size
, GFP_ATOMIC
);
1952 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__
, size
));
1956 /* Read mem content */
1957 printk(KERN_DEBUG
"Dump dongle memory");
1960 read_size
= min(MEMBLOCK
, size
);
1961 ret
= dhdsdio_membytes(bus
, false, start
, databuf
, read_size
);
1963 DHD_ERROR(("%s: Error membytes %d\n", __func__
, ret
));
1969 /* Decrement size and increment start address */
1972 databuf
+= read_size
;
1974 printk(KERN_DEBUG
"Done\n");
1976 /* free buf before return !!! */
1977 if (write_to_file(bus
->dhd
, buf
, bus
->ramsize
)) {
1978 DHD_ERROR(("%s: Error writing to files\n", __func__
));
1982 /* buf free handled in write_to_file, not here */
1986 #define CONSOLE_LINE_MAX 192
1988 static int dhdsdio_readconsole(dhd_bus_t
*bus
)
1990 dhd_console_t
*c
= &bus
->console
;
1991 u8 line
[CONSOLE_LINE_MAX
], ch
;
1995 /* Don't do anything until FWREADY updates console address */
1996 if (bus
->console_addr
== 0)
1999 /* Read console log struct */
2000 addr
= bus
->console_addr
+ offsetof(hndrte_cons_t
, log
);
2001 rv
= dhdsdio_membytes(bus
, false, addr
, (u8
*)&c
->log
,
2006 /* Allocate console buffer (one time only) */
2007 if (c
->buf
== NULL
) {
2008 c
->bufsize
= le32_to_cpu(c
->log
.buf_size
);
2009 c
->buf
= kmalloc(c
->bufsize
, GFP_ATOMIC
);
2014 idx
= le32_to_cpu(c
->log
.idx
);
2016 /* Protect against corrupt value */
2017 if (idx
> c
->bufsize
)
2020 /* Skip reading the console buffer if the index pointer
2025 /* Read the console buffer */
2026 addr
= le32_to_cpu(c
->log
.buf
);
2027 rv
= dhdsdio_membytes(bus
, false, addr
, c
->buf
, c
->bufsize
);
2031 while (c
->last
!= idx
) {
2032 for (n
= 0; n
< CONSOLE_LINE_MAX
- 2; n
++) {
2033 if (c
->last
== idx
) {
2034 /* This would output a partial line.
2036 * the buffer pointer and output this
2037 * line next time around.
2042 c
->last
= c
->bufsize
- n
;
2045 ch
= c
->buf
[c
->last
];
2046 c
->last
= (c
->last
+ 1) % c
->bufsize
;
2053 if (line
[n
- 1] == '\r')
2056 printk(KERN_DEBUG
"CONSOLE: %s\n", line
);
2063 #endif /* DHD_DEBUG */
2065 int dhdsdio_downloadvars(dhd_bus_t
*bus
, void *arg
, int len
)
2067 int bcmerror
= BCME_OK
;
2069 DHD_TRACE(("%s: Enter\n", __func__
));
2071 /* Basic sanity checks */
2073 bcmerror
= BCME_NOTDOWN
;
2077 bcmerror
= BCME_BUFTOOSHORT
;
2081 /* Free the old ones and replace with passed variables */
2084 bus
->vars
= kmalloc(len
, GFP_ATOMIC
);
2085 bus
->varsz
= bus
->vars
? len
: 0;
2086 if (bus
->vars
== NULL
) {
2087 bcmerror
= BCME_NOMEM
;
2091 /* Copy the passed variables, which should include the
2092 terminating double-null */
2093 memcpy(bus
->vars
, arg
, bus
->varsz
);
2099 dhdsdio_doiovar(dhd_bus_t
*bus
, const bcm_iovar_t
*vi
, u32 actionid
,
2100 const char *name
, void *params
, int plen
, void *arg
, int len
,
2107 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2108 "len %d val_size %d\n",
2109 __func__
, actionid
, name
, params
, plen
, arg
, len
, val_size
));
2111 bcmerror
= bcm_iovar_lencheck(vi
, arg
, len
, IOV_ISSET(actionid
));
2115 if (plen
>= (int)sizeof(int_val
))
2116 memcpy(&int_val
, params
, sizeof(int_val
));
2118 bool_val
= (int_val
!= 0) ? true : false;
2120 /* Some ioctls use the bus */
2121 dhd_os_sdlock(bus
->dhd
);
2123 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2124 if (bus
->dhd
->dongle_reset
&& !(actionid
== IOV_SVAL(IOV_DEVRESET
) ||
2125 actionid
== IOV_GVAL(IOV_DEVRESET
))) {
2126 bcmerror
= BCME_NOTREADY
;
2130 /* Handle sleep stuff before any clock mucking */
2131 if (vi
->varid
== IOV_SLEEP
) {
2132 if (IOV_ISSET(actionid
)) {
2133 bcmerror
= dhdsdio_bussleep(bus
, bool_val
);
2135 int_val
= (s32
) bus
->sleeping
;
2136 memcpy(arg
, &int_val
, val_size
);
2141 /* Request clock to allow SDIO accesses */
2142 if (!bus
->dhd
->dongle_reset
) {
2144 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
2148 case IOV_GVAL(IOV_INTR
):
2149 int_val
= (s32
) bus
->intr
;
2150 memcpy(arg
, &int_val
, val_size
);
2153 case IOV_SVAL(IOV_INTR
):
2154 bus
->intr
= bool_val
;
2155 bus
->intdis
= false;
2158 DHD_INTR(("%s: enable SDIO device interrupts\n",
2160 bcmsdh_intr_enable(bus
->sdh
);
2162 DHD_INTR(("%s: disable SDIO interrupts\n",
2164 bcmsdh_intr_disable(bus
->sdh
);
2169 case IOV_GVAL(IOV_POLLRATE
):
2170 int_val
= (s32
) bus
->pollrate
;
2171 memcpy(arg
, &int_val
, val_size
);
2174 case IOV_SVAL(IOV_POLLRATE
):
2175 bus
->pollrate
= (uint
) int_val
;
2176 bus
->poll
= (bus
->pollrate
!= 0);
2179 case IOV_GVAL(IOV_IDLETIME
):
2180 int_val
= bus
->idletime
;
2181 memcpy(arg
, &int_val
, val_size
);
2184 case IOV_SVAL(IOV_IDLETIME
):
2185 if ((int_val
< 0) && (int_val
!= DHD_IDLE_IMMEDIATE
))
2186 bcmerror
= BCME_BADARG
;
2188 bus
->idletime
= int_val
;
2191 case IOV_GVAL(IOV_IDLECLOCK
):
2192 int_val
= (s32
) bus
->idleclock
;
2193 memcpy(arg
, &int_val
, val_size
);
2196 case IOV_SVAL(IOV_IDLECLOCK
):
2197 bus
->idleclock
= int_val
;
2200 case IOV_GVAL(IOV_SD1IDLE
):
2201 int_val
= (s32
) sd1idle
;
2202 memcpy(arg
, &int_val
, val_size
);
2205 case IOV_SVAL(IOV_SD1IDLE
):
2209 case IOV_SVAL(IOV_MEMBYTES
):
2210 case IOV_GVAL(IOV_MEMBYTES
):
2216 bool set
= (actionid
== IOV_SVAL(IOV_MEMBYTES
));
2218 ASSERT(plen
>= 2 * sizeof(int));
2220 address
= (u32
) int_val
;
2221 memcpy(&int_val
, (char *)params
+ sizeof(int_val
),
2223 size
= (uint
) int_val
;
2225 /* Do some validation */
2226 dsize
= set
? plen
- (2 * sizeof(int)) : len
;
2228 DHD_ERROR(("%s: error on %s membytes, addr "
2229 "0x%08x size %d dsize %d\n",
2230 __func__
, (set
? "set" : "get"),
2231 address
, size
, dsize
));
2232 bcmerror
= BCME_BADARG
;
2236 DHD_INFO(("%s: Request to %s %d bytes at address "
2238 __func__
, (set
? "write" : "read"), size
, address
));
2240 /* If we know about SOCRAM, check for a fit */
2241 if ((bus
->orig_ramsize
) &&
2242 ((address
> bus
->orig_ramsize
)
2243 || (address
+ size
> bus
->orig_ramsize
))) {
2244 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2245 "bytes at 0x%08x\n",
2246 __func__
, bus
->orig_ramsize
, size
, address
));
2247 bcmerror
= BCME_BADARG
;
2251 /* Generate the actual data pointer */
2253 set
? (u8
*) params
+
2254 2 * sizeof(int) : (u8
*) arg
;
2256 /* Call to do the transfer */
2258 dhdsdio_membytes(bus
, set
, address
, data
, size
);
2263 case IOV_GVAL(IOV_MEMSIZE
):
2264 int_val
= (s32
) bus
->ramsize
;
2265 memcpy(arg
, &int_val
, val_size
);
2268 case IOV_GVAL(IOV_SDIOD_DRIVE
):
2269 int_val
= (s32
) dhd_sdiod_drive_strength
;
2270 memcpy(arg
, &int_val
, val_size
);
2273 case IOV_SVAL(IOV_SDIOD_DRIVE
):
2274 dhd_sdiod_drive_strength
= int_val
;
2275 si_sdiod_drive_strength_init(bus
->sih
,
2276 dhd_sdiod_drive_strength
);
2279 case IOV_SVAL(IOV_DOWNLOAD
):
2280 bcmerror
= dhdsdio_download_state(bus
, bool_val
);
2283 case IOV_SVAL(IOV_VARS
):
2284 bcmerror
= dhdsdio_downloadvars(bus
, arg
, len
);
2287 case IOV_GVAL(IOV_READAHEAD
):
2288 int_val
= (s32
) dhd_readahead
;
2289 memcpy(arg
, &int_val
, val_size
);
2292 case IOV_SVAL(IOV_READAHEAD
):
2293 if (bool_val
&& !dhd_readahead
)
2295 dhd_readahead
= bool_val
;
2298 case IOV_GVAL(IOV_SDRXCHAIN
):
2299 int_val
= (s32
) bus
->use_rxchain
;
2300 memcpy(arg
, &int_val
, val_size
);
2303 case IOV_SVAL(IOV_SDRXCHAIN
):
2304 if (bool_val
&& !bus
->sd_rxchain
)
2305 bcmerror
= BCME_UNSUPPORTED
;
2307 bus
->use_rxchain
= bool_val
;
2309 case IOV_GVAL(IOV_ALIGNCTL
):
2310 int_val
= (s32
) dhd_alignctl
;
2311 memcpy(arg
, &int_val
, val_size
);
2314 case IOV_SVAL(IOV_ALIGNCTL
):
2315 dhd_alignctl
= bool_val
;
2318 case IOV_GVAL(IOV_SDALIGN
):
2319 int_val
= DHD_SDALIGN
;
2320 memcpy(arg
, &int_val
, val_size
);
2324 case IOV_GVAL(IOV_VARS
):
2325 if (bus
->varsz
< (uint
) len
)
2326 memcpy(arg
, bus
->vars
, bus
->varsz
);
2328 bcmerror
= BCME_BUFTOOSHORT
;
2330 #endif /* DHD_DEBUG */
2333 case IOV_GVAL(IOV_SDREG
):
2338 sd_ptr
= (sdreg_t
*) params
;
2340 addr
= (unsigned long)bus
->regs
+ sd_ptr
->offset
;
2341 size
= sd_ptr
->func
;
2342 int_val
= (s32
) bcmsdh_reg_read(bus
->sdh
, addr
, size
);
2343 if (bcmsdh_regfail(bus
->sdh
))
2344 bcmerror
= BCME_SDIO_ERROR
;
2345 memcpy(arg
, &int_val
, sizeof(s32
));
2349 case IOV_SVAL(IOV_SDREG
):
2354 sd_ptr
= (sdreg_t
*) params
;
2356 addr
= (unsigned long)bus
->regs
+ sd_ptr
->offset
;
2357 size
= sd_ptr
->func
;
2358 bcmsdh_reg_write(bus
->sdh
, addr
, size
, sd_ptr
->value
);
2359 if (bcmsdh_regfail(bus
->sdh
))
2360 bcmerror
= BCME_SDIO_ERROR
;
2364 /* Same as above, but offset is not backplane
2366 case IOV_GVAL(IOV_SBREG
):
2371 memcpy(&sdreg
, params
, sizeof(sdreg
));
2373 addr
= SI_ENUM_BASE
+ sdreg
.offset
;
2375 int_val
= (s32
) bcmsdh_reg_read(bus
->sdh
, addr
, size
);
2376 if (bcmsdh_regfail(bus
->sdh
))
2377 bcmerror
= BCME_SDIO_ERROR
;
2378 memcpy(arg
, &int_val
, sizeof(s32
));
2382 case IOV_SVAL(IOV_SBREG
):
2387 memcpy(&sdreg
, params
, sizeof(sdreg
));
2389 addr
= SI_ENUM_BASE
+ sdreg
.offset
;
2391 bcmsdh_reg_write(bus
->sdh
, addr
, size
, sdreg
.value
);
2392 if (bcmsdh_regfail(bus
->sdh
))
2393 bcmerror
= BCME_SDIO_ERROR
;
2397 case IOV_GVAL(IOV_SDCIS
):
2401 strcat(arg
, "\nFunc 0\n");
2402 bcmsdh_cis_read(bus
->sdh
, 0x10,
2403 (u8
*) arg
+ strlen(arg
),
2404 SBSDIO_CIS_SIZE_LIMIT
);
2405 strcat(arg
, "\nFunc 1\n");
2406 bcmsdh_cis_read(bus
->sdh
, 0x11,
2407 (u8
*) arg
+ strlen(arg
),
2408 SBSDIO_CIS_SIZE_LIMIT
);
2409 strcat(arg
, "\nFunc 2\n");
2410 bcmsdh_cis_read(bus
->sdh
, 0x12,
2411 (u8
*) arg
+ strlen(arg
),
2412 SBSDIO_CIS_SIZE_LIMIT
);
2416 case IOV_GVAL(IOV_FORCEEVEN
):
2417 int_val
= (s32
) forcealign
;
2418 memcpy(arg
, &int_val
, val_size
);
2421 case IOV_SVAL(IOV_FORCEEVEN
):
2422 forcealign
= bool_val
;
2425 case IOV_GVAL(IOV_TXBOUND
):
2426 int_val
= (s32
) dhd_txbound
;
2427 memcpy(arg
, &int_val
, val_size
);
2430 case IOV_SVAL(IOV_TXBOUND
):
2431 dhd_txbound
= (uint
) int_val
;
2434 case IOV_GVAL(IOV_RXBOUND
):
2435 int_val
= (s32
) dhd_rxbound
;
2436 memcpy(arg
, &int_val
, val_size
);
2439 case IOV_SVAL(IOV_RXBOUND
):
2440 dhd_rxbound
= (uint
) int_val
;
2443 case IOV_GVAL(IOV_TXMINMAX
):
2444 int_val
= (s32
) dhd_txminmax
;
2445 memcpy(arg
, &int_val
, val_size
);
2448 case IOV_SVAL(IOV_TXMINMAX
):
2449 dhd_txminmax
= (uint
) int_val
;
2451 #endif /* DHD_DEBUG */
2454 case IOV_GVAL(IOV_EXTLOOP
):
2455 int_val
= (s32
) bus
->ext_loop
;
2456 memcpy(arg
, &int_val
, val_size
);
2459 case IOV_SVAL(IOV_EXTLOOP
):
2460 bus
->ext_loop
= bool_val
;
2463 case IOV_GVAL(IOV_PKTGEN
):
2464 bcmerror
= dhdsdio_pktgen_get(bus
, arg
);
2467 case IOV_SVAL(IOV_PKTGEN
):
2468 bcmerror
= dhdsdio_pktgen_set(bus
, arg
);
2472 case IOV_SVAL(IOV_DEVRESET
):
2473 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2475 __func__
, bool_val
, bus
->dhd
->dongle_reset
,
2476 bus
->dhd
->busstate
));
2478 dhd_bus_devreset(bus
->dhd
, (u8
) bool_val
);
2482 case IOV_GVAL(IOV_DEVRESET
):
2483 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__
));
2485 /* Get its status */
2486 int_val
= (bool) bus
->dhd
->dongle_reset
;
2487 memcpy(arg
, &int_val
, val_size
);
2492 bcmerror
= BCME_UNSUPPORTED
;
2497 if ((bus
->idletime
== DHD_IDLE_IMMEDIATE
) && !bus
->dpc_sched
) {
2498 bus
->activity
= false;
2499 dhdsdio_clkctl(bus
, CLK_NONE
, true);
2502 dhd_os_sdunlock(bus
->dhd
);
2504 if (actionid
== IOV_SVAL(IOV_DEVRESET
) && bool_val
== false)
2505 dhd_preinit_ioctls((dhd_pub_t
*) bus
->dhd
);
2510 static int dhdsdio_write_vars(dhd_bus_t
*bus
)
2518 char *nvram_ularray
;
2519 #endif /* DHD_DEBUG */
2521 /* Even if there are no vars are to be written, we still
2522 need to set the ramsize. */
2523 varsize
= bus
->varsz
? roundup(bus
->varsz
, 4) : 0;
2524 varaddr
= (bus
->ramsize
- 4) - varsize
;
2527 vbuffer
= kzalloc(varsize
, GFP_ATOMIC
);
2531 memcpy(vbuffer
, bus
->vars
, bus
->varsz
);
2533 /* Write the vars list */
2535 dhdsdio_membytes(bus
, true, varaddr
, vbuffer
, varsize
);
2537 /* Verify NVRAM bytes */
2538 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize
));
2539 nvram_ularray
= kmalloc(varsize
, GFP_ATOMIC
);
2543 /* Upload image to verify downloaded contents. */
2544 memset(nvram_ularray
, 0xaa, varsize
);
2546 /* Read the vars list to temp buffer for comparison */
2548 dhdsdio_membytes(bus
, false, varaddr
, nvram_ularray
,
2551 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2552 "0x%08x\n", __func__
, bcmerror
, varsize
, varaddr
));
2554 /* Compare the org NVRAM with the one read from RAM */
2555 if (memcmp(vbuffer
, nvram_ularray
, varsize
)) {
2556 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2559 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2562 kfree(nvram_ularray
);
2563 #endif /* DHD_DEBUG */
2568 /* adjust to the user specified RAM */
2569 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2570 bus
->orig_ramsize
, bus
->ramsize
));
2571 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr
, varsize
));
2572 varsize
= ((bus
->orig_ramsize
- 4) - varaddr
);
2575 * Determine the length token:
2576 * Varsize, converted to words, in lower 16-bits, checksum
2582 varsizew
= varsize
/ 4;
2583 varsizew
= (~varsizew
<< 16) | (varsizew
& 0x0000FFFF);
2584 varsizew
= cpu_to_le32(varsizew
);
2587 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize
,
2590 /* Write the length token to the last word */
2591 bcmerror
= dhdsdio_membytes(bus
, true, (bus
->orig_ramsize
- 4),
2592 (u8
*)&varsizew
, 4);
2597 static int dhdsdio_download_state(dhd_bus_t
*bus
, bool enter
)
2602 /* To enter download state, disable ARM and reset SOCRAM.
2603 * To exit download state, simply reset ARM (default is RAM boot).
2607 bus
->alp_only
= true;
2609 if (!(si_setcore(bus
->sih
, ARM7S_CORE_ID
, 0)) &&
2610 !(si_setcore(bus
->sih
, ARMCM3_CORE_ID
, 0))) {
2611 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__
));
2612 bcmerror
= BCME_ERROR
;
2616 si_core_disable(bus
->sih
, 0);
2617 if (bcmsdh_regfail(bus
->sdh
)) {
2618 bcmerror
= BCME_SDIO_ERROR
;
2622 if (!(si_setcore(bus
->sih
, SOCRAM_CORE_ID
, 0))) {
2623 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2625 bcmerror
= BCME_ERROR
;
2629 si_core_reset(bus
->sih
, 0, 0);
2630 if (bcmsdh_regfail(bus
->sdh
)) {
2631 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
2633 bcmerror
= BCME_SDIO_ERROR
;
2637 /* Clear the top bit of memory */
2640 dhdsdio_membytes(bus
, true, bus
->ramsize
- 4,
2644 if (!(si_setcore(bus
->sih
, SOCRAM_CORE_ID
, 0))) {
2645 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2647 bcmerror
= BCME_ERROR
;
2651 if (!si_iscoreup(bus
->sih
)) {
2652 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2654 bcmerror
= BCME_ERROR
;
2658 bcmerror
= dhdsdio_write_vars(bus
);
2660 DHD_ERROR(("%s: no vars written to RAM\n", __func__
));
2664 if (!si_setcore(bus
->sih
, PCMCIA_CORE_ID
, 0) &&
2665 !si_setcore(bus
->sih
, SDIOD_CORE_ID
, 0)) {
2666 DHD_ERROR(("%s: Can't change back to SDIO core?\n",
2668 bcmerror
= BCME_ERROR
;
2671 W_SDREG(0xFFFFFFFF, &bus
->regs
->intstatus
, retries
);
2673 if (!(si_setcore(bus
->sih
, ARM7S_CORE_ID
, 0)) &&
2674 !(si_setcore(bus
->sih
, ARMCM3_CORE_ID
, 0))) {
2675 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__
));
2676 bcmerror
= BCME_ERROR
;
2680 si_core_reset(bus
->sih
, 0, 0);
2681 if (bcmsdh_regfail(bus
->sdh
)) {
2682 DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
2684 bcmerror
= BCME_SDIO_ERROR
;
2688 /* Allow HT Clock now that the ARM is running. */
2689 bus
->alp_only
= false;
2691 bus
->dhd
->busstate
= DHD_BUS_LOAD
;
2695 /* Always return to SDIOD core */
2696 if (!si_setcore(bus
->sih
, PCMCIA_CORE_ID
, 0))
2697 si_setcore(bus
->sih
, SDIOD_CORE_ID
, 0);
2703 dhd_bus_iovar_op(dhd_pub_t
*dhdp
, const char *name
,
2704 void *params
, int plen
, void *arg
, int len
, bool set
)
2706 dhd_bus_t
*bus
= dhdp
->bus
;
2707 const bcm_iovar_t
*vi
= NULL
;
2712 DHD_TRACE(("%s: Enter\n", __func__
));
2717 /* Get MUST have return space */
2718 ASSERT(set
|| (arg
&& len
));
2720 /* Set does NOT take qualifiers */
2721 ASSERT(!set
|| (!params
&& !plen
));
2723 /* Look up var locally; if not found pass to host driver */
2724 vi
= bcm_iovar_lookup(dhdsdio_iovars
, name
);
2726 dhd_os_sdlock(bus
->dhd
);
2730 /* Turn on clock in case SD command needs backplane */
2731 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
2734 bcmsdh_iovar_op(bus
->sdh
, name
, params
, plen
, arg
, len
,
2737 /* Check for bus configuration changes of interest */
2739 /* If it was divisor change, read the new one */
2740 if (set
&& strcmp(name
, "sd_divisor") == 0) {
2741 if (bcmsdh_iovar_op(bus
->sdh
, "sd_divisor", NULL
, 0,
2742 &bus
->sd_divisor
, sizeof(s32
),
2743 false) != BCME_OK
) {
2744 bus
->sd_divisor
= -1;
2745 DHD_ERROR(("%s: fail on %s get\n", __func__
,
2748 DHD_INFO(("%s: noted %s update, value now %d\n",
2749 __func__
, name
, bus
->sd_divisor
));
2752 /* If it was a mode change, read the new one */
2753 if (set
&& strcmp(name
, "sd_mode") == 0) {
2754 if (bcmsdh_iovar_op(bus
->sdh
, "sd_mode", NULL
, 0,
2755 &bus
->sd_mode
, sizeof(s32
),
2756 false) != BCME_OK
) {
2758 DHD_ERROR(("%s: fail on %s get\n", __func__
,
2761 DHD_INFO(("%s: noted %s update, value now %d\n",
2762 __func__
, name
, bus
->sd_mode
));
2765 /* Similar check for blocksize change */
2766 if (set
&& strcmp(name
, "sd_blocksize") == 0) {
2769 (bus
->sdh
, "sd_blocksize", &fnum
, sizeof(s32
),
2770 &bus
->blocksize
, sizeof(s32
),
2771 false) != BCME_OK
) {
2773 DHD_ERROR(("%s: fail on %s get\n", __func__
,
2776 DHD_INFO(("%s: noted %s update, value now %d\n",
2777 __func__
, "sd_blocksize",
2781 bus
->roundup
= min(max_roundup
, bus
->blocksize
);
2783 if ((bus
->idletime
== DHD_IDLE_IMMEDIATE
) && !bus
->dpc_sched
) {
2784 bus
->activity
= false;
2785 dhdsdio_clkctl(bus
, CLK_NONE
, true);
2788 dhd_os_sdunlock(bus
->dhd
);
2792 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__
,
2793 name
, (set
? "set" : "get"), len
, plen
));
2795 /* set up 'params' pointer in case this is a set command so that
2796 * the convenience int and bool code can be common to set and get
2798 if (params
== NULL
) {
2803 if (vi
->type
== IOVT_VOID
)
2805 else if (vi
->type
== IOVT_BUFFER
)
2808 /* all other types are integer sized */
2809 val_size
= sizeof(int);
2811 actionid
= set
? IOV_SVAL(vi
->varid
) : IOV_GVAL(vi
->varid
);
2813 dhdsdio_doiovar(bus
, vi
, actionid
, name
, params
, plen
, arg
, len
,
2820 void dhd_bus_stop(struct dhd_bus
*bus
, bool enforce_mutex
)
2822 u32 local_hostintmask
;
2827 DHD_TRACE(("%s: Enter\n", __func__
));
2830 dhd_os_sdlock(bus
->dhd
);
2834 /* Enable clock for device interrupts */
2835 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
2837 /* Disable and clear interrupts at the chip level also */
2838 W_SDREG(0, &bus
->regs
->hostintmask
, retries
);
2839 local_hostintmask
= bus
->hostintmask
;
2840 bus
->hostintmask
= 0;
2842 /* Change our idea of bus state */
2843 bus
->dhd
->busstate
= DHD_BUS_DOWN
;
2845 /* Force clocks on backplane to be sure F2 interrupt propagates */
2847 bcmsdh_cfg_read(bus
->sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
2850 bcmsdh_cfg_write(bus
->sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
2851 (saveclk
| SBSDIO_FORCE_HT
), &err
);
2854 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2858 /* Turn off the bus (F2), free any pending packets */
2859 DHD_INTR(("%s: disable SDIO interrupts\n", __func__
));
2860 bcmsdh_intr_disable(bus
->sdh
);
2861 bcmsdh_cfg_write(bus
->sdh
, SDIO_FUNC_0
, SDIOD_CCCR_IOEN
,
2862 SDIO_FUNC_ENABLE_1
, NULL
);
2864 /* Clear any pending interrupts now that F2 is disabled */
2865 W_SDREG(local_hostintmask
, &bus
->regs
->intstatus
, retries
);
2867 /* Turn off the backplane clock (only) */
2868 dhdsdio_clkctl(bus
, CLK_SDONLY
, false);
2870 /* Clear the data packet queues */
2871 pktq_flush(&bus
->txq
, true);
2873 /* Clear any held glomming stuff */
2875 pkt_buf_free_skb(bus
->glomd
);
2878 pkt_buf_free_skb(bus
->glom
);
2880 bus
->glom
= bus
->glomd
= NULL
;
2882 /* Clear rx control and wake any waiters */
2884 dhd_os_ioctl_resp_wake(bus
->dhd
);
2886 /* Reset some F2 state stuff */
2887 bus
->rxskip
= false;
2888 bus
->tx_seq
= bus
->rx_seq
= 0;
2891 dhd_os_sdunlock(bus
->dhd
);
2894 int dhd_bus_init(dhd_pub_t
*dhdp
, bool enforce_mutex
)
2896 dhd_bus_t
*bus
= dhdp
->bus
;
2903 DHD_TRACE(("%s: Enter\n", __func__
));
2910 dhd_os_sdlock(bus
->dhd
);
2912 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2913 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
2914 if (bus
->clkstate
!= CLK_AVAIL
)
2917 /* Force clocks on backplane to be sure F2 interrupt propagates */
2919 bcmsdh_cfg_read(bus
->sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
2922 bcmsdh_cfg_write(bus
->sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
2923 (saveclk
| SBSDIO_FORCE_HT
), &err
);
2926 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2931 /* Enable function 2 (frame transfers) */
2932 W_SDREG((SDPCM_PROT_VERSION
<< SMB_DATA_VERSION_SHIFT
),
2933 &bus
->regs
->tosbmailboxdata
, retries
);
2934 enable
= (SDIO_FUNC_ENABLE_1
| SDIO_FUNC_ENABLE_2
);
2936 bcmsdh_cfg_write(bus
->sdh
, SDIO_FUNC_0
, SDIOD_CCCR_IOEN
, enable
, NULL
);
2938 /* Give the dongle some time to do its thing and set IOR2 */
2939 dhd_timeout_start(&tmo
, DHD_WAIT_F2RDY
* 1000);
2942 while (ready
!= enable
&& !dhd_timeout_expired(&tmo
))
2944 bcmsdh_cfg_read(bus
->sdh
, SDIO_FUNC_0
, SDIOD_CCCR_IORDY
,
2947 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
2948 __func__
, enable
, ready
, tmo
.elapsed
));
2950 /* If F2 successfully enabled, set core and enable interrupts */
2951 if (ready
== enable
) {
2952 /* Make sure we're talking to the core. */
2953 bus
->regs
= si_setcore(bus
->sih
, PCMCIA_CORE_ID
, 0);
2955 bus
->regs
= si_setcore(bus
->sih
, SDIOD_CORE_ID
, 0);
2957 /* Set up the interrupt mask and enable interrupts */
2958 bus
->hostintmask
= HOSTINTMASK
;
2959 W_SDREG(bus
->hostintmask
, &bus
->regs
->hostintmask
, retries
);
2961 bcmsdh_cfg_write(bus
->sdh
, SDIO_FUNC_1
, SBSDIO_WATERMARK
,
2962 (u8
) watermark
, &err
);
2964 /* Set bus state according to enable result */
2965 dhdp
->busstate
= DHD_BUS_DATA
;
2967 /* bcmsdh_intr_unmask(bus->sdh); */
2969 bus
->intdis
= false;
2971 DHD_INTR(("%s: enable SDIO device interrupts\n",
2973 bcmsdh_intr_enable(bus
->sdh
);
2975 DHD_INTR(("%s: disable SDIO interrupts\n", __func__
));
2976 bcmsdh_intr_disable(bus
->sdh
);
2982 /* Disable F2 again */
2983 enable
= SDIO_FUNC_ENABLE_1
;
2984 bcmsdh_cfg_write(bus
->sdh
, SDIO_FUNC_0
, SDIOD_CCCR_IOEN
, enable
,
2988 /* Restore previous clock setting */
2989 bcmsdh_cfg_write(bus
->sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
2992 /* If we didn't come up, turn off backplane clock */
2993 if (dhdp
->busstate
!= DHD_BUS_DATA
)
2994 dhdsdio_clkctl(bus
, CLK_NONE
, false);
2998 dhd_os_sdunlock(bus
->dhd
);
3003 static void dhdsdio_rxfail(dhd_bus_t
*bus
, bool abort
, bool rtx
)
3005 bcmsdh_info_t
*sdh
= bus
->sdh
;
3006 sdpcmd_regs_t
*regs
= bus
->regs
;
3012 DHD_ERROR(("%s: %sterminate frame%s\n", __func__
,
3013 (abort
? "abort command, " : ""),
3014 (rtx
? ", send NAK" : "")));
3017 bcmsdh_abort(sdh
, SDIO_FUNC_2
);
3019 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_FRAMECTRL
, SFC_RF_TERM
,
3023 /* Wait until the packet has been flushed (device/FIFO stable) */
3024 for (lastrbc
= retries
= 0xffff; retries
> 0; retries
--) {
3025 hi
= bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_RFRAMEBCHI
,
3027 lo
= bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_RFRAMEBCLO
,
3029 bus
->f1regdata
+= 2;
3031 if ((hi
== 0) && (lo
== 0))
3034 if ((hi
> (lastrbc
>> 8)) && (lo
> (lastrbc
& 0x00ff))) {
3035 DHD_ERROR(("%s: count growing: last 0x%04x now "
3037 __func__
, lastrbc
, ((hi
<< 8) + lo
)));
3039 lastrbc
= (hi
<< 8) + lo
;
3043 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3044 __func__
, lastrbc
));
3046 DHD_INFO(("%s: flush took %d iterations\n", __func__
,
3047 (0xffff - retries
)));
3052 W_SDREG(SMB_NAK
, ®s
->tosbmailbox
, retries
);
3054 if (retries
<= retry_limit
)
3058 /* Clear partial in any case */
3061 /* If we can't reach the device, signal failure */
3062 if (err
|| bcmsdh_regfail(sdh
))
3063 bus
->dhd
->busstate
= DHD_BUS_DOWN
;
3067 dhdsdio_read_control(dhd_bus_t
*bus
, u8
*hdr
, uint len
, uint doff
)
3069 bcmsdh_info_t
*sdh
= bus
->sdh
;
3074 DHD_TRACE(("%s: Enter\n", __func__
));
3076 /* Control data already received in aligned rxctl */
3077 if ((bus
->bus
== SPI_BUS
) && (!bus
->usebufpool
))
3081 /* Set rxctl for frame (w/optional alignment) */
3082 bus
->rxctl
= bus
->rxbuf
;
3084 bus
->rxctl
+= firstread
;
3085 pad
= ((unsigned long)bus
->rxctl
% DHD_SDALIGN
);
3087 bus
->rxctl
+= (DHD_SDALIGN
- pad
);
3088 bus
->rxctl
-= firstread
;
3090 ASSERT(bus
->rxctl
>= bus
->rxbuf
);
3092 /* Copy the already-read portion over */
3093 memcpy(bus
->rxctl
, hdr
, firstread
);
3094 if (len
<= firstread
)
3097 /* Copy the full data pkt in gSPI case and process ioctl. */
3098 if (bus
->bus
== SPI_BUS
) {
3099 memcpy(bus
->rxctl
, hdr
, len
);
3103 /* Raise rdlen to next SDIO block to avoid tail command */
3104 rdlen
= len
- firstread
;
3105 if (bus
->roundup
&& bus
->blocksize
&& (rdlen
> bus
->blocksize
)) {
3106 pad
= bus
->blocksize
- (rdlen
% bus
->blocksize
);
3107 if ((pad
<= bus
->roundup
) && (pad
< bus
->blocksize
) &&
3108 ((len
+ pad
) < bus
->dhd
->maxctl
))
3110 } else if (rdlen
% DHD_SDALIGN
) {
3111 rdlen
+= DHD_SDALIGN
- (rdlen
% DHD_SDALIGN
);
3114 /* Satisfy length-alignment requirements */
3115 if (forcealign
&& (rdlen
& (ALIGNMENT
- 1)))
3116 rdlen
= roundup(rdlen
, ALIGNMENT
);
3118 /* Drop if the read is too big or it exceeds our maximum */
3119 if ((rdlen
+ firstread
) > bus
->dhd
->maxctl
) {
3120 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3121 __func__
, rdlen
, bus
->dhd
->maxctl
));
3122 bus
->dhd
->rx_errors
++;
3123 dhdsdio_rxfail(bus
, false, false);
3127 if ((len
- doff
) > bus
->dhd
->maxctl
) {
3128 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3130 __func__
, len
, (len
- doff
), bus
->dhd
->maxctl
));
3131 bus
->dhd
->rx_errors
++;
3133 dhdsdio_rxfail(bus
, false, false);
3137 /* Read remainder of frame body into the rxctl buffer */
3139 dhd_bcmsdh_recv_buf(bus
, bcmsdh_cur_sbwad(sdh
), SDIO_FUNC_2
, F2SYNC
,
3140 (bus
->rxctl
+ firstread
), rdlen
, NULL
, NULL
,
3143 ASSERT(sdret
!= BCME_PENDING
);
3145 /* Control frame failures need retransmission */
3147 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3148 __func__
, rdlen
, sdret
));
3149 bus
->rxc_errors
++; /* dhd.rx_ctlerrs is higher level */
3150 dhdsdio_rxfail(bus
, true, true);
3157 if (DHD_BYTES_ON() && DHD_CTL_ON())
3158 prhex("RxCtrl", bus
->rxctl
, len
);
3161 /* Point to valid data and indicate its length */
3163 bus
->rxlen
= len
- doff
;
3166 /* Awake any waiters */
3167 dhd_os_ioctl_resp_wake(bus
->dhd
);
3170 static u8
dhdsdio_rxglom(dhd_bus_t
*bus
, u8 rxseq
)
3176 struct sk_buff
*pfirst
, *plast
, *pnext
, *save_pfirst
;
3179 u8 chan
, seq
, doff
, sfdoff
;
3183 bool usechain
= bus
->use_rxchain
;
3185 /* If packets, issue read(s) and send up packet chain */
3186 /* Return sequence numbers consumed? */
3188 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus
->glomd
,
3191 /* If there's a descriptor, generate the packet chain */
3193 dhd_os_sdlock_rxq(bus
->dhd
);
3195 pfirst
= plast
= pnext
= NULL
;
3196 dlen
= (u16
) (bus
->glomd
->len
);
3197 dptr
= bus
->glomd
->data
;
3198 if (!dlen
|| (dlen
& 1)) {
3199 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3204 for (totlen
= num
= 0; dlen
; num
++) {
3205 /* Get (and move past) next length */
3206 sublen
= get_unaligned_le16(dptr
);
3207 dlen
-= sizeof(u16
);
3208 dptr
+= sizeof(u16
);
3209 if ((sublen
< SDPCM_HDRLEN
) ||
3210 ((num
== 0) && (sublen
< (2 * SDPCM_HDRLEN
)))) {
3211 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3212 __func__
, num
, sublen
));
3216 if (sublen
% DHD_SDALIGN
) {
3217 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3218 __func__
, sublen
, DHD_SDALIGN
));
3223 /* For last frame, adjust read len so total
3224 is a block multiple */
3227 (roundup(totlen
, bus
->blocksize
) - totlen
);
3228 totlen
= roundup(totlen
, bus
->blocksize
);
3231 /* Allocate/chain packet for next subframe */
3232 pnext
= pkt_buf_get_skb(sublen
+ DHD_SDALIGN
);
3233 if (pnext
== NULL
) {
3234 DHD_ERROR(("%s: pkt_buf_get_skb failed, num %d len %d\n",
3235 __func__
, num
, sublen
));
3238 ASSERT(!(pnext
->prev
));
3241 pfirst
= plast
= pnext
;
3244 plast
->next
= pnext
;
3248 /* Adhere to start alignment requirements */
3249 PKTALIGN(pnext
, sublen
, DHD_SDALIGN
);
3252 /* If all allocations succeeded, save packet chain
3255 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3256 "subframes\n", __func__
, totlen
, num
));
3257 if (DHD_GLOM_ON() && bus
->nextlen
) {
3258 if (totlen
!= bus
->nextlen
) {
3259 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3260 __func__
, bus
->nextlen
,
3265 pfirst
= pnext
= NULL
;
3268 pkt_buf_free_skb(pfirst
);
3273 /* Done with descriptor packet */
3274 pkt_buf_free_skb(bus
->glomd
);
3278 dhd_os_sdunlock_rxq(bus
->dhd
);
3281 /* Ok -- either we just generated a packet chain,
3282 or had one from before */
3284 if (DHD_GLOM_ON()) {
3285 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3287 for (pnext
= bus
->glom
; pnext
; pnext
= pnext
->next
) {
3288 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3289 pnext
, (u8
*) (pnext
->data
),
3290 pnext
->len
, pnext
->len
));
3295 dlen
= (u16
) pkttotlen(pfirst
);
3297 /* Do an SDIO read for the superframe. Configurable iovar to
3298 * read directly into the chained packet, or allocate a large
3299 * packet and and copy into the chain.
3302 errcode
= dhd_bcmsdh_recv_buf(bus
,
3304 (bus
->sdh
), SDIO_FUNC_2
,
3306 (u8
*) pfirst
->data
,
3307 dlen
, pfirst
, NULL
, NULL
);
3308 } else if (bus
->dataptr
) {
3309 errcode
= dhd_bcmsdh_recv_buf(bus
,
3311 (bus
->sdh
), SDIO_FUNC_2
,
3312 F2SYNC
, bus
->dataptr
,
3313 dlen
, NULL
, NULL
, NULL
);
3315 (u16
) pktfrombuf(pfirst
, 0, dlen
,
3317 if (sublen
!= dlen
) {
3318 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3319 __func__
, dlen
, sublen
));
3324 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3329 ASSERT(errcode
!= BCME_PENDING
);
3331 /* On failure, kill the superframe, allow a couple retries */
3333 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3334 __func__
, dlen
, errcode
));
3335 bus
->dhd
->rx_errors
++;
3337 if (bus
->glomerr
++ < 3) {
3338 dhdsdio_rxfail(bus
, true, true);
3341 dhdsdio_rxfail(bus
, true, false);
3342 dhd_os_sdlock_rxq(bus
->dhd
);
3343 pkt_buf_free_skb(bus
->glom
);
3344 dhd_os_sdunlock_rxq(bus
->dhd
);
3351 if (DHD_GLOM_ON()) {
3352 prhex("SUPERFRAME", pfirst
->data
,
3353 min_t(int, pfirst
->len
, 48));
3357 /* Validate the superframe header */
3358 dptr
= (u8
*) (pfirst
->data
);
3359 sublen
= get_unaligned_le16(dptr
);
3360 check
= get_unaligned_le16(dptr
+ sizeof(u16
));
3362 chan
= SDPCM_PACKET_CHANNEL(&dptr
[SDPCM_FRAMETAG_LEN
]);
3363 seq
= SDPCM_PACKET_SEQUENCE(&dptr
[SDPCM_FRAMETAG_LEN
]);
3364 bus
->nextlen
= dptr
[SDPCM_FRAMETAG_LEN
+ SDPCM_NEXTLEN_OFFSET
];
3365 if ((bus
->nextlen
<< 4) > MAX_RX_DATASZ
) {
3366 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3367 __func__
, bus
->nextlen
, seq
));
3370 doff
= SDPCM_DOFFSET_VALUE(&dptr
[SDPCM_FRAMETAG_LEN
]);
3371 txmax
= SDPCM_WINDOW_VALUE(&dptr
[SDPCM_FRAMETAG_LEN
]);
3374 if ((u16
)~(sublen
^ check
)) {
3375 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3376 "0x%04x/0x%04x\n", __func__
, sublen
, check
));
3378 } else if (roundup(sublen
, bus
->blocksize
) != dlen
) {
3379 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3380 "0x%04x, expect 0x%04x\n",
3382 roundup(sublen
, bus
->blocksize
), dlen
));
3384 } else if (SDPCM_PACKET_CHANNEL(&dptr
[SDPCM_FRAMETAG_LEN
]) !=
3385 SDPCM_GLOM_CHANNEL
) {
3386 DHD_ERROR(("%s (superframe): bad channel %d\n",
3388 SDPCM_PACKET_CHANNEL(&dptr
3389 [SDPCM_FRAMETAG_LEN
])));
3391 } else if (SDPCM_GLOMDESC(&dptr
[SDPCM_FRAMETAG_LEN
])) {
3392 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3395 } else if ((doff
< SDPCM_HDRLEN
) ||
3396 (doff
> (pfirst
->len
- SDPCM_HDRLEN
))) {
3397 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3399 __func__
, doff
, sublen
,
3400 pfirst
->len
, SDPCM_HDRLEN
));
3404 /* Check sequence number of superframe SW header */
3406 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3407 __func__
, seq
, rxseq
));
3412 /* Check window for sanity */
3413 if ((u8
) (txmax
- bus
->tx_seq
) > 0x40) {
3414 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3415 __func__
, txmax
, bus
->tx_seq
));
3416 txmax
= bus
->tx_seq
+ 2;
3418 bus
->tx_max
= txmax
;
3420 /* Remove superframe header, remember offset */
3421 skb_pull(pfirst
, doff
);
3424 /* Validate all the subframe headers */
3425 for (num
= 0, pnext
= pfirst
; pnext
&& !errcode
;
3426 num
++, pnext
= pnext
->next
) {
3427 dptr
= (u8
*) (pnext
->data
);
3428 dlen
= (u16
) (pnext
->len
);
3429 sublen
= get_unaligned_le16(dptr
);
3430 check
= get_unaligned_le16(dptr
+ sizeof(u16
));
3431 chan
= SDPCM_PACKET_CHANNEL(&dptr
[SDPCM_FRAMETAG_LEN
]);
3432 doff
= SDPCM_DOFFSET_VALUE(&dptr
[SDPCM_FRAMETAG_LEN
]);
3435 prhex("subframe", dptr
, 32);
3438 if ((u16
)~(sublen
^ check
)) {
3439 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3440 "len/check 0x%04x/0x%04x\n",
3441 __func__
, num
, sublen
, check
));
3443 } else if ((sublen
> dlen
) || (sublen
< SDPCM_HDRLEN
)) {
3444 DHD_ERROR(("%s (subframe %d): length mismatch: "
3445 "len 0x%04x, expect 0x%04x\n",
3446 __func__
, num
, sublen
, dlen
));
3448 } else if ((chan
!= SDPCM_DATA_CHANNEL
) &&
3449 (chan
!= SDPCM_EVENT_CHANNEL
)) {
3450 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3451 __func__
, num
, chan
));
3453 } else if ((doff
< SDPCM_HDRLEN
) || (doff
> sublen
)) {
3454 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3455 __func__
, num
, doff
, sublen
,
3462 /* Terminate frame on error, request
3464 if (bus
->glomerr
++ < 3) {
3465 /* Restore superframe header space */
3466 skb_push(pfirst
, sfdoff
);
3467 dhdsdio_rxfail(bus
, true, true);
3470 dhdsdio_rxfail(bus
, true, false);
3471 dhd_os_sdlock_rxq(bus
->dhd
);
3472 pkt_buf_free_skb(bus
->glom
);
3473 dhd_os_sdunlock_rxq(bus
->dhd
);
3481 /* Basic SD framing looks ok - process each packet (header) */
3482 save_pfirst
= pfirst
;
3486 dhd_os_sdlock_rxq(bus
->dhd
);
3487 for (num
= 0; pfirst
; rxseq
++, pfirst
= pnext
) {
3488 pnext
= pfirst
->next
;
3489 pfirst
->next
= NULL
;
3491 dptr
= (u8
*) (pfirst
->data
);
3492 sublen
= get_unaligned_le16(dptr
);
3493 chan
= SDPCM_PACKET_CHANNEL(&dptr
[SDPCM_FRAMETAG_LEN
]);
3494 seq
= SDPCM_PACKET_SEQUENCE(&dptr
[SDPCM_FRAMETAG_LEN
]);
3495 doff
= SDPCM_DOFFSET_VALUE(&dptr
[SDPCM_FRAMETAG_LEN
]);
3497 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3499 __func__
, num
, pfirst
, pfirst
->data
,
3500 pfirst
->len
, sublen
, chan
, seq
));
3502 ASSERT((chan
== SDPCM_DATA_CHANNEL
)
3503 || (chan
== SDPCM_EVENT_CHANNEL
));
3506 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3507 __func__
, seq
, rxseq
));
3512 if (DHD_BYTES_ON() && DHD_DATA_ON())
3513 prhex("Rx Subframe Data", dptr
, dlen
);
3516 __skb_trim(pfirst
, sublen
);
3517 skb_pull(pfirst
, doff
);
3519 if (pfirst
->len
== 0) {
3520 pkt_buf_free_skb(pfirst
);
3522 plast
->next
= pnext
;
3524 ASSERT(save_pfirst
== pfirst
);
3525 save_pfirst
= pnext
;
3528 } else if (dhd_prot_hdrpull(bus
->dhd
, &ifidx
, pfirst
) !=
3530 DHD_ERROR(("%s: rx protocol error\n",
3532 bus
->dhd
->rx_errors
++;
3533 pkt_buf_free_skb(pfirst
);
3535 plast
->next
= pnext
;
3537 ASSERT(save_pfirst
== pfirst
);
3538 save_pfirst
= pnext
;
3543 /* this packet will go up, link back into
3544 chain and count it */
3545 pfirst
->next
= pnext
;
3550 if (DHD_GLOM_ON()) {
3551 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3553 __func__
, num
, pfirst
, pfirst
->data
,
3554 pfirst
->len
, pfirst
->next
,
3556 prhex("", (u8
*) pfirst
->data
,
3557 min_t(int, pfirst
->len
, 32));
3559 #endif /* DHD_DEBUG */
3561 dhd_os_sdunlock_rxq(bus
->dhd
);
3563 dhd_os_sdunlock(bus
->dhd
);
3564 dhd_rx_frame(bus
->dhd
, ifidx
, save_pfirst
, num
);
3565 dhd_os_sdlock(bus
->dhd
);
3568 bus
->rxglomframes
++;
3569 bus
->rxglompkts
+= num
;
3574 /* Return true if there may be more frames to read */
3575 static uint
dhdsdio_readframes(dhd_bus_t
*bus
, uint maxframes
, bool *finished
)
3577 bcmsdh_info_t
*sdh
= bus
->sdh
;
3579 u16 len
, check
; /* Extracted hardware header fields */
3580 u8 chan
, seq
, doff
; /* Extracted software header fields */
3581 u8 fcbits
; /* Extracted fcbits from software header */
3584 struct sk_buff
*pkt
; /* Packet for event or data frames */
3585 u16 pad
; /* Number of pad bytes to read */
3586 u16 rdlen
; /* Total number of bytes to read */
3587 u8 rxseq
; /* Next sequence number to expect */
3588 uint rxleft
= 0; /* Remaining number of frames allowed */
3589 int sdret
; /* Return code from bcmsdh calls */
3590 u8 txmax
; /* Maximum tx sequence offered */
3591 bool len_consistent
; /* Result of comparing readahead len and
3595 uint rxcount
= 0; /* Total frames read */
3597 #if defined(DHD_DEBUG) || defined(SDTEST)
3598 bool sdtest
= false; /* To limit message spew from test mode */
3601 DHD_TRACE(("%s: Enter\n", __func__
));
3606 /* Allow pktgen to override maxframes */
3607 if (bus
->pktgen_count
&& (bus
->pktgen_mode
== DHD_PKTGEN_RECV
)) {
3608 maxframes
= bus
->pktgen_count
;
3613 /* Not finished unless we encounter no more frames indication */
3616 for (rxseq
= bus
->rx_seq
, rxleft
= maxframes
;
3617 !bus
->rxskip
&& rxleft
&& bus
->dhd
->busstate
!= DHD_BUS_DOWN
;
3618 rxseq
++, rxleft
--) {
3620 /* Handle glomming separately */
3621 if (bus
->glom
|| bus
->glomd
) {
3623 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3624 __func__
, bus
->glomd
, bus
->glom
));
3625 cnt
= dhdsdio_rxglom(bus
, rxseq
);
3626 DHD_GLOM(("%s: rxglom returned %d\n", __func__
, cnt
));
3628 rxleft
= (rxleft
> cnt
) ? (rxleft
- cnt
) : 1;
3632 /* Try doing single read if we can */
3633 if (dhd_readahead
&& bus
->nextlen
) {
3634 u16 nextlen
= bus
->nextlen
;
3637 if (bus
->bus
== SPI_BUS
) {
3638 rdlen
= len
= nextlen
;
3640 rdlen
= len
= nextlen
<< 4;
3642 /* Pad read to blocksize for efficiency */
3643 if (bus
->roundup
&& bus
->blocksize
3644 && (rdlen
> bus
->blocksize
)) {
3647 (rdlen
% bus
->blocksize
);
3648 if ((pad
<= bus
->roundup
)
3649 && (pad
< bus
->blocksize
)
3650 && ((rdlen
+ pad
+ firstread
) <
3653 } else if (rdlen
% DHD_SDALIGN
) {
3655 DHD_SDALIGN
- (rdlen
% DHD_SDALIGN
);
3659 /* We use bus->rxctl buffer in WinXP for initial
3660 * control pkt receives.
3661 * Later we use buffer-poll for data as well
3662 * as control packets.
3663 * This is required because dhd receives full
3664 * frame in gSPI unlike SDIO.
3665 * After the frame is received we have to
3666 * distinguish whether it is data
3667 * or non-data frame.
3669 /* Allocate a packet buffer */
3670 dhd_os_sdlock_rxq(bus
->dhd
);
3671 pkt
= pkt_buf_get_skb(rdlen
+ DHD_SDALIGN
);
3673 if (bus
->bus
== SPI_BUS
) {
3674 bus
->usebufpool
= false;
3675 bus
->rxctl
= bus
->rxbuf
;
3677 bus
->rxctl
+= firstread
;
3678 pad
= ((unsigned long)bus
->rxctl
%
3682 (DHD_SDALIGN
- pad
);
3683 bus
->rxctl
-= firstread
;
3685 ASSERT(bus
->rxctl
>= bus
->rxbuf
);
3687 /* Read the entire frame */
3688 sdret
= dhd_bcmsdh_recv_buf(bus
,
3697 ASSERT(sdret
!= BCME_PENDING
);
3699 /* Control frame failures need
3702 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3705 /* dhd.rx_ctlerrs is higher */
3707 dhd_os_sdunlock_rxq(bus
->dhd
);
3708 dhdsdio_rxfail(bus
, true,
3716 request rtx of events */
3717 DHD_ERROR(("%s (nextlen): pkt_buf_get_skb failed: len %d rdlen %d " "expected rxseq %d\n",
3718 __func__
, len
, rdlen
, rxseq
));
3719 /* Just go try again w/normal
3721 dhd_os_sdunlock_rxq(bus
->dhd
);
3725 if (bus
->bus
== SPI_BUS
)
3726 bus
->usebufpool
= true;
3728 ASSERT(!(pkt
->prev
));
3729 PKTALIGN(pkt
, rdlen
, DHD_SDALIGN
);
3730 rxbuf
= (u8
*) (pkt
->data
);
3731 /* Read the entire frame */
3733 dhd_bcmsdh_recv_buf(bus
,
3734 bcmsdh_cur_sbwad(sdh
),
3735 SDIO_FUNC_2
, F2SYNC
,
3736 rxbuf
, rdlen
, pkt
, NULL
,
3739 ASSERT(sdret
!= BCME_PENDING
);
3742 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3743 __func__
, rdlen
, sdret
));
3744 pkt_buf_free_skb(pkt
);
3745 bus
->dhd
->rx_errors
++;
3746 dhd_os_sdunlock_rxq(bus
->dhd
);
3747 /* Force retry w/normal header read.
3748 * Don't attempt NAK for
3751 dhdsdio_rxfail(bus
, true,
3758 dhd_os_sdunlock_rxq(bus
->dhd
);
3760 /* Now check the header */
3761 memcpy(bus
->rxhdr
, rxbuf
, SDPCM_HDRLEN
);
3763 /* Extract hardware header fields */
3764 len
= get_unaligned_le16(bus
->rxhdr
);
3765 check
= get_unaligned_le16(bus
->rxhdr
+ sizeof(u16
));
3767 /* All zeros means readahead info was bad */
3768 if (!(len
| check
)) {
3769 DHD_INFO(("%s (nextlen): read zeros in HW "
3770 "header???\n", __func__
));
3771 dhd_os_sdlock_rxq(bus
->dhd
);
3773 dhd_os_sdunlock_rxq(bus
->dhd
);
3774 GSPI_PR55150_BAILOUT
;
3778 /* Validate check bytes */
3779 if ((u16
)~(len
^ check
)) {
3780 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
3781 __func__
, nextlen
, len
, check
));
3782 dhd_os_sdlock_rxq(bus
->dhd
);
3784 dhd_os_sdunlock_rxq(bus
->dhd
);
3786 dhdsdio_rxfail(bus
, false, false);
3787 GSPI_PR55150_BAILOUT
;
3791 /* Validate frame length */
3792 if (len
< SDPCM_HDRLEN
) {
3793 DHD_ERROR(("%s (nextlen): HW hdr length "
3794 "invalid: %d\n", __func__
, len
));
3795 dhd_os_sdlock_rxq(bus
->dhd
);
3797 dhd_os_sdunlock_rxq(bus
->dhd
);
3798 GSPI_PR55150_BAILOUT
;
3802 /* Check for consistency withreadahead info */
3803 len_consistent
= (nextlen
!= (roundup(len
, 16) >> 4));
3804 if (len_consistent
) {
3805 /* Mismatch, force retry w/normal
3806 header (may be >4K) */
3807 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
3809 len
, roundup(len
, 16), rxseq
));
3810 dhd_os_sdlock_rxq(bus
->dhd
);
3812 dhd_os_sdunlock_rxq(bus
->dhd
);
3813 dhdsdio_rxfail(bus
, true,
3815 SPI_BUS
) ? false : true);
3816 GSPI_PR55150_BAILOUT
;
3820 /* Extract software header fields */
3822 SDPCM_PACKET_CHANNEL(&bus
->rxhdr
3823 [SDPCM_FRAMETAG_LEN
]);
3825 SDPCM_PACKET_SEQUENCE(&bus
->rxhdr
3826 [SDPCM_FRAMETAG_LEN
]);
3828 SDPCM_DOFFSET_VALUE(&bus
->rxhdr
3829 [SDPCM_FRAMETAG_LEN
]);
3831 SDPCM_WINDOW_VALUE(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
3834 bus
->rxhdr
[SDPCM_FRAMETAG_LEN
+
3835 SDPCM_NEXTLEN_OFFSET
];
3836 if ((bus
->nextlen
<< 4) > MAX_RX_DATASZ
) {
3837 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3838 __func__
, bus
->nextlen
, seq
));
3842 bus
->dhd
->rx_readahead_cnt
++;
3843 /* Handle Flow Control */
3845 SDPCM_FCMASK_VALUE(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
3848 if (~bus
->flowcontrol
& fcbits
) {
3852 if (bus
->flowcontrol
& ~fcbits
) {
3859 bus
->flowcontrol
= fcbits
;
3862 /* Check and update sequence number */
3864 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3865 "%d\n", __func__
, seq
, rxseq
));
3870 /* Check window for sanity */
3871 if ((u8
) (txmax
- bus
->tx_seq
) > 0x40) {
3872 DHD_ERROR(("%s: got unlikely tx max %d with "
3874 __func__
, txmax
, bus
->tx_seq
));
3875 txmax
= bus
->tx_seq
+ 2;
3877 bus
->tx_max
= txmax
;
3880 if (DHD_BYTES_ON() && DHD_DATA_ON())
3881 prhex("Rx Data", rxbuf
, len
);
3882 else if (DHD_HDRS_ON())
3883 prhex("RxHdr", bus
->rxhdr
, SDPCM_HDRLEN
);
3886 if (chan
== SDPCM_CONTROL_CHANNEL
) {
3887 if (bus
->bus
== SPI_BUS
) {
3888 dhdsdio_read_control(bus
, rxbuf
, len
,
3890 if (bus
->usebufpool
) {
3891 dhd_os_sdlock_rxq(bus
->dhd
);
3892 pkt_buf_free_skb(pkt
);
3893 dhd_os_sdunlock_rxq(bus
->dhd
);
3897 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3899 /* Force retry w/normal header read */
3901 dhdsdio_rxfail(bus
, false, true);
3902 dhd_os_sdlock_rxq(bus
->dhd
);
3904 dhd_os_sdunlock_rxq(bus
->dhd
);
3909 if ((bus
->bus
== SPI_BUS
) && !bus
->usebufpool
) {
3910 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3915 /* Validate data offset */
3916 if ((doff
< SDPCM_HDRLEN
) || (doff
> len
)) {
3917 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3918 __func__
, doff
, len
, SDPCM_HDRLEN
));
3919 dhd_os_sdlock_rxq(bus
->dhd
);
3921 dhd_os_sdunlock_rxq(bus
->dhd
);
3923 dhdsdio_rxfail(bus
, false, false);
3927 /* All done with this one -- now deliver the packet */
3930 /* gSPI frames should not be handled in fractions */
3931 if (bus
->bus
== SPI_BUS
)
3934 /* Read frame header (hardware and software) */
3936 dhd_bcmsdh_recv_buf(bus
, bcmsdh_cur_sbwad(sdh
), SDIO_FUNC_2
,
3937 F2SYNC
, bus
->rxhdr
, firstread
, NULL
,
3940 ASSERT(sdret
!= BCME_PENDING
);
3943 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__
,
3946 dhdsdio_rxfail(bus
, true, true);
3950 if (DHD_BYTES_ON() || DHD_HDRS_ON())
3951 prhex("RxHdr", bus
->rxhdr
, SDPCM_HDRLEN
);
3954 /* Extract hardware header fields */
3955 len
= get_unaligned_le16(bus
->rxhdr
);
3956 check
= get_unaligned_le16(bus
->rxhdr
+ sizeof(u16
));
3958 /* All zeros means no more frames */
3959 if (!(len
| check
)) {
3964 /* Validate check bytes */
3965 if ((u16
) ~(len
^ check
)) {
3966 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
3967 __func__
, len
, check
));
3969 dhdsdio_rxfail(bus
, false, false);
3973 /* Validate frame length */
3974 if (len
< SDPCM_HDRLEN
) {
3975 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
3980 /* Extract software header fields */
3981 chan
= SDPCM_PACKET_CHANNEL(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
3982 seq
= SDPCM_PACKET_SEQUENCE(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
3983 doff
= SDPCM_DOFFSET_VALUE(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
3984 txmax
= SDPCM_WINDOW_VALUE(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
3986 /* Validate data offset */
3987 if ((doff
< SDPCM_HDRLEN
) || (doff
> len
)) {
3988 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
3990 __func__
, doff
, len
, SDPCM_HDRLEN
, seq
));
3993 dhdsdio_rxfail(bus
, false, false);
3997 /* Save the readahead length if there is one */
3999 bus
->rxhdr
[SDPCM_FRAMETAG_LEN
+ SDPCM_NEXTLEN_OFFSET
];
4000 if ((bus
->nextlen
<< 4) > MAX_RX_DATASZ
) {
4001 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4003 __func__
, bus
->nextlen
, seq
));
4007 /* Handle Flow Control */
4008 fcbits
= SDPCM_FCMASK_VALUE(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
]);
4011 if (~bus
->flowcontrol
& fcbits
) {
4015 if (bus
->flowcontrol
& ~fcbits
) {
4022 bus
->flowcontrol
= fcbits
;
4025 /* Check and update sequence number */
4027 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__
,
4033 /* Check window for sanity */
4034 if ((u8
) (txmax
- bus
->tx_seq
) > 0x40) {
4035 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4036 __func__
, txmax
, bus
->tx_seq
));
4037 txmax
= bus
->tx_seq
+ 2;
4039 bus
->tx_max
= txmax
;
4041 /* Call a separate function for control frames */
4042 if (chan
== SDPCM_CONTROL_CHANNEL
) {
4043 dhdsdio_read_control(bus
, bus
->rxhdr
, len
, doff
);
4047 ASSERT((chan
== SDPCM_DATA_CHANNEL
)
4048 || (chan
== SDPCM_EVENT_CHANNEL
)
4049 || (chan
== SDPCM_TEST_CHANNEL
)
4050 || (chan
== SDPCM_GLOM_CHANNEL
));
4052 /* Length to read */
4053 rdlen
= (len
> firstread
) ? (len
- firstread
) : 0;
4055 /* May pad read to blocksize for efficiency */
4056 if (bus
->roundup
&& bus
->blocksize
&&
4057 (rdlen
> bus
->blocksize
)) {
4058 pad
= bus
->blocksize
- (rdlen
% bus
->blocksize
);
4059 if ((pad
<= bus
->roundup
) && (pad
< bus
->blocksize
) &&
4060 ((rdlen
+ pad
+ firstread
) < MAX_RX_DATASZ
))
4062 } else if (rdlen
% DHD_SDALIGN
) {
4063 rdlen
+= DHD_SDALIGN
- (rdlen
% DHD_SDALIGN
);
4066 /* Satisfy length-alignment requirements */
4067 if (forcealign
&& (rdlen
& (ALIGNMENT
- 1)))
4068 rdlen
= roundup(rdlen
, ALIGNMENT
);
4070 if ((rdlen
+ firstread
) > MAX_RX_DATASZ
) {
4071 /* Too long -- skip this frame */
4072 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4073 __func__
, len
, rdlen
));
4074 bus
->dhd
->rx_errors
++;
4076 dhdsdio_rxfail(bus
, false, false);
4080 dhd_os_sdlock_rxq(bus
->dhd
);
4081 pkt
= pkt_buf_get_skb(rdlen
+ firstread
+ DHD_SDALIGN
);
4083 /* Give up on data, request rtx of events */
4084 DHD_ERROR(("%s: pkt_buf_get_skb failed: rdlen %d chan %d\n",
4085 __func__
, rdlen
, chan
));
4086 bus
->dhd
->rx_dropped
++;
4087 dhd_os_sdunlock_rxq(bus
->dhd
);
4088 dhdsdio_rxfail(bus
, false, RETRYCHAN(chan
));
4091 dhd_os_sdunlock_rxq(bus
->dhd
);
4093 ASSERT(!(pkt
->prev
));
4095 /* Leave room for what we already read, and align remainder */
4096 ASSERT(firstread
< pkt
->len
);
4097 skb_pull(pkt
, firstread
);
4098 PKTALIGN(pkt
, rdlen
, DHD_SDALIGN
);
4100 /* Read the remaining frame data */
4102 dhd_bcmsdh_recv_buf(bus
, bcmsdh_cur_sbwad(sdh
), SDIO_FUNC_2
,
4103 F2SYNC
, ((u8
*) (pkt
->data
)), rdlen
,
4106 ASSERT(sdret
!= BCME_PENDING
);
4109 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4112 SDPCM_EVENT_CHANNEL
) ? "event" : ((chan
==
4114 ? "data" : "test")),
4116 dhd_os_sdlock_rxq(bus
->dhd
);
4117 pkt_buf_free_skb(pkt
);
4118 dhd_os_sdunlock_rxq(bus
->dhd
);
4119 bus
->dhd
->rx_errors
++;
4120 dhdsdio_rxfail(bus
, true, RETRYCHAN(chan
));
4124 /* Copy the already-read portion */
4125 skb_push(pkt
, firstread
);
4126 memcpy(pkt
->data
, bus
->rxhdr
, firstread
);
4129 if (DHD_BYTES_ON() && DHD_DATA_ON())
4130 prhex("Rx Data", pkt
->data
, len
);
4134 /* Save superframe descriptor and allocate packet frame */
4135 if (chan
== SDPCM_GLOM_CHANNEL
) {
4136 if (SDPCM_GLOMDESC(&bus
->rxhdr
[SDPCM_FRAMETAG_LEN
])) {
4137 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4140 if (DHD_GLOM_ON()) {
4141 prhex("Glom Data", pkt
->data
, len
);
4144 __skb_trim(pkt
, len
);
4145 ASSERT(doff
== SDPCM_HDRLEN
);
4146 skb_pull(pkt
, SDPCM_HDRLEN
);
4149 DHD_ERROR(("%s: glom superframe w/o "
4150 "descriptor!\n", __func__
));
4151 dhdsdio_rxfail(bus
, false, false);
4156 /* Fill in packet len and prio, deliver upward */
4157 __skb_trim(pkt
, len
);
4158 skb_pull(pkt
, doff
);
4161 /* Test channel packets are processed separately */
4162 if (chan
== SDPCM_TEST_CHANNEL
) {
4163 dhdsdio_testrcv(bus
, pkt
, seq
);
4168 if (pkt
->len
== 0) {
4169 dhd_os_sdlock_rxq(bus
->dhd
);
4170 pkt_buf_free_skb(pkt
);
4171 dhd_os_sdunlock_rxq(bus
->dhd
);
4173 } else if (dhd_prot_hdrpull(bus
->dhd
, &ifidx
, pkt
) != 0) {
4174 DHD_ERROR(("%s: rx protocol error\n", __func__
));
4175 dhd_os_sdlock_rxq(bus
->dhd
);
4176 pkt_buf_free_skb(pkt
);
4177 dhd_os_sdunlock_rxq(bus
->dhd
);
4178 bus
->dhd
->rx_errors
++;
4182 /* Unlock during rx call */
4183 dhd_os_sdunlock(bus
->dhd
);
4184 dhd_rx_frame(bus
->dhd
, ifidx
, pkt
, 1);
4185 dhd_os_sdlock(bus
->dhd
);
4187 rxcount
= maxframes
- rxleft
;
4189 /* Message if we hit the limit */
4190 if (!rxleft
&& !sdtest
)
4191 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__
,
4194 #endif /* DHD_DEBUG */
4195 DHD_DATA(("%s: processed %d frames\n", __func__
, rxcount
));
4196 /* Back off rxseq if awaiting rtx, update rx_seq */
4199 bus
->rx_seq
= rxseq
;
4204 static u32
dhdsdio_hostmail(dhd_bus_t
*bus
)
4206 sdpcmd_regs_t
*regs
= bus
->regs
;
4212 DHD_TRACE(("%s: Enter\n", __func__
));
4214 /* Read mailbox data and ack that we did so */
4215 R_SDREG(hmb_data
, ®s
->tohostmailboxdata
, retries
);
4216 if (retries
<= retry_limit
)
4217 W_SDREG(SMB_INT_ACK
, ®s
->tosbmailbox
, retries
);
4218 bus
->f1regdata
+= 2;
4220 /* Dongle recomposed rx frames, accept them again */
4221 if (hmb_data
& HMB_DATA_NAKHANDLED
) {
4222 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4225 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__
));
4227 bus
->rxskip
= false;
4228 intstatus
|= I_HMB_FRAME_IND
;
4232 * DEVREADY does not occur with gSPI.
4234 if (hmb_data
& (HMB_DATA_DEVREADY
| HMB_DATA_FWREADY
)) {
4236 (hmb_data
& HMB_DATA_VERSION_MASK
) >>
4237 HMB_DATA_VERSION_SHIFT
;
4238 if (bus
->sdpcm_ver
!= SDPCM_PROT_VERSION
)
4239 DHD_ERROR(("Version mismatch, dongle reports %d, "
4241 bus
->sdpcm_ver
, SDPCM_PROT_VERSION
));
4243 DHD_INFO(("Dongle ready, protocol version %d\n",
4248 * Flow Control has been moved into the RX headers and this out of band
4249 * method isn't used any more. Leae this here for possibly
4250 * remaining backward
4251 * compatible with older dongles
4253 if (hmb_data
& HMB_DATA_FC
) {
4255 (hmb_data
& HMB_DATA_FCDATA_MASK
) >> HMB_DATA_FCDATA_SHIFT
;
4257 if (fcbits
& ~bus
->flowcontrol
)
4259 if (bus
->flowcontrol
& ~fcbits
)
4263 bus
->flowcontrol
= fcbits
;
4266 /* Shouldn't be any others */
4267 if (hmb_data
& ~(HMB_DATA_DEVREADY
|
4268 HMB_DATA_NAKHANDLED
|
4271 HMB_DATA_FCDATA_MASK
| HMB_DATA_VERSION_MASK
)) {
4272 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data
));
4278 bool dhdsdio_dpc(dhd_bus_t
*bus
)
4280 bcmsdh_info_t
*sdh
= bus
->sdh
;
4281 sdpcmd_regs_t
*regs
= bus
->regs
;
4282 u32 intstatus
, newstatus
= 0;
4284 uint rxlimit
= dhd_rxbound
; /* Rx frames to read before resched */
4285 uint txlimit
= dhd_txbound
; /* Tx frames to send before resched */
4286 uint framecnt
= 0; /* Temporary counter of tx/rx frames */
4287 bool rxdone
= true; /* Flag for no more read data */
4288 bool resched
= false; /* Flag indicating resched wanted */
4290 DHD_TRACE(("%s: Enter\n", __func__
));
4292 /* Start with leftover status bits */
4293 intstatus
= bus
->intstatus
;
4295 dhd_os_sdlock(bus
->dhd
);
4297 /* If waiting for HTAVAIL, check status */
4298 if (bus
->clkstate
== CLK_PENDING
) {
4300 u8 clkctl
, devctl
= 0;
4303 /* Check for inconsistent device control */
4305 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
, &err
);
4307 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4309 bus
->dhd
->busstate
= DHD_BUS_DOWN
;
4311 ASSERT(devctl
& SBSDIO_DEVCTL_CA_INT_ONLY
);
4313 #endif /* DHD_DEBUG */
4315 /* Read CSR, if clock on switch to AVAIL, else ignore */
4317 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
4320 DHD_ERROR(("%s: error reading CSR: %d\n", __func__
,
4322 bus
->dhd
->busstate
= DHD_BUS_DOWN
;
4325 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl
,
4328 if (SBSDIO_HTAV(clkctl
)) {
4330 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
,
4333 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4335 bus
->dhd
->busstate
= DHD_BUS_DOWN
;
4337 devctl
&= ~SBSDIO_DEVCTL_CA_INT_ONLY
;
4338 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_DEVICE_CTL
,
4341 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4343 bus
->dhd
->busstate
= DHD_BUS_DOWN
;
4345 bus
->clkstate
= CLK_AVAIL
;
4353 /* Make sure backplane clock is on */
4354 dhdsdio_clkctl(bus
, CLK_AVAIL
, true);
4355 if (bus
->clkstate
== CLK_PENDING
)
4358 /* Pending interrupt indicates new device status */
4361 R_SDREG(newstatus
, ®s
->intstatus
, retries
);
4363 if (bcmsdh_regfail(bus
->sdh
))
4365 newstatus
&= bus
->hostintmask
;
4366 bus
->fcstate
= !!(newstatus
& I_HMB_FC_STATE
);
4368 W_SDREG(newstatus
, ®s
->intstatus
, retries
);
4373 /* Merge new bits with previous */
4374 intstatus
|= newstatus
;
4377 /* Handle flow-control change: read new state in case our ack
4378 * crossed another change interrupt. If change still set, assume
4379 * FC ON for safety, let next loop through do the debounce.
4381 if (intstatus
& I_HMB_FC_CHANGE
) {
4382 intstatus
&= ~I_HMB_FC_CHANGE
;
4383 W_SDREG(I_HMB_FC_CHANGE
, ®s
->intstatus
, retries
);
4384 R_SDREG(newstatus
, ®s
->intstatus
, retries
);
4385 bus
->f1regdata
+= 2;
4387 !!(newstatus
& (I_HMB_FC_STATE
| I_HMB_FC_CHANGE
));
4388 intstatus
|= (newstatus
& bus
->hostintmask
);
4391 /* Handle host mailbox indication */
4392 if (intstatus
& I_HMB_HOST_INT
) {
4393 intstatus
&= ~I_HMB_HOST_INT
;
4394 intstatus
|= dhdsdio_hostmail(bus
);
4397 /* Generally don't ask for these, can get CRC errors... */
4398 if (intstatus
& I_WR_OOSYNC
) {
4399 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4400 intstatus
&= ~I_WR_OOSYNC
;
4403 if (intstatus
& I_RD_OOSYNC
) {
4404 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4405 intstatus
&= ~I_RD_OOSYNC
;
4408 if (intstatus
& I_SBINT
) {
4409 DHD_ERROR(("Dongle reports SBINT\n"));
4410 intstatus
&= ~I_SBINT
;
4413 /* Would be active due to wake-wlan in gSPI */
4414 if (intstatus
& I_CHIPACTIVE
) {
4415 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4416 intstatus
&= ~I_CHIPACTIVE
;
4419 /* Ignore frame indications if rxskip is set */
4421 intstatus
&= ~I_HMB_FRAME_IND
;
4423 /* On frame indication, read available frames */
4424 if (PKT_AVAILABLE()) {
4425 framecnt
= dhdsdio_readframes(bus
, rxlimit
, &rxdone
);
4426 if (rxdone
|| bus
->rxskip
)
4427 intstatus
&= ~I_HMB_FRAME_IND
;
4428 rxlimit
-= min(framecnt
, rxlimit
);
4431 /* Keep still-pending events for next scheduling */
4432 bus
->intstatus
= intstatus
;
4435 #if defined(OOB_INTR_ONLY)
4436 bcmsdh_oob_intr_set(1);
4437 #endif /* (OOB_INTR_ONLY) */
4438 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4439 * or clock availability. (Allows tx loop to check ipend if desired.)
4440 * (Unless register access seems hosed, as we may not be able to ACK...)
4442 if (bus
->intr
&& bus
->intdis
&& !bcmsdh_regfail(sdh
)) {
4443 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4444 __func__
, rxdone
, framecnt
));
4445 bus
->intdis
= false;
4446 bcmsdh_intr_enable(sdh
);
4449 if (DATAOK(bus
) && bus
->ctrl_frame_stat
&&
4450 (bus
->clkstate
== CLK_AVAIL
)) {
4454 dhd_bcmsdh_send_buf(bus
, bcmsdh_cur_sbwad(sdh
), SDIO_FUNC_2
,
4455 F2SYNC
, (u8
*) bus
->ctrl_frame_buf
,
4456 (u32
) bus
->ctrl_frame_len
, NULL
,
4458 ASSERT(ret
!= BCME_PENDING
);
4461 /* On failure, abort the command and
4462 terminate the frame */
4463 DHD_INFO(("%s: sdio error %d, abort command and "
4464 "terminate frame.\n", __func__
, ret
));
4467 bcmsdh_abort(sdh
, SDIO_FUNC_2
);
4469 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
,
4470 SBSDIO_FUNC1_FRAMECTRL
, SFC_WF_TERM
,
4474 for (i
= 0; i
< 3; i
++) {
4476 hi
= bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
,
4477 SBSDIO_FUNC1_WFRAMEBCHI
,
4479 lo
= bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
,
4480 SBSDIO_FUNC1_WFRAMEBCLO
,
4482 bus
->f1regdata
+= 2;
4483 if ((hi
== 0) && (lo
== 0))
4489 bus
->tx_seq
= (bus
->tx_seq
+ 1) % SDPCM_SEQUENCE_WRAP
;
4491 DHD_INFO(("Return_dpc value is : %d\n", ret
));
4492 bus
->ctrl_frame_stat
= false;
4493 dhd_wait_event_wakeup(bus
->dhd
);
4495 /* Send queued frames (limit 1 if rx may still be pending) */
4496 else if ((bus
->clkstate
== CLK_AVAIL
) && !bus
->fcstate
&&
4497 pktq_mlen(&bus
->txq
, ~bus
->flowcontrol
) && txlimit
4499 framecnt
= rxdone
? txlimit
: min(txlimit
, dhd_txminmax
);
4500 framecnt
= dhdsdio_sendfromq(bus
, framecnt
);
4501 txlimit
-= framecnt
;
4504 /* Resched if events or tx frames are pending,
4505 else await next interrupt */
4506 /* On failed register access, all bets are off:
4507 no resched or interrupts */
4508 if ((bus
->dhd
->busstate
== DHD_BUS_DOWN
) || bcmsdh_regfail(sdh
)) {
4509 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4510 "operation %d\n", __func__
, bcmsdh_regfail(sdh
)));
4511 bus
->dhd
->busstate
= DHD_BUS_DOWN
;
4513 } else if (bus
->clkstate
== CLK_PENDING
) {
4514 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4515 "I_CHIPACTIVE interrupt\n", __func__
));
4517 } else if (bus
->intstatus
|| bus
->ipend
||
4518 (!bus
->fcstate
&& pktq_mlen(&bus
->txq
, ~bus
->flowcontrol
) &&
4519 DATAOK(bus
)) || PKT_AVAILABLE()) {
4523 bus
->dpc_sched
= resched
;
4525 /* If we're done for now, turn off clock request. */
4526 if ((bus
->clkstate
!= CLK_PENDING
)
4527 && bus
->idletime
== DHD_IDLE_IMMEDIATE
) {
4528 bus
->activity
= false;
4529 dhdsdio_clkctl(bus
, CLK_NONE
, false);
4532 dhd_os_sdunlock(bus
->dhd
);
4537 bool dhd_bus_dpc(struct dhd_bus
*bus
)
4541 /* Call the DPC directly. */
4542 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__
));
4543 resched
= dhdsdio_dpc(bus
);
4548 void dhdsdio_isr(void *arg
)
4550 dhd_bus_t
*bus
= (dhd_bus_t
*) arg
;
4553 DHD_TRACE(("%s: Enter\n", __func__
));
4556 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__
));
4561 if (bus
->dhd
->busstate
== DHD_BUS_DOWN
) {
4562 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4566 /* Count the interrupt call */
4570 /* Shouldn't get this interrupt if we're sleeping? */
4571 if (bus
->sleeping
) {
4572 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4576 /* Disable additional interrupts (is this needed now)? */
4578 DHD_INTR(("%s: disable SDIO interrupts\n", __func__
));
4580 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4582 bcmsdh_intr_disable(sdh
);
4585 #if defined(SDIO_ISR_THREAD)
4586 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__
));
4587 while (dhdsdio_dpc(bus
))
4590 bus
->dpc_sched
= true;
4591 dhd_sched_dpc(bus
->dhd
);
4597 static void dhdsdio_pktgen_init(dhd_bus_t
*bus
)
4599 /* Default to specified length, or full range */
4600 if (dhd_pktgen_len
) {
4601 bus
->pktgen_maxlen
= min(dhd_pktgen_len
, MAX_PKTGEN_LEN
);
4602 bus
->pktgen_minlen
= bus
->pktgen_maxlen
;
4604 bus
->pktgen_maxlen
= MAX_PKTGEN_LEN
;
4605 bus
->pktgen_minlen
= 0;
4607 bus
->pktgen_len
= (u16
) bus
->pktgen_minlen
;
4609 /* Default to per-watchdog burst with 10s print time */
4610 bus
->pktgen_freq
= 1;
4611 bus
->pktgen_print
= 10000 / dhd_watchdog_ms
;
4612 bus
->pktgen_count
= (dhd_pktgen
* dhd_watchdog_ms
+ 999) / 1000;
4614 /* Default to echo mode */
4615 bus
->pktgen_mode
= DHD_PKTGEN_ECHO
;
4616 bus
->pktgen_stop
= 1;
4619 static void dhdsdio_pktgen(dhd_bus_t
*bus
)
4621 struct sk_buff
*pkt
;
4627 /* Display current count if appropriate */
4628 if (bus
->pktgen_print
&& (++bus
->pktgen_ptick
>= bus
->pktgen_print
)) {
4629 bus
->pktgen_ptick
= 0;
4630 printk(KERN_DEBUG
"%s: send attempts %d rcvd %d\n",
4631 __func__
, bus
->pktgen_sent
, bus
->pktgen_rcvd
);
4634 /* For recv mode, just make sure dongle has started sending */
4635 if (bus
->pktgen_mode
== DHD_PKTGEN_RECV
) {
4636 if (!bus
->pktgen_rcvd
)
4637 dhdsdio_sdtest_set(bus
, true);
4641 /* Otherwise, generate or request the specified number of packets */
4642 for (pktcount
= 0; pktcount
< bus
->pktgen_count
; pktcount
++) {
4643 /* Stop if total has been reached */
4644 if (bus
->pktgen_total
4645 && (bus
->pktgen_sent
>= bus
->pktgen_total
)) {
4646 bus
->pktgen_count
= 0;
4650 /* Allocate an appropriate-sized packet */
4651 len
= bus
->pktgen_len
;
4652 pkt
= pkt_buf_get_skb(
4653 (len
+ SDPCM_HDRLEN
+ SDPCM_TEST_HDRLEN
+ DHD_SDALIGN
),
4656 DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__
));
4659 PKTALIGN(pkt
, (len
+ SDPCM_HDRLEN
+ SDPCM_TEST_HDRLEN
),
4661 data
= (u8
*) (pkt
->data
) + SDPCM_HDRLEN
;
4663 /* Write test header cmd and extra based on mode */
4664 switch (bus
->pktgen_mode
) {
4665 case DHD_PKTGEN_ECHO
:
4666 *data
++ = SDPCM_TEST_ECHOREQ
;
4667 *data
++ = (u8
) bus
->pktgen_sent
;
4670 case DHD_PKTGEN_SEND
:
4671 *data
++ = SDPCM_TEST_DISCARD
;
4672 *data
++ = (u8
) bus
->pktgen_sent
;
4675 case DHD_PKTGEN_RXBURST
:
4676 *data
++ = SDPCM_TEST_BURST
;
4677 *data
++ = (u8
) bus
->pktgen_count
;
4681 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4683 pkt_buf_free_skb(pkt
, true);
4684 bus
->pktgen_count
= 0;
4688 /* Write test header length field */
4689 *data
++ = (len
>> 0);
4690 *data
++ = (len
>> 8);
4692 /* Then fill in the remainder -- N/A for burst,
4694 for (fillbyte
= 0; fillbyte
< len
; fillbyte
++)
4696 SDPCM_TEST_FILL(fillbyte
, (u8
) bus
->pktgen_sent
);
4699 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4700 data
= (u8
*) (pkt
->data
) + SDPCM_HDRLEN
;
4701 prhex("dhdsdio_pktgen: Tx Data", data
,
4702 pkt
->len
- SDPCM_HDRLEN
);
4707 if (dhdsdio_txpkt(bus
, pkt
, SDPCM_TEST_CHANNEL
, true)) {
4709 if (bus
->pktgen_stop
4710 && bus
->pktgen_stop
== bus
->pktgen_fail
)
4711 bus
->pktgen_count
= 0;
4715 /* Bump length if not fixed, wrap at max */
4716 if (++bus
->pktgen_len
> bus
->pktgen_maxlen
)
4717 bus
->pktgen_len
= (u16
) bus
->pktgen_minlen
;
4719 /* Special case for burst mode: just send one request! */
4720 if (bus
->pktgen_mode
== DHD_PKTGEN_RXBURST
)
4725 static void dhdsdio_sdtest_set(dhd_bus_t
*bus
, bool start
)
4727 struct sk_buff
*pkt
;
4730 /* Allocate the packet */
4731 pkt
= pkt_buf_get_skb(SDPCM_HDRLEN
+ SDPCM_TEST_HDRLEN
+ DHD_SDALIGN
,
4734 DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__
));
4737 PKTALIGN(pkt
, (SDPCM_HDRLEN
+ SDPCM_TEST_HDRLEN
), DHD_SDALIGN
);
4738 data
= (u8
*) (pkt
->data
) + SDPCM_HDRLEN
;
4740 /* Fill in the test header */
4741 *data
++ = SDPCM_TEST_SEND
;
4743 *data
++ = (bus
->pktgen_maxlen
>> 0);
4744 *data
++ = (bus
->pktgen_maxlen
>> 8);
4747 if (dhdsdio_txpkt(bus
, pkt
, SDPCM_TEST_CHANNEL
, true))
4751 static void dhdsdio_testrcv(dhd_bus_t
*bus
, struct sk_buff
*pkt
, uint seq
)
4761 /* Check for min length */
4763 if (pktlen
< SDPCM_TEST_HDRLEN
) {
4764 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4766 pkt_buf_free_skb(pkt
, false);
4770 /* Extract header fields */
4775 len
+= *data
++ << 8;
4777 /* Check length for relevant commands */
4778 if (cmd
== SDPCM_TEST_DISCARD
|| cmd
== SDPCM_TEST_ECHOREQ
4779 || cmd
== SDPCM_TEST_ECHORSP
) {
4780 if (pktlen
!= len
+ SDPCM_TEST_HDRLEN
) {
4781 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4782 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4783 pktlen
, seq
, cmd
, extra
, len
));
4784 pkt_buf_free_skb(pkt
, false);
4789 /* Process as per command */
4791 case SDPCM_TEST_ECHOREQ
:
4792 /* Rx->Tx turnaround ok (even on NDIS w/current
4794 *(u8
*) (pkt
->data
) = SDPCM_TEST_ECHORSP
;
4795 if (dhdsdio_txpkt(bus
, pkt
, SDPCM_TEST_CHANNEL
, true) == 0) {
4799 pkt_buf_free_skb(pkt
, false);
4804 case SDPCM_TEST_ECHORSP
:
4805 if (bus
->ext_loop
) {
4806 pkt_buf_free_skb(pkt
, false);
4811 for (offset
= 0; offset
< len
; offset
++, data
++) {
4812 if (*data
!= SDPCM_TEST_FILL(offset
, extra
)) {
4813 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4815 SDPCM_TEST_FILL(offset
, extra
), *data
));
4819 pkt_buf_free_skb(pkt
, false);
4823 case SDPCM_TEST_DISCARD
:
4824 pkt_buf_free_skb(pkt
, false);
4828 case SDPCM_TEST_BURST
:
4829 case SDPCM_TEST_SEND
:
4831 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4832 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4833 pktlen
, seq
, cmd
, extra
, len
));
4834 pkt_buf_free_skb(pkt
, false);
4838 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4839 if (bus
->pktgen_mode
== DHD_PKTGEN_RECV
) {
4840 if (bus
->pktgen_total
4841 && (bus
->pktgen_rcvd
>= bus
->pktgen_total
)) {
4842 bus
->pktgen_count
= 0;
4843 dhdsdio_sdtest_set(bus
, false);
4849 extern bool dhd_bus_watchdog(dhd_pub_t
*dhdp
)
4853 DHD_TIMER(("%s: Enter\n", __func__
));
4857 if (bus
->dhd
->dongle_reset
)
4860 /* Ignore the timer if simulating bus down */
4864 dhd_os_sdlock(bus
->dhd
);
4866 /* Poll period: check device if appropriate. */
4867 if (bus
->poll
&& (++bus
->polltick
>= bus
->pollrate
)) {
4870 /* Reset poll tick */
4873 /* Check device if no interrupts */
4874 if (!bus
->intr
|| (bus
->intrcount
== bus
->lastintrs
)) {
4876 if (!bus
->dpc_sched
) {
4878 devpend
= bcmsdh_cfg_read(bus
->sdh
, SDIO_FUNC_0
,
4882 devpend
& (INTR_STATUS_FUNC1
|
4886 /* If there is something, make like the ISR and
4892 bcmsdh_intr_disable(bus
->sdh
);
4894 bus
->dpc_sched
= true;
4895 dhd_sched_dpc(bus
->dhd
);
4900 /* Update interrupt tracking */
4901 bus
->lastintrs
= bus
->intrcount
;
4904 /* Poll for console output periodically */
4905 if (dhdp
->busstate
== DHD_BUS_DATA
&& dhd_console_ms
!= 0) {
4906 bus
->console
.count
+= dhd_watchdog_ms
;
4907 if (bus
->console
.count
>= dhd_console_ms
) {
4908 bus
->console
.count
-= dhd_console_ms
;
4909 /* Make sure backplane clock is on */
4910 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
4911 if (dhdsdio_readconsole(bus
) < 0)
4912 dhd_console_ms
= 0; /* On error,
4916 #endif /* DHD_DEBUG */
4919 /* Generate packets if configured */
4920 if (bus
->pktgen_count
&& (++bus
->pktgen_tick
>= bus
->pktgen_freq
)) {
4921 /* Make sure backplane clock is on */
4922 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
4923 bus
->pktgen_tick
= 0;
4924 dhdsdio_pktgen(bus
);
4928 /* On idle timeout clear activity flag and/or turn off clock */
4929 if ((bus
->idletime
> 0) && (bus
->clkstate
== CLK_AVAIL
)) {
4930 if (++bus
->idlecount
>= bus
->idletime
) {
4932 if (bus
->activity
) {
4933 bus
->activity
= false;
4934 dhd_os_wd_timer(bus
->dhd
, dhd_watchdog_ms
);
4936 dhdsdio_clkctl(bus
, CLK_NONE
, false);
4941 dhd_os_sdunlock(bus
->dhd
);
4947 extern int dhd_bus_console_in(dhd_pub_t
*dhdp
, unsigned char *msg
, uint msglen
)
4949 dhd_bus_t
*bus
= dhdp
->bus
;
4952 struct sk_buff
*pkt
;
4954 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4955 if (bus
->console_addr
== 0)
4956 return BCME_UNSUPPORTED
;
4958 /* Exclusive bus access */
4959 dhd_os_sdlock(bus
->dhd
);
4961 /* Don't allow input if dongle is in reset */
4962 if (bus
->dhd
->dongle_reset
) {
4963 dhd_os_sdunlock(bus
->dhd
);
4964 return BCME_NOTREADY
;
4967 /* Request clock to allow SDIO accesses */
4969 /* No pend allowed since txpkt is called later, ht clk has to be on */
4970 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
4972 /* Zero cbuf_index */
4973 addr
= bus
->console_addr
+ offsetof(hndrte_cons_t
, cbuf_idx
);
4974 val
= cpu_to_le32(0);
4975 rv
= dhdsdio_membytes(bus
, true, addr
, (u8
*)&val
, sizeof(val
));
4979 /* Write message into cbuf */
4980 addr
= bus
->console_addr
+ offsetof(hndrte_cons_t
, cbuf
);
4981 rv
= dhdsdio_membytes(bus
, true, addr
, (u8
*)msg
, msglen
);
4985 /* Write length into vcons_in */
4986 addr
= bus
->console_addr
+ offsetof(hndrte_cons_t
, vcons_in
);
4987 val
= cpu_to_le32(msglen
);
4988 rv
= dhdsdio_membytes(bus
, true, addr
, (u8
*)&val
, sizeof(val
));
4992 /* Bump dongle by sending an empty event pkt.
4993 * sdpcm_sendup (RX) checks for virtual console input.
4995 pkt
= pkt_buf_get_skb(4 + SDPCM_RESERVE
);
4996 if ((pkt
!= NULL
) && bus
->clkstate
== CLK_AVAIL
)
4997 dhdsdio_txpkt(bus
, pkt
, SDPCM_EVENT_CHANNEL
, true);
5000 if ((bus
->idletime
== DHD_IDLE_IMMEDIATE
) && !bus
->dpc_sched
) {
5001 bus
->activity
= false;
5002 dhdsdio_clkctl(bus
, CLK_NONE
, true);
5005 dhd_os_sdunlock(bus
->dhd
);
5009 #endif /* DHD_DEBUG */
5012 static void dhd_dump_cis(uint fn
, u8
*cis
)
5014 uint byte
, tag
, tdata
;
5015 DHD_INFO(("Function %d CIS:\n", fn
));
5017 for (tdata
= byte
= 0; byte
< SBSDIO_CIS_SIZE_LIMIT
; byte
++) {
5018 if ((byte
% 16) == 0)
5020 DHD_INFO(("%02x ", cis
[byte
]));
5021 if ((byte
% 16) == 15)
5029 else if ((byte
+ 1) < SBSDIO_CIS_SIZE_LIMIT
)
5030 tdata
= cis
[byte
+ 1] + 1;
5035 if ((byte
% 16) != 15)
5038 #endif /* DHD_DEBUG */
5040 static bool dhdsdio_chipmatch(u16 chipid
)
5042 if (chipid
== BCM4325_CHIP_ID
)
5044 if (chipid
== BCM4329_CHIP_ID
)
5046 if (chipid
== BCM4319_CHIP_ID
)
5051 static void *dhdsdio_probe(u16 venid
, u16 devid
, u16 bus_no
,
5052 u16 slot
, u16 func
, uint bustype
, void *regsva
,
5058 /* Init global variables at run-time, not as part of the declaration.
5059 * This is required to support init/de-init of the driver.
5061 * of globals as part of the declaration results in non-deterministic
5062 * behavior since the value of the globals may be different on the
5063 * first time that the driver is initialized vs subsequent
5066 dhd_txbound
= DHD_TXBOUND
;
5067 dhd_rxbound
= DHD_RXBOUND
;
5068 dhd_alignctl
= true;
5070 dhd_readahead
= true;
5072 dhd_dongle_memsize
= 0;
5073 dhd_txminmax
= DHD_TXMINMAX
;
5079 DHD_TRACE(("%s: Enter\n", __func__
));
5080 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__
, venid
, devid
));
5082 /* We make assumptions about address window mappings */
5083 ASSERT((unsigned long)regsva
== SI_ENUM_BASE
);
5085 /* BCMSDH passes venid and devid based on CIS parsing -- but
5087 * means early parse could fail, so here we should get either an ID
5088 * we recognize OR (-1) indicating we must request power first.
5090 /* Check the Vendor ID */
5093 case PCI_VENDOR_ID_BROADCOM
:
5096 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__
, venid
));
5100 /* Check the Device ID and make sure it's one that we support */
5102 case BCM4325_D11DUAL_ID
: /* 4325 802.11a/g id */
5103 case BCM4325_D11G_ID
: /* 4325 802.11g 2.4Ghz band id */
5104 case BCM4325_D11A_ID
: /* 4325 802.11a 5Ghz band id */
5105 DHD_INFO(("%s: found 4325 Dongle\n", __func__
));
5107 case BCM4329_D11NDUAL_ID
: /* 4329 802.11n dualband device */
5108 case BCM4329_D11N2G_ID
: /* 4329 802.11n 2.4G device */
5109 case BCM4329_D11N5G_ID
: /* 4329 802.11n 5G device */
5111 DHD_INFO(("%s: found 4329 Dongle\n", __func__
));
5113 case BCM4319_D11N_ID
: /* 4319 802.11n id */
5114 case BCM4319_D11N2G_ID
: /* 4319 802.11n2g id */
5115 case BCM4319_D11N5G_ID
: /* 4319 802.11n5g id */
5116 DHD_INFO(("%s: found 4319 Dongle\n", __func__
));
5119 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5124 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5125 __func__
, venid
, devid
));
5129 /* Allocate private bus interface state */
5130 bus
= kzalloc(sizeof(dhd_bus_t
), GFP_ATOMIC
);
5132 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__
));
5136 bus
->cl_devid
= (u16
) devid
;
5138 bus
->tx_seq
= SDPCM_SEQUENCE_WRAP
- 1;
5139 bus
->usebufpool
= false; /* Use bufpool if allocated,
5140 else use locally malloced rxbuf */
5142 /* attempt to attach to the dongle */
5143 if (!(dhdsdio_probe_attach(bus
, sdh
, regsva
, devid
))) {
5144 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__
));
5148 /* Attach to the dhd/OS/network interface */
5149 bus
->dhd
= dhd_attach(bus
, SDPCM_RESERVE
);
5151 DHD_ERROR(("%s: dhd_attach failed\n", __func__
));
5155 /* Allocate buffers */
5156 if (!(dhdsdio_probe_malloc(bus
, sdh
))) {
5157 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__
));
5161 if (!(dhdsdio_probe_init(bus
, sdh
))) {
5162 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__
));
5166 /* Register interrupt callback, but mask it (not operational yet). */
5167 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5169 bcmsdh_intr_disable(sdh
);
5170 ret
= bcmsdh_intr_reg(sdh
, dhdsdio_isr
, bus
);
5172 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5176 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__
));
5178 DHD_INFO(("%s: completed!!\n", __func__
));
5180 /* if firmware path present try to download and bring up bus */
5181 ret
= dhd_bus_start(bus
->dhd
);
5183 if (ret
== BCME_NOTUP
) {
5184 DHD_ERROR(("%s: dongle is not responding\n", __func__
));
5188 /* Ok, have the per-port tell the stack we're open for business */
5189 if (dhd_net_attach(bus
->dhd
, 0) != 0) {
5190 DHD_ERROR(("%s: Net attach failed!!\n", __func__
));
5197 dhdsdio_release(bus
);
5202 dhdsdio_probe_attach(struct dhd_bus
*bus
, void *sdh
, void *regsva
, u16 devid
)
5207 bus
->alp_only
= true;
5209 /* Return the window to backplane enumeration space for core access */
5210 if (dhdsdio_set_siaddr_window(bus
, SI_ENUM_BASE
))
5211 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__
));
5214 printk(KERN_DEBUG
"F1 signature read @0x18000000=0x%4x\n",
5215 bcmsdh_reg_read(bus
->sdh
, SI_ENUM_BASE
, 4));
5217 #endif /* DHD_DEBUG */
5219 /* Force PLL off until si_attach() programs PLL control regs */
5221 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
5222 DHD_INIT_CLKCTL1
, &err
);
5225 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
5228 if (err
|| ((clkctl
& ~SBSDIO_AVBITS
) != DHD_INIT_CLKCTL1
)) {
5229 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5230 "0x%02x read 0x%02x\n",
5231 err
, DHD_INIT_CLKCTL1
, clkctl
));
5235 if (DHD_INFO_ON()) {
5237 u8
*cis
[SDIOD_MAX_IOFUNCS
];
5240 numfn
= bcmsdh_query_iofnum(sdh
);
5241 ASSERT(numfn
<= SDIOD_MAX_IOFUNCS
);
5243 /* Make sure ALP is available before trying to read CIS */
5244 SPINWAIT(((clkctl
= bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
,
5245 SBSDIO_FUNC1_CHIPCLKCSR
,
5247 !SBSDIO_ALPAV(clkctl
)), PMU_MAX_TRANSITION_DLY
);
5249 /* Now request ALP be put on the bus */
5250 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
5251 DHD_INIT_CLKCTL2
, &err
);
5254 for (fn
= 0; fn
<= numfn
; fn
++) {
5255 cis
[fn
] = kzalloc(SBSDIO_CIS_SIZE_LIMIT
, GFP_ATOMIC
);
5257 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5262 err
= bcmsdh_cis_read(sdh
, fn
, cis
[fn
],
5263 SBSDIO_CIS_SIZE_LIMIT
);
5265 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5266 "err %d\n", fn
, err
));
5270 dhd_dump_cis(fn
, cis
[fn
]);
5279 DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5283 #endif /* DHD_DEBUG */
5285 /* si_attach() will provide an SI handle and scan the backplane */
5286 bus
->sih
= si_attach((uint
) devid
, regsva
, DHD_BUS
, sdh
,
5287 &bus
->vars
, &bus
->varsz
);
5289 DHD_ERROR(("%s: si_attach failed!\n", __func__
));
5293 bcmsdh_chipinfo(sdh
, bus
->sih
->chip
, bus
->sih
->chiprev
);
5295 if (!dhdsdio_chipmatch((u16
) bus
->sih
->chip
)) {
5296 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5297 __func__
, bus
->sih
->chip
));
5301 si_sdiod_drive_strength_init(bus
->sih
, dhd_sdiod_drive_strength
);
5303 /* Get info on the ARM and SOCRAM cores... */
5304 if (!DHD_NOPMU(bus
)) {
5305 if ((si_setcore(bus
->sih
, ARM7S_CORE_ID
, 0)) ||
5306 (si_setcore(bus
->sih
, ARMCM3_CORE_ID
, 0))) {
5307 bus
->armrev
= si_corerev(bus
->sih
);
5309 DHD_ERROR(("%s: failed to find ARM core!\n", __func__
));
5312 bus
->orig_ramsize
= si_socram_size(bus
->sih
);
5313 if (!(bus
->orig_ramsize
)) {
5314 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5318 bus
->ramsize
= bus
->orig_ramsize
;
5319 if (dhd_dongle_memsize
)
5320 dhd_dongle_setmemsize(bus
, dhd_dongle_memsize
);
5322 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5323 bus
->ramsize
, bus
->orig_ramsize
));
5326 /* ...but normally deal with the SDPCMDEV core */
5327 bus
->regs
= si_setcore(bus
->sih
, PCMCIA_CORE_ID
, 0);
5329 bus
->regs
= si_setcore(bus
->sih
, SDIOD_CORE_ID
, 0);
5331 DHD_ERROR(("%s: failed to find SDIODEV core!\n",
5336 bus
->sdpcmrev
= si_corerev(bus
->sih
);
5338 /* Set core control so an SDIO reset does a backplane reset */
5339 OR_REG(&bus
->regs
->corecontrol
, CC_BPRESEN
);
5341 pktq_init(&bus
->txq
, (PRIOMASK
+ 1), TXQLEN
);
5343 /* Locate an appropriately-aligned portion of hdrbuf */
5344 bus
->rxhdr
= (u8
*) roundup((unsigned long)&bus
->hdrbuf
[0], DHD_SDALIGN
);
5346 /* Set the poll and/or interrupt flags */
5347 bus
->intr
= (bool) dhd_intr
;
5348 bus
->poll
= (bool) dhd_poll
;
5358 static bool dhdsdio_probe_malloc(dhd_bus_t
*bus
, void *sdh
)
5360 DHD_TRACE(("%s: Enter\n", __func__
));
5362 if (bus
->dhd
->maxctl
) {
5364 roundup((bus
->dhd
->maxctl
+ SDPCM_HDRLEN
),
5365 ALIGNMENT
) + DHD_SDALIGN
;
5366 bus
->rxbuf
= kmalloc(bus
->rxblen
, GFP_ATOMIC
);
5367 if (!(bus
->rxbuf
)) {
5368 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5369 __func__
, bus
->rxblen
));
5374 /* Allocate buffer to receive glomed packet */
5375 bus
->databuf
= kmalloc(MAX_DATA_BUF
, GFP_ATOMIC
);
5376 if (!(bus
->databuf
)) {
5377 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5378 __func__
, MAX_DATA_BUF
));
5379 /* release rxbuf which was already located as above */
5385 /* Align the buffer */
5386 if ((unsigned long)bus
->databuf
% DHD_SDALIGN
)
5388 bus
->databuf
+ (DHD_SDALIGN
-
5389 ((unsigned long)bus
->databuf
% DHD_SDALIGN
));
5391 bus
->dataptr
= bus
->databuf
;
5399 static bool dhdsdio_probe_init(dhd_bus_t
*bus
, void *sdh
)
5403 DHD_TRACE(("%s: Enter\n", __func__
));
5406 dhdsdio_pktgen_init(bus
);
5409 /* Disable F2 to clear any intermediate frame state on the dongle */
5410 bcmsdh_cfg_write(sdh
, SDIO_FUNC_0
, SDIOD_CCCR_IOEN
, SDIO_FUNC_ENABLE_1
,
5413 bus
->dhd
->busstate
= DHD_BUS_DOWN
;
5414 bus
->sleeping
= false;
5415 bus
->rxflow
= false;
5416 bus
->prev_rxlim_hit
= 0;
5418 /* Done with backplane-dependent accesses, can drop clock... */
5419 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
, 0, NULL
);
5421 /* ...and initialize clock/power states */
5422 bus
->clkstate
= CLK_SDONLY
;
5423 bus
->idletime
= (s32
) dhd_idletime
;
5424 bus
->idleclock
= DHD_IDLE_ACTIVE
;
5426 /* Query the SD clock speed */
5427 if (bcmsdh_iovar_op(sdh
, "sd_divisor", NULL
, 0,
5428 &bus
->sd_divisor
, sizeof(s32
),
5429 false) != BCME_OK
) {
5430 DHD_ERROR(("%s: fail on %s get\n", __func__
, "sd_divisor"));
5431 bus
->sd_divisor
= -1;
5433 DHD_INFO(("%s: Initial value for %s is %d\n",
5434 __func__
, "sd_divisor", bus
->sd_divisor
));
5437 /* Query the SD bus mode */
5438 if (bcmsdh_iovar_op(sdh
, "sd_mode", NULL
, 0,
5439 &bus
->sd_mode
, sizeof(s32
), false) != BCME_OK
) {
5440 DHD_ERROR(("%s: fail on %s get\n", __func__
, "sd_mode"));
5443 DHD_INFO(("%s: Initial value for %s is %d\n",
5444 __func__
, "sd_mode", bus
->sd_mode
));
5447 /* Query the F2 block size, set roundup accordingly */
5449 if (bcmsdh_iovar_op(sdh
, "sd_blocksize", &fnum
, sizeof(s32
),
5450 &bus
->blocksize
, sizeof(s32
), false) != BCME_OK
) {
5452 DHD_ERROR(("%s: fail on %s get\n", __func__
, "sd_blocksize"));
5454 DHD_INFO(("%s: Initial value for %s is %d\n",
5455 __func__
, "sd_blocksize", bus
->blocksize
));
5457 bus
->roundup
= min(max_roundup
, bus
->blocksize
);
5459 /* Query if bus module supports packet chaining,
5460 default to use if supported */
5461 if (bcmsdh_iovar_op(sdh
, "sd_rxchain", NULL
, 0,
5462 &bus
->sd_rxchain
, sizeof(s32
),
5463 false) != BCME_OK
) {
5464 bus
->sd_rxchain
= false;
5466 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5468 (bus
->sd_rxchain
? "supports" : "does not support")));
5470 bus
->use_rxchain
= (bool) bus
->sd_rxchain
;
5476 dhd_bus_download_firmware(struct dhd_bus
*bus
, char *fw_path
, char *nv_path
)
5479 bus
->fw_path
= fw_path
;
5480 bus
->nv_path
= nv_path
;
5482 ret
= dhdsdio_download_firmware(bus
, bus
->sdh
);
5488 dhdsdio_download_firmware(struct dhd_bus
*bus
, void *sdh
)
5492 /* Download the firmware */
5493 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
5495 ret
= _dhdsdio_download_firmware(bus
) == 0;
5497 dhdsdio_clkctl(bus
, CLK_SDONLY
, false);
5502 /* Detach and free everything */
5503 static void dhdsdio_release(dhd_bus_t
*bus
)
5505 DHD_TRACE(("%s: Enter\n", __func__
));
5508 /* De-register interrupt handler */
5509 bcmsdh_intr_disable(bus
->sdh
);
5510 bcmsdh_intr_dereg(bus
->sdh
);
5514 dhdsdio_release_dongle(bus
);
5516 dhd_detach(bus
->dhd
);
5520 dhdsdio_release_malloc(bus
);
5525 DHD_TRACE(("%s: Disconnected\n", __func__
));
5528 static void dhdsdio_release_malloc(dhd_bus_t
*bus
)
5530 DHD_TRACE(("%s: Enter\n", __func__
));
5532 if (bus
->dhd
&& bus
->dhd
->dongle_reset
)
5537 bus
->rxctl
= bus
->rxbuf
= NULL
;
5541 kfree(bus
->databuf
);
5542 bus
->databuf
= NULL
;
5545 static void dhdsdio_release_dongle(dhd_bus_t
*bus
)
5547 DHD_TRACE(("%s: Enter\n", __func__
));
5549 if (bus
->dhd
&& bus
->dhd
->dongle_reset
)
5553 dhdsdio_clkctl(bus
, CLK_AVAIL
, false);
5554 #if !defined(BCMLXSDMMC)
5555 si_watchdog(bus
->sih
, 4);
5556 #endif /* !defined(BCMLXSDMMC) */
5557 dhdsdio_clkctl(bus
, CLK_NONE
, false);
5558 si_detach(bus
->sih
);
5559 if (bus
->vars
&& bus
->varsz
)
5564 DHD_TRACE(("%s: Disconnected\n", __func__
));
5567 static void dhdsdio_disconnect(void *ptr
)
5569 dhd_bus_t
*bus
= (dhd_bus_t
*)ptr
;
5571 DHD_TRACE(("%s: Enter\n", __func__
));
5575 dhdsdio_release(bus
);
5578 DHD_TRACE(("%s: Disconnected\n", __func__
));
5581 /* Register/Unregister functions are called by the main DHD entry
5582 * point (e.g. module insertion) to link with the bus driver, in
5583 * order to look for or await the device.
5586 static bcmsdh_driver_t dhd_sdio
= {
5591 int dhd_bus_register(void)
5593 DHD_TRACE(("%s: Enter\n", __func__
));
5595 return bcmsdh_register(&dhd_sdio
);
5598 void dhd_bus_unregister(void)
5600 DHD_TRACE(("%s: Enter\n", __func__
));
5602 bcmsdh_unregister();
5605 #ifdef BCMEMBEDIMAGE
5606 static int dhdsdio_download_code_array(struct dhd_bus
*bus
)
5611 DHD_INFO(("%s: download embedded firmware...\n", __func__
));
5613 /* Download image */
5614 while ((offset
+ MEMBLOCK
) < sizeof(dlarray
)) {
5616 dhdsdio_membytes(bus
, true, offset
, dlarray
+ offset
,
5619 DHD_ERROR(("%s: error %d on writing %d membytes at "
5621 __func__
, bcmerror
, MEMBLOCK
, offset
));
5628 if (offset
< sizeof(dlarray
)) {
5629 bcmerror
= dhdsdio_membytes(bus
, true, offset
,
5631 sizeof(dlarray
) - offset
);
5633 DHD_ERROR(("%s: error %d on writing %d membytes at "
5634 "0x%08x\n", __func__
, bcmerror
,
5635 sizeof(dlarray
) - offset
, offset
));
5640 /* Upload and compare the downloaded code */
5642 unsigned char *ularray
;
5644 ularray
= kmalloc(bus
->ramsize
, GFP_ATOMIC
);
5646 bcmerror
= BCME_NOMEM
;
5649 /* Upload image to verify downloaded contents. */
5651 memset(ularray
, 0xaa, bus
->ramsize
);
5652 while ((offset
+ MEMBLOCK
) < sizeof(dlarray
)) {
5654 dhdsdio_membytes(bus
, false, offset
,
5655 ularray
+ offset
, MEMBLOCK
);
5657 DHD_ERROR(("%s: error %d on reading %d membytes"
5659 __func__
, bcmerror
, MEMBLOCK
, offset
));
5666 if (offset
< sizeof(dlarray
)) {
5667 bcmerror
= dhdsdio_membytes(bus
, false, offset
,
5669 sizeof(dlarray
) - offset
);
5671 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5673 sizeof(dlarray
) - offset
, offset
));
5678 if (memcmp(dlarray
, ularray
, sizeof(dlarray
))) {
5679 DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5684 DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5689 #endif /* DHD_DEBUG */
5694 #endif /* BCMEMBEDIMAGE */
5696 static int dhdsdio_download_code_file(struct dhd_bus
*bus
, char *fw_path
)
5702 u8
*memblock
= NULL
, *memptr
;
5704 DHD_INFO(("%s: download firmware %s\n", __func__
, fw_path
));
5706 image
= dhd_os_open_image(fw_path
);
5710 memptr
= memblock
= kmalloc(MEMBLOCK
+ DHD_SDALIGN
, GFP_ATOMIC
);
5711 if (memblock
== NULL
) {
5712 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5713 __func__
, MEMBLOCK
));
5716 if ((u32
)(unsigned long)memblock
% DHD_SDALIGN
)
5718 (DHD_SDALIGN
- ((u32
)(unsigned long)memblock
% DHD_SDALIGN
));
5720 /* Download image */
5722 dhd_os_get_image_block((char *)memptr
, MEMBLOCK
, image
))) {
5723 bcmerror
= dhdsdio_membytes(bus
, true, offset
, memptr
, len
);
5725 DHD_ERROR(("%s: error %d on writing %d membytes at "
5726 "0x%08x\n", __func__
, bcmerror
, MEMBLOCK
, offset
));
5737 dhd_os_close_image(image
);
5743 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5744 * and ending in a NUL.
5745 * Removes carriage returns, empty lines, comment lines, and converts
5747 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5751 static uint
process_nvram_vars(char *varbuf
, uint len
)
5760 findNewline
= false;
5763 for (n
= 0; n
< len
; n
++) {
5766 if (varbuf
[n
] == '\r')
5768 if (findNewline
&& varbuf
[n
] != '\n')
5770 findNewline
= false;
5771 if (varbuf
[n
] == '#') {
5775 if (varbuf
[n
] == '\n') {
5785 buf_len
= dp
- varbuf
;
5787 while (dp
< varbuf
+ n
)
5794 EXAMPLE: nvram_array
5797 Use carriage return at the end of each assignment,
5798 and an empty string with
5799 carriage return at the end of array.
5802 unsigned char nvram_array[] = {"name1=value1\n",
5803 "name2=value2\n", "\n"};
5804 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5806 Search "EXAMPLE: nvram_array" to see how the array is activated.
5809 void dhd_bus_set_nvram_params(struct dhd_bus
*bus
, const char *nvram_params
)
5811 bus
->nvram_params
= nvram_params
;
5814 static int dhdsdio_download_nvram(struct dhd_bus
*bus
)
5819 char *memblock
= NULL
;
5822 bool nvram_file_exists
;
5824 nv_path
= bus
->nv_path
;
5826 nvram_file_exists
= ((nv_path
!= NULL
) && (nv_path
[0] != '\0'));
5827 if (!nvram_file_exists
&& (bus
->nvram_params
== NULL
))
5830 if (nvram_file_exists
) {
5831 image
= dhd_os_open_image(nv_path
);
5836 memblock
= kmalloc(MEMBLOCK
, GFP_ATOMIC
);
5837 if (memblock
== NULL
) {
5838 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5839 __func__
, MEMBLOCK
));
5843 /* Download variables */
5844 if (nvram_file_exists
) {
5845 len
= dhd_os_get_image_block(memblock
, MEMBLOCK
, image
);
5847 len
= strlen(bus
->nvram_params
);
5848 ASSERT(len
<= MEMBLOCK
);
5851 memcpy(memblock
, bus
->nvram_params
, len
);
5854 if (len
> 0 && len
< MEMBLOCK
) {
5855 bufp
= (char *)memblock
;
5857 len
= process_nvram_vars(bufp
, len
);
5861 bcmerror
= dhdsdio_downloadvars(bus
, memblock
, len
+ 1);
5863 DHD_ERROR(("%s: error downloading vars: %d\n",
5864 __func__
, bcmerror
));
5867 DHD_ERROR(("%s: error reading nvram file: %d\n",
5869 bcmerror
= BCME_SDIO_ERROR
;
5876 dhd_os_close_image(image
);
5881 static int _dhdsdio_download_firmware(struct dhd_bus
*bus
)
5885 bool embed
= false; /* download embedded firmware */
5886 bool dlok
= false; /* download firmware succeeded */
5888 /* Out immediately if no image to download */
5889 if ((bus
->fw_path
== NULL
) || (bus
->fw_path
[0] == '\0')) {
5890 #ifdef BCMEMBEDIMAGE
5897 /* Keep arm in reset */
5898 if (dhdsdio_download_state(bus
, true)) {
5899 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__
));
5903 /* External image takes precedence if specified */
5904 if ((bus
->fw_path
!= NULL
) && (bus
->fw_path
[0] != '\0')) {
5905 if (dhdsdio_download_code_file(bus
, bus
->fw_path
)) {
5906 DHD_ERROR(("%s: dongle image file download failed\n",
5908 #ifdef BCMEMBEDIMAGE
5918 #ifdef BCMEMBEDIMAGE
5920 if (dhdsdio_download_code_array(bus
)) {
5921 DHD_ERROR(("%s: dongle image array download failed\n",
5930 DHD_ERROR(("%s: dongle image download failed\n", __func__
));
5934 /* EXAMPLE: nvram_array */
5935 /* If a valid nvram_arry is specified as above, it can be passed
5937 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5939 /* External nvram takes precedence if specified */
5940 if (dhdsdio_download_nvram(bus
)) {
5941 DHD_ERROR(("%s: dongle nvram file download failed\n",
5945 /* Take arm out of reset */
5946 if (dhdsdio_download_state(bus
, false)) {
5947 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5959 dhd_bcmsdh_recv_buf(dhd_bus_t
*bus
, u32 addr
, uint fn
, uint flags
,
5960 u8
*buf
, uint nbytes
, struct sk_buff
*pkt
,
5961 bcmsdh_cmplt_fn_t complete
, void *handle
)
5965 /* 4329: GSPI check */
5967 bcmsdh_recv_buf(bus
->sdh
, addr
, fn
, flags
, buf
, nbytes
, pkt
,
5973 dhd_bcmsdh_send_buf(dhd_bus_t
*bus
, u32 addr
, uint fn
, uint flags
,
5974 u8
*buf
, uint nbytes
, struct sk_buff
*pkt
,
5975 bcmsdh_cmplt_fn_t complete
, void *handle
)
5977 return bcmsdh_send_buf
5978 (bus
->sdh
, addr
, fn
, flags
, buf
, nbytes
, pkt
, complete
,
5982 uint
dhd_bus_chip(struct dhd_bus
*bus
)
5984 ASSERT(bus
->sih
!= NULL
);
5985 return bus
->sih
->chip
;
5988 void *dhd_bus_pub(struct dhd_bus
*bus
)
5993 void *dhd_bus_txq(struct dhd_bus
*bus
)
5998 uint
dhd_bus_hdrlen(struct dhd_bus
*bus
)
6000 return SDPCM_HDRLEN
;
6003 int dhd_bus_devreset(dhd_pub_t
*dhdp
, u8 flag
)
6011 if (!bus
->dhd
->dongle_reset
) {
6012 /* Expect app to have torn down any
6013 connection before calling */
6014 /* Stop the bus, disable F2 */
6015 dhd_bus_stop(bus
, false);
6017 /* Clean tx/rx buffer pointers,
6018 detach from the dongle */
6019 dhdsdio_release_dongle(bus
);
6021 bus
->dhd
->dongle_reset
= true;
6022 bus
->dhd
->up
= false;
6024 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__
));
6025 /* App can now remove power from device */
6027 bcmerror
= BCME_SDIO_ERROR
;
6029 /* App must have restored power to device before calling */
6031 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__
));
6033 if (bus
->dhd
->dongle_reset
) {
6035 /* Reset SD client */
6036 bcmsdh_reset(bus
->sdh
);
6038 /* Attempt to re-attach & download */
6039 if (dhdsdio_probe_attach(bus
, bus
->sdh
,
6040 (u32
*) SI_ENUM_BASE
,
6042 /* Attempt to download binary to the dongle */
6043 if (dhdsdio_probe_init
6045 && dhdsdio_download_firmware(bus
,
6048 /* Re-init bus, enable F2 transfer */
6049 dhd_bus_init((dhd_pub_t
*) bus
->dhd
,
6052 #if defined(OOB_INTR_ONLY)
6053 dhd_enable_oob_intr(bus
, true);
6054 #endif /* defined(OOB_INTR_ONLY) */
6056 bus
->dhd
->dongle_reset
= false;
6057 bus
->dhd
->up
= true;
6059 DHD_TRACE(("%s: WLAN ON DONE\n",
6062 bcmerror
= BCME_SDIO_ERROR
;
6064 bcmerror
= BCME_SDIO_ERROR
;
6066 bcmerror
= BCME_NOTDOWN
;
6067 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6068 "is on\n", __func__
));
6069 bcmerror
= BCME_SDIO_ERROR
;