2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 /***************************************************
28 * Definition IGA1 Design Method of CRTC Registers *
29 ****************************************************/
30 #define IGA1_HOR_TOTAL_FORMULA(x) (((x)/8)-5)
31 #define IGA1_HOR_ADDR_FORMULA(x) (((x)/8)-1)
32 #define IGA1_HOR_BLANK_START_FORMULA(x) (((x)/8)-1)
33 #define IGA1_HOR_BLANK_END_FORMULA(x, y) (((x+y)/8)-1)
34 #define IGA1_HOR_SYNC_START_FORMULA(x) ((x)/8)
35 #define IGA1_HOR_SYNC_END_FORMULA(x, y) ((x+y)/8)
37 #define IGA1_VER_TOTAL_FORMULA(x) ((x)-2)
38 #define IGA1_VER_ADDR_FORMULA(x) ((x)-1)
39 #define IGA1_VER_BLANK_START_FORMULA(x) ((x)-1)
40 #define IGA1_VER_BLANK_END_FORMULA(x, y) ((x+y)-1)
41 #define IGA1_VER_SYNC_START_FORMULA(x) ((x)-1)
42 #define IGA1_VER_SYNC_END_FORMULA(x, y) ((x+y)-1)
44 /***************************************************
45 ** Definition IGA2 Design Method of CRTC Registers *
46 ****************************************************/
47 #define IGA2_HOR_TOTAL_FORMULA(x) ((x)-1)
48 #define IGA2_HOR_ADDR_FORMULA(x) ((x)-1)
49 #define IGA2_HOR_BLANK_START_FORMULA(x) ((x)-1)
50 #define IGA2_HOR_BLANK_END_FORMULA(x, y) ((x+y)-1)
51 #define IGA2_HOR_SYNC_START_FORMULA(x) ((x)-1)
52 #define IGA2_HOR_SYNC_END_FORMULA(x, y) ((x+y)-1)
54 #define IGA2_VER_TOTAL_FORMULA(x) ((x)-1)
55 #define IGA2_VER_ADDR_FORMULA(x) ((x)-1)
56 #define IGA2_VER_BLANK_START_FORMULA(x) ((x)-1)
57 #define IGA2_VER_BLANK_END_FORMULA(x, y) ((x+y)-1)
58 #define IGA2_VER_SYNC_START_FORMULA(x) ((x)-1)
59 #define IGA2_VER_SYNC_END_FORMULA(x, y) ((x+y)-1)
61 /**********************************************************/
62 /* Definition IGA2 Design Method of CRTC Shadow Registers */
63 /**********************************************************/
64 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) ((x/8)-5)
65 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) (((x+y)/8)-1)
66 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x) ((x)-2)
67 #define IGA2_VER_ADDR_SHADOW_FORMULA(x) ((x)-1)
68 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) ((x)-1)
69 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) ((x+y)-1)
70 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x)
71 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y)
73 /* Define Register Number for IGA1 CRTC Timing */
75 /* location: {CR00,0,7},{CR36,3,3} */
76 #define IGA1_HOR_TOTAL_REG_NUM 2
77 /* location: {CR01,0,7} */
78 #define IGA1_HOR_ADDR_REG_NUM 1
79 /* location: {CR02,0,7} */
80 #define IGA1_HOR_BLANK_START_REG_NUM 1
81 /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */
82 #define IGA1_HOR_BLANK_END_REG_NUM 3
83 /* location: {CR04,0,7},{CR33,4,4} */
84 #define IGA1_HOR_SYNC_START_REG_NUM 2
85 /* location: {CR05,0,4} */
86 #define IGA1_HOR_SYNC_END_REG_NUM 1
87 /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */
88 #define IGA1_VER_TOTAL_REG_NUM 4
89 /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */
90 #define IGA1_VER_ADDR_REG_NUM 4
91 /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */
92 #define IGA1_VER_BLANK_START_REG_NUM 4
93 /* location: {CR16,0,7} */
94 #define IGA1_VER_BLANK_END_REG_NUM 1
95 /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */
96 #define IGA1_VER_SYNC_START_REG_NUM 4
97 /* location: {CR11,0,3} */
98 #define IGA1_VER_SYNC_END_REG_NUM 1
100 /* Define Register Number for IGA2 Shadow CRTC Timing */
102 /* location: {CR6D,0,7},{CR71,3,3} */
103 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM 2
104 /* location: {CR6E,0,7} */
105 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM 1
106 /* location: {CR6F,0,7},{CR71,0,2} */
107 #define IGA2_SHADOW_VER_TOTAL_REG_NUM 2
108 /* location: {CR70,0,7},{CR71,4,6} */
109 #define IGA2_SHADOW_VER_ADDR_REG_NUM 2
110 /* location: {CR72,0,7},{CR74,4,6} */
111 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
112 /* location: {CR73,0,7},{CR74,0,2} */
113 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM 2
114 /* location: {CR75,0,7},{CR76,4,6} */
115 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM 2
116 /* location: {CR76,0,3} */
117 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1
119 /* Define Register Number for IGA2 CRTC Timing */
121 /* location: {CR50,0,7},{CR55,0,3} */
122 #define IGA2_HOR_TOTAL_REG_NUM 2
123 /* location: {CR51,0,7},{CR55,4,6} */
124 #define IGA2_HOR_ADDR_REG_NUM 2
125 /* location: {CR52,0,7},{CR54,0,2} */
126 #define IGA2_HOR_BLANK_START_REG_NUM 2
127 /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6]
128 is reserved, so it may have problem to set 1600x1200 on IGA2. */
129 /* Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */
130 #define IGA2_HOR_BLANK_END_REG_NUM 3
131 /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */
132 /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */
133 #define IGA2_HOR_SYNC_START_REG_NUM 4
135 /* location: {CR57,0,7},{CR5C,6,6} */
136 #define IGA2_HOR_SYNC_END_REG_NUM 2
137 /* location: {CR58,0,7},{CR5D,0,2} */
138 #define IGA2_VER_TOTAL_REG_NUM 2
139 /* location: {CR59,0,7},{CR5D,3,5} */
140 #define IGA2_VER_ADDR_REG_NUM 2
141 /* location: {CR5A,0,7},{CR5C,0,2} */
142 #define IGA2_VER_BLANK_START_REG_NUM 2
143 /* location: {CR5E,0,7},{CR5C,3,5} */
144 #define IGA2_VER_BLANK_END_REG_NUM 2
145 /* location: {CR5E,0,7},{CR5F,5,7} */
146 #define IGA2_VER_SYNC_START_REG_NUM 2
147 /* location: {CR5F,0,4} */
148 #define IGA2_VER_SYNC_END_REG_NUM 1
150 /* Define Fetch Count Register*/
152 /* location: {SR1C,0,7},{SR1D,0,1} */
153 #define IGA1_FETCH_COUNT_REG_NUM 2
154 /* 16 bytes alignment. */
155 #define IGA1_FETCH_COUNT_ALIGN_BYTE 16
156 /* x: H resolution, y: color depth */
157 #define IGA1_FETCH_COUNT_PATCH_VALUE 4
158 #define IGA1_FETCH_COUNT_FORMULA(x, y) \
159 (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
161 /* location: {CR65,0,7},{CR67,2,3} */
162 #define IGA2_FETCH_COUNT_REG_NUM 2
163 #define IGA2_FETCH_COUNT_ALIGN_BYTE 16
164 #define IGA2_FETCH_COUNT_PATCH_VALUE 0
165 #define IGA2_FETCH_COUNT_FORMULA(x, y) \
166 (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
170 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
171 #define IGA1_STARTING_ADDR_REG_NUM 4
172 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
173 #define IGA2_STARTING_ADDR_REG_NUM 3
175 /* Define Display OFFSET*/
176 /* These value are by HW suggested value*/
177 /* location: {SR17,0,7} */
178 #define K800_IGA1_FIFO_MAX_DEPTH 384
179 /* location: {SR16,0,5},{SR16,7,7} */
180 #define K800_IGA1_FIFO_THRESHOLD 328
181 /* location: {SR18,0,5},{SR18,7,7} */
182 #define K800_IGA1_FIFO_HIGH_THRESHOLD 296
183 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
184 /* because HW only 5 bits */
185 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
187 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
188 #define K800_IGA2_FIFO_MAX_DEPTH 384
189 /* location: {CR68,0,3},{CR95,4,6} */
190 #define K800_IGA2_FIFO_THRESHOLD 328
191 /* location: {CR92,0,3},{CR95,0,2} */
192 #define K800_IGA2_FIFO_HIGH_THRESHOLD 296
193 /* location: {CR94,0,6} */
194 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
196 /* location: {SR17,0,7} */
197 #define P880_IGA1_FIFO_MAX_DEPTH 192
198 /* location: {SR16,0,5},{SR16,7,7} */
199 #define P880_IGA1_FIFO_THRESHOLD 128
200 /* location: {SR18,0,5},{SR18,7,7} */
201 #define P880_IGA1_FIFO_HIGH_THRESHOLD 64
202 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
203 /* because HW only 5 bits */
204 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
206 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
207 #define P880_IGA2_FIFO_MAX_DEPTH 96
208 /* location: {CR68,0,3},{CR95,4,6} */
209 #define P880_IGA2_FIFO_THRESHOLD 64
210 /* location: {CR92,0,3},{CR95,0,2} */
211 #define P880_IGA2_FIFO_HIGH_THRESHOLD 32
212 /* location: {CR94,0,6} */
213 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
217 /* location: {SR17,0,7} */
218 #define CN700_IGA1_FIFO_MAX_DEPTH 96
219 /* location: {SR16,0,5},{SR16,7,7} */
220 #define CN700_IGA1_FIFO_THRESHOLD 80
221 /* location: {SR18,0,5},{SR18,7,7} */
222 #define CN700_IGA1_FIFO_HIGH_THRESHOLD 64
223 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
224 because HW only 5 bits */
225 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
226 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
227 #define CN700_IGA2_FIFO_MAX_DEPTH 96
228 /* location: {CR68,0,3},{CR95,4,6} */
229 #define CN700_IGA2_FIFO_THRESHOLD 80
230 /* location: {CR92,0,3},{CR95,0,2} */
231 #define CN700_IGA2_FIFO_HIGH_THRESHOLD 32
232 /* location: {CR94,0,6} */
233 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
235 /* For VT3324, these values are suggested by HW */
236 /* location: {SR17,0,7} */
237 #define CX700_IGA1_FIFO_MAX_DEPTH 192
238 /* location: {SR16,0,5},{SR16,7,7} */
239 #define CX700_IGA1_FIFO_THRESHOLD 128
240 /* location: {SR18,0,5},{SR18,7,7} */
241 #define CX700_IGA1_FIFO_HIGH_THRESHOLD 128
242 /* location: {SR22,0,4} */
243 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124
245 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
246 #define CX700_IGA2_FIFO_MAX_DEPTH 96
247 /* location: {CR68,0,3},{CR95,4,6} */
248 #define CX700_IGA2_FIFO_THRESHOLD 64
249 /* location: {CR92,0,3},{CR95,0,2} */
250 #define CX700_IGA2_FIFO_HIGH_THRESHOLD 32
251 /* location: {CR94,0,6} */
252 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
255 /* location: {SR17,0,7} */
256 #define K8M890_IGA1_FIFO_MAX_DEPTH 360
257 /* location: {SR16,0,5},{SR16,7,7} */
258 #define K8M890_IGA1_FIFO_THRESHOLD 328
259 /* location: {SR18,0,5},{SR18,7,7} */
260 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD 296
261 /* location: {SR22,0,4}. */
262 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124
264 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
265 #define K8M890_IGA2_FIFO_MAX_DEPTH 360
266 /* location: {CR68,0,3},{CR95,4,6} */
267 #define K8M890_IGA2_FIFO_THRESHOLD 328
268 /* location: {CR92,0,3},{CR95,0,2} */
269 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD 296
270 /* location: {CR94,0,6} */
271 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 124
274 /* location: {SR17,0,7} */
275 #define P4M890_IGA1_FIFO_MAX_DEPTH 96
276 /* location: {SR16,0,5},{SR16,7,7} */
277 #define P4M890_IGA1_FIFO_THRESHOLD 76
278 /* location: {SR18,0,5},{SR18,7,7} */
279 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD 64
280 /* location: {SR22,0,4}. (32/4) =8 */
281 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32
282 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
283 #define P4M890_IGA2_FIFO_MAX_DEPTH 96
284 /* location: {CR68,0,3},{CR95,4,6} */
285 #define P4M890_IGA2_FIFO_THRESHOLD 76
286 /* location: {CR92,0,3},{CR95,0,2} */
287 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD 64
288 /* location: {CR94,0,6} */
289 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32
292 /* location: {SR17,0,7} */
293 #define P4M900_IGA1_FIFO_MAX_DEPTH 96
294 /* location: {SR16,0,5},{SR16,7,7} */
295 #define P4M900_IGA1_FIFO_THRESHOLD 76
296 /* location: {SR18,0,5},{SR18,7,7} */
297 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD 76
298 /* location: {SR22,0,4}. */
299 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32
300 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
301 #define P4M900_IGA2_FIFO_MAX_DEPTH 96
302 /* location: {CR68,0,3},{CR95,4,6} */
303 #define P4M900_IGA2_FIFO_THRESHOLD 76
304 /* location: {CR92,0,3},{CR95,0,2} */
305 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD 76
306 /* location: {CR94,0,6} */
307 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32
309 /* For VT3353, these values are suggested by HW */
310 /* location: {SR17,0,7} */
311 #define VX800_IGA1_FIFO_MAX_DEPTH 192
312 /* location: {SR16,0,5},{SR16,7,7} */
313 #define VX800_IGA1_FIFO_THRESHOLD 152
314 /* location: {SR18,0,5},{SR18,7,7} */
315 #define VX800_IGA1_FIFO_HIGH_THRESHOLD 152
316 /* location: {SR22,0,4} */
317 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 64
318 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
319 #define VX800_IGA2_FIFO_MAX_DEPTH 96
320 /* location: {CR68,0,3},{CR95,4,6} */
321 #define VX800_IGA2_FIFO_THRESHOLD 64
322 /* location: {CR92,0,3},{CR95,0,2} */
323 #define VX800_IGA2_FIFO_HIGH_THRESHOLD 32
324 /* location: {CR94,0,6} */
325 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
327 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
328 #define IGA1_FIFO_THRESHOLD_REG_NUM 2
329 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
330 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
332 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM 3
333 #define IGA2_FIFO_THRESHOLD_REG_NUM 2
334 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM 2
335 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
337 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) ((x/2)-1)
338 #define IGA1_FIFO_THRESHOLD_FORMULA(x) (x/4)
339 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
340 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
341 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) (((x/2)/4)-1)
342 #define IGA2_FIFO_THRESHOLD_FORMULA(x) (x/4)
343 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
344 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
346 /************************************************************************/
348 /************************************************************************/
350 /* 500 ms = 500000 us */
351 #define LCD_POWER_SEQ_TD0 500000
352 /* 50 ms = 50000 us */
353 #define LCD_POWER_SEQ_TD1 50000
355 #define LCD_POWER_SEQ_TD2 0
356 /* 210 ms = 210000 us */
357 #define LCD_POWER_SEQ_TD3 210000
358 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
359 #define CLE266_POWER_SEQ_UNIT 71
360 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
361 #define K800_POWER_SEQ_UNIT 142
362 /* 2^13 * (1/14.31818M) = 572.1 us */
363 #define P880_POWER_SEQ_UNIT 572
365 #define CLE266_POWER_SEQ_FORMULA(x) ((x)/CLE266_POWER_SEQ_UNIT)
366 #define K800_POWER_SEQ_FORMULA(x) ((x)/K800_POWER_SEQ_UNIT)
367 #define P880_POWER_SEQ_FORMULA(x) ((x)/P880_POWER_SEQ_UNIT)
369 /* location: {CR8B,0,7},{CR8F,0,3} */
370 #define LCD_POWER_SEQ_TD0_REG_NUM 2
371 /* location: {CR8C,0,7},{CR8F,4,7} */
372 #define LCD_POWER_SEQ_TD1_REG_NUM 2
373 /* location: {CR8D,0,7},{CR90,0,3} */
374 #define LCD_POWER_SEQ_TD2_REG_NUM 2
375 /* location: {CR8E,0,7},{CR90,4,7} */
376 #define LCD_POWER_SEQ_TD3_REG_NUM 2
378 /* LCD Scaling factor*/
379 /* x: indicate setting horizontal size*/
380 /* y: indicate panel horizontal size*/
382 /* Horizontal scaling factor 10 bits (2^10) */
383 #define CLE266_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1))
384 /* Vertical scaling factor 10 bits (2^10) */
385 #define CLE266_LCD_VER_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1))
386 /* Horizontal scaling factor 10 bits (2^12) */
387 #define K800_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*4096)/(y-1))
388 /* Vertical scaling factor 10 bits (2^11) */
389 #define K800_LCD_VER_SCF_FORMULA(x, y) (((x-1)*2048)/(y-1))
391 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
392 #define LCD_HOR_SCALING_FACTOR_REG_NUM 3
393 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
394 #define LCD_VER_SCALING_FACTOR_REG_NUM 3
395 /* location: {CR77,0,7},{CR79,4,5} */
396 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE 2
397 /* location: {CR78,0,7},{CR79,6,7} */
398 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2
400 /************************************************
401 ***** Define IGA1 Display Timing *****
402 ************************************************/
409 /* IGA1 Horizontal Total */
410 struct iga1_hor_total
{
412 struct io_register reg
[IGA1_HOR_TOTAL_REG_NUM
];
415 /* IGA1 Horizontal Addressable Video */
416 struct iga1_hor_addr
{
418 struct io_register reg
[IGA1_HOR_ADDR_REG_NUM
];
421 /* IGA1 Horizontal Blank Start */
422 struct iga1_hor_blank_start
{
424 struct io_register reg
[IGA1_HOR_BLANK_START_REG_NUM
];
427 /* IGA1 Horizontal Blank End */
428 struct iga1_hor_blank_end
{
430 struct io_register reg
[IGA1_HOR_BLANK_END_REG_NUM
];
433 /* IGA1 Horizontal Sync Start */
434 struct iga1_hor_sync_start
{
436 struct io_register reg
[IGA1_HOR_SYNC_START_REG_NUM
];
439 /* IGA1 Horizontal Sync End */
440 struct iga1_hor_sync_end
{
442 struct io_register reg
[IGA1_HOR_SYNC_END_REG_NUM
];
445 /* IGA1 Vertical Total */
446 struct iga1_ver_total
{
448 struct io_register reg
[IGA1_VER_TOTAL_REG_NUM
];
451 /* IGA1 Vertical Addressable Video */
452 struct iga1_ver_addr
{
454 struct io_register reg
[IGA1_VER_ADDR_REG_NUM
];
457 /* IGA1 Vertical Blank Start */
458 struct iga1_ver_blank_start
{
460 struct io_register reg
[IGA1_VER_BLANK_START_REG_NUM
];
463 /* IGA1 Vertical Blank End */
464 struct iga1_ver_blank_end
{
466 struct io_register reg
[IGA1_VER_BLANK_END_REG_NUM
];
469 /* IGA1 Vertical Sync Start */
470 struct iga1_ver_sync_start
{
472 struct io_register reg
[IGA1_VER_SYNC_START_REG_NUM
];
475 /* IGA1 Vertical Sync End */
476 struct iga1_ver_sync_end
{
478 struct io_register reg
[IGA1_VER_SYNC_END_REG_NUM
];
481 /*****************************************************
482 ** Define IGA2 Shadow Display Timing ****
483 *****************************************************/
485 /* IGA2 Shadow Horizontal Total */
486 struct iga2_shadow_hor_total
{
488 struct io_register reg
[IGA2_SHADOW_HOR_TOTAL_REG_NUM
];
491 /* IGA2 Shadow Horizontal Blank End */
492 struct iga2_shadow_hor_blank_end
{
494 struct io_register reg
[IGA2_SHADOW_HOR_BLANK_END_REG_NUM
];
497 /* IGA2 Shadow Vertical Total */
498 struct iga2_shadow_ver_total
{
500 struct io_register reg
[IGA2_SHADOW_VER_TOTAL_REG_NUM
];
503 /* IGA2 Shadow Vertical Addressable Video */
504 struct iga2_shadow_ver_addr
{
506 struct io_register reg
[IGA2_SHADOW_VER_ADDR_REG_NUM
];
509 /* IGA2 Shadow Vertical Blank Start */
510 struct iga2_shadow_ver_blank_start
{
512 struct io_register reg
[IGA2_SHADOW_VER_BLANK_START_REG_NUM
];
515 /* IGA2 Shadow Vertical Blank End */
516 struct iga2_shadow_ver_blank_end
{
518 struct io_register reg
[IGA2_SHADOW_VER_BLANK_END_REG_NUM
];
521 /* IGA2 Shadow Vertical Sync Start */
522 struct iga2_shadow_ver_sync_start
{
524 struct io_register reg
[IGA2_SHADOW_VER_SYNC_START_REG_NUM
];
527 /* IGA2 Shadow Vertical Sync End */
528 struct iga2_shadow_ver_sync_end
{
530 struct io_register reg
[IGA2_SHADOW_VER_SYNC_END_REG_NUM
];
533 /*****************************************************
534 ** Define IGA2 Display Timing ****
535 ******************************************************/
537 /* IGA2 Horizontal Total */
538 struct iga2_hor_total
{
540 struct io_register reg
[IGA2_HOR_TOTAL_REG_NUM
];
543 /* IGA2 Horizontal Addressable Video */
544 struct iga2_hor_addr
{
546 struct io_register reg
[IGA2_HOR_ADDR_REG_NUM
];
549 /* IGA2 Horizontal Blank Start */
550 struct iga2_hor_blank_start
{
552 struct io_register reg
[IGA2_HOR_BLANK_START_REG_NUM
];
555 /* IGA2 Horizontal Blank End */
556 struct iga2_hor_blank_end
{
558 struct io_register reg
[IGA2_HOR_BLANK_END_REG_NUM
];
561 /* IGA2 Horizontal Sync Start */
562 struct iga2_hor_sync_start
{
564 struct io_register reg
[IGA2_HOR_SYNC_START_REG_NUM
];
567 /* IGA2 Horizontal Sync End */
568 struct iga2_hor_sync_end
{
570 struct io_register reg
[IGA2_HOR_SYNC_END_REG_NUM
];
573 /* IGA2 Vertical Total */
574 struct iga2_ver_total
{
576 struct io_register reg
[IGA2_VER_TOTAL_REG_NUM
];
579 /* IGA2 Vertical Addressable Video */
580 struct iga2_ver_addr
{
582 struct io_register reg
[IGA2_VER_ADDR_REG_NUM
];
585 /* IGA2 Vertical Blank Start */
586 struct iga2_ver_blank_start
{
588 struct io_register reg
[IGA2_VER_BLANK_START_REG_NUM
];
591 /* IGA2 Vertical Blank End */
592 struct iga2_ver_blank_end
{
594 struct io_register reg
[IGA2_VER_BLANK_END_REG_NUM
];
597 /* IGA2 Vertical Sync Start */
598 struct iga2_ver_sync_start
{
600 struct io_register reg
[IGA2_VER_SYNC_START_REG_NUM
];
603 /* IGA2 Vertical Sync End */
604 struct iga2_ver_sync_end
{
606 struct io_register reg
[IGA2_VER_SYNC_END_REG_NUM
];
609 /* IGA1 Fetch Count Register */
610 struct iga1_fetch_count
{
612 struct io_register reg
[IGA1_FETCH_COUNT_REG_NUM
];
615 /* IGA2 Fetch Count Register */
616 struct iga2_fetch_count
{
618 struct io_register reg
[IGA2_FETCH_COUNT_REG_NUM
];
622 struct iga1_fetch_count iga1_fetch_count_reg
;
623 struct iga2_fetch_count iga2_fetch_count_reg
;
626 /* Starting Address Register */
627 struct iga1_starting_addr
{
629 struct io_register reg
[IGA1_STARTING_ADDR_REG_NUM
];
632 struct iga2_starting_addr
{
634 struct io_register reg
[IGA2_STARTING_ADDR_REG_NUM
];
637 struct starting_addr
{
638 struct iga1_starting_addr iga1_starting_addr_reg
;
639 struct iga2_starting_addr iga2_starting_addr_reg
;
642 /* LCD Power Sequence Timer */
643 struct lcd_pwd_seq_td0
{
645 struct io_register reg
[LCD_POWER_SEQ_TD0_REG_NUM
];
648 struct lcd_pwd_seq_td1
{
650 struct io_register reg
[LCD_POWER_SEQ_TD1_REG_NUM
];
653 struct lcd_pwd_seq_td2
{
655 struct io_register reg
[LCD_POWER_SEQ_TD2_REG_NUM
];
658 struct lcd_pwd_seq_td3
{
660 struct io_register reg
[LCD_POWER_SEQ_TD3_REG_NUM
];
663 struct _lcd_pwd_seq_timer
{
664 struct lcd_pwd_seq_td0 td0
;
665 struct lcd_pwd_seq_td1 td1
;
666 struct lcd_pwd_seq_td2 td2
;
667 struct lcd_pwd_seq_td3 td3
;
670 /* LCD Scaling Factor */
671 struct _lcd_hor_scaling_factor
{
673 struct io_register reg
[LCD_HOR_SCALING_FACTOR_REG_NUM
];
676 struct _lcd_ver_scaling_factor
{
678 struct io_register reg
[LCD_VER_SCALING_FACTOR_REG_NUM
];
681 struct _lcd_scaling_factor
{
682 struct _lcd_hor_scaling_factor lcd_hor_scaling_factor
;
683 struct _lcd_ver_scaling_factor lcd_ver_scaling_factor
;
699 struct lcd_pwd_seq_timer
{
706 /* Display FIFO Relation Registers*/
707 struct iga1_fifo_depth_select
{
709 struct io_register reg
[IGA1_FIFO_DEPTH_SELECT_REG_NUM
];
712 struct iga1_fifo_threshold_select
{
714 struct io_register reg
[IGA1_FIFO_THRESHOLD_REG_NUM
];
717 struct iga1_fifo_high_threshold_select
{
719 struct io_register reg
[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM
];
722 struct iga1_display_queue_expire_num
{
724 struct io_register reg
[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM
];
727 struct iga2_fifo_depth_select
{
729 struct io_register reg
[IGA2_FIFO_DEPTH_SELECT_REG_NUM
];
732 struct iga2_fifo_threshold_select
{
734 struct io_register reg
[IGA2_FIFO_THRESHOLD_REG_NUM
];
737 struct iga2_fifo_high_threshold_select
{
739 struct io_register reg
[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM
];
742 struct iga2_display_queue_expire_num
{
744 struct io_register reg
[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM
];
747 struct fifo_depth_select
{
748 struct iga1_fifo_depth_select iga1_fifo_depth_select_reg
;
749 struct iga2_fifo_depth_select iga2_fifo_depth_select_reg
;
752 struct fifo_threshold_select
{
753 struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg
;
754 struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg
;
757 struct fifo_high_threshold_select
{
758 struct iga1_fifo_high_threshold_select
759 iga1_fifo_high_threshold_select_reg
;
760 struct iga2_fifo_high_threshold_select
761 iga2_fifo_high_threshold_select_reg
;
764 struct display_queue_expire_num
{
765 struct iga1_display_queue_expire_num
766 iga1_display_queue_expire_num_reg
;
767 struct iga2_display_queue_expire_num
768 iga2_display_queue_expire_num_reg
;
771 struct iga1_crtc_timing
{
772 struct iga1_hor_total hor_total
;
773 struct iga1_hor_addr hor_addr
;
774 struct iga1_hor_blank_start hor_blank_start
;
775 struct iga1_hor_blank_end hor_blank_end
;
776 struct iga1_hor_sync_start hor_sync_start
;
777 struct iga1_hor_sync_end hor_sync_end
;
778 struct iga1_ver_total ver_total
;
779 struct iga1_ver_addr ver_addr
;
780 struct iga1_ver_blank_start ver_blank_start
;
781 struct iga1_ver_blank_end ver_blank_end
;
782 struct iga1_ver_sync_start ver_sync_start
;
783 struct iga1_ver_sync_end ver_sync_end
;
786 struct iga2_shadow_crtc_timing
{
787 struct iga2_shadow_hor_total hor_total_shadow
;
788 struct iga2_shadow_hor_blank_end hor_blank_end_shadow
;
789 struct iga2_shadow_ver_total ver_total_shadow
;
790 struct iga2_shadow_ver_addr ver_addr_shadow
;
791 struct iga2_shadow_ver_blank_start ver_blank_start_shadow
;
792 struct iga2_shadow_ver_blank_end ver_blank_end_shadow
;
793 struct iga2_shadow_ver_sync_start ver_sync_start_shadow
;
794 struct iga2_shadow_ver_sync_end ver_sync_end_shadow
;
797 struct iga2_crtc_timing
{
798 struct iga2_hor_total hor_total
;
799 struct iga2_hor_addr hor_addr
;
800 struct iga2_hor_blank_start hor_blank_start
;
801 struct iga2_hor_blank_end hor_blank_end
;
802 struct iga2_hor_sync_start hor_sync_start
;
803 struct iga2_hor_sync_end hor_sync_end
;
804 struct iga2_ver_total ver_total
;
805 struct iga2_ver_addr ver_addr
;
806 struct iga2_ver_blank_start ver_blank_start
;
807 struct iga2_ver_blank_end ver_blank_end
;
808 struct iga2_ver_sync_start ver_sync_start
;
809 struct iga2_ver_sync_end ver_sync_end
;
813 #define CLE266 0x3123
815 #define CN400_FUNCTION2 0x2259
816 #define CN400_FUNCTION3 0x3259
817 /* support VT3314 chipset */
818 #define CN700_FUNCTION2 0x2314
819 #define CN700_FUNCTION3 0x3208
821 #define CX700_FUNCTION2 0x2324
822 #define CX700_FUNCTION3 0x3324
824 #define KM800_FUNCTION3 0x3204
826 #define KM890_FUNCTION3 0x3336
828 #define P4M890_FUNCTION3 0x3327
830 #define CN750_FUNCTION3 0x3208
832 #define P4M900_FUNCTION3 0x3364
834 #define VX800_FUNCTION3 0x3353
836 #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
844 struct pci_device_id_info
{
850 extern unsigned int viafb_second_virtual_xres
;
851 extern unsigned int viafb_second_offset
;
852 extern int viafb_second_size
;
853 extern int viafb_SAMM_ON
;
854 extern int viafb_dual_fb
;
855 extern int viafb_LCD2_ON
;
856 extern int viafb_LCD_ON
;
857 extern int viafb_DVI_ON
;
858 extern int viafb_hotplug
;
860 void viafb_write_reg_mask(u8 index
, int io_port
, u8 data
, u8 mask
);
861 void viafb_set_output_path(int device
, int set_iga
,
862 int output_interface
);
863 void viafb_fill_crtc_timing(struct crt_mode_table
*crt_table
,
864 int mode_index
, int bpp_byte
, int set_iga
);
866 void viafb_set_vclock(u32 CLK
, int set_iga
);
867 void viafb_load_reg(int timing_value
, int viafb_load_reg_num
,
868 struct io_register
*reg
,
870 void viafb_crt_disable(void);
871 void viafb_crt_enable(void);
872 void init_ad9389(void);
873 /* Access I/O Function */
874 void viafb_write_reg(u8 index
, u16 io_port
, u8 data
);
875 u8
viafb_read_reg(int io_port
, u8 index
);
876 void viafb_lock_crt(void);
877 void viafb_unlock_crt(void);
878 void viafb_load_fetch_count_reg(int h_addr
, int bpp_byte
, int set_iga
);
879 void viafb_write_regx(struct io_reg RegTable
[], int ItemNum
);
880 struct VideoModeTable
*viafb_get_modetbl_pointer(int Index
);
881 u32
viafb_get_clk_value(int clk
);
882 void viafb_load_FIFO_reg(int set_iga
, int hor_active
, int ver_active
);
883 void viafb_set_color_depth(int bpp_byte
, int set_iga
);
884 void viafb_set_dpa_gfx(int output_interface
, struct GFX_DPA_SETTING\
887 int viafb_setmode(int vmode_index
, int hor_res
, int ver_res
,
888 int video_bpp
, int vmode_index1
, int hor_res1
,
889 int ver_res1
, int video_bpp1
);
890 void viafb_init_chip_info(void);
891 void viafb_init_dac(int set_iga
);
892 int viafb_get_pixclock(int hres
, int vres
, int vmode_refresh
);
893 int viafb_get_refresh(int hres
, int vres
, u32 float_refresh
);
894 void viafb_update_device_setting(int hres
, int vres
, int bpp
,
895 int vmode_refresh
, int flag
);
896 void viafb_get_mmio_info(unsigned long *mmio_base
, u32
*mmio_len
);
898 void viafb_set_iga_path(void);
899 void viafb_set_primary_address(u32 addr
);
900 void viafb_set_secondary_address(u32 addr
);
901 void viafb_set_primary_pitch(u32 pitch
);
902 void viafb_set_secondary_pitch(u32 pitch
);
903 void viafb_get_fb_info(unsigned int *fb_base
, unsigned int *fb_len
);
905 #endif /* __HW_H__ */