2 * processor_idle - idle state submodule to the ACPI processor driver
4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de>
7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
8 * - Added processor hotplug support
9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
10 * - Added support for C3 on SMP
12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or (at
17 * your option) any later version.
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/cpufreq.h>
35 #include <linux/proc_fs.h>
36 #include <linux/seq_file.h>
37 #include <linux/acpi.h>
38 #include <linux/dmi.h>
39 #include <linux/moduleparam.h>
40 #include <linux/sched.h> /* need_resched() */
41 #include <linux/pm_qos_params.h>
42 #include <linux/clockchips.h>
43 #include <linux/cpuidle.h>
44 #include <linux/irqflags.h>
47 * Include the apic definitions for x86 to have the APIC timer related defines
48 * available also for UP (on SMP it gets magically included via linux/smp.h).
49 * asm/acpi.h is not an option, as it would require more include magic. Also
50 * creating an empty asm-ia64/apic.h would just trade pest vs. cholera.
57 #include <asm/uaccess.h>
59 #include <acpi/acpi_bus.h>
60 #include <acpi/processor.h>
61 #include <asm/processor.h>
63 #define ACPI_PROCESSOR_CLASS "processor"
64 #define _COMPONENT ACPI_PROCESSOR_COMPONENT
65 ACPI_MODULE_NAME("processor_idle");
66 #define ACPI_PROCESSOR_FILE_POWER "power"
67 #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000)
68 #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY)
69 #ifndef CONFIG_CPU_IDLE
70 #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */
71 #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */
72 static void (*pm_idle_save
) (void) __read_mostly
;
74 #define C2_OVERHEAD 1 /* 1us */
75 #define C3_OVERHEAD 1 /* 1us */
77 #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000))
79 static unsigned int max_cstate __read_mostly
= ACPI_PROCESSOR_MAX_POWER
;
80 #ifdef CONFIG_CPU_IDLE
81 module_param(max_cstate
, uint
, 0000);
83 module_param(max_cstate
, uint
, 0644);
85 static unsigned int nocst __read_mostly
;
86 module_param(nocst
, uint
, 0000);
88 #ifndef CONFIG_CPU_IDLE
90 * bm_history -- bit-mask with a bit per jiffy of bus-master activity
91 * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms
92 * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms
93 * 100 HZ: 0x0000000F: 4 jiffies = 40ms
94 * reduce history for more aggressive entry into C3
96 static unsigned int bm_history __read_mostly
=
97 (HZ
>= 800 ? 0xFFFFFFFF : ((1U << (HZ
/ 25)) - 1));
98 module_param(bm_history
, uint
, 0644);
100 static int acpi_processor_set_power_policy(struct acpi_processor
*pr
);
102 #else /* CONFIG_CPU_IDLE */
103 static unsigned int latency_factor __read_mostly
= 2;
104 module_param(latency_factor
, uint
, 0644);
108 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
109 * For now disable this. Probably a bug somewhere else.
111 * To skip this limit, boot/load with a large max_cstate limit.
113 static int set_max_cstate(const struct dmi_system_id
*id
)
115 if (max_cstate
> ACPI_PROCESSOR_MAX_POWER
)
118 printk(KERN_NOTICE PREFIX
"%s detected - limiting to C%ld max_cstate."
119 " Override with \"processor.max_cstate=%d\"\n", id
->ident
,
120 (long)id
->driver_data
, ACPI_PROCESSOR_MAX_POWER
+ 1);
122 max_cstate
= (long)id
->driver_data
;
127 /* Actually this shouldn't be __cpuinitdata, would be better to fix the
128 callers to only run once -AK */
129 static struct dmi_system_id __cpuinitdata processor_power_dmi_table
[] = {
130 { set_max_cstate
, "IBM ThinkPad R40e", {
131 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
132 DMI_MATCH(DMI_BIOS_VERSION
,"1SET70WW")}, (void *)1},
133 { set_max_cstate
, "IBM ThinkPad R40e", {
134 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
135 DMI_MATCH(DMI_BIOS_VERSION
,"1SET60WW")}, (void *)1},
136 { set_max_cstate
, "IBM ThinkPad R40e", {
137 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
138 DMI_MATCH(DMI_BIOS_VERSION
,"1SET43WW") }, (void*)1},
139 { set_max_cstate
, "IBM ThinkPad R40e", {
140 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
141 DMI_MATCH(DMI_BIOS_VERSION
,"1SET45WW") }, (void*)1},
142 { set_max_cstate
, "IBM ThinkPad R40e", {
143 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
144 DMI_MATCH(DMI_BIOS_VERSION
,"1SET47WW") }, (void*)1},
145 { set_max_cstate
, "IBM ThinkPad R40e", {
146 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
147 DMI_MATCH(DMI_BIOS_VERSION
,"1SET50WW") }, (void*)1},
148 { set_max_cstate
, "IBM ThinkPad R40e", {
149 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
150 DMI_MATCH(DMI_BIOS_VERSION
,"1SET52WW") }, (void*)1},
151 { set_max_cstate
, "IBM ThinkPad R40e", {
152 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
153 DMI_MATCH(DMI_BIOS_VERSION
,"1SET55WW") }, (void*)1},
154 { set_max_cstate
, "IBM ThinkPad R40e", {
155 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
156 DMI_MATCH(DMI_BIOS_VERSION
,"1SET56WW") }, (void*)1},
157 { set_max_cstate
, "IBM ThinkPad R40e", {
158 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
159 DMI_MATCH(DMI_BIOS_VERSION
,"1SET59WW") }, (void*)1},
160 { set_max_cstate
, "IBM ThinkPad R40e", {
161 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
162 DMI_MATCH(DMI_BIOS_VERSION
,"1SET60WW") }, (void*)1},
163 { set_max_cstate
, "IBM ThinkPad R40e", {
164 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
165 DMI_MATCH(DMI_BIOS_VERSION
,"1SET61WW") }, (void*)1},
166 { set_max_cstate
, "IBM ThinkPad R40e", {
167 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
168 DMI_MATCH(DMI_BIOS_VERSION
,"1SET62WW") }, (void*)1},
169 { set_max_cstate
, "IBM ThinkPad R40e", {
170 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
171 DMI_MATCH(DMI_BIOS_VERSION
,"1SET64WW") }, (void*)1},
172 { set_max_cstate
, "IBM ThinkPad R40e", {
173 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
174 DMI_MATCH(DMI_BIOS_VERSION
,"1SET65WW") }, (void*)1},
175 { set_max_cstate
, "IBM ThinkPad R40e", {
176 DMI_MATCH(DMI_BIOS_VENDOR
,"IBM"),
177 DMI_MATCH(DMI_BIOS_VERSION
,"1SET68WW") }, (void*)1},
178 { set_max_cstate
, "Medion 41700", {
179 DMI_MATCH(DMI_BIOS_VENDOR
,"Phoenix Technologies LTD"),
180 DMI_MATCH(DMI_BIOS_VERSION
,"R01-A1J")}, (void *)1},
181 { set_max_cstate
, "Clevo 5600D", {
182 DMI_MATCH(DMI_BIOS_VENDOR
,"Phoenix Technologies LTD"),
183 DMI_MATCH(DMI_BIOS_VERSION
,"SHE845M0.86C.0013.D.0302131307")},
188 static inline u32
ticks_elapsed(u32 t1
, u32 t2
)
192 else if (!(acpi_gbl_FADT
.flags
& ACPI_FADT_32BIT_TIMER
))
193 return (((0x00FFFFFF - t1
) + t2
) & 0x00FFFFFF);
195 return ((0xFFFFFFFF - t1
) + t2
);
198 static inline u32
ticks_elapsed_in_us(u32 t1
, u32 t2
)
201 return PM_TIMER_TICKS_TO_US(t2
- t1
);
202 else if (!(acpi_gbl_FADT
.flags
& ACPI_FADT_32BIT_TIMER
))
203 return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1
) + t2
) & 0x00FFFFFF);
205 return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1
) + t2
);
209 * Callers should disable interrupts before the call and enable
210 * interrupts after return.
212 static void acpi_safe_halt(void)
214 current_thread_info()->status
&= ~TS_POLLING
;
216 * TS_POLLING-cleared state must be visible before we
220 if (!need_resched()) {
224 current_thread_info()->status
|= TS_POLLING
;
227 #ifndef CONFIG_CPU_IDLE
230 acpi_processor_power_activate(struct acpi_processor
*pr
,
231 struct acpi_processor_cx
*new)
233 struct acpi_processor_cx
*old
;
238 old
= pr
->power
.state
;
241 old
->promotion
.count
= 0;
242 new->demotion
.count
= 0;
244 pr
->power
.state
= new;
249 static atomic_t c3_cpu_count
;
251 /* Common C-state entry for C2, C3, .. */
252 static void acpi_cstate_enter(struct acpi_processor_cx
*cstate
)
254 /* Don't trace irqs off for idle */
255 stop_critical_timings();
256 if (cstate
->entry_method
== ACPI_CSTATE_FFH
) {
257 /* Call into architectural FFH based C-state */
258 acpi_processor_ffh_cstate_enter(cstate
);
261 /* IO port based C-state */
262 inb(cstate
->address
);
263 /* Dummy wait op - must do something useless after P_LVL2 read
264 because chipsets cannot guarantee that STPCLK# signal
265 gets asserted in time to freeze execution properly. */
266 unused
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
268 start_critical_timings();
270 #endif /* !CONFIG_CPU_IDLE */
272 #ifdef ARCH_APICTIMER_STOPS_ON_C3
275 * Some BIOS implementations switch to C3 in the published C2 state.
276 * This seems to be a common problem on AMD boxen, but other vendors
277 * are affected too. We pick the most conservative approach: we assume
278 * that the local APIC stops in both C2 and C3.
280 static void acpi_timer_check_state(int state
, struct acpi_processor
*pr
,
281 struct acpi_processor_cx
*cx
)
283 struct acpi_processor_power
*pwr
= &pr
->power
;
284 u8 type
= local_apic_timer_c2_ok
? ACPI_STATE_C3
: ACPI_STATE_C2
;
287 * Check, if one of the previous states already marked the lapic
290 if (pwr
->timer_broadcast_on_state
< state
)
293 if (cx
->type
>= type
)
294 pr
->power
.timer_broadcast_on_state
= state
;
297 static void acpi_propagate_timer_broadcast(struct acpi_processor
*pr
)
299 unsigned long reason
;
301 reason
= pr
->power
.timer_broadcast_on_state
< INT_MAX
?
302 CLOCK_EVT_NOTIFY_BROADCAST_ON
: CLOCK_EVT_NOTIFY_BROADCAST_OFF
;
304 clockevents_notify(reason
, &pr
->id
);
307 /* Power(C) State timer broadcast control */
308 static void acpi_state_timer_broadcast(struct acpi_processor
*pr
,
309 struct acpi_processor_cx
*cx
,
312 int state
= cx
- pr
->power
.states
;
314 if (state
>= pr
->power
.timer_broadcast_on_state
) {
315 unsigned long reason
;
317 reason
= broadcast
? CLOCK_EVT_NOTIFY_BROADCAST_ENTER
:
318 CLOCK_EVT_NOTIFY_BROADCAST_EXIT
;
319 clockevents_notify(reason
, &pr
->id
);
325 static void acpi_timer_check_state(int state
, struct acpi_processor
*pr
,
326 struct acpi_processor_cx
*cstate
) { }
327 static void acpi_propagate_timer_broadcast(struct acpi_processor
*pr
) { }
328 static void acpi_state_timer_broadcast(struct acpi_processor
*pr
,
329 struct acpi_processor_cx
*cx
,
337 * Suspend / resume control
339 static int acpi_idle_suspend
;
341 int acpi_processor_suspend(struct acpi_device
* device
, pm_message_t state
)
343 acpi_idle_suspend
= 1;
347 int acpi_processor_resume(struct acpi_device
* device
)
349 acpi_idle_suspend
= 0;
353 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
354 static int tsc_halts_in_c(int state
)
356 switch (boot_cpu_data
.x86_vendor
) {
358 case X86_VENDOR_INTEL
:
360 * AMD Fam10h TSC will tick in all
361 * C/P/S0/S1 states when this bit is set.
363 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
368 return state
> ACPI_STATE_C1
;
373 #ifndef CONFIG_CPU_IDLE
374 static void acpi_processor_idle(void)
376 struct acpi_processor
*pr
= NULL
;
377 struct acpi_processor_cx
*cx
= NULL
;
378 struct acpi_processor_cx
*next_state
= NULL
;
383 * Interrupts must be disabled during bus mastering calculations and
384 * for C2/C3 transitions.
388 pr
= __get_cpu_var(processors
);
395 * Check whether we truly need to go idle, or should
398 if (unlikely(need_resched())) {
403 cx
= pr
->power
.state
;
404 if (!cx
|| acpi_idle_suspend
) {
406 pm_idle_save(); /* enables IRQs */
418 * Check for bus mastering activity (if required), record, and check
421 if (pr
->flags
.bm_check
) {
423 unsigned long diff
= jiffies
- pr
->power
.bm_check_timestamp
;
428 pr
->power
.bm_activity
<<= diff
;
430 acpi_get_register_unlocked(ACPI_BITREG_BUS_MASTER_STATUS
, &bm_status
);
432 pr
->power
.bm_activity
|= 0x1;
433 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS
, 1);
436 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
437 * the true state of bus mastering activity; forcing us to
438 * manually check the BMIDEA bit of each IDE channel.
440 else if (errata
.piix4
.bmisx
) {
441 if ((inb_p(errata
.piix4
.bmisx
+ 0x02) & 0x01)
442 || (inb_p(errata
.piix4
.bmisx
+ 0x0A) & 0x01))
443 pr
->power
.bm_activity
|= 0x1;
446 pr
->power
.bm_check_timestamp
= jiffies
;
449 * If bus mastering is or was active this jiffy, demote
450 * to avoid a faulty transition. Note that the processor
451 * won't enter a low-power state during this call (to this
452 * function) but should upon the next.
454 * TBD: A better policy might be to fallback to the demotion
455 * state (use it for this quantum only) istead of
456 * demoting -- and rely on duration as our sole demotion
457 * qualification. This may, however, introduce DMA
458 * issues (e.g. floppy DMA transfer overrun/underrun).
460 if ((pr
->power
.bm_activity
& 0x1) &&
461 cx
->demotion
.threshold
.bm
) {
463 next_state
= cx
->demotion
.state
;
468 #ifdef CONFIG_HOTPLUG_CPU
470 * Check for P_LVL2_UP flag before entering C2 and above on
471 * an SMP system. We do it here instead of doing it at _CST/P_LVL
472 * detection phase, to work cleanly with logical CPU hotplug.
474 if ((cx
->type
!= ACPI_STATE_C1
) && (num_online_cpus() > 1) &&
475 !pr
->flags
.has_cst
&& !(acpi_gbl_FADT
.flags
& ACPI_FADT_C2_MP_SUPPORTED
))
476 cx
= &pr
->power
.states
[ACPI_STATE_C1
];
482 * Invoke the current Cx state to put the processor to sleep.
484 if (cx
->type
== ACPI_STATE_C2
|| cx
->type
== ACPI_STATE_C3
) {
485 current_thread_info()->status
&= ~TS_POLLING
;
487 * TS_POLLING-cleared state must be visible before we
491 if (need_resched()) {
492 current_thread_info()->status
|= TS_POLLING
;
503 * Use the appropriate idle routine, the one that would
504 * be used without acpi C-states.
507 pm_idle_save(); /* enables IRQs */
514 * TBD: Can't get time duration while in C1, as resumes
515 * go to an ISR rather than here. Need to instrument
516 * base interrupt handler.
518 * Note: the TSC better not stop in C1, sched_clock() will
521 sleep_ticks
= 0xFFFFFFFF;
526 /* Get start time (ticks) */
527 t1
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
528 /* Tell the scheduler that we are going deep-idle: */
529 sched_clock_idle_sleep_event();
531 acpi_state_timer_broadcast(pr
, cx
, 1);
532 acpi_cstate_enter(cx
);
533 /* Get end time (ticks) */
534 t2
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
536 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
537 /* TSC halts in C2, so notify users */
538 if (tsc_halts_in_c(ACPI_STATE_C2
))
539 mark_tsc_unstable("possible TSC halt in C2");
541 /* Compute time (ticks) that we were actually asleep */
542 sleep_ticks
= ticks_elapsed(t1
, t2
);
544 /* Tell the scheduler how much we idled: */
545 sched_clock_idle_wakeup_event(sleep_ticks
*PM_TIMER_TICK_NS
);
547 /* Re-enable interrupts */
549 /* Do not account our idle-switching overhead: */
550 sleep_ticks
-= cx
->latency_ticks
+ C2_OVERHEAD
;
552 current_thread_info()->status
|= TS_POLLING
;
553 acpi_state_timer_broadcast(pr
, cx
, 0);
557 acpi_unlazy_tlb(smp_processor_id());
559 * Must be done before busmaster disable as we might
560 * need to access HPET !
562 acpi_state_timer_broadcast(pr
, cx
, 1);
565 * bm_check implies we need ARB_DIS
566 * !bm_check implies we need cache flush
567 * bm_control implies whether we can do ARB_DIS
569 * That leaves a case where bm_check is set and bm_control is
570 * not set. In that case we cannot do much, we enter C3
571 * without doing anything.
573 if (pr
->flags
.bm_check
&& pr
->flags
.bm_control
) {
574 if (atomic_inc_return(&c3_cpu_count
) ==
577 * All CPUs are trying to go to C3
578 * Disable bus master arbitration
580 acpi_set_register(ACPI_BITREG_ARB_DISABLE
, 1);
582 } else if (!pr
->flags
.bm_check
) {
583 /* SMP with no shared cache... Invalidate cache */
584 ACPI_FLUSH_CPU_CACHE();
587 /* Get start time (ticks) */
588 t1
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
590 /* Tell the scheduler that we are going deep-idle: */
591 sched_clock_idle_sleep_event();
592 acpi_cstate_enter(cx
);
593 /* Get end time (ticks) */
594 t2
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
595 if (pr
->flags
.bm_check
&& pr
->flags
.bm_control
) {
596 /* Enable bus master arbitration */
597 atomic_dec(&c3_cpu_count
);
598 acpi_set_register(ACPI_BITREG_ARB_DISABLE
, 0);
601 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
602 /* TSC halts in C3, so notify users */
603 if (tsc_halts_in_c(ACPI_STATE_C3
))
604 mark_tsc_unstable("TSC halts in C3");
606 /* Compute time (ticks) that we were actually asleep */
607 sleep_ticks
= ticks_elapsed(t1
, t2
);
608 /* Tell the scheduler how much we idled: */
609 sched_clock_idle_wakeup_event(sleep_ticks
*PM_TIMER_TICK_NS
);
611 /* Re-enable interrupts */
613 /* Do not account our idle-switching overhead: */
614 sleep_ticks
-= cx
->latency_ticks
+ C3_OVERHEAD
;
616 current_thread_info()->status
|= TS_POLLING
;
617 acpi_state_timer_broadcast(pr
, cx
, 0);
625 if ((cx
->type
!= ACPI_STATE_C1
) && (sleep_ticks
> 0))
626 cx
->time
+= sleep_ticks
;
628 next_state
= pr
->power
.state
;
630 #ifdef CONFIG_HOTPLUG_CPU
631 /* Don't do promotion/demotion */
632 if ((cx
->type
== ACPI_STATE_C1
) && (num_online_cpus() > 1) &&
633 !pr
->flags
.has_cst
&& !(acpi_gbl_FADT
.flags
& ACPI_FADT_C2_MP_SUPPORTED
)) {
642 * Track the number of longs (time asleep is greater than threshold)
643 * and promote when the count threshold is reached. Note that bus
644 * mastering activity may prevent promotions.
645 * Do not promote above max_cstate.
647 if (cx
->promotion
.state
&&
648 ((cx
->promotion
.state
- pr
->power
.states
) <= max_cstate
)) {
649 if (sleep_ticks
> cx
->promotion
.threshold
.ticks
&&
650 cx
->promotion
.state
->latency
<=
651 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY
)) {
652 cx
->promotion
.count
++;
653 cx
->demotion
.count
= 0;
654 if (cx
->promotion
.count
>=
655 cx
->promotion
.threshold
.count
) {
656 if (pr
->flags
.bm_check
) {
658 (pr
->power
.bm_activity
& cx
->
659 promotion
.threshold
.bm
)) {
665 next_state
= cx
->promotion
.state
;
675 * Track the number of shorts (time asleep is less than time threshold)
676 * and demote when the usage threshold is reached.
678 if (cx
->demotion
.state
) {
679 if (sleep_ticks
< cx
->demotion
.threshold
.ticks
) {
680 cx
->demotion
.count
++;
681 cx
->promotion
.count
= 0;
682 if (cx
->demotion
.count
>= cx
->demotion
.threshold
.count
) {
683 next_state
= cx
->demotion
.state
;
691 * Demote if current state exceeds max_cstate
692 * or if the latency of the current state is unacceptable
694 if ((pr
->power
.state
- pr
->power
.states
) > max_cstate
||
695 pr
->power
.state
->latency
>
696 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY
)) {
697 if (cx
->demotion
.state
)
698 next_state
= cx
->demotion
.state
;
704 * If we're going to start using a new Cx state we must clean up
705 * from the previous and prepare to use the new.
707 if (next_state
!= pr
->power
.state
)
708 acpi_processor_power_activate(pr
, next_state
);
711 static int acpi_processor_set_power_policy(struct acpi_processor
*pr
)
714 unsigned int state_is_set
= 0;
715 struct acpi_processor_cx
*lower
= NULL
;
716 struct acpi_processor_cx
*higher
= NULL
;
717 struct acpi_processor_cx
*cx
;
724 * This function sets the default Cx state policy (OS idle handler).
725 * Our scheme is to promote quickly to C2 but more conservatively
726 * to C3. We're favoring C2 for its characteristics of low latency
727 * (quick response), good power savings, and ability to allow bus
728 * mastering activity. Note that the Cx state policy is completely
729 * customizable and can be altered dynamically.
733 for (i
= 1; i
< ACPI_PROCESSOR_MAX_POWER
; i
++) {
734 cx
= &pr
->power
.states
[i
];
739 pr
->power
.state
= cx
;
748 for (i
= 1; i
< ACPI_PROCESSOR_MAX_POWER
; i
++) {
749 cx
= &pr
->power
.states
[i
];
754 cx
->demotion
.state
= lower
;
755 cx
->demotion
.threshold
.ticks
= cx
->latency_ticks
;
756 cx
->demotion
.threshold
.count
= 1;
757 if (cx
->type
== ACPI_STATE_C3
)
758 cx
->demotion
.threshold
.bm
= bm_history
;
765 for (i
= (ACPI_PROCESSOR_MAX_POWER
- 1); i
> 0; i
--) {
766 cx
= &pr
->power
.states
[i
];
771 cx
->promotion
.state
= higher
;
772 cx
->promotion
.threshold
.ticks
= cx
->latency_ticks
;
773 if (cx
->type
>= ACPI_STATE_C2
)
774 cx
->promotion
.threshold
.count
= 4;
776 cx
->promotion
.threshold
.count
= 10;
777 if (higher
->type
== ACPI_STATE_C3
)
778 cx
->promotion
.threshold
.bm
= bm_history
;
786 #endif /* !CONFIG_CPU_IDLE */
788 static int acpi_processor_get_power_info_fadt(struct acpi_processor
*pr
)
797 /* if info is obtained from pblk/fadt, type equals state */
798 pr
->power
.states
[ACPI_STATE_C2
].type
= ACPI_STATE_C2
;
799 pr
->power
.states
[ACPI_STATE_C3
].type
= ACPI_STATE_C3
;
801 #ifndef CONFIG_HOTPLUG_CPU
803 * Check for P_LVL2_UP flag before entering C2 and above on
806 if ((num_online_cpus() > 1) &&
807 !(acpi_gbl_FADT
.flags
& ACPI_FADT_C2_MP_SUPPORTED
))
811 /* determine C2 and C3 address from pblk */
812 pr
->power
.states
[ACPI_STATE_C2
].address
= pr
->pblk
+ 4;
813 pr
->power
.states
[ACPI_STATE_C3
].address
= pr
->pblk
+ 5;
815 /* determine latencies from FADT */
816 pr
->power
.states
[ACPI_STATE_C2
].latency
= acpi_gbl_FADT
.C2latency
;
817 pr
->power
.states
[ACPI_STATE_C3
].latency
= acpi_gbl_FADT
.C3latency
;
819 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
820 "lvl2[0x%08x] lvl3[0x%08x]\n",
821 pr
->power
.states
[ACPI_STATE_C2
].address
,
822 pr
->power
.states
[ACPI_STATE_C3
].address
));
827 static int acpi_processor_get_power_info_default(struct acpi_processor
*pr
)
829 if (!pr
->power
.states
[ACPI_STATE_C1
].valid
) {
830 /* set the first C-State to C1 */
831 /* all processors need to support C1 */
832 pr
->power
.states
[ACPI_STATE_C1
].type
= ACPI_STATE_C1
;
833 pr
->power
.states
[ACPI_STATE_C1
].valid
= 1;
834 pr
->power
.states
[ACPI_STATE_C1
].entry_method
= ACPI_CSTATE_HALT
;
836 /* the C0 state only exists as a filler in our array */
837 pr
->power
.states
[ACPI_STATE_C0
].valid
= 1;
841 static int acpi_processor_get_power_info_cst(struct acpi_processor
*pr
)
843 acpi_status status
= 0;
847 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
848 union acpi_object
*cst
;
856 status
= acpi_evaluate_object(pr
->handle
, "_CST", NULL
, &buffer
);
857 if (ACPI_FAILURE(status
)) {
858 ACPI_DEBUG_PRINT((ACPI_DB_INFO
, "No _CST, giving up\n"));
862 cst
= buffer
.pointer
;
864 /* There must be at least 2 elements */
865 if (!cst
|| (cst
->type
!= ACPI_TYPE_PACKAGE
) || cst
->package
.count
< 2) {
866 printk(KERN_ERR PREFIX
"not enough elements in _CST\n");
871 count
= cst
->package
.elements
[0].integer
.value
;
873 /* Validate number of power states. */
874 if (count
< 1 || count
!= cst
->package
.count
- 1) {
875 printk(KERN_ERR PREFIX
"count given by _CST is not valid\n");
880 /* Tell driver that at least _CST is supported. */
881 pr
->flags
.has_cst
= 1;
883 for (i
= 1; i
<= count
; i
++) {
884 union acpi_object
*element
;
885 union acpi_object
*obj
;
886 struct acpi_power_register
*reg
;
887 struct acpi_processor_cx cx
;
889 memset(&cx
, 0, sizeof(cx
));
891 element
= &(cst
->package
.elements
[i
]);
892 if (element
->type
!= ACPI_TYPE_PACKAGE
)
895 if (element
->package
.count
!= 4)
898 obj
= &(element
->package
.elements
[0]);
900 if (obj
->type
!= ACPI_TYPE_BUFFER
)
903 reg
= (struct acpi_power_register
*)obj
->buffer
.pointer
;
905 if (reg
->space_id
!= ACPI_ADR_SPACE_SYSTEM_IO
&&
906 (reg
->space_id
!= ACPI_ADR_SPACE_FIXED_HARDWARE
))
909 /* There should be an easy way to extract an integer... */
910 obj
= &(element
->package
.elements
[1]);
911 if (obj
->type
!= ACPI_TYPE_INTEGER
)
914 cx
.type
= obj
->integer
.value
;
916 * Some buggy BIOSes won't list C1 in _CST -
917 * Let acpi_processor_get_power_info_default() handle them later
919 if (i
== 1 && cx
.type
!= ACPI_STATE_C1
)
922 cx
.address
= reg
->address
;
923 cx
.index
= current_count
+ 1;
925 cx
.entry_method
= ACPI_CSTATE_SYSTEMIO
;
926 if (reg
->space_id
== ACPI_ADR_SPACE_FIXED_HARDWARE
) {
927 if (acpi_processor_ffh_cstate_probe
928 (pr
->id
, &cx
, reg
) == 0) {
929 cx
.entry_method
= ACPI_CSTATE_FFH
;
930 } else if (cx
.type
== ACPI_STATE_C1
) {
932 * C1 is a special case where FIXED_HARDWARE
933 * can be handled in non-MWAIT way as well.
934 * In that case, save this _CST entry info.
935 * Otherwise, ignore this info and continue.
937 cx
.entry_method
= ACPI_CSTATE_HALT
;
938 snprintf(cx
.desc
, ACPI_CX_DESC_LEN
, "ACPI HLT");
942 if (cx
.type
== ACPI_STATE_C1
&&
943 (idle_halt
|| idle_nomwait
)) {
945 * In most cases the C1 space_id obtained from
946 * _CST object is FIXED_HARDWARE access mode.
947 * But when the option of idle=halt is added,
948 * the entry_method type should be changed from
949 * CSTATE_FFH to CSTATE_HALT.
950 * When the option of idle=nomwait is added,
951 * the C1 entry_method type should be
954 cx
.entry_method
= ACPI_CSTATE_HALT
;
955 snprintf(cx
.desc
, ACPI_CX_DESC_LEN
, "ACPI HLT");
958 snprintf(cx
.desc
, ACPI_CX_DESC_LEN
, "ACPI IOPORT 0x%x",
962 if (cx
.type
== ACPI_STATE_C1
) {
966 obj
= &(element
->package
.elements
[2]);
967 if (obj
->type
!= ACPI_TYPE_INTEGER
)
970 cx
.latency
= obj
->integer
.value
;
972 obj
= &(element
->package
.elements
[3]);
973 if (obj
->type
!= ACPI_TYPE_INTEGER
)
976 cx
.power
= obj
->integer
.value
;
979 memcpy(&(pr
->power
.states
[current_count
]), &cx
, sizeof(cx
));
982 * We support total ACPI_PROCESSOR_MAX_POWER - 1
983 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1)
985 if (current_count
>= (ACPI_PROCESSOR_MAX_POWER
- 1)) {
987 "Limiting number of power states to max (%d)\n",
988 ACPI_PROCESSOR_MAX_POWER
);
990 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n");
995 ACPI_DEBUG_PRINT((ACPI_DB_INFO
, "Found %d power states\n",
998 /* Validate number of power states discovered */
999 if (current_count
< 2)
1003 kfree(buffer
.pointer
);
1008 static void acpi_processor_power_verify_c2(struct acpi_processor_cx
*cx
)
1015 * C2 latency must be less than or equal to 100
1018 else if (cx
->latency
> ACPI_PROCESSOR_MAX_C2_LATENCY
) {
1019 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
1020 "latency too large [%d]\n", cx
->latency
));
1025 * Otherwise we've met all of our C2 requirements.
1026 * Normalize the C2 latency to expidite policy
1030 #ifndef CONFIG_CPU_IDLE
1031 cx
->latency_ticks
= US_TO_PM_TIMER_TICKS(cx
->latency
);
1033 cx
->latency_ticks
= cx
->latency
;
1039 static void acpi_processor_power_verify_c3(struct acpi_processor
*pr
,
1040 struct acpi_processor_cx
*cx
)
1042 static int bm_check_flag
;
1049 * C3 latency must be less than or equal to 1000
1052 else if (cx
->latency
> ACPI_PROCESSOR_MAX_C3_LATENCY
) {
1053 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
1054 "latency too large [%d]\n", cx
->latency
));
1059 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast)
1060 * DMA transfers are used by any ISA device to avoid livelock.
1061 * Note that we could disable Type-F DMA (as recommended by
1062 * the erratum), but this is known to disrupt certain ISA
1063 * devices thus we take the conservative approach.
1065 else if (errata
.piix4
.fdma
) {
1066 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
1067 "C3 not supported on PIIX4 with Type-F DMA\n"));
1071 /* All the logic here assumes flags.bm_check is same across all CPUs */
1072 if (!bm_check_flag
) {
1073 /* Determine whether bm_check is needed based on CPU */
1074 acpi_processor_power_init_bm_check(&(pr
->flags
), pr
->id
);
1075 bm_check_flag
= pr
->flags
.bm_check
;
1077 pr
->flags
.bm_check
= bm_check_flag
;
1080 if (pr
->flags
.bm_check
) {
1081 if (!pr
->flags
.bm_control
) {
1082 if (pr
->flags
.has_cst
!= 1) {
1083 /* bus mastering control is necessary */
1084 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
1085 "C3 support requires BM control\n"));
1088 /* Here we enter C3 without bus mastering */
1089 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
1090 "C3 support without BM control\n"));
1095 * WBINVD should be set in fadt, for C3 state to be
1096 * supported on when bm_check is not required.
1098 if (!(acpi_gbl_FADT
.flags
& ACPI_FADT_WBINVD
)) {
1099 ACPI_DEBUG_PRINT((ACPI_DB_INFO
,
1100 "Cache invalidation should work properly"
1101 " for C3 to be enabled on SMP systems\n"));
1107 * Otherwise we've met all of our C3 requirements.
1108 * Normalize the C3 latency to expidite policy. Enable
1109 * checking of bus mastering status (bm_check) so we can
1110 * use this in our C3 policy
1114 #ifndef CONFIG_CPU_IDLE
1115 cx
->latency_ticks
= US_TO_PM_TIMER_TICKS(cx
->latency
);
1117 cx
->latency_ticks
= cx
->latency
;
1120 * On older chipsets, BM_RLD needs to be set
1121 * in order for Bus Master activity to wake the
1122 * system from C3. Newer chipsets handle DMA
1123 * during C3 automatically and BM_RLD is a NOP.
1124 * In either case, the proper way to
1125 * handle BM_RLD is to set it and leave it set.
1127 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD
, 1);
1132 static int acpi_processor_power_verify(struct acpi_processor
*pr
)
1135 unsigned int working
= 0;
1137 pr
->power
.timer_broadcast_on_state
= INT_MAX
;
1139 for (i
= 1; i
< ACPI_PROCESSOR_MAX_POWER
; i
++) {
1140 struct acpi_processor_cx
*cx
= &pr
->power
.states
[i
];
1148 acpi_processor_power_verify_c2(cx
);
1150 acpi_timer_check_state(i
, pr
, cx
);
1154 acpi_processor_power_verify_c3(pr
, cx
);
1156 acpi_timer_check_state(i
, pr
, cx
);
1164 acpi_propagate_timer_broadcast(pr
);
1169 static int acpi_processor_get_power_info(struct acpi_processor
*pr
)
1175 /* NOTE: the idle thread may not be running while calling
1178 /* Zero initialize all the C-states info. */
1179 memset(pr
->power
.states
, 0, sizeof(pr
->power
.states
));
1181 result
= acpi_processor_get_power_info_cst(pr
);
1182 if (result
== -ENODEV
)
1183 result
= acpi_processor_get_power_info_fadt(pr
);
1188 acpi_processor_get_power_info_default(pr
);
1190 pr
->power
.count
= acpi_processor_power_verify(pr
);
1192 #ifndef CONFIG_CPU_IDLE
1194 * Set Default Policy
1195 * ------------------
1196 * Now that we know which states are supported, set the default
1197 * policy. Note that this policy can be changed dynamically
1198 * (e.g. encourage deeper sleeps to conserve battery life when
1201 result
= acpi_processor_set_power_policy(pr
);
1207 * if one state of type C2 or C3 is available, mark this
1208 * CPU as being "idle manageable"
1210 for (i
= 1; i
< ACPI_PROCESSOR_MAX_POWER
; i
++) {
1211 if (pr
->power
.states
[i
].valid
) {
1212 pr
->power
.count
= i
;
1213 if (pr
->power
.states
[i
].type
>= ACPI_STATE_C2
)
1214 pr
->flags
.power
= 1;
1221 static int acpi_processor_power_seq_show(struct seq_file
*seq
, void *offset
)
1223 struct acpi_processor
*pr
= seq
->private;
1230 seq_printf(seq
, "active state: C%zd\n"
1232 "bus master activity: %08x\n"
1233 "maximum allowed latency: %d usec\n",
1234 pr
->power
.state
? pr
->power
.state
- pr
->power
.states
: 0,
1235 max_cstate
, (unsigned)pr
->power
.bm_activity
,
1236 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY
));
1238 seq_puts(seq
, "states:\n");
1240 for (i
= 1; i
<= pr
->power
.count
; i
++) {
1241 seq_printf(seq
, " %cC%d: ",
1242 (&pr
->power
.states
[i
] ==
1243 pr
->power
.state
? '*' : ' '), i
);
1245 if (!pr
->power
.states
[i
].valid
) {
1246 seq_puts(seq
, "<not supported>\n");
1250 switch (pr
->power
.states
[i
].type
) {
1252 seq_printf(seq
, "type[C1] ");
1255 seq_printf(seq
, "type[C2] ");
1258 seq_printf(seq
, "type[C3] ");
1261 seq_printf(seq
, "type[--] ");
1265 if (pr
->power
.states
[i
].promotion
.state
)
1266 seq_printf(seq
, "promotion[C%zd] ",
1267 (pr
->power
.states
[i
].promotion
.state
-
1270 seq_puts(seq
, "promotion[--] ");
1272 if (pr
->power
.states
[i
].demotion
.state
)
1273 seq_printf(seq
, "demotion[C%zd] ",
1274 (pr
->power
.states
[i
].demotion
.state
-
1277 seq_puts(seq
, "demotion[--] ");
1279 seq_printf(seq
, "latency[%03d] usage[%08d] duration[%020llu]\n",
1280 pr
->power
.states
[i
].latency
,
1281 pr
->power
.states
[i
].usage
,
1282 (unsigned long long)pr
->power
.states
[i
].time
);
1289 static int acpi_processor_power_open_fs(struct inode
*inode
, struct file
*file
)
1291 return single_open(file
, acpi_processor_power_seq_show
,
1295 static const struct file_operations acpi_processor_power_fops
= {
1296 .owner
= THIS_MODULE
,
1297 .open
= acpi_processor_power_open_fs
,
1299 .llseek
= seq_lseek
,
1300 .release
= single_release
,
1303 #ifndef CONFIG_CPU_IDLE
1305 int acpi_processor_cst_has_changed(struct acpi_processor
*pr
)
1309 if (boot_option_idle_override
)
1319 if (!pr
->flags
.power_setup_done
)
1323 * Fall back to the default idle loop, when pm_idle_save had
1327 pm_idle
= pm_idle_save
;
1328 /* Relies on interrupts forcing exit from idle. */
1329 synchronize_sched();
1332 pr
->flags
.power
= 0;
1333 result
= acpi_processor_get_power_info(pr
);
1334 if ((pr
->flags
.power
== 1) && (pr
->flags
.power_setup_done
))
1335 pm_idle
= acpi_processor_idle
;
1341 static void smp_callback(void *v
)
1343 /* we already woke the CPU up, nothing more to do */
1347 * This function gets called when a part of the kernel has a new latency
1348 * requirement. This means we need to get all processors out of their C-state,
1349 * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that
1350 * wakes them all right up.
1352 static int acpi_processor_latency_notify(struct notifier_block
*b
,
1353 unsigned long l
, void *v
)
1355 smp_call_function(smp_callback
, NULL
, 1);
1359 static struct notifier_block acpi_processor_latency_notifier
= {
1360 .notifier_call
= acpi_processor_latency_notify
,
1365 #else /* CONFIG_CPU_IDLE */
1368 * acpi_idle_bm_check - checks if bus master activity was detected
1370 static int acpi_idle_bm_check(void)
1374 acpi_get_register_unlocked(ACPI_BITREG_BUS_MASTER_STATUS
, &bm_status
);
1376 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS
, 1);
1378 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
1379 * the true state of bus mastering activity; forcing us to
1380 * manually check the BMIDEA bit of each IDE channel.
1382 else if (errata
.piix4
.bmisx
) {
1383 if ((inb_p(errata
.piix4
.bmisx
+ 0x02) & 0x01)
1384 || (inb_p(errata
.piix4
.bmisx
+ 0x0A) & 0x01))
1391 * acpi_idle_do_entry - a helper function that does C2 and C3 type entry
1394 * Caller disables interrupt before call and enables interrupt after return.
1396 static inline void acpi_idle_do_entry(struct acpi_processor_cx
*cx
)
1398 /* Don't trace irqs off for idle */
1399 stop_critical_timings();
1400 if (cx
->entry_method
== ACPI_CSTATE_FFH
) {
1401 /* Call into architectural FFH based C-state */
1402 acpi_processor_ffh_cstate_enter(cx
);
1403 } else if (cx
->entry_method
== ACPI_CSTATE_HALT
) {
1407 /* IO port based C-state */
1409 /* Dummy wait op - must do something useless after P_LVL2 read
1410 because chipsets cannot guarantee that STPCLK# signal
1411 gets asserted in time to freeze execution properly. */
1412 unused
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
1414 start_critical_timings();
1418 * acpi_idle_enter_c1 - enters an ACPI C1 state-type
1419 * @dev: the target CPU
1420 * @state: the state data
1422 * This is equivalent to the HALT instruction.
1424 static int acpi_idle_enter_c1(struct cpuidle_device
*dev
,
1425 struct cpuidle_state
*state
)
1428 struct acpi_processor
*pr
;
1429 struct acpi_processor_cx
*cx
= cpuidle_get_statedata(state
);
1431 pr
= __get_cpu_var(processors
);
1436 local_irq_disable();
1438 /* Do not access any ACPI IO ports in suspend path */
1439 if (acpi_idle_suspend
) {
1445 t1
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
1446 acpi_idle_do_entry(cx
);
1447 t2
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
1452 return ticks_elapsed_in_us(t1
, t2
);
1456 * acpi_idle_enter_simple - enters an ACPI state without BM handling
1457 * @dev: the target CPU
1458 * @state: the state data
1460 static int acpi_idle_enter_simple(struct cpuidle_device
*dev
,
1461 struct cpuidle_state
*state
)
1463 struct acpi_processor
*pr
;
1464 struct acpi_processor_cx
*cx
= cpuidle_get_statedata(state
);
1466 int sleep_ticks
= 0;
1468 pr
= __get_cpu_var(processors
);
1473 if (acpi_idle_suspend
)
1474 return(acpi_idle_enter_c1(dev
, state
));
1476 local_irq_disable();
1477 current_thread_info()->status
&= ~TS_POLLING
;
1479 * TS_POLLING-cleared state must be visible before we test
1484 if (unlikely(need_resched())) {
1485 current_thread_info()->status
|= TS_POLLING
;
1491 * Must be done before busmaster disable as we might need to
1494 acpi_state_timer_broadcast(pr
, cx
, 1);
1496 if (cx
->type
== ACPI_STATE_C3
)
1497 ACPI_FLUSH_CPU_CACHE();
1499 t1
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
1500 /* Tell the scheduler that we are going deep-idle: */
1501 sched_clock_idle_sleep_event();
1502 acpi_idle_do_entry(cx
);
1503 t2
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
1505 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
1506 /* TSC could halt in idle, so notify users */
1507 if (tsc_halts_in_c(cx
->type
))
1508 mark_tsc_unstable("TSC halts in idle");;
1510 sleep_ticks
= ticks_elapsed(t1
, t2
);
1512 /* Tell the scheduler how much we idled: */
1513 sched_clock_idle_wakeup_event(sleep_ticks
*PM_TIMER_TICK_NS
);
1516 current_thread_info()->status
|= TS_POLLING
;
1520 acpi_state_timer_broadcast(pr
, cx
, 0);
1521 cx
->time
+= sleep_ticks
;
1522 return ticks_elapsed_in_us(t1
, t2
);
1525 static int c3_cpu_count
;
1526 static DEFINE_SPINLOCK(c3_lock
);
1529 * acpi_idle_enter_bm - enters C3 with proper BM handling
1530 * @dev: the target CPU
1531 * @state: the state data
1533 * If BM is detected, the deepest non-C3 idle state is entered instead.
1535 static int acpi_idle_enter_bm(struct cpuidle_device
*dev
,
1536 struct cpuidle_state
*state
)
1538 struct acpi_processor
*pr
;
1539 struct acpi_processor_cx
*cx
= cpuidle_get_statedata(state
);
1541 int sleep_ticks
= 0;
1543 pr
= __get_cpu_var(processors
);
1548 if (acpi_idle_suspend
)
1549 return(acpi_idle_enter_c1(dev
, state
));
1551 if (acpi_idle_bm_check()) {
1552 if (dev
->safe_state
) {
1553 dev
->last_state
= dev
->safe_state
;
1554 return dev
->safe_state
->enter(dev
, dev
->safe_state
);
1556 local_irq_disable();
1563 local_irq_disable();
1564 current_thread_info()->status
&= ~TS_POLLING
;
1566 * TS_POLLING-cleared state must be visible before we test
1571 if (unlikely(need_resched())) {
1572 current_thread_info()->status
|= TS_POLLING
;
1577 acpi_unlazy_tlb(smp_processor_id());
1579 /* Tell the scheduler that we are going deep-idle: */
1580 sched_clock_idle_sleep_event();
1582 * Must be done before busmaster disable as we might need to
1585 acpi_state_timer_broadcast(pr
, cx
, 1);
1588 * disable bus master
1589 * bm_check implies we need ARB_DIS
1590 * !bm_check implies we need cache flush
1591 * bm_control implies whether we can do ARB_DIS
1593 * That leaves a case where bm_check is set and bm_control is
1594 * not set. In that case we cannot do much, we enter C3
1595 * without doing anything.
1597 if (pr
->flags
.bm_check
&& pr
->flags
.bm_control
) {
1598 spin_lock(&c3_lock
);
1600 /* Disable bus master arbitration when all CPUs are in C3 */
1601 if (c3_cpu_count
== num_online_cpus())
1602 acpi_set_register(ACPI_BITREG_ARB_DISABLE
, 1);
1603 spin_unlock(&c3_lock
);
1604 } else if (!pr
->flags
.bm_check
) {
1605 ACPI_FLUSH_CPU_CACHE();
1608 t1
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
1609 acpi_idle_do_entry(cx
);
1610 t2
= inl(acpi_gbl_FADT
.xpm_timer_block
.address
);
1612 /* Re-enable bus master arbitration */
1613 if (pr
->flags
.bm_check
&& pr
->flags
.bm_control
) {
1614 spin_lock(&c3_lock
);
1615 acpi_set_register(ACPI_BITREG_ARB_DISABLE
, 0);
1617 spin_unlock(&c3_lock
);
1620 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
1621 /* TSC could halt in idle, so notify users */
1622 if (tsc_halts_in_c(ACPI_STATE_C3
))
1623 mark_tsc_unstable("TSC halts in idle");
1625 sleep_ticks
= ticks_elapsed(t1
, t2
);
1626 /* Tell the scheduler how much we idled: */
1627 sched_clock_idle_wakeup_event(sleep_ticks
*PM_TIMER_TICK_NS
);
1630 current_thread_info()->status
|= TS_POLLING
;
1634 acpi_state_timer_broadcast(pr
, cx
, 0);
1635 cx
->time
+= sleep_ticks
;
1636 return ticks_elapsed_in_us(t1
, t2
);
1639 struct cpuidle_driver acpi_idle_driver
= {
1640 .name
= "acpi_idle",
1641 .owner
= THIS_MODULE
,
1645 * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE
1646 * @pr: the ACPI processor
1648 static int acpi_processor_setup_cpuidle(struct acpi_processor
*pr
)
1650 int i
, count
= CPUIDLE_DRIVER_STATE_START
;
1651 struct acpi_processor_cx
*cx
;
1652 struct cpuidle_state
*state
;
1653 struct cpuidle_device
*dev
= &pr
->power
.dev
;
1655 if (!pr
->flags
.power_setup_done
)
1658 if (pr
->flags
.power
== 0) {
1663 for (i
= 0; i
< CPUIDLE_STATE_MAX
; i
++) {
1664 dev
->states
[i
].name
[0] = '\0';
1665 dev
->states
[i
].desc
[0] = '\0';
1668 for (i
= 1; i
< ACPI_PROCESSOR_MAX_POWER
&& i
<= max_cstate
; i
++) {
1669 cx
= &pr
->power
.states
[i
];
1670 state
= &dev
->states
[count
];
1675 #ifdef CONFIG_HOTPLUG_CPU
1676 if ((cx
->type
!= ACPI_STATE_C1
) && (num_online_cpus() > 1) &&
1677 !pr
->flags
.has_cst
&&
1678 !(acpi_gbl_FADT
.flags
& ACPI_FADT_C2_MP_SUPPORTED
))
1681 cpuidle_set_statedata(state
, cx
);
1683 snprintf(state
->name
, CPUIDLE_NAME_LEN
, "C%d", i
);
1684 strncpy(state
->desc
, cx
->desc
, CPUIDLE_DESC_LEN
);
1685 state
->exit_latency
= cx
->latency
;
1686 state
->target_residency
= cx
->latency
* latency_factor
;
1687 state
->power_usage
= cx
->power
;
1692 state
->flags
|= CPUIDLE_FLAG_SHALLOW
;
1693 if (cx
->entry_method
== ACPI_CSTATE_FFH
)
1694 state
->flags
|= CPUIDLE_FLAG_TIME_VALID
;
1696 state
->enter
= acpi_idle_enter_c1
;
1697 dev
->safe_state
= state
;
1701 state
->flags
|= CPUIDLE_FLAG_BALANCED
;
1702 state
->flags
|= CPUIDLE_FLAG_TIME_VALID
;
1703 state
->enter
= acpi_idle_enter_simple
;
1704 dev
->safe_state
= state
;
1708 state
->flags
|= CPUIDLE_FLAG_DEEP
;
1709 state
->flags
|= CPUIDLE_FLAG_TIME_VALID
;
1710 state
->flags
|= CPUIDLE_FLAG_CHECK_BM
;
1711 state
->enter
= pr
->flags
.bm_check
?
1712 acpi_idle_enter_bm
:
1713 acpi_idle_enter_simple
;
1718 if (count
== CPUIDLE_STATE_MAX
)
1722 dev
->state_count
= count
;
1730 int acpi_processor_cst_has_changed(struct acpi_processor
*pr
)
1734 if (boot_option_idle_override
)
1744 if (!pr
->flags
.power_setup_done
)
1747 cpuidle_pause_and_lock();
1748 cpuidle_disable_device(&pr
->power
.dev
);
1749 acpi_processor_get_power_info(pr
);
1750 if (pr
->flags
.power
) {
1751 acpi_processor_setup_cpuidle(pr
);
1752 ret
= cpuidle_enable_device(&pr
->power
.dev
);
1754 cpuidle_resume_and_unlock();
1759 #endif /* CONFIG_CPU_IDLE */
1761 int __cpuinit
acpi_processor_power_init(struct acpi_processor
*pr
,
1762 struct acpi_device
*device
)
1764 acpi_status status
= 0;
1765 static int first_run
;
1766 struct proc_dir_entry
*entry
= NULL
;
1769 if (boot_option_idle_override
)
1775 * When the boot option of "idle=halt" is added, halt
1776 * is used for CPU IDLE.
1777 * In such case C2/C3 is meaningless. So the max_cstate
1782 dmi_check_system(processor_power_dmi_table
);
1783 max_cstate
= acpi_processor_cstate_check(max_cstate
);
1784 if (max_cstate
< ACPI_C_STATES_MAX
)
1786 "ACPI: processor limited to max C-state %d\n",
1789 #if !defined(CONFIG_CPU_IDLE) && defined(CONFIG_SMP)
1790 pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY
,
1791 &acpi_processor_latency_notifier
);
1798 if (acpi_gbl_FADT
.cst_control
&& !nocst
) {
1800 acpi_os_write_port(acpi_gbl_FADT
.smi_command
, acpi_gbl_FADT
.cst_control
, 8);
1801 if (ACPI_FAILURE(status
)) {
1802 ACPI_EXCEPTION((AE_INFO
, status
,
1803 "Notifying BIOS of _CST ability failed"));
1807 acpi_processor_get_power_info(pr
);
1808 pr
->flags
.power_setup_done
= 1;
1811 * Install the idle handler if processor power management is supported.
1812 * Note that we use previously set idle handler will be used on
1813 * platforms that only support C1.
1815 if (pr
->flags
.power
) {
1816 #ifdef CONFIG_CPU_IDLE
1817 acpi_processor_setup_cpuidle(pr
);
1818 if (cpuidle_register_device(&pr
->power
.dev
))
1822 printk(KERN_INFO PREFIX
"CPU%d (power states:", pr
->id
);
1823 for (i
= 1; i
<= pr
->power
.count
; i
++)
1824 if (pr
->power
.states
[i
].valid
)
1825 printk(" C%d[C%d]", i
,
1826 pr
->power
.states
[i
].type
);
1829 #ifndef CONFIG_CPU_IDLE
1831 pm_idle_save
= pm_idle
;
1832 pm_idle
= acpi_processor_idle
;
1838 entry
= proc_create_data(ACPI_PROCESSOR_FILE_POWER
,
1839 S_IRUGO
, acpi_device_dir(device
),
1840 &acpi_processor_power_fops
,
1841 acpi_driver_data(device
));
1847 int acpi_processor_power_exit(struct acpi_processor
*pr
,
1848 struct acpi_device
*device
)
1850 if (boot_option_idle_override
)
1853 #ifdef CONFIG_CPU_IDLE
1854 cpuidle_unregister_device(&pr
->power
.dev
);
1856 pr
->flags
.power_setup_done
= 0;
1858 if (acpi_device_dir(device
))
1859 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER
,
1860 acpi_device_dir(device
));
1862 #ifndef CONFIG_CPU_IDLE
1864 /* Unregister the idle handler when processor #0 is removed. */
1867 pm_idle
= pm_idle_save
;
1870 * We are about to unload the current idle thread pm callback
1871 * (pm_idle), Wait for all processors to update cached/local
1872 * copies of pm_idle before proceeding.
1876 pm_qos_remove_notifier(PM_QOS_CPU_DMA_LATENCY
,
1877 &acpi_processor_latency_notifier
);