arch/x86/pci/irq.c

   1 /*
   2  *      Low-Level PCI Support for PC -- Routing of Interrupts
   3  *
   4  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   5  */
   6
   7 #include <linux/types.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pci.h>
  10 #include <linux/init.h>
  11 #include <linux/slab.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/dmi.h>
  14 #include <linux/io.h>
  15 #include <linux/smp.h>
  16 #include <asm/io_apic.h>
  17 #include <linux/irq.h>
  18 #include <linux/acpi.h>
  19 #include <asm/pci_x86.h>
  20
  21 #define PIRQ_SIGNATURE  (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
  22 #define PIRQ_VERSION 0x0100
  23
  24 static int broken_hp_bios_irq9;
  25 static int acer_tm360_irqrouting;
  26
  27 static struct irq_routing_table *pirq_table;
  28
  29 static int pirq_enable_irq(struct pci_dev *dev);
  30
  31 /*
  32  * Never use: 0, 1, 2 (timer, keyboard, and cascade)
  33  * Avoid using: 13, 14 and 15 (FP error and IDE).
  34  * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
  35  */
  36 unsigned int pcibios_irq_mask = 0xfff8;
  37
  38 static int pirq_penalty[16] = {
  39         1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
  40         0, 0, 0, 0, 1000, 100000, 100000, 100000
  41 };
  42
  43 struct irq_router {
  44         char *name;
  45         u16 vendor, device;
  46         int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
  47         int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
  48                 int new);
  49 };
  50
  51 struct irq_router_handler {
  52         u16 vendor;
  53         int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
  54 };
  55
  56 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
  57 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
  58
  59 /*
  60  *  Check passed address for the PCI IRQ Routing Table signature
  61  *  and perform checksum verification.
  62  */
  63
  64 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
  65 {
  66         struct irq_routing_table *rt;
  67         int i;
  68         u8 sum;
  69
  70         rt = (struct irq_routing_table *) addr;
  71         if (rt->signature != PIRQ_SIGNATURE ||
  72             rt->version != PIRQ_VERSION ||
  73             rt->size % 16 ||
  74             rt->size < sizeof(struct irq_routing_table))
  75                 return NULL;
  76         sum = 0;
  77         for (i = 0; i < rt->size; i++)
  78                 sum += addr[i];
  79         if (!sum) {
  80                 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n",
  81                         rt);
  82                 return rt;
  83         }
  84         return NULL;
  85 }
  86
  87
  88
  89 /*
  90  *  Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
  91  */
  92
  93 static struct irq_routing_table * __init pirq_find_routing_table(void)
  94 {
  95         u8 *addr;
  96         struct irq_routing_table *rt;
  97
  98         if (pirq_table_addr) {
  99                 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr));
 100                 if (rt)
 101                         return rt;
 102                 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
 103         }
 104         for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
 105                 rt = pirq_check_routing_table(addr);
 106                 if (rt)
 107                         return rt;
 108         }
 109         return NULL;
 110 }
 111
 112 /*
 113  *  If we have a IRQ routing table, use it to search for peer host
 114  *  bridges.  It's a gross hack, but since there are no other known
 115  *  ways how to get a list of buses, we have to go this way.
 116  */
 117
 118 static void __init pirq_peer_trick(void)
 119 {
 120         struct irq_routing_table *rt = pirq_table;
 121         u8 busmap[256];
 122         int i;
 123         struct irq_info *e;
 124
 125         memset(busmap, 0, sizeof(busmap));
 126         for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
 127                 e = &rt->slots[i];
 128 #ifdef DEBUG
 129                 {
 130                         int j;
 131                         DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
 132                         for (j = 0; j < 4; j++)
 133                                 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
 134                         DBG("\n");
 135                 }
 136 #endif
 137                 busmap[e->bus] = 1;
 138         }
 139         for (i = 1; i < 256; i++) {
 140                 int node;
 141                 if (!busmap[i] || pci_find_bus(0, i))
 142                         continue;
 143                 node = get_mp_bus_to_node(i);
 144                 if (pci_scan_bus_on_node(i, &pci_root_ops, node))
 145                         printk(KERN_INFO "PCI: Discovered primary peer "
 146                                "bus %02x [IRQ]\n", i);
 147         }
 148         pcibios_last_bus = -1;
 149 }
 150
 151 /*
 152  *  Code for querying and setting of IRQ routes on various interrupt routers.
 153  */
 154
 155 void eisa_set_level_irq(unsigned int irq)
 156 {
 157         unsigned char mask = 1 << (irq & 7);
 158         unsigned int port = 0x4d0 + (irq >> 3);
 159         unsigned char val;
 160         static u16 eisa_irq_mask;
 161
 162         if (irq >= 16 || (1 << irq) & eisa_irq_mask)
 163                 return;
 164
 165         eisa_irq_mask |= (1 << irq);
 166         printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
 167         val = inb(port);
 168         if (!(val & mask)) {
 169                 DBG(KERN_DEBUG " -> edge");
 170                 outb(val | mask, port);
 171         }
 172 }
 173
 174 /*
 175  * Common IRQ routing practice: nibbles in config space,
 176  * offset by some magic constant.
 177  */
 178 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
 179 {
 180         u8 x;
 181         unsigned reg = offset + (nr >> 1);
 182
 183         pci_read_config_byte(router, reg, &x);
 184         return (nr & 1) ? (x >> 4) : (x & 0xf);
 185 }
 186
 187 static void write_config_nybble(struct pci_dev *router, unsigned offset,
 188         unsigned nr, unsigned int val)
 189 {
 190         u8 x;
 191         unsigned reg = offset + (nr >> 1);
 192
 193         pci_read_config_byte(router, reg, &x);
 194         x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
 195         pci_write_config_byte(router, reg, x);
 196 }
 197
 198 /*
 199  * ALI pirq entries are damn ugly, and completely undocumented.
 200  * This has been figured out from pirq tables, and it's not a pretty
 201  * picture.
 202  */
 203 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 204 {
 205         static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
 206
 207         WARN_ON_ONCE(pirq > 16);
 208         return irqmap[read_config_nybble(router, 0x48, pirq-1)];
 209 }
 210
 211 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 212 {
 213         static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
 214         unsigned int val = irqmap[irq];
 215
 216         WARN_ON_ONCE(pirq > 16);
 217         if (val) {
 218                 write_config_nybble(router, 0x48, pirq-1, val);
 219                 return 1;
 220         }
 221         return 0;
 222 }
 223
 224 /*
 225  * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
 226  * just a pointer to the config space.
 227  */
 228 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 229 {
 230         u8 x;
 231
 232         pci_read_config_byte(router, pirq, &x);
 233         return (x < 16) ? x : 0;
 234 }
 235
 236 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 237 {
 238         pci_write_config_byte(router, pirq, irq);
 239         return 1;
 240 }
 241
 242 /*
 243  * The VIA pirq rules are nibble-based, like ALI,
 244  * but without the ugly irq number munging.
 245  * However, PIRQD is in the upper instead of lower 4 bits.
 246  */
 247 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 248 {
 249         return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
 250 }
 251
 252 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 253 {
 254         write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
 255         return 1;
 256 }
 257
 258 /*
 259  * The VIA pirq rules are nibble-based, like ALI,
 260  * but without the ugly irq number munging.
 261  * However, for 82C586, nibble map is different .
 262  */
 263 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 264 {
 265         static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
 266
 267         WARN_ON_ONCE(pirq > 5);
 268         return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
 269 }
 270
 271 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 272 {
 273         static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
 274
 275         WARN_ON_ONCE(pirq > 5);
 276         write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
 277         return 1;
 278 }
 279
 280 /*
 281  * ITE 8330G pirq rules are nibble-based
 282  * FIXME: pirqmap may be { 1, 0, 3, 2 },
 283  *        2+3 are both mapped to irq 9 on my system
 284  */
 285 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 286 {
 287         static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
 288
 289         WARN_ON_ONCE(pirq > 4);
 290         return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
 291 }
 292
 293 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 294 {
 295         static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
 296
 297         WARN_ON_ONCE(pirq > 4);
 298         write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
 299         return 1;
 300 }
 301
 302 /*
 303  * OPTI: high four bits are nibble pointer..
 304  * I wonder what the low bits do?
 305  */
 306 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 307 {
 308         return read_config_nybble(router, 0xb8, pirq >> 4);
 309 }
 310
 311 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 312 {
 313         write_config_nybble(router, 0xb8, pirq >> 4, irq);
 314         return 1;
 315 }
 316
 317 /*
 318  * Cyrix: nibble offset 0x5C
 319  * 0x5C bits 7:4 is INTB bits 3:0 is INTA
 320  * 0x5D bits 7:4 is INTD bits 3:0 is INTC
 321  */
 322 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 323 {
 324         return read_config_nybble(router, 0x5C, (pirq-1)^1);
 325 }
 326
 327 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 328 {
 329         write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
 330         return 1;
 331 }
 332
 333 /*
 334  *      PIRQ routing for SiS 85C503 router used in several SiS chipsets.
 335  *      We have to deal with the following issues here:
 336  *      - vendors have different ideas about the meaning of link values
 337  *      - some onboard devices (integrated in the chipset) have special
 338  *        links and are thus routed differently (i.e. not via PCI INTA-INTD)
 339  *      - different revision of the router have a different layout for
 340  *        the routing registers, particularly for the onchip devices
 341  *
 342  *      For all routing registers the common thing is we have one byte
 343  *      per routeable link which is defined as:
 344  *               bit 7      IRQ mapping enabled (0) or disabled (1)
 345  *               bits [6:4] reserved (sometimes used for onchip devices)
 346  *               bits [3:0] IRQ to map to
 347  *                   allowed: 3-7, 9-12, 14-15
 348  *                   reserved: 0, 1, 2, 8, 13
 349  *
 350  *      The config-space registers located at 0x41/0x42/0x43/0x44 are
 351  *      always used to route the normal PCI INT A/B/C/D respectively.
 352  *      Apparently there are systems implementing PCI routing table using
 353  *      link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
 354  *      We try our best to handle both link mappings.
 355  *
 356  *      Currently (2003-05-21) it appears most SiS chipsets follow the
 357  *      definition of routing registers from the SiS-5595 southbridge.
 358  *      According to the SiS 5595 datasheets the revision id's of the
 359  *      router (ISA-bridge) should be 0x01 or 0xb0.
 360  *
 361  *      Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
 362  *      Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
 363  *      They seem to work with the current routing code. However there is
 364  *      some concern because of the two USB-OHCI HCs (original SiS 5595
 365  *      had only one). YMMV.
 366  *
 367  *      Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
 368  *
 369  *      0x61:   IDEIRQ:
 370  *              bits [6:5] must be written 01
 371  *              bit 4 channel-select primary (0), secondary (1)
 372  *
 373  *      0x62:   USBIRQ:
 374  *              bit 6 OHCI function disabled (0), enabled (1)
 375  *
 376  *      0x6a:   ACPI/SCI IRQ: bits 4-6 reserved
 377  *
 378  *      0x7e:   Data Acq. Module IRQ - bits 4-6 reserved
 379  *
 380  *      We support USBIRQ (in addition to INTA-INTD) and keep the
 381  *      IDE, ACPI and DAQ routing untouched as set by the BIOS.
 382  *
 383  *      Currently the only reported exception is the new SiS 65x chipset
 384  *      which includes the SiS 69x southbridge. Here we have the 85C503
 385  *      router revision 0x04 and there are changes in the register layout
 386  *      mostly related to the different USB HCs with USB 2.0 support.
 387  *
 388  *      Onchip routing for router rev-id 0x04 (try-and-error observation)
 389  *
 390  *      0x60/0x61/0x62/0x63:    1xEHCI and 3xOHCI (companion) USB-HCs
 391  *                              bit 6-4 are probably unused, not like 5595
 392  */
 393
 394 #define PIRQ_SIS_IRQ_MASK       0x0f
 395 #define PIRQ_SIS_IRQ_DISABLE    0x80
 396 #define PIRQ_SIS_USB_ENABLE     0x40
 397
 398 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 399 {
 400         u8 x;
 401         int reg;
 402
 403         reg = pirq;
 404         if (reg >= 0x01 && reg <= 0x04)
 405                 reg += 0x40;
 406         pci_read_config_byte(router, reg, &x);
 407         return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
 408 }
 409
 410 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 411 {
 412         u8 x;
 413         int reg;
 414
 415         reg = pirq;
 416         if (reg >= 0x01 && reg <= 0x04)
 417                 reg += 0x40;
 418         pci_read_config_byte(router, reg, &x);
 419         x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
 420         x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
 421         pci_write_config_byte(router, reg, x);
 422         return 1;
 423 }
 424
 425
 426 /*
 427  * VLSI: nibble offset 0x74 - educated guess due to routing table and
 428  *       config space of VLSI 82C534 PCI-bridge/router (1004:0102)
 429  *       Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
 430  *       devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
 431  *       for the busbridge to the docking station.
 432  */
 433
 434 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 435 {
 436         WARN_ON_ONCE(pirq >= 9);
 437         if (pirq > 8) {
 438                 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
 439                 return 0;
 440         }
 441         return read_config_nybble(router, 0x74, pirq-1);
 442 }
 443
 444 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 445 {
 446         WARN_ON_ONCE(pirq >= 9);
 447         if (pirq > 8) {
 448                 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
 449                 return 0;
 450         }
 451         write_config_nybble(router, 0x74, pirq-1, irq);
 452         return 1;
 453 }
 454
 455 /*
 456  * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
 457  * and Redirect I/O registers (0x0c00 and 0x0c01).  The Index register
 458  * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a.  The Redirect
 459  * register is a straight binary coding of desired PIC IRQ (low nibble).
 460  *
 461  * The 'link' value in the PIRQ table is already in the correct format
 462  * for the Index register.  There are some special index values:
 463  * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
 464  * and 0x03 for SMBus.
 465  */
 466 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 467 {
 468         outb(pirq, 0xc00);
 469         return inb(0xc01) & 0xf;
 470 }
 471
 472 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
 473         int pirq, int irq)
 474 {
 475         outb(pirq, 0xc00);
 476         outb(irq, 0xc01);
 477         return 1;
 478 }
 479
 480 /* Support for AMD756 PCI IRQ Routing
 481  * Jhon H. Caicedo <jhcaiced@osso.org.co>
 482  * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
 483  * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
 484  * The AMD756 pirq rules are nibble-based
 485  * offset 0x56 0-3 PIRQA  4-7  PIRQB
 486  * offset 0x57 0-3 PIRQC  4-7  PIRQD
 487  */
 488 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 489 {
 490         u8 irq;
 491         irq = 0;
 492         if (pirq <= 4)
 493                 irq = read_config_nybble(router, 0x56, pirq - 1);
 494         dev_info(&dev->dev,
 495                  "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
 496                  dev->vendor, dev->device, pirq, irq);
 497         return irq;
 498 }
 499
 500 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 501 {
 502         dev_info(&dev->dev,
 503                  "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
 504                  dev->vendor, dev->device, pirq, irq);
 505         if (pirq <= 4)
 506                 write_config_nybble(router, 0x56, pirq - 1, irq);
 507         return 1;
 508 }
 509
 510 /*
 511  * PicoPower PT86C523
 512  */
 513 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 514 {
 515         outb(0x10 + ((pirq - 1) >> 1), 0x24);
 516         return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
 517 }
 518
 519 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
 520                         int irq)
 521 {
 522         unsigned int x;
 523         outb(0x10 + ((pirq - 1) >> 1), 0x24);
 524         x = inb(0x26);
 525         x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
 526         outb(x, 0x26);
 527         return 1;
 528 }
 529
 530 #ifdef CONFIG_PCI_BIOS
 531
 532 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 533 {
 534         struct pci_dev *bridge;
 535         int pin = pci_get_interrupt_pin(dev, &bridge);
 536         return pcibios_set_irq_routing(bridge, pin - 1, irq);
 537 }
 538
 539 #endif
 540
 541 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 542 {
 543         static struct pci_device_id __initdata pirq_440gx[] = {
 544                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
 545                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
 546                 { },
 547         };
 548
 549         /* 440GX has a proprietary PIRQ router -- don't use it */
 550         if (pci_dev_present(pirq_440gx))
 551                 return 0;
 552
 553         switch (device) {
 554         case PCI_DEVICE_ID_INTEL_82371FB_0:
 555         case PCI_DEVICE_ID_INTEL_82371SB_0:
 556         case PCI_DEVICE_ID_INTEL_82371AB_0:
 557         case PCI_DEVICE_ID_INTEL_82371MX:
 558         case PCI_DEVICE_ID_INTEL_82443MX_0:
 559         case PCI_DEVICE_ID_INTEL_82801AA_0:
 560         case PCI_DEVICE_ID_INTEL_82801AB_0:
 561         case PCI_DEVICE_ID_INTEL_82801BA_0:
 562         case PCI_DEVICE_ID_INTEL_82801BA_10:
 563         case PCI_DEVICE_ID_INTEL_82801CA_0:
 564         case PCI_DEVICE_ID_INTEL_82801CA_12:
 565         case PCI_DEVICE_ID_INTEL_82801DB_0:
 566         case PCI_DEVICE_ID_INTEL_82801E_0:
 567         case PCI_DEVICE_ID_INTEL_82801EB_0:
 568         case PCI_DEVICE_ID_INTEL_ESB_1:
 569         case PCI_DEVICE_ID_INTEL_ICH6_0:
 570         case PCI_DEVICE_ID_INTEL_ICH6_1:
 571         case PCI_DEVICE_ID_INTEL_ICH7_0:
 572         case PCI_DEVICE_ID_INTEL_ICH7_1:
 573         case PCI_DEVICE_ID_INTEL_ICH7_30:
 574         case PCI_DEVICE_ID_INTEL_ICH7_31:
 575         case PCI_DEVICE_ID_INTEL_TGP_LPC:
 576         case PCI_DEVICE_ID_INTEL_ESB2_0:
 577         case PCI_DEVICE_ID_INTEL_ICH8_0:
 578         case PCI_DEVICE_ID_INTEL_ICH8_1:
 579         case PCI_DEVICE_ID_INTEL_ICH8_2:
 580         case PCI_DEVICE_ID_INTEL_ICH8_3:
 581         case PCI_DEVICE_ID_INTEL_ICH8_4:
 582         case PCI_DEVICE_ID_INTEL_ICH9_0:
 583         case PCI_DEVICE_ID_INTEL_ICH9_1:
 584         case PCI_DEVICE_ID_INTEL_ICH9_2:
 585         case PCI_DEVICE_ID_INTEL_ICH9_3:
 586         case PCI_DEVICE_ID_INTEL_ICH9_4:
 587         case PCI_DEVICE_ID_INTEL_ICH9_5:
 588         case PCI_DEVICE_ID_INTEL_TOLAPAI_0:
 589         case PCI_DEVICE_ID_INTEL_ICH10_0:
 590         case PCI_DEVICE_ID_INTEL_ICH10_1:
 591         case PCI_DEVICE_ID_INTEL_ICH10_2:
 592         case PCI_DEVICE_ID_INTEL_ICH10_3:
 593         case PCI_DEVICE_ID_INTEL_CPT_LPC1:
 594         case PCI_DEVICE_ID_INTEL_CPT_LPC2:
 595                 r->name = "PIIX/ICH";
 596                 r->get = pirq_piix_get;
 597                 r->set = pirq_piix_set;
 598                 return 1;
 599         }
 600
 601         if ((device >= PCI_DEVICE_ID_INTEL_PCH_LPC_MIN) &&
 602                 (device <= PCI_DEVICE_ID_INTEL_PCH_LPC_MAX)) {
 603                 r->name = "PIIX/ICH";
 604                 r->get = pirq_piix_get;
 605                 r->set = pirq_piix_set;
 606                 return 1;
 607         }
 608
 609         return 0;
 610 }
 611
 612 static __init int via_router_probe(struct irq_router *r,
 613                                 struct pci_dev *router, u16 device)
 614 {
 615         /* FIXME: We should move some of the quirk fixup stuff here */
 616
 617         /*
 618          * workarounds for some buggy BIOSes
 619          */
 620         if (device == PCI_DEVICE_ID_VIA_82C586_0) {
 621                 switch (router->device) {
 622                 case PCI_DEVICE_ID_VIA_82C686:
 623                         /*
 624                          * Asus k7m bios wrongly reports 82C686A
 625                          * as 586-compatible
 626                          */
 627                         device = PCI_DEVICE_ID_VIA_82C686;
 628                         break;
 629                 case PCI_DEVICE_ID_VIA_8235:
 630                         /**
 631                          * Asus a7v-x bios wrongly reports 8235
 632                          * as 586-compatible
 633                          */
 634                         device = PCI_DEVICE_ID_VIA_8235;
 635                         break;
 636                 case PCI_DEVICE_ID_VIA_8237:
 637                         /**
 638                          * Asus a7v600 bios wrongly reports 8237
 639                          * as 586-compatible
 640                          */
 641                         device = PCI_DEVICE_ID_VIA_8237;
 642                         break;
 643                 }
 644         }
 645
 646         switch (device) {
 647         case PCI_DEVICE_ID_VIA_82C586_0:
 648                 r->name = "VIA";
 649                 r->get = pirq_via586_get;
 650                 r->set = pirq_via586_set;
 651                 return 1;
 652         case PCI_DEVICE_ID_VIA_82C596:
 653         case PCI_DEVICE_ID_VIA_82C686:
 654         case PCI_DEVICE_ID_VIA_8231:
 655         case PCI_DEVICE_ID_VIA_8233A:
 656         case PCI_DEVICE_ID_VIA_8235:
 657         case PCI_DEVICE_ID_VIA_8237:
 658                 /* FIXME: add new ones for 8233/5 */
 659                 r->name = "VIA";
 660                 r->get = pirq_via_get;
 661                 r->set = pirq_via_set;
 662                 return 1;
 663         }
 664         return 0;
 665 }
 666
 667 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 668 {
 669         switch (device) {
 670         case PCI_DEVICE_ID_VLSI_82C534:
 671                 r->name = "VLSI 82C534";
 672                 r->get = pirq_vlsi_get;
 673                 r->set = pirq_vlsi_set;
 674                 return 1;
 675         }
 676         return 0;
 677 }
 678
 679
 680 static __init int serverworks_router_probe(struct irq_router *r,
 681                 struct pci_dev *router, u16 device)
 682 {
 683         switch (device) {
 684         case PCI_DEVICE_ID_SERVERWORKS_OSB4:
 685         case PCI_DEVICE_ID_SERVERWORKS_CSB5:
 686                 r->name = "ServerWorks";
 687                 r->get = pirq_serverworks_get;
 688                 r->set = pirq_serverworks_set;
 689                 return 1;
 690         }
 691         return 0;
 692 }
 693
 694 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 695 {
 696         if (device != PCI_DEVICE_ID_SI_503)
 697                 return 0;
 698
 699         r->name = "SIS";
 700         r->get = pirq_sis_get;
 701         r->set = pirq_sis_set;
 702         return 1;
 703 }
 704
 705 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 706 {
 707         switch (device) {
 708         case PCI_DEVICE_ID_CYRIX_5520:
 709                 r->name = "NatSemi";
 710                 r->get = pirq_cyrix_get;
 711                 r->set = pirq_cyrix_set;
 712                 return 1;
 713         }
 714         return 0;
 715 }
 716
 717 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 718 {
 719         switch (device) {
 720         case PCI_DEVICE_ID_OPTI_82C700:
 721                 r->name = "OPTI";
 722                 r->get = pirq_opti_get;
 723                 r->set = pirq_opti_set;
 724                 return 1;
 725         }
 726         return 0;
 727 }
 728
 729 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 730 {
 731         switch (device) {
 732         case PCI_DEVICE_ID_ITE_IT8330G_0:
 733                 r->name = "ITE";
 734                 r->get = pirq_ite_get;
 735                 r->set = pirq_ite_set;
 736                 return 1;
 737         }
 738         return 0;
 739 }
 740
 741 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 742 {
 743         switch (device) {
 744         case PCI_DEVICE_ID_AL_M1533:
 745         case PCI_DEVICE_ID_AL_M1563:
 746                 r->name = "ALI";
 747                 r->get = pirq_ali_get;
 748                 r->set = pirq_ali_set;
 749                 return 1;
 750         }
 751         return 0;
 752 }
 753
 754 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 755 {
 756         switch (device) {
 757         case PCI_DEVICE_ID_AMD_VIPER_740B:
 758                 r->name = "AMD756";
 759                 break;
 760         case PCI_DEVICE_ID_AMD_VIPER_7413:
 761                 r->name = "AMD766";
 762                 break;
 763         case PCI_DEVICE_ID_AMD_VIPER_7443:
 764                 r->name = "AMD768";
 765                 break;
 766         default:
 767                 return 0;
 768         }
 769         r->get = pirq_amd756_get;
 770         r->set = pirq_amd756_set;
 771         return 1;
 772 }
 773
 774 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 775 {
 776         switch (device) {
 777         case PCI_DEVICE_ID_PICOPOWER_PT86C523:
 778                 r->name = "PicoPower PT86C523";
 779                 r->get = pirq_pico_get;
 780                 r->set = pirq_pico_set;
 781                 return 1;
 782
 783         case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
 784                 r->name = "PicoPower PT86C523 rev. BB+";
 785                 r->get = pirq_pico_get;
 786                 r->set = pirq_pico_set;
 787                 return 1;
 788         }
 789         return 0;
 790 }
 791
 792 static __initdata struct irq_router_handler pirq_routers[] = {
 793         { PCI_VENDOR_ID_INTEL, intel_router_probe },
 794         { PCI_VENDOR_ID_AL, ali_router_probe },
 795         { PCI_VENDOR_ID_ITE, ite_router_probe },
 796         { PCI_VENDOR_ID_VIA, via_router_probe },
 797         { PCI_VENDOR_ID_OPTI, opti_router_probe },
 798         { PCI_VENDOR_ID_SI, sis_router_probe },
 799         { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
 800         { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
 801         { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
 802         { PCI_VENDOR_ID_AMD, amd_router_probe },
 803         { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
 804         /* Someone with docs needs to add the ATI Radeon IGP */
 805         { 0, NULL }
 806 };
 807 static struct irq_router pirq_router;
 808 static struct pci_dev *pirq_router_dev;
 809
 810
 811 /*
 812  *      FIXME: should we have an option to say "generic for
 813  *      chipset" ?
 814  */
 815
 816 static void __init pirq_find_router(struct irq_router *r)
 817 {
 818         struct irq_routing_table *rt = pirq_table;
 819         struct irq_router_handler *h;
 820
 821 #ifdef CONFIG_PCI_BIOS
 822         if (!rt->signature) {
 823                 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
 824                 r->set = pirq_bios_set;
 825                 r->name = "BIOS";
 826                 return;
 827         }
 828 #endif
 829
 830         /* Default unless a driver reloads it */
 831         r->name = "default";
 832         r->get = NULL;
 833         r->set = NULL;
 834
 835         DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
 836             rt->rtr_vendor, rt->rtr_device);
 837
 838         pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn);
 839         if (!pirq_router_dev) {
 840                 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
 841                         "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
 842                 return;
 843         }
 844
 845         for (h = pirq_routers; h->vendor; h++) {
 846                 /* First look for a router match */
 847                 if (rt->rtr_vendor == h->vendor &&
 848                         h->probe(r, pirq_router_dev, rt->rtr_device))
 849                         break;
 850                 /* Fall back to a device match */
 851                 if (pirq_router_dev->vendor == h->vendor &&
 852                         h->probe(r, pirq_router_dev, pirq_router_dev->device))
 853                         break;
 854         }
 855         dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
 856                  pirq_router.name,
 857                  pirq_router_dev->vendor, pirq_router_dev->device);
 858
 859         /* The device remains referenced for the kernel lifetime */
 860 }
 861
 862 static struct irq_info *pirq_get_info(struct pci_dev *dev)
 863 {
 864         struct irq_routing_table *rt = pirq_table;
 865         int entries = (rt->size - sizeof(struct irq_routing_table)) /
 866                 sizeof(struct irq_info);
 867         struct irq_info *info;
 868
 869         for (info = rt->slots; entries--; info++)
 870                 if (info->bus == dev->bus->number &&
 871                         PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
 872                         return info;
 873         return NULL;
 874 }
 875
 876 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
 877 {
 878         u8 pin;
 879         struct irq_info *info;
 880         int i, pirq, newirq;
 881         int irq = 0;
 882         u32 mask;
 883         struct irq_router *r = &pirq_router;
 884         struct pci_dev *dev2 = NULL;
 885         char *msg = NULL;
 886
 887         /* Find IRQ pin */
 888         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
 889         if (!pin) {
 890                 dev_dbg(&dev->dev, "no interrupt pin\n");
 891                 return 0;
 892         }
 893
 894         if (io_apic_assign_pci_irqs)
 895                 return 0;
 896
 897         /* Find IRQ routing entry */
 898
 899         if (!pirq_table)
 900                 return 0;
 901
 902         info = pirq_get_info(dev);
 903         if (!info) {
 904                 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
 905                         'A' + pin - 1);
 906                 return 0;
 907         }
 908         pirq = info->irq[pin - 1].link;
 909         mask = info->irq[pin - 1].bitmap;
 910         if (!pirq) {
 911                 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1);
 912                 return 0;
 913         }
 914         dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
 915                 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs);
 916         mask &= pcibios_irq_mask;
 917
 918         /* Work around broken HP Pavilion Notebooks which assign USB to
 919            IRQ 9 even though it is actually wired to IRQ 11 */
 920
 921         if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
 922                 dev->irq = 11;
 923                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
 924                 r->set(pirq_router_dev, dev, pirq, 11);
 925         }
 926
 927         /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
 928         if (acer_tm360_irqrouting && dev->irq == 11 &&
 929                 dev->vendor == PCI_VENDOR_ID_O2) {
 930                 pirq = 0x68;
 931                 mask = 0x400;
 932                 dev->irq = r->get(pirq_router_dev, dev, pirq);
 933                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 934         }
 935
 936         /*
 937          * Find the best IRQ to assign: use the one
 938          * reported by the device if possible.
 939          */
 940         newirq = dev->irq;
 941         if (newirq && !((1 << newirq) & mask)) {
 942                 if (pci_probe & PCI_USE_PIRQ_MASK)
 943                         newirq = 0;
 944                 else
 945                         dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
 946                                  "%#x; try pci=usepirqmask\n", newirq, mask);
 947         }
 948         if (!newirq && assign) {
 949                 for (i = 0; i < 16; i++) {
 950                         if (!(mask & (1 << i)))
 951                                 continue;
 952                         if (pirq_penalty[i] < pirq_penalty[newirq] &&
 953                                 can_request_irq(i, IRQF_SHARED))
 954                                 newirq = i;
 955                 }
 956         }
 957         dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq);
 958
 959         /* Check if it is hardcoded */
 960         if ((pirq & 0xf0) == 0xf0) {
 961                 irq = pirq & 0xf;
 962                 msg = "hardcoded";
 963         } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
 964         ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
 965                 msg = "found";
 966                 eisa_set_level_irq(irq);
 967         } else if (newirq && r->set &&
 968                 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
 969                 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
 970                         eisa_set_level_irq(newirq);
 971                         msg = "assigned";
 972                         irq = newirq;
 973                 }
 974         }
 975
 976         if (!irq) {
 977                 if (newirq && mask == (1 << newirq)) {
 978                         msg = "guessed";
 979                         irq = newirq;
 980                 } else {
 981                         dev_dbg(&dev->dev, "can't route interrupt\n");
 982                         return 0;
 983                 }
 984         }
 985         dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq);
 986
 987         /* Update IRQ for all devices with the same pirq value */
 988         while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
 989                 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
 990                 if (!pin)
 991                         continue;
 992
 993                 info = pirq_get_info(dev2);
 994                 if (!info)
 995                         continue;
 996                 if (info->irq[pin - 1].link == pirq) {
 997                         /*
 998                          * We refuse to override the dev->irq
 999                          * information. Give a warning!
1000                          */
1001                         if (dev2->irq && dev2->irq != irq && \
1002                         (!(pci_probe & PCI_USE_PIRQ_MASK) || \
1003                         ((1 << dev2->irq) & mask))) {
1004 #ifndef CONFIG_PCI_MSI
1005                                 dev_info(&dev2->dev, "IRQ routing conflict: "
1006                                          "have IRQ %d, want IRQ %d\n",
1007                                          dev2->irq, irq);
1008 #endif
1009                                 continue;
1010                         }
1011                         dev2->irq = irq;
1012                         pirq_penalty[irq]++;
1013                         if (dev != dev2)
1014                                 dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1015                                          irq, pci_name(dev2));
1016                 }
1017         }
1018         return 1;
1019 }
1020
1021 static void __init pcibios_fixup_irqs(void)
1022 {
1023         struct pci_dev *dev = NULL;
1024         u8 pin;
1025
1026         DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1027         while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1028                 /*
1029                  * If the BIOS has set an out of range IRQ number, just
1030                  * ignore it.  Also keep track of which IRQ's are
1031                  * already in use.
1032                  */
1033                 if (dev->irq >= 16) {
1034                         dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1035                         dev->irq = 0;
1036                 }
1037                 /*
1038                  * If the IRQ is already assigned to a PCI device,
1039                  * ignore its ISA use penalty
1040                  */
1041                 if (pirq_penalty[dev->irq] >= 100 &&
1042                                 pirq_penalty[dev->irq] < 100000)
1043                         pirq_penalty[dev->irq] = 0;
1044                 pirq_penalty[dev->irq]++;
1045         }
1046
1047         if (io_apic_assign_pci_irqs)
1048                 return;
1049
1050         dev = NULL;
1051         while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1052                 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1053                 if (!pin)
1054                         continue;
1055
1056                 /*
1057                  * Still no IRQ? Try to lookup one...
1058                  */
1059                 if (!dev->irq)
1060                         pcibios_lookup_irq(dev, 0);
1061         }
1062 }
1063
1064 /*
1065  * Work around broken HP Pavilion Notebooks which assign USB to
1066  * IRQ 9 even though it is actually wired to IRQ 11
1067  */
1068 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1069 {
1070         if (!broken_hp_bios_irq9) {
1071                 broken_hp_bios_irq9 = 1;
1072                 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1073                         d->ident);
1074         }
1075         return 0;
1076 }
1077
1078 /*
1079  * Work around broken Acer TravelMate 360 Notebooks which assign
1080  * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1081  */
1082 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1083 {
1084         if (!acer_tm360_irqrouting) {
1085                 acer_tm360_irqrouting = 1;
1086                 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1087                         d->ident);
1088         }
1089         return 0;
1090 }
1091
1092 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
1093         {
1094                 .callback = fix_broken_hp_bios_irq9,
1095                 .ident = "HP Pavilion N5400 Series Laptop",
1096                 .matches = {
1097                         DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1098                         DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1099                         DMI_MATCH(DMI_PRODUCT_VERSION,
1100                                 "HP Pavilion Notebook Model GE"),
1101                         DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1102                 },
1103         },
1104         {
1105                 .callback = fix_acer_tm360_irqrouting,
1106                 .ident = "Acer TravelMate 36x Laptop",
1107                 .matches = {
1108                         DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1109                         DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1110                 },
1111         },
1112         { }
1113 };
1114
1115 int __init pcibios_irq_init(void)
1116 {
1117         DBG(KERN_DEBUG "PCI: IRQ init\n");
1118
1119         if (pcibios_enable_irq || raw_pci_ops == NULL)
1120                 return 0;
1121
1122         dmi_check_system(pciirq_dmi_table);
1123
1124         pirq_table = pirq_find_routing_table();
1125
1126 #ifdef CONFIG_PCI_BIOS
1127         if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
1128                 pirq_table = pcibios_get_irq_routing_table();
1129 #endif
1130         if (pirq_table) {
1131                 pirq_peer_trick();
1132                 pirq_find_router(&pirq_router);
1133                 if (pirq_table->exclusive_irqs) {
1134                         int i;
1135                         for (i = 0; i < 16; i++)
1136                                 if (!(pirq_table->exclusive_irqs & (1 << i)))
1137                                         pirq_penalty[i] += 100;
1138                 }
1139                 /*
1140                  * If we're using the I/O APIC, avoid using the PCI IRQ
1141                  * routing table
1142                  */
1143                 if (io_apic_assign_pci_irqs)
1144                         pirq_table = NULL;
1145         }
1146
1147         pcibios_enable_irq = pirq_enable_irq;
1148
1149         pcibios_fixup_irqs();
1150
1151         if (io_apic_assign_pci_irqs && pci_routeirq) {
1152                 struct pci_dev *dev = NULL;
1153                 /*
1154                  * PCI IRQ routing is set up by pci_enable_device(), but we
1155                  * also do it here in case there are still broken drivers that
1156                  * don't use pci_enable_device().
1157                  */
1158                 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
1159                 for_each_pci_dev(dev)
1160                         pirq_enable_irq(dev);
1161         }
1162
1163         return 0;
1164 }
1165
1166 static void pirq_penalize_isa_irq(int irq, int active)
1167 {
1168         /*
1169          *  If any ISAPnP device reports an IRQ in its list of possible
1170          *  IRQ's, we try to avoid assigning it to PCI devices.
1171          */
1172         if (irq < 16) {
1173                 if (active)
1174                         pirq_penalty[irq] += 1000;
1175                 else
1176                         pirq_penalty[irq] += 100;
1177         }
1178 }
1179
1180 void pcibios_penalize_isa_irq(int irq, int active)
1181 {
1182 #ifdef CONFIG_ACPI
1183         if (!acpi_noirq)
1184                 acpi_penalize_isa_irq(irq, active);
1185         else
1186 #endif
1187                 pirq_penalize_isa_irq(irq, active);
1188 }
1189
1190 static int pirq_enable_irq(struct pci_dev *dev)
1191 {
1192         u8 pin;
1193
1194         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1195         if (pin && !pcibios_lookup_irq(dev, 1)) {
1196                 char *msg = "";
1197
1198                 if (!io_apic_assign_pci_irqs && dev->irq)
1199                         return 0;
1200
1201                 if (io_apic_assign_pci_irqs) {
1202 #ifdef CONFIG_X86_IO_APIC
1203                         struct pci_dev *temp_dev;
1204                         int irq;
1205                         struct io_apic_irq_attr irq_attr;
1206
1207                         irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
1208                                                 PCI_SLOT(dev->devfn),
1209                                                 pin - 1, &irq_attr);
1210                         /*
1211                          * Busses behind bridges are typically not listed in the MP-table.
1212                          * In this case we have to look up the IRQ based on the parent bus,
1213                          * parent slot, and pin number. The SMP code detects such bridged
1214                          * busses itself so we should get into this branch reliably.
1215                          */
1216                         temp_dev = dev;
1217                         while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1218                                 struct pci_dev *bridge = dev->bus->self;
1219
1220                                 pin = pci_swizzle_interrupt_pin(dev, pin);
1221                                 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1222                                                 PCI_SLOT(bridge->devfn),
1223                                                 pin - 1, &irq_attr);
1224                                 if (irq >= 0)
1225                                         dev_warn(&dev->dev, "using bridge %s "
1226                                                  "INT %c to get IRQ %d\n",
1227                                                  pci_name(bridge), 'A' + pin - 1,
1228                                                  irq);
1229                                 dev = bridge;
1230                         }
1231                         dev = temp_dev;
1232                         if (irq >= 0) {
1233                                 io_apic_set_pci_routing(&dev->dev, irq,
1234                                                          &irq_attr);
1235                                 dev->irq = irq;
1236                                 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1237                                          "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
1238                                 return 0;
1239                         } else
1240                                 msg = "; probably buggy MP table";
1241 #endif
1242                 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1243                         msg = "";
1244                 else
1245                         msg = "; please try using pci=biosirq";
1246
1247                 /*
1248                  * With IDE legacy devices the IRQ lookup failure is not
1249                  * a problem..
1250                  */
1251                 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1252                                 !(dev->class & 0x5))
1253                         return 0;
1254
1255                 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1256                          'A' + pin - 1, msg);
1257         }
1258         return 0;
1259 }