arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <linux/smp.h>
   5 #include <linux/prctl.h>
   6 #include <linux/slab.h>
   7 #include <linux/sched.h>
   8 #include <linux/module.h>
   9 #include <linux/pm.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/ftrace.h>
  12 #include <asm/system.h>
  13 #include <asm/apic.h>
  14 #include <asm/idle.h>
  15 #include <asm/uaccess.h>
  16 #include <asm/i387.h>
  17
  18 unsigned long idle_halt;
  19 EXPORT_SYMBOL(idle_halt);
  20 unsigned long idle_nomwait;
  21 EXPORT_SYMBOL(idle_nomwait);
  22
  23 struct kmem_cache *task_xstate_cachep;
  24
  25 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  26 {
  27         *dst = *src;
  28         if (src->thread.xstate) {
  29                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
  30                                                       GFP_KERNEL);
  31                 if (!dst->thread.xstate)
  32                         return -ENOMEM;
  33                 WARN_ON((unsigned long)dst->thread.xstate & 15);
  34                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
  35         }
  36         return 0;
  37 }
  38
  39 void free_thread_xstate(struct task_struct *tsk)
  40 {
  41         if (tsk->thread.xstate) {
  42                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
  43                 tsk->thread.xstate = NULL;
  44         }
  45 }
  46
  47 void free_thread_info(struct thread_info *ti)
  48 {
  49         free_thread_xstate(ti->task);
  50         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  51 }
  52
  53 void arch_task_cache_init(void)
  54 {
  55         task_xstate_cachep =
  56                 kmem_cache_create("task_xstate", xstate_size,
  57                                   __alignof__(union thread_xstate),
  58                                   SLAB_PANIC, NULL);
  59 }
  60
  61 /*
  62  * Free current thread data structures etc..
  63  */
  64 void exit_thread(void)
  65 {
  66         struct task_struct *me = current;
  67         struct thread_struct *t = &me->thread;
  68
  69         if (me->thread.io_bitmap_ptr) {
  70                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
  71
  72                 kfree(t->io_bitmap_ptr);
  73                 t->io_bitmap_ptr = NULL;
  74                 clear_thread_flag(TIF_IO_BITMAP);
  75                 /*
  76                  * Careful, clear this in the TSS too:
  77                  */
  78                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
  79                 t->io_bitmap_max = 0;
  80                 put_cpu();
  81         }
  82
  83         ds_exit_thread(current);
  84 }
  85
  86 void flush_thread(void)
  87 {
  88         struct task_struct *tsk = current;
  89
  90 #ifdef CONFIG_X86_64
  91         if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
  92                 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
  93                 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
  94                         clear_tsk_thread_flag(tsk, TIF_IA32);
  95                 } else {
  96                         set_tsk_thread_flag(tsk, TIF_IA32);
  97                         current_thread_info()->status |= TS_COMPAT;
  98                 }
  99         }
 100 #endif
 101
 102         clear_tsk_thread_flag(tsk, TIF_DEBUG);
 103
 104         tsk->thread.debugreg0 = 0;
 105         tsk->thread.debugreg1 = 0;
 106         tsk->thread.debugreg2 = 0;
 107         tsk->thread.debugreg3 = 0;
 108         tsk->thread.debugreg6 = 0;
 109         tsk->thread.debugreg7 = 0;
 110         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 111         /*
 112          * Forget coprocessor state..
 113          */
 114         tsk->fpu_counter = 0;
 115         clear_fpu(tsk);
 116         clear_used_math();
 117 }
 118
 119 static void hard_disable_TSC(void)
 120 {
 121         write_cr4(read_cr4() | X86_CR4_TSD);
 122 }
 123
 124 void disable_TSC(void)
 125 {
 126         preempt_disable();
 127         if (!test_and_set_thread_flag(TIF_NOTSC))
 128                 /*
 129                  * Must flip the CPU state synchronously with
 130                  * TIF_NOTSC in the current running context.
 131                  */
 132                 hard_disable_TSC();
 133         preempt_enable();
 134 }
 135
 136 static void hard_enable_TSC(void)
 137 {
 138         write_cr4(read_cr4() & ~X86_CR4_TSD);
 139 }
 140
 141 static void enable_TSC(void)
 142 {
 143         preempt_disable();
 144         if (test_and_clear_thread_flag(TIF_NOTSC))
 145                 /*
 146                  * Must flip the CPU state synchronously with
 147                  * TIF_NOTSC in the current running context.
 148                  */
 149                 hard_enable_TSC();
 150         preempt_enable();
 151 }
 152
 153 int get_tsc_mode(unsigned long adr)
 154 {
 155         unsigned int val;
 156
 157         if (test_thread_flag(TIF_NOTSC))
 158                 val = PR_TSC_SIGSEGV;
 159         else
 160                 val = PR_TSC_ENABLE;
 161
 162         return put_user(val, (unsigned int __user *)adr);
 163 }
 164
 165 int set_tsc_mode(unsigned int val)
 166 {
 167         if (val == PR_TSC_SIGSEGV)
 168                 disable_TSC();
 169         else if (val == PR_TSC_ENABLE)
 170                 enable_TSC();
 171         else
 172                 return -EINVAL;
 173
 174         return 0;
 175 }
 176
 177 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 178                       struct tss_struct *tss)
 179 {
 180         struct thread_struct *prev, *next;
 181
 182         prev = &prev_p->thread;
 183         next = &next_p->thread;
 184
 185         if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
 186             test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
 187                 ds_switch_to(prev_p, next_p);
 188         else if (next->debugctlmsr != prev->debugctlmsr)
 189                 update_debugctlmsr(next->debugctlmsr);
 190
 191         if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
 192                 set_debugreg(next->debugreg0, 0);
 193                 set_debugreg(next->debugreg1, 1);
 194                 set_debugreg(next->debugreg2, 2);
 195                 set_debugreg(next->debugreg3, 3);
 196                 /* no 4 and 5 */
 197                 set_debugreg(next->debugreg6, 6);
 198                 set_debugreg(next->debugreg7, 7);
 199         }
 200
 201         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 202             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 203                 /* prev and next are different */
 204                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 205                         hard_disable_TSC();
 206                 else
 207                         hard_enable_TSC();
 208         }
 209
 210         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 211                 /*
 212                  * Copy the relevant range of the IO bitmap.
 213                  * Normally this is 128 bytes or less:
 214                  */
 215                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 216                        max(prev->io_bitmap_max, next->io_bitmap_max));
 217         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 218                 /*
 219                  * Clear any possible leftover bits:
 220                  */
 221                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 222         }
 223 }
 224
 225 int sys_fork(struct pt_regs *regs)
 226 {
 227         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
 228 }
 229
 230 /*
 231  * This is trivial, and on the face of it looks like it
 232  * could equally well be done in user mode.
 233  *
 234  * Not so, for quite unobvious reasons - register pressure.
 235  * In user mode vfork() cannot have a stack frame, and if
 236  * done by calling the "clone()" system call directly, you
 237  * do not have enough call-clobbered registers to hold all
 238  * the information you need.
 239  */
 240 int sys_vfork(struct pt_regs *regs)
 241 {
 242         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
 243                        NULL, NULL);
 244 }
 245
 246
 247 /*
 248  * Idle related variables and functions
 249  */
 250 unsigned long boot_option_idle_override = 0;
 251 EXPORT_SYMBOL(boot_option_idle_override);
 252
 253 /*
 254  * Powermanagement idle function, if any..
 255  */
 256 void (*pm_idle)(void);
 257 EXPORT_SYMBOL(pm_idle);
 258
 259 #ifdef CONFIG_X86_32
 260 /*
 261  * This halt magic was a workaround for ancient floppy DMA
 262  * wreckage. It should be safe to remove.
 263  */
 264 static int hlt_counter;
 265 void disable_hlt(void)
 266 {
 267         hlt_counter++;
 268 }
 269 EXPORT_SYMBOL(disable_hlt);
 270
 271 void enable_hlt(void)
 272 {
 273         hlt_counter--;
 274 }
 275 EXPORT_SYMBOL(enable_hlt);
 276
 277 static inline int hlt_use_halt(void)
 278 {
 279         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
 280 }
 281 #else
 282 static inline int hlt_use_halt(void)
 283 {
 284         return 1;
 285 }
 286 #endif
 287
 288 /*
 289  * We use this if we don't have any better
 290  * idle routine..
 291  */
 292 void default_idle(void)
 293 {
 294         if (hlt_use_halt()) {
 295                 struct power_trace it;
 296
 297                 trace_power_start(&it, POWER_CSTATE, 1);
 298                 current_thread_info()->status &= ~TS_POLLING;
 299                 /*
 300                  * TS_POLLING-cleared state must be visible before we
 301                  * test NEED_RESCHED:
 302                  */
 303                 smp_mb();
 304
 305                 if (!need_resched())
 306                         safe_halt();    /* enables interrupts racelessly */
 307                 else
 308                         local_irq_enable();
 309                 current_thread_info()->status |= TS_POLLING;
 310                 trace_power_end(&it);
 311         } else {
 312                 local_irq_enable();
 313                 /* loop is done by the caller */
 314                 cpu_relax();
 315         }
 316 }
 317 #ifdef CONFIG_APM_MODULE
 318 EXPORT_SYMBOL(default_idle);
 319 #endif
 320
 321 void stop_this_cpu(void *dummy)
 322 {
 323         local_irq_disable();
 324         /*
 325          * Remove this CPU:
 326          */
 327         set_cpu_online(smp_processor_id(), false);
 328         disable_local_APIC();
 329
 330         for (;;) {
 331                 if (hlt_works(smp_processor_id()))
 332                         halt();
 333         }
 334 }
 335
 336 static void do_nothing(void *unused)
 337 {
 338 }
 339
 340 /*
 341  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 342  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 343  * handler on SMP systems.
 344  *
 345  * Caller must have changed pm_idle to the new value before the call. Old
 346  * pm_idle value will not be used by any CPU after the return of this function.
 347  */
 348 void cpu_idle_wait(void)
 349 {
 350         smp_mb();
 351         /* kick all the CPUs so that they exit out of pm_idle */
 352         smp_call_function(do_nothing, NULL, 1);
 353 }
 354 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 355
 356 /*
 357  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 358  * which can obviate IPI to trigger checking of need_resched.
 359  * We execute MONITOR against need_resched and enter optimized wait state
 360  * through MWAIT. Whenever someone changes need_resched, we would be woken
 361  * up from MWAIT (without an IPI).
 362  *
 363  * New with Core Duo processors, MWAIT can take some hints based on CPU
 364  * capability.
 365  */
 366 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 367 {
 368         struct power_trace it;
 369
 370         trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
 371         if (!need_resched()) {
 372                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 373                         clflush((void *)&current_thread_info()->flags);
 374
 375                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 376                 smp_mb();
 377                 if (!need_resched())
 378                         __mwait(ax, cx);
 379         }
 380         trace_power_end(&it);
 381 }
 382
 383 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 384 static void mwait_idle(void)
 385 {
 386         struct power_trace it;
 387         if (!need_resched()) {
 388                 trace_power_start(&it, POWER_CSTATE, 1);
 389                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 390                         clflush((void *)&current_thread_info()->flags);
 391
 392                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 393                 smp_mb();
 394                 if (!need_resched())
 395                         __sti_mwait(0, 0);
 396                 else
 397                         local_irq_enable();
 398                 trace_power_end(&it);
 399         } else
 400                 local_irq_enable();
 401 }
 402
 403 /*
 404  * On SMP it's slightly faster (but much more power-consuming!)
 405  * to poll the ->work.need_resched flag instead of waiting for the
 406  * cross-CPU IPI to arrive. Use this option with caution.
 407  */
 408 static void poll_idle(void)
 409 {
 410         struct power_trace it;
 411
 412         trace_power_start(&it, POWER_CSTATE, 0);
 413         local_irq_enable();
 414         while (!need_resched())
 415                 cpu_relax();
 416         trace_power_end(&it);
 417 }
 418
 419 /*
 420  * mwait selection logic:
 421  *
 422  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 423  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 424  * then depend on a clock divisor and current Pstate of the core. If
 425  * all cores of a processor are in halt state (C1) the processor can
 426  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 427  * happen.
 428  *
 429  * idle=mwait overrides this decision and forces the usage of mwait.
 430  */
 431 static int __cpuinitdata force_mwait;
 432
 433 #define MWAIT_INFO                      0x05
 434 #define MWAIT_ECX_EXTENDED_INFO         0x01
 435 #define MWAIT_EDX_C1                    0xf0
 436
 437 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 438 {
 439         u32 eax, ebx, ecx, edx;
 440
 441         if (force_mwait)
 442                 return 1;
 443
 444         if (c->cpuid_level < MWAIT_INFO)
 445                 return 0;
 446
 447         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 448         /* Check, whether EDX has extended info about MWAIT */
 449         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 450                 return 1;
 451
 452         /*
 453          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 454          * C1  supports MWAIT
 455          */
 456         return (edx & MWAIT_EDX_C1);
 457 }
 458
 459 /*
 460  * Check for AMD CPUs, which have potentially C1E support
 461  */
 462 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 463 {
 464         if (c->x86_vendor != X86_VENDOR_AMD)
 465                 return 0;
 466
 467         if (c->x86 < 0x0F)
 468                 return 0;
 469
 470         /* Family 0x0f models < rev F do not have C1E */
 471         if (c->x86 == 0x0f && c->x86_model < 0x40)
 472                 return 0;
 473
 474         return 1;
 475 }
 476
 477 static cpumask_var_t c1e_mask;
 478 static int c1e_detected;
 479
 480 void c1e_remove_cpu(int cpu)
 481 {
 482         if (c1e_mask != NULL)
 483                 cpumask_clear_cpu(cpu, c1e_mask);
 484 }
 485
 486 /*
 487  * C1E aware idle routine. We check for C1E active in the interrupt
 488  * pending message MSR. If we detect C1E, then we handle it the same
 489  * way as C3 power states (local apic timer and TSC stop)
 490  */
 491 static void c1e_idle(void)
 492 {
 493         if (need_resched())
 494                 return;
 495
 496         if (!c1e_detected) {
 497                 u32 lo, hi;
 498
 499                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 500                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 501                         c1e_detected = 1;
 502                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 503                                 mark_tsc_unstable("TSC halt in AMD C1E");
 504                         printk(KERN_INFO "System has AMD C1E enabled\n");
 505                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
 506                 }
 507         }
 508
 509         if (c1e_detected) {
 510                 int cpu = smp_processor_id();
 511
 512                 if (!cpumask_test_cpu(cpu, c1e_mask)) {
 513                         cpumask_set_cpu(cpu, c1e_mask);
 514                         /*
 515                          * Force broadcast so ACPI can not interfere. Needs
 516                          * to run with interrupts enabled as it uses
 517                          * smp_function_call.
 518                          */
 519                         local_irq_enable();
 520                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 521                                            &cpu);
 522                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 523                                cpu);
 524                         local_irq_disable();
 525                 }
 526                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 527
 528                 default_idle();
 529
 530                 /*
 531                  * The switch back from broadcast mode needs to be
 532                  * called with interrupts disabled.
 533                  */
 534                  local_irq_disable();
 535                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 536                  local_irq_enable();
 537         } else
 538                 default_idle();
 539 }
 540
 541 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 542 {
 543 #ifdef CONFIG_SMP
 544         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 545                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
 546                         " performance may degrade.\n");
 547         }
 548 #endif
 549         if (pm_idle)
 550                 return;
 551
 552         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 553                 /*
 554                  * One CPU supports mwait => All CPUs supports mwait
 555                  */
 556                 printk(KERN_INFO "using mwait in idle threads.\n");
 557                 pm_idle = mwait_idle;
 558         } else if (check_c1e_idle(c)) {
 559                 printk(KERN_INFO "using C1E aware idle routine\n");
 560                 pm_idle = c1e_idle;
 561         } else
 562                 pm_idle = default_idle;
 563 }
 564
 565 void __init init_c1e_mask(void)
 566 {
 567         /* If we're using c1e_idle, we need to allocate c1e_mask. */
 568         if (pm_idle == c1e_idle) {
 569                 alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
 570                 cpumask_clear(c1e_mask);
 571         }
 572 }
 573
 574 static int __init idle_setup(char *str)
 575 {
 576         if (!str)
 577                 return -EINVAL;
 578
 579         if (!strcmp(str, "poll")) {
 580                 printk("using polling idle threads.\n");
 581                 pm_idle = poll_idle;
 582         } else if (!strcmp(str, "mwait"))
 583                 force_mwait = 1;
 584         else if (!strcmp(str, "halt")) {
 585                 /*
 586                  * When the boot option of idle=halt is added, halt is
 587                  * forced to be used for CPU idle. In such case CPU C2/C3
 588                  * won't be used again.
 589                  * To continue to load the CPU idle driver, don't touch
 590                  * the boot_option_idle_override.
 591                  */
 592                 pm_idle = default_idle;
 593                 idle_halt = 1;
 594                 return 0;
 595         } else if (!strcmp(str, "nomwait")) {
 596                 /*
 597                  * If the boot option of "idle=nomwait" is added,
 598                  * it means that mwait will be disabled for CPU C2/C3
 599                  * states. In such case it won't touch the variable
 600                  * of boot_option_idle_override.
 601                  */
 602                 idle_nomwait = 1;
 603                 return 0;
 604         } else
 605                 return -1;
 606
 607         boot_option_idle_override = 1;
 608         return 0;
 609 }
 610 early_param("idle", idle_setup);
 611