arch/x86/kernel/cpu/common.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3 #include <linux/sched.h>
   4 #include <linux/string.h>
   5 #include <linux/bootmem.h>
   6 #include <linux/bitops.h>
   7 #include <linux/module.h>
   8 #include <linux/kgdb.h>
   9 #include <linux/topology.h>
  10 #include <linux/delay.h>
  11 #include <linux/smp.h>
  12 #include <linux/percpu.h>
  13 #include <asm/i387.h>
  14 #include <asm/msr.h>
  15 #include <asm/io.h>
  16 #include <asm/linkage.h>
  17 #include <asm/mmu_context.h>
  18 #include <asm/mtrr.h>
  19 #include <asm/mce.h>
  20 #include <asm/pat.h>
  21 #include <asm/asm.h>
  22 #include <asm/numa.h>
  23 #include <asm/smp.h>
  24 #include <asm/cpu.h>
  25 #include <asm/cpumask.h>
  26 #include <asm/apic.h>
  27
  28 #ifdef CONFIG_X86_LOCAL_APIC
  29 #include <asm/uv/uv.h>
  30 #endif
  31
  32 #include <asm/pgtable.h>
  33 #include <asm/processor.h>
  34 #include <asm/desc.h>
  35 #include <asm/atomic.h>
  36 #include <asm/proto.h>
  37 #include <asm/sections.h>
  38 #include <asm/setup.h>
  39 #include <asm/hypervisor.h>
  40 #include <asm/stackprotector.h>
  41
  42 #include "cpu.h"
  43
  44 /* all of these masks are initialized in setup_cpu_local_masks() */
  45 cpumask_var_t cpu_callin_mask;
  46 cpumask_var_t cpu_callout_mask;
  47 cpumask_var_t cpu_initialized_mask;
  48
  49 /* representing cpus for which sibling maps can be computed */
  50 cpumask_var_t cpu_sibling_setup_mask;
  51
  52 /* correctly size the local cpu masks */
  53 void __init setup_cpu_local_masks(void)
  54 {
  55         alloc_bootmem_cpumask_var(&cpu_initialized_mask);
  56         alloc_bootmem_cpumask_var(&cpu_callin_mask);
  57         alloc_bootmem_cpumask_var(&cpu_callout_mask);
  58         alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
  59 }
  60
  61 static struct cpu_dev *this_cpu __cpuinitdata;
  62
  63 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
  64 #ifdef CONFIG_X86_64
  65         /*
  66          * We need valid kernel segments for data and code in long mode too
  67          * IRET will check the segment types  kkeil 2000/10/28
  68          * Also sysret mandates a special GDT layout
  69          *
  70          * The TLS descriptors are currently at a different place compared to i386.
  71          * Hopefully nobody expects them at a fixed place (Wine?)
  72          */
  73         [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
  74         [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
  75         [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
  76         [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
  77         [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
  78         [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
  79 #else
  80         [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
  81         [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
  82         [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
  83         [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
  84         /*
  85          * Segments used for calling PnP BIOS have byte granularity.
  86          * They code segments and data segments have fixed 64k limits,
  87          * the transfer segment sizes are set at run time.
  88          */
  89         /* 32-bit code */
  90         [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
  91         /* 16-bit code */
  92         [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
  93         /* 16-bit data */
  94         [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
  95         /* 16-bit data */
  96         [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
  97         /* 16-bit data */
  98         [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
  99         /*
 100          * The APM segments have byte granularity and their bases
 101          * are set at run time.  All have 64k limits.
 102          */
 103         /* 32-bit code */
 104         [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
 105         /* 16-bit code */
 106         [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
 107         /* data */
 108         [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
 109
 110         [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
 111         [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } },
 112         GDT_STACK_CANARY_INIT
 113 #endif
 114 } };
 115 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
 116
 117 #ifdef CONFIG_X86_32
 118 static int cachesize_override __cpuinitdata = -1;
 119 static int disable_x86_serial_nr __cpuinitdata = 1;
 120
 121 static int __init cachesize_setup(char *str)
 122 {
 123         get_option(&str, &cachesize_override);
 124         return 1;
 125 }
 126 __setup("cachesize=", cachesize_setup);
 127
 128 static int __init x86_fxsr_setup(char *s)
 129 {
 130         setup_clear_cpu_cap(X86_FEATURE_FXSR);
 131         setup_clear_cpu_cap(X86_FEATURE_XMM);
 132         return 1;
 133 }
 134 __setup("nofxsr", x86_fxsr_setup);
 135
 136 static int __init x86_sep_setup(char *s)
 137 {
 138         setup_clear_cpu_cap(X86_FEATURE_SEP);
 139         return 1;
 140 }
 141 __setup("nosep", x86_sep_setup);
 142
 143 /* Standard macro to see if a specific flag is changeable */
 144 static inline int flag_is_changeable_p(u32 flag)
 145 {
 146         u32 f1, f2;
 147
 148         /*
 149          * Cyrix and IDT cpus allow disabling of CPUID
 150          * so the code below may return different results
 151          * when it is executed before and after enabling
 152          * the CPUID. Add "volatile" to not allow gcc to
 153          * optimize the subsequent calls to this function.
 154          */
 155         asm volatile ("pushfl\n\t"
 156                       "pushfl\n\t"
 157                       "popl %0\n\t"
 158                       "movl %0,%1\n\t"
 159                       "xorl %2,%0\n\t"
 160                       "pushl %0\n\t"
 161                       "popfl\n\t"
 162                       "pushfl\n\t"
 163                       "popl %0\n\t"
 164                       "popfl\n\t"
 165                       : "=&r" (f1), "=&r" (f2)
 166                       : "ir" (flag));
 167
 168         return ((f1^f2) & flag) != 0;
 169 }
 170
 171 /* Probe for the CPUID instruction */
 172 static int __cpuinit have_cpuid_p(void)
 173 {
 174         return flag_is_changeable_p(X86_EFLAGS_ID);
 175 }
 176
 177 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 178 {
 179         if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
 180                 /* Disable processor serial number */
 181                 unsigned long lo, hi;
 182                 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 183                 lo |= 0x200000;
 184                 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 185                 printk(KERN_NOTICE "CPU serial number disabled.\n");
 186                 clear_cpu_cap(c, X86_FEATURE_PN);
 187
 188                 /* Disabling the serial number may affect the cpuid level */
 189                 c->cpuid_level = cpuid_eax(0);
 190         }
 191 }
 192
 193 static int __init x86_serial_nr_setup(char *s)
 194 {
 195         disable_x86_serial_nr = 0;
 196         return 1;
 197 }
 198 __setup("serialnumber", x86_serial_nr_setup);
 199 #else
 200 static inline int flag_is_changeable_p(u32 flag)
 201 {
 202         return 1;
 203 }
 204 /* Probe for the CPUID instruction */
 205 static inline int have_cpuid_p(void)
 206 {
 207         return 1;
 208 }
 209 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 210 {
 211 }
 212 #endif
 213
 214 /*
 215  * Some CPU features depend on higher CPUID levels, which may not always
 216  * be available due to CPUID level capping or broken virtualization
 217  * software.  Add those features to this table to auto-disable them.
 218  */
 219 struct cpuid_dependent_feature {
 220         u32 feature;
 221         u32 level;
 222 };
 223 static const struct cpuid_dependent_feature __cpuinitconst
 224 cpuid_dependent_features[] = {
 225         { X86_FEATURE_MWAIT,            0x00000005 },
 226         { X86_FEATURE_DCA,              0x00000009 },
 227         { X86_FEATURE_XSAVE,            0x0000000d },
 228         { 0, 0 }
 229 };
 230
 231 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
 232 {
 233         const struct cpuid_dependent_feature *df;
 234         for (df = cpuid_dependent_features; df->feature; df++) {
 235                 /*
 236                  * Note: cpuid_level is set to -1 if unavailable, but
 237                  * extended_extended_level is set to 0 if unavailable
 238                  * and the legitimate extended levels are all negative
 239                  * when signed; hence the weird messing around with
 240                  * signs here...
 241                  */
 242                 if (cpu_has(c, df->feature) &&
 243                     ((s32)df->level < 0 ?
 244                      (u32)df->level > (u32)c->extended_cpuid_level :
 245                      (s32)df->level > (s32)c->cpuid_level)) {
 246                         clear_cpu_cap(c, df->feature);
 247                         if (warn)
 248                                 printk(KERN_WARNING
 249                                        "CPU: CPU feature %s disabled "
 250                                        "due to lack of CPUID level 0x%x\n",
 251                                        x86_cap_flags[df->feature],
 252                                        df->level);
 253                 }
 254         }
 255 }
 256
 257 /*
 258  * Naming convention should be: <Name> [(<Codename>)]
 259  * This table only is used unless init_<vendor>() below doesn't set it;
 260  * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
 261  *
 262  */
 263
 264 /* Look up CPU names by table lookup. */
 265 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
 266 {
 267         struct cpu_model_info *info;
 268
 269         if (c->x86_model >= 16)
 270                 return NULL;    /* Range check */
 271
 272         if (!this_cpu)
 273                 return NULL;
 274
 275         info = this_cpu->c_models;
 276
 277         while (info && info->family) {
 278                 if (info->family == c->x86)
 279                         return info->model_names[c->x86_model];
 280                 info++;
 281         }
 282         return NULL;            /* Not found */
 283 }
 284
 285 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
 286
 287 void load_percpu_segment(int cpu)
 288 {
 289 #ifdef CONFIG_X86_32
 290         loadsegment(fs, __KERNEL_PERCPU);
 291 #else
 292         loadsegment(gs, 0);
 293         wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
 294 #endif
 295         load_stack_canary_segment();
 296 }
 297
 298 /* Current gdt points %fs at the "master" per-cpu area: after this,
 299  * it's on the real one. */
 300 void switch_to_new_gdt(int cpu)
 301 {
 302         struct desc_ptr gdt_descr;
 303
 304         gdt_descr.address = (long)get_cpu_gdt_table(cpu);
 305         gdt_descr.size = GDT_SIZE - 1;
 306         load_gdt(&gdt_descr);
 307         /* Reload the per-cpu base */
 308
 309         load_percpu_segment(cpu);
 310 }
 311
 312 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
 313
 314 static void __cpuinit default_init(struct cpuinfo_x86 *c)
 315 {
 316 #ifdef CONFIG_X86_64
 317         display_cacheinfo(c);
 318 #else
 319         /* Not much we can do here... */
 320         /* Check if at least it has cpuid */
 321         if (c->cpuid_level == -1) {
 322                 /* No cpuid. It must be an ancient CPU */
 323                 if (c->x86 == 4)
 324                         strcpy(c->x86_model_id, "486");
 325                 else if (c->x86 == 3)
 326                         strcpy(c->x86_model_id, "386");
 327         }
 328 #endif
 329 }
 330
 331 static struct cpu_dev __cpuinitdata default_cpu = {
 332         .c_init = default_init,
 333         .c_vendor = "Unknown",
 334         .c_x86_vendor = X86_VENDOR_UNKNOWN,
 335 };
 336
 337 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
 338 {
 339         unsigned int *v;
 340         char *p, *q;
 341
 342         if (c->extended_cpuid_level < 0x80000004)
 343                 return;
 344
 345         v = (unsigned int *) c->x86_model_id;
 346         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 347         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 348         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 349         c->x86_model_id[48] = 0;
 350
 351         /* Intel chips right-justify this string for some dumb reason;
 352            undo that brain damage */
 353         p = q = &c->x86_model_id[0];
 354         while (*p == ' ')
 355              p++;
 356         if (p != q) {
 357              while (*p)
 358                   *q++ = *p++;
 359              while (q <= &c->x86_model_id[48])
 360                   *q++ = '\0';  /* Zero-pad the rest */
 361         }
 362 }
 363
 364 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 365 {
 366         unsigned int n, dummy, ebx, ecx, edx, l2size;
 367
 368         n = c->extended_cpuid_level;
 369
 370         if (n >= 0x80000005) {
 371                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 372                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
 373                                 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
 374                 c->x86_cache_size = (ecx>>24) + (edx>>24);
 375 #ifdef CONFIG_X86_64
 376                 /* On K8 L1 TLB is inclusive, so don't count it */
 377                 c->x86_tlbsize = 0;
 378 #endif
 379         }
 380
 381         if (n < 0x80000006)     /* Some chips just has a large L1. */
 382                 return;
 383
 384         cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 385         l2size = ecx >> 16;
 386
 387 #ifdef CONFIG_X86_64
 388         c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 389 #else
 390         /* do processor-specific cache resizing */
 391         if (this_cpu->c_size_cache)
 392                 l2size = this_cpu->c_size_cache(c, l2size);
 393
 394         /* Allow user to override all this if necessary. */
 395         if (cachesize_override != -1)
 396                 l2size = cachesize_override;
 397
 398         if (l2size == 0)
 399                 return;         /* Again, no L2 cache is possible */
 400 #endif
 401
 402         c->x86_cache_size = l2size;
 403
 404         printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 405                         l2size, ecx & 0xFF);
 406 }
 407
 408 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 409 {
 410 #ifdef CONFIG_X86_HT
 411         u32 eax, ebx, ecx, edx;
 412         int index_msb, core_bits;
 413
 414         if (!cpu_has(c, X86_FEATURE_HT))
 415                 return;
 416
 417         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
 418                 goto out;
 419
 420         if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
 421                 return;
 422
 423         cpuid(1, &eax, &ebx, &ecx, &edx);
 424
 425         smp_num_siblings = (ebx & 0xff0000) >> 16;
 426
 427         if (smp_num_siblings == 1) {
 428                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
 429         } else if (smp_num_siblings > 1) {
 430
 431                 if (smp_num_siblings > nr_cpu_ids) {
 432                         printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
 433                                         smp_num_siblings);
 434                         smp_num_siblings = 1;
 435                         return;
 436                 }
 437
 438                 index_msb = get_count_order(smp_num_siblings);
 439                 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
 440
 441                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 442
 443                 index_msb = get_count_order(smp_num_siblings);
 444
 445                 core_bits = get_count_order(c->x86_max_cores);
 446
 447                 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
 448                                                ((1 << core_bits) - 1);
 449         }
 450
 451 out:
 452         if ((c->x86_max_cores * smp_num_siblings) > 1) {
 453                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
 454                        c->phys_proc_id);
 455                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
 456                        c->cpu_core_id);
 457         }
 458 #endif
 459 }
 460
 461 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 462 {
 463         char *v = c->x86_vendor_id;
 464         int i;
 465         static int printed;
 466
 467         for (i = 0; i < X86_VENDOR_NUM; i++) {
 468                 if (!cpu_devs[i])
 469                         break;
 470
 471                 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
 472                     (cpu_devs[i]->c_ident[1] &&
 473                      !strcmp(v, cpu_devs[i]->c_ident[1]))) {
 474                         this_cpu = cpu_devs[i];
 475                         c->x86_vendor = this_cpu->c_x86_vendor;
 476                         return;
 477                 }
 478         }
 479
 480         if (!printed) {
 481                 printed++;
 482                 printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
 483                 printk(KERN_ERR "CPU: Your system may be unstable.\n");
 484         }
 485
 486         c->x86_vendor = X86_VENDOR_UNKNOWN;
 487         this_cpu = &default_cpu;
 488 }
 489
 490 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
 491 {
 492         /* Get vendor name */
 493         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 494               (unsigned int *)&c->x86_vendor_id[0],
 495               (unsigned int *)&c->x86_vendor_id[8],
 496               (unsigned int *)&c->x86_vendor_id[4]);
 497
 498         c->x86 = 4;
 499         /* Intel-defined flags: level 0x00000001 */
 500         if (c->cpuid_level >= 0x00000001) {
 501                 u32 junk, tfms, cap0, misc;
 502                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
 503                 c->x86 = (tfms >> 8) & 0xf;
 504                 c->x86_model = (tfms >> 4) & 0xf;
 505                 c->x86_mask = tfms & 0xf;
 506                 if (c->x86 == 0xf)
 507                         c->x86 += (tfms >> 20) & 0xff;
 508                 if (c->x86 >= 0x6)
 509                         c->x86_model += ((tfms >> 16) & 0xf) << 4;
 510                 if (cap0 & (1<<19)) {
 511                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
 512                         c->x86_cache_alignment = c->x86_clflush_size;
 513                 }
 514         }
 515 }
 516
 517 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 518 {
 519         u32 tfms, xlvl;
 520         u32 ebx;
 521
 522         /* Intel-defined flags: level 0x00000001 */
 523         if (c->cpuid_level >= 0x00000001) {
 524                 u32 capability, excap;
 525                 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
 526                 c->x86_capability[0] = capability;
 527                 c->x86_capability[4] = excap;
 528         }
 529
 530         /* AMD-defined flags: level 0x80000001 */
 531         xlvl = cpuid_eax(0x80000000);
 532         c->extended_cpuid_level = xlvl;
 533         if ((xlvl & 0xffff0000) == 0x80000000) {
 534                 if (xlvl >= 0x80000001) {
 535                         c->x86_capability[1] = cpuid_edx(0x80000001);
 536                         c->x86_capability[6] = cpuid_ecx(0x80000001);
 537                 }
 538         }
 539
 540 #ifdef CONFIG_X86_64
 541         if (c->extended_cpuid_level >= 0x80000008) {
 542                 u32 eax = cpuid_eax(0x80000008);
 543
 544                 c->x86_virt_bits = (eax >> 8) & 0xff;
 545                 c->x86_phys_bits = eax & 0xff;
 546         }
 547 #endif
 548
 549         if (c->extended_cpuid_level >= 0x80000007)
 550                 c->x86_power = cpuid_edx(0x80000007);
 551
 552 }
 553
 554 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
 555 {
 556 #ifdef CONFIG_X86_32
 557         int i;
 558
 559         /*
 560          * First of all, decide if this is a 486 or higher
 561          * It's a 486 if we can modify the AC flag
 562          */
 563         if (flag_is_changeable_p(X86_EFLAGS_AC))
 564                 c->x86 = 4;
 565         else
 566                 c->x86 = 3;
 567
 568         for (i = 0; i < X86_VENDOR_NUM; i++)
 569                 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
 570                         c->x86_vendor_id[0] = 0;
 571                         cpu_devs[i]->c_identify(c);
 572                         if (c->x86_vendor_id[0]) {
 573                                 get_cpu_vendor(c);
 574                                 break;
 575                         }
 576                 }
 577 #endif
 578 }
 579
 580 /*
 581  * Do minimum CPU detection early.
 582  * Fields really needed: vendor, cpuid_level, family, model, mask,
 583  * cache alignment.
 584  * The others are not touched to avoid unwanted side effects.
 585  *
 586  * WARNING: this function is only called on the BP.  Don't add code here
 587  * that is supposed to run on all CPUs.
 588  */
 589 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 590 {
 591 #ifdef CONFIG_X86_64
 592         c->x86_clflush_size = 64;
 593 #else
 594         c->x86_clflush_size = 32;
 595 #endif
 596         c->x86_cache_alignment = c->x86_clflush_size;
 597
 598         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 599         c->extended_cpuid_level = 0;
 600
 601         if (!have_cpuid_p())
 602                 identify_cpu_without_cpuid(c);
 603
 604         /* cyrix could have cpuid enabled via c_identify()*/
 605         if (!have_cpuid_p())
 606                 return;
 607
 608         cpu_detect(c);
 609
 610         get_cpu_vendor(c);
 611
 612         get_cpu_cap(c);
 613
 614         if (this_cpu->c_early_init)
 615                 this_cpu->c_early_init(c);
 616
 617 #ifdef CONFIG_SMP
 618         c->cpu_index = boot_cpu_id;
 619 #endif
 620         filter_cpuid_features(c, false);
 621 }
 622
 623 void __init early_cpu_init(void)
 624 {
 625         struct cpu_dev **cdev;
 626         int count = 0;
 627
 628         printk("KERNEL supported cpus:\n");
 629         for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
 630                 struct cpu_dev *cpudev = *cdev;
 631                 unsigned int j;
 632
 633                 if (count >= X86_VENDOR_NUM)
 634                         break;
 635                 cpu_devs[count] = cpudev;
 636                 count++;
 637
 638                 for (j = 0; j < 2; j++) {
 639                         if (!cpudev->c_ident[j])
 640                                 continue;
 641                         printk("  %s %s\n", cpudev->c_vendor,
 642                                 cpudev->c_ident[j]);
 643                 }
 644         }
 645
 646         early_identify_cpu(&boot_cpu_data);
 647 }
 648
 649 /*
 650  * The NOPL instruction is supposed to exist on all CPUs with
 651  * family >= 6; unfortunately, that's not true in practice because
 652  * of early VIA chips and (more importantly) broken virtualizers that
 653  * are not easy to detect.  In the latter case it doesn't even *fail*
 654  * reliably, so probing for it doesn't even work.  Disable it completely
 655  * unless we can find a reliable way to detect all the broken cases.
 656  */
 657 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
 658 {
 659         clear_cpu_cap(c, X86_FEATURE_NOPL);
 660 }
 661
 662 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 663 {
 664         c->extended_cpuid_level = 0;
 665
 666         if (!have_cpuid_p())
 667                 identify_cpu_without_cpuid(c);
 668
 669         /* cyrix could have cpuid enabled via c_identify()*/
 670         if (!have_cpuid_p())
 671                 return;
 672
 673         cpu_detect(c);
 674
 675         get_cpu_vendor(c);
 676
 677         get_cpu_cap(c);
 678
 679         if (c->cpuid_level >= 0x00000001) {
 680                 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
 681 #ifdef CONFIG_X86_32
 682 # ifdef CONFIG_X86_HT
 683                 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
 684 # else
 685                 c->apicid = c->initial_apicid;
 686 # endif
 687 #endif
 688
 689 #ifdef CONFIG_X86_HT
 690                 c->phys_proc_id = c->initial_apicid;
 691 #endif
 692         }
 693
 694         get_model_name(c); /* Default name */
 695
 696         init_scattered_cpuid_features(c);
 697         detect_nopl(c);
 698 }
 699
 700 /*
 701  * This does the hard work of actually picking apart the CPU stuff...
 702  */
 703 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 704 {
 705         int i;
 706
 707         c->loops_per_jiffy = loops_per_jiffy;
 708         c->x86_cache_size = -1;
 709         c->x86_vendor = X86_VENDOR_UNKNOWN;
 710         c->x86_model = c->x86_mask = 0; /* So far unknown... */
 711         c->x86_vendor_id[0] = '\0'; /* Unset */
 712         c->x86_model_id[0] = '\0';  /* Unset */
 713         c->x86_max_cores = 1;
 714         c->x86_coreid_bits = 0;
 715 #ifdef CONFIG_X86_64
 716         c->x86_clflush_size = 64;
 717 #else
 718         c->cpuid_level = -1;    /* CPUID not detected */
 719         c->x86_clflush_size = 32;
 720 #endif
 721         c->x86_cache_alignment = c->x86_clflush_size;
 722         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 723
 724         generic_identify(c);
 725
 726         if (this_cpu->c_identify)
 727                 this_cpu->c_identify(c);
 728
 729 #ifdef CONFIG_X86_64
 730         c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
 731 #endif
 732
 733         /*
 734          * Vendor-specific initialization.  In this section we
 735          * canonicalize the feature flags, meaning if there are
 736          * features a certain CPU supports which CPUID doesn't
 737          * tell us, CPUID claiming incorrect flags, or other bugs,
 738          * we handle them here.
 739          *
 740          * At the end of this section, c->x86_capability better
 741          * indicate the features this CPU genuinely supports!
 742          */
 743         if (this_cpu->c_init)
 744                 this_cpu->c_init(c);
 745
 746         /* Disable the PN if appropriate */
 747         squash_the_stupid_serial_number(c);
 748
 749         /*
 750          * The vendor-specific functions might have changed features.  Now
 751          * we do "generic changes."
 752          */
 753
 754         /* Filter out anything that depends on CPUID levels we don't have */
 755         filter_cpuid_features(c, true);
 756
 757         /* If the model name is still unset, do table lookup. */
 758         if (!c->x86_model_id[0]) {
 759                 char *p;
 760                 p = table_lookup_model(c);
 761                 if (p)
 762                         strcpy(c->x86_model_id, p);
 763                 else
 764                         /* Last resort... */
 765                         sprintf(c->x86_model_id, "%02x/%02x",
 766                                 c->x86, c->x86_model);
 767         }
 768
 769 #ifdef CONFIG_X86_64
 770         detect_ht(c);
 771 #endif
 772
 773         init_hypervisor(c);
 774         /*
 775          * On SMP, boot_cpu_data holds the common feature set between
 776          * all CPUs; so make sure that we indicate which features are
 777          * common between the CPUs.  The first time this routine gets
 778          * executed, c == &boot_cpu_data.
 779          */
 780         if (c != &boot_cpu_data) {
 781                 /* AND the already accumulated flags with these */
 782                 for (i = 0; i < NCAPINTS; i++)
 783                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
 784         }
 785
 786         /* Clear all flags overriden by options */
 787         for (i = 0; i < NCAPINTS; i++)
 788                 c->x86_capability[i] &= ~cleared_cpu_caps[i];
 789
 790 #ifdef CONFIG_X86_MCE
 791         /* Init Machine Check Exception if available. */
 792         mcheck_init(c);
 793 #endif
 794
 795         select_idle_routine(c);
 796
 797 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 798         numa_add_cpu(smp_processor_id());
 799 #endif
 800 }
 801
 802 #ifdef CONFIG_X86_64
 803 static void vgetcpu_set_mode(void)
 804 {
 805         if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
 806                 vgetcpu_mode = VGETCPU_RDTSCP;
 807         else
 808                 vgetcpu_mode = VGETCPU_LSL;
 809 }
 810 #endif
 811
 812 void __init identify_boot_cpu(void)
 813 {
 814         identify_cpu(&boot_cpu_data);
 815         init_c1e_mask();
 816 #ifdef CONFIG_X86_32
 817         sysenter_setup();
 818         enable_sep_cpu();
 819 #else
 820         vgetcpu_set_mode();
 821 #endif
 822 }
 823
 824 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
 825 {
 826         BUG_ON(c == &boot_cpu_data);
 827         identify_cpu(c);
 828 #ifdef CONFIG_X86_32
 829         enable_sep_cpu();
 830 #endif
 831         mtrr_ap_init();
 832 }
 833
 834 struct msr_range {
 835         unsigned min;
 836         unsigned max;
 837 };
 838
 839 static struct msr_range msr_range_array[] __cpuinitdata = {
 840         { 0x00000000, 0x00000418},
 841         { 0xc0000000, 0xc000040b},
 842         { 0xc0010000, 0xc0010142},
 843         { 0xc0011000, 0xc001103b},
 844 };
 845
 846 static void __cpuinit print_cpu_msr(void)
 847 {
 848         unsigned index;
 849         u64 val;
 850         int i;
 851         unsigned index_min, index_max;
 852
 853         for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
 854                 index_min = msr_range_array[i].min;
 855                 index_max = msr_range_array[i].max;
 856                 for (index = index_min; index < index_max; index++) {
 857                         if (rdmsrl_amd_safe(index, &val))
 858                                 continue;
 859                         printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
 860                 }
 861         }
 862 }
 863
 864 static int show_msr __cpuinitdata;
 865 static __init int setup_show_msr(char *arg)
 866 {
 867         int num;
 868
 869         get_option(&arg, &num);
 870
 871         if (num > 0)
 872                 show_msr = num;
 873         return 1;
 874 }
 875 __setup("show_msr=", setup_show_msr);
 876
 877 static __init int setup_noclflush(char *arg)
 878 {
 879         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
 880         return 1;
 881 }
 882 __setup("noclflush", setup_noclflush);
 883
 884 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
 885 {
 886         char *vendor = NULL;
 887
 888         if (c->x86_vendor < X86_VENDOR_NUM)
 889                 vendor = this_cpu->c_vendor;
 890         else if (c->cpuid_level >= 0)
 891                 vendor = c->x86_vendor_id;
 892
 893         if (vendor && !strstr(c->x86_model_id, vendor))
 894                 printk(KERN_CONT "%s ", vendor);
 895
 896         if (c->x86_model_id[0])
 897                 printk(KERN_CONT "%s", c->x86_model_id);
 898         else
 899                 printk(KERN_CONT "%d86", c->x86);
 900
 901         if (c->x86_mask || c->cpuid_level >= 0)
 902                 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
 903         else
 904                 printk(KERN_CONT "\n");
 905
 906 #ifdef CONFIG_SMP
 907         if (c->cpu_index < show_msr)
 908                 print_cpu_msr();
 909 #else
 910         if (show_msr)
 911                 print_cpu_msr();
 912 #endif
 913 }
 914
 915 static __init int setup_disablecpuid(char *arg)
 916 {
 917         int bit;
 918         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
 919                 setup_clear_cpu_cap(bit);
 920         else
 921                 return 0;
 922         return 1;
 923 }
 924 __setup("clearcpuid=", setup_disablecpuid);
 925
 926 #ifdef CONFIG_X86_64
 927 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
 928
 929 DEFINE_PER_CPU_FIRST(union irq_stack_union,
 930                      irq_stack_union) __aligned(PAGE_SIZE);
 931 DEFINE_PER_CPU(char *, irq_stack_ptr) =
 932         init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
 933
 934 DEFINE_PER_CPU(unsigned long, kernel_stack) =
 935         (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
 936 EXPORT_PER_CPU_SYMBOL(kernel_stack);
 937
 938 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
 939
 940 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
 941         [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ])
 942         __aligned(PAGE_SIZE);
 943
 944 extern asmlinkage void ignore_sysret(void);
 945
 946 /* May not be marked __init: used by software suspend */
 947 void syscall_init(void)
 948 {
 949         /*
 950          * LSTAR and STAR live in a bit strange symbiosis.
 951          * They both write to the same internal register. STAR allows to
 952          * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
 953          */
 954         wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
 955         wrmsrl(MSR_LSTAR, system_call);
 956         wrmsrl(MSR_CSTAR, ignore_sysret);
 957
 958 #ifdef CONFIG_IA32_EMULATION
 959         syscall32_cpu_init();
 960 #endif
 961
 962         /* Flags to clear on syscall */
 963         wrmsrl(MSR_SYSCALL_MASK,
 964                X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
 965 }
 966
 967 unsigned long kernel_eflags;
 968
 969 /*
 970  * Copies of the original ist values from the tss are only accessed during
 971  * debugging, no special alignment required.
 972  */
 973 DEFINE_PER_CPU(struct orig_ist, orig_ist);
 974
 975 #else   /* x86_64 */
 976
 977 #ifdef CONFIG_CC_STACKPROTECTOR
 978 DEFINE_PER_CPU(unsigned long, stack_canary);
 979 #endif
 980
 981 /* Make sure %fs and %gs are initialized properly in idle threads */
 982 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
 983 {
 984         memset(regs, 0, sizeof(struct pt_regs));
 985         regs->fs = __KERNEL_PERCPU;
 986         regs->gs = __KERNEL_STACK_CANARY;
 987         return regs;
 988 }
 989 #endif  /* x86_64 */
 990
 991 /*
 992  * cpu_init() initializes state that is per-CPU. Some data is already
 993  * initialized (naturally) in the bootstrap process, such as the GDT
 994  * and IDT. We reload them nevertheless, this function acts as a
 995  * 'CPU state barrier', nothing should get across.
 996  * A lot of state is already set up in PDA init for 64 bit
 997  */
 998 #ifdef CONFIG_X86_64
 999 void __cpuinit cpu_init(void)
1000 {
1001         int cpu = stack_smp_processor_id();
1002         struct tss_struct *t = &per_cpu(init_tss, cpu);
1003         struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
1004         unsigned long v;
1005         struct task_struct *me;
1006         int i;
1007
1008 #ifdef CONFIG_NUMA
1009         if (cpu != 0 && percpu_read(node_number) == 0 &&
1010             cpu_to_node(cpu) != NUMA_NO_NODE)
1011                 percpu_write(node_number, cpu_to_node(cpu));
1012 #endif
1013
1014         me = current;
1015
1016         if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1017                 panic("CPU#%d already initialized!\n", cpu);
1018
1019         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1020
1021         clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1022
1023         /*
1024          * Initialize the per-CPU GDT with the boot GDT,
1025          * and set up the GDT descriptor:
1026          */
1027
1028         switch_to_new_gdt(cpu);
1029         loadsegment(fs, 0);
1030
1031         load_idt((const struct desc_ptr *)&idt_descr);
1032
1033         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1034         syscall_init();
1035
1036         wrmsrl(MSR_FS_BASE, 0);
1037         wrmsrl(MSR_KERNEL_GS_BASE, 0);
1038         barrier();
1039
1040         check_efer();
1041         if (cpu != 0)
1042                 enable_x2apic();
1043
1044         /*
1045          * set up and load the per-CPU TSS
1046          */
1047         if (!orig_ist->ist[0]) {
1048                 static const unsigned int sizes[N_EXCEPTION_STACKS] = {
1049                   [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1050                   [DEBUG_STACK - 1] = DEBUG_STKSZ
1051                 };
1052                 char *estacks = per_cpu(exception_stacks, cpu);
1053                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1054                         estacks += sizes[v];
1055                         orig_ist->ist[v] = t->x86_tss.ist[v] =
1056                                         (unsigned long)estacks;
1057                 }
1058         }
1059
1060         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1061         /*
1062          * <= is required because the CPU will access up to
1063          * 8 bits beyond the end of the IO permission bitmap.
1064          */
1065         for (i = 0; i <= IO_BITMAP_LONGS; i++)
1066                 t->io_bitmap[i] = ~0UL;
1067
1068         atomic_inc(&init_mm.mm_count);
1069         me->active_mm = &init_mm;
1070         if (me->mm)
1071                 BUG();
1072         enter_lazy_tlb(&init_mm, me);
1073
1074         load_sp0(t, &current->thread);
1075         set_tss_desc(cpu, t);
1076         load_TR_desc();
1077         load_LDT(&init_mm.context);
1078
1079 #ifdef CONFIG_KGDB
1080         /*
1081          * If the kgdb is connected no debug regs should be altered.  This
1082          * is only applicable when KGDB and a KGDB I/O module are built
1083          * into the kernel and you are using early debugging with
1084          * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1085          */
1086         if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1087                 arch_kgdb_ops.correct_hw_break();
1088         else
1089 #endif
1090         {
1091                 /*
1092                  * Clear all 6 debug registers:
1093                  */
1094                 set_debugreg(0UL, 0);
1095                 set_debugreg(0UL, 1);
1096                 set_debugreg(0UL, 2);
1097                 set_debugreg(0UL, 3);
1098                 set_debugreg(0UL, 6);
1099                 set_debugreg(0UL, 7);
1100         }
1101
1102         fpu_init();
1103
1104         raw_local_save_flags(kernel_eflags);
1105
1106         if (is_uv_system())
1107                 uv_cpu_init();
1108 }
1109
1110 #else
1111
1112 void __cpuinit cpu_init(void)
1113 {
1114         int cpu = smp_processor_id();
1115         struct task_struct *curr = current;
1116         struct tss_struct *t = &per_cpu(init_tss, cpu);
1117         struct thread_struct *thread = &curr->thread;
1118
1119         if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1120                 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1121                 for (;;) local_irq_enable();
1122         }
1123
1124         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1125
1126         if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1127                 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1128
1129         load_idt(&idt_descr);
1130         switch_to_new_gdt(cpu);
1131
1132         /*
1133          * Set up and load the per-CPU TSS and LDT
1134          */
1135         atomic_inc(&init_mm.mm_count);
1136         curr->active_mm = &init_mm;
1137         if (curr->mm)
1138                 BUG();
1139         enter_lazy_tlb(&init_mm, curr);
1140
1141         load_sp0(t, thread);
1142         set_tss_desc(cpu, t);
1143         load_TR_desc();
1144         load_LDT(&init_mm.context);
1145
1146 #ifdef CONFIG_DOUBLEFAULT
1147         /* Set up doublefault TSS pointer in the GDT */
1148         __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1149 #endif
1150
1151         /* Clear all 6 debug registers: */
1152         set_debugreg(0, 0);
1153         set_debugreg(0, 1);
1154         set_debugreg(0, 2);
1155         set_debugreg(0, 3);
1156         set_debugreg(0, 6);
1157         set_debugreg(0, 7);
1158
1159         /*
1160          * Force FPU initialization:
1161          */
1162         if (cpu_has_xsave)
1163                 current_thread_info()->status = TS_XSAVE;
1164         else
1165                 current_thread_info()->status = 0;
1166         clear_used_math();
1167         mxcsr_feature_mask_init();
1168
1169         /*
1170          * Boot processor to setup the FP and extended state context info.
1171          */
1172         if (smp_processor_id() == boot_cpu_id)
1173                 init_thread_xstate();
1174
1175         xsave_init();
1176 }
1177
1178
1179 #endif