1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G-2 10/100 Network Connection
31 * 82562GT 10/100 Network Connection
32 * 82562GT-2 10/100 Network Connection
33 * 82562V 10/100 Network Connection
34 * 82562V-2 10/100 Network Connection
35 * 82566DC-2 Gigabit Network Connection
36 * 82566DC Gigabit Network Connection
37 * 82566DM-2 Gigabit Network Connection
38 * 82566DM Gigabit Network Connection
39 * 82566MC Gigabit Network Connection
40 * 82566MM Gigabit Network Connection
41 * 82567LM Gigabit Network Connection
42 * 82567LF Gigabit Network Connection
43 * 82567LM-2 Gigabit Network Connection
44 * 82567LF-2 Gigabit Network Connection
45 * 82567V-2 Gigabit Network Connection
46 * 82567LF-3 Gigabit Network Connection
47 * 82567LM-3 Gigabit Network Connection
48 * 82567LM-4 Gigabit Network Connection
51 #include <linux/netdevice.h>
52 #include <linux/ethtool.h>
53 #include <linux/delay.h>
54 #include <linux/pci.h>
58 #define ICH_FLASH_GFPREG 0x0000
59 #define ICH_FLASH_HSFSTS 0x0004
60 #define ICH_FLASH_HSFCTL 0x0006
61 #define ICH_FLASH_FADDR 0x0008
62 #define ICH_FLASH_FDATA0 0x0010
63 #define ICH_FLASH_PR0 0x0074
65 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
66 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
67 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
68 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
69 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
71 #define ICH_CYCLE_READ 0
72 #define ICH_CYCLE_WRITE 2
73 #define ICH_CYCLE_ERASE 3
75 #define FLASH_GFPREG_BASE_MASK 0x1FFF
76 #define FLASH_SECTOR_ADDR_SHIFT 12
78 #define ICH_FLASH_SEG_SIZE_256 256
79 #define ICH_FLASH_SEG_SIZE_4K 4096
80 #define ICH_FLASH_SEG_SIZE_8K 8192
81 #define ICH_FLASH_SEG_SIZE_64K 65536
84 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
86 #define E1000_ICH_MNG_IAMT_MODE 0x2
88 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
89 (ID_LED_DEF1_OFF2 << 8) | \
90 (ID_LED_DEF1_ON2 << 4) | \
93 #define E1000_ICH_NVM_SIG_WORD 0x13
94 #define E1000_ICH_NVM_SIG_MASK 0xC000
96 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
98 #define E1000_FEXTNVM_SW_CONFIG 1
99 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
101 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
103 #define E1000_ICH_RAR_ENTRIES 7
105 #define PHY_PAGE_SHIFT 5
106 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
107 ((reg) & MAX_PHY_REG_ADDRESS))
108 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
109 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
111 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
112 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
113 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
115 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
116 /* Offset 04h HSFSTS */
117 union ich8_hws_flash_status
{
119 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
120 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
121 u16 dael
:1; /* bit 2 Direct Access error Log */
122 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
123 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
124 u16 reserved1
:2; /* bit 13:6 Reserved */
125 u16 reserved2
:6; /* bit 13:6 Reserved */
126 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
127 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
132 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
133 /* Offset 06h FLCTL */
134 union ich8_hws_flash_ctrl
{
135 struct ich8_hsflctl
{
136 u16 flcgo
:1; /* 0 Flash Cycle Go */
137 u16 flcycle
:2; /* 2:1 Flash Cycle */
138 u16 reserved
:5; /* 7:3 Reserved */
139 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
140 u16 flockdn
:6; /* 15:10 Reserved */
145 /* ICH Flash Region Access Permissions */
146 union ich8_hws_flash_regacc
{
148 u32 grra
:8; /* 0:7 GbE region Read Access */
149 u32 grwa
:8; /* 8:15 GbE region Write Access */
150 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
151 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
156 /* ICH Flash Protected Region */
157 union ich8_flash_protected_range
{
159 u32 base
:13; /* 0:12 Protected Range Base */
160 u32 reserved1
:2; /* 13:14 Reserved */
161 u32 rpe
:1; /* 15 Read Protection Enable */
162 u32 limit
:13; /* 16:28 Protected Range Limit */
163 u32 reserved2
:2; /* 29:30 Reserved */
164 u32 wpe
:1; /* 31 Write Protection Enable */
169 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
);
170 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
171 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
172 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
);
173 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
174 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
175 u32 offset
, u8 byte
);
176 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
178 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
180 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
182 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
);
183 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
184 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
);
186 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
188 return readw(hw
->flash_address
+ reg
);
191 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
193 return readl(hw
->flash_address
+ reg
);
196 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
198 writew(val
, hw
->flash_address
+ reg
);
201 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
203 writel(val
, hw
->flash_address
+ reg
);
206 #define er16flash(reg) __er16flash(hw, (reg))
207 #define er32flash(reg) __er32flash(hw, (reg))
208 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
209 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
212 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
213 * @hw: pointer to the HW structure
215 * Initialize family-specific PHY parameters and function pointers.
217 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
219 struct e1000_phy_info
*phy
= &hw
->phy
;
224 phy
->reset_delay_us
= 100;
227 * We may need to do this twice - once for IGP and if that fails,
228 * we'll set BM func pointers and try again
230 ret_val
= e1000e_determine_phy_address(hw
);
232 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
233 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
234 ret_val
= e1000e_determine_phy_address(hw
);
240 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
243 ret_val
= e1000e_get_phy_id(hw
);
250 case IGP03E1000_E_PHY_ID
:
251 phy
->type
= e1000_phy_igp_3
;
252 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
255 case IFE_PLUS_E_PHY_ID
:
257 phy
->type
= e1000_phy_ife
;
258 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
260 case BME1000_E_PHY_ID
:
261 phy
->type
= e1000_phy_bm
;
262 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
263 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
264 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
265 hw
->phy
.ops
.commit_phy
= e1000e_phy_sw_reset
;
268 return -E1000_ERR_PHY
;
276 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
277 * @hw: pointer to the HW structure
279 * Initialize family-specific NVM parameters and function
282 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
284 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
285 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
287 u32 sector_base_addr
;
291 /* Can't read flash registers if the register set isn't mapped. */
292 if (!hw
->flash_address
) {
293 hw_dbg(hw
, "ERROR: Flash registers not mapped\n");
294 return -E1000_ERR_CONFIG
;
297 nvm
->type
= e1000_nvm_flash_sw
;
299 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
302 * sector_X_addr is a "sector"-aligned address (4096 bytes)
303 * Add 1 to sector_end_addr since this sector is included in
306 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
307 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
309 /* flash_base_addr is byte-aligned */
310 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
313 * find total size of the NVM, then cut in half since the total
314 * size represents two separate NVM banks.
316 nvm
->flash_bank_size
= (sector_end_addr
- sector_base_addr
)
317 << FLASH_SECTOR_ADDR_SHIFT
;
318 nvm
->flash_bank_size
/= 2;
319 /* Adjust to word count */
320 nvm
->flash_bank_size
/= sizeof(u16
);
322 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
324 /* Clear shadow ram */
325 for (i
= 0; i
< nvm
->word_size
; i
++) {
326 dev_spec
->shadow_ram
[i
].modified
= 0;
327 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
334 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
335 * @hw: pointer to the HW structure
337 * Initialize family-specific MAC parameters and function
340 static s32
e1000_init_mac_params_ich8lan(struct e1000_adapter
*adapter
)
342 struct e1000_hw
*hw
= &adapter
->hw
;
343 struct e1000_mac_info
*mac
= &hw
->mac
;
345 /* Set media type function pointer */
346 hw
->phy
.media_type
= e1000_media_type_copper
;
348 /* Set mta register count */
349 mac
->mta_reg_count
= 32;
350 /* Set rar entry count */
351 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
352 if (mac
->type
== e1000_ich8lan
)
353 mac
->rar_entry_count
--;
354 /* Set if manageability features are enabled. */
355 mac
->arc_subsystem_valid
= 1;
357 /* Enable PCS Lock-loss workaround for ICH8 */
358 if (mac
->type
== e1000_ich8lan
)
359 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, 1);
364 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
366 struct e1000_hw
*hw
= &adapter
->hw
;
369 rc
= e1000_init_mac_params_ich8lan(adapter
);
373 rc
= e1000_init_nvm_params_ich8lan(hw
);
377 rc
= e1000_init_phy_params_ich8lan(hw
);
381 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
382 (adapter
->hw
.phy
.type
== e1000_phy_igp_3
))
383 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
388 static DEFINE_MUTEX(nvm_mutex
);
389 static pid_t nvm_owner
= -1;
392 * e1000_acquire_swflag_ich8lan - Acquire software control flag
393 * @hw: pointer to the HW structure
395 * Acquires the software control flag for performing NVM and PHY
396 * operations. This is a function pointer entry point only called by
397 * read/write routines for the PHY and NVM parts.
399 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
402 u32 timeout
= PHY_CFG_TIMEOUT
;
406 if (!mutex_trylock(&nvm_mutex
)) {
407 WARN(1, KERN_ERR
"e1000e mutex contention. Owned by pid %d\n",
409 mutex_lock(&nvm_mutex
);
411 nvm_owner
= current
->pid
;
414 extcnf_ctrl
= er32(EXTCNF_CTRL
);
415 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
416 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
418 extcnf_ctrl
= er32(EXTCNF_CTRL
);
419 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
426 hw_dbg(hw
, "FW or HW has locked the resource for too long.\n");
427 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
428 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
430 mutex_unlock(&nvm_mutex
);
431 return -E1000_ERR_CONFIG
;
438 * e1000_release_swflag_ich8lan - Release software control flag
439 * @hw: pointer to the HW structure
441 * Releases the software control flag for performing NVM and PHY operations.
442 * This is a function pointer entry point only called by read/write
443 * routines for the PHY and NVM parts.
445 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
449 extcnf_ctrl
= er32(EXTCNF_CTRL
);
450 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
451 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
454 mutex_unlock(&nvm_mutex
);
458 * e1000_check_mng_mode_ich8lan - Checks management mode
459 * @hw: pointer to the HW structure
461 * This checks if the adapter has manageability enabled.
462 * This is a function pointer entry point only called by read/write
463 * routines for the PHY and NVM parts.
465 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
467 u32 fwsm
= er32(FWSM
);
469 return (fwsm
& E1000_FWSM_MODE_MASK
) ==
470 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
);
474 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
475 * @hw: pointer to the HW structure
477 * Checks if firmware is blocking the reset of the PHY.
478 * This is a function pointer entry point only called by
481 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
487 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
491 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
492 * @hw: pointer to the HW structure
494 * Forces the speed and duplex settings of the PHY.
495 * This is a function pointer entry point only called by
496 * PHY setup routines.
498 static s32
e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw
*hw
)
500 struct e1000_phy_info
*phy
= &hw
->phy
;
505 if (phy
->type
!= e1000_phy_ife
) {
506 ret_val
= e1000e_phy_force_speed_duplex_igp(hw
);
510 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &data
);
514 e1000e_phy_force_speed_duplex_setup(hw
, &data
);
516 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, data
);
520 /* Disable MDI-X support for 10/100 */
521 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
525 data
&= ~IFE_PMC_AUTO_MDIX
;
526 data
&= ~IFE_PMC_FORCE_MDIX
;
528 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, data
);
532 hw_dbg(hw
, "IFE PMC: %X\n", data
);
536 if (phy
->autoneg_wait_to_complete
) {
537 hw_dbg(hw
, "Waiting for forced speed/duplex link on IFE phy.\n");
539 ret_val
= e1000e_phy_has_link_generic(hw
,
547 hw_dbg(hw
, "Link taking longer than expected.\n");
550 ret_val
= e1000e_phy_has_link_generic(hw
,
562 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
563 * @hw: pointer to the HW structure
566 * This is a function pointer entry point called by drivers
567 * or other shared routines.
569 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
571 struct e1000_phy_info
*phy
= &hw
->phy
;
573 u32 data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
575 u16 loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
576 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
578 ret_val
= e1000e_phy_hw_reset_generic(hw
);
583 * Initialize the PHY from the NVM on ICH platforms. This
584 * is needed due to an issue where the NVM configuration is
585 * not properly autoloaded after power transitions.
586 * Therefore, after each PHY reset, we will load the
587 * configuration data out of the NVM manually.
589 if (hw
->mac
.type
== e1000_ich8lan
&& phy
->type
== e1000_phy_igp_3
) {
590 struct e1000_adapter
*adapter
= hw
->adapter
;
592 /* Check if SW needs configure the PHY */
593 if ((adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M_AMT
) ||
594 (adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M
))
595 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
597 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
599 data
= er32(FEXTNVM
);
600 if (!(data
& sw_cfg_mask
))
603 /* Wait for basic configuration completes before proceeding*/
606 data
&= E1000_STATUS_LAN_INIT_DONE
;
608 } while ((!data
) && --loop
);
611 * If basic configuration is incomplete before the above loop
612 * count reaches 0, loading the configuration from NVM will
613 * leave the PHY in a bad state possibly resulting in no link.
616 hw_dbg(hw
, "LAN_INIT_DONE not set, increase timeout\n");
619 /* Clear the Init Done bit for the next init event */
621 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
625 * Make sure HW does not configure LCD from PHY
626 * extended configuration before SW configuration
628 data
= er32(EXTCNF_CTRL
);
629 if (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
)
632 cnf_size
= er32(EXTCNF_SIZE
);
633 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
634 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
638 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
639 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
641 /* Configure LCD from extended configuration region. */
643 /* cnf_base_addr is in DWORD */
644 word_addr
= (u16
)(cnf_base_addr
<< 1);
646 for (i
= 0; i
< cnf_size
; i
++) {
647 ret_val
= e1000_read_nvm(hw
,
654 ret_val
= e1000_read_nvm(hw
,
655 (word_addr
+ i
* 2 + 1),
661 /* Save off the PHY page for future writes. */
662 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
667 reg_addr
|= phy_page
;
669 ret_val
= e1e_wphy(hw
, (u32
)reg_addr
, reg_data
);
679 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
680 * @hw: pointer to the HW structure
682 * Populates "phy" structure with various feature states.
683 * This function is only called by other family-specific
686 static s32
e1000_get_phy_info_ife_ich8lan(struct e1000_hw
*hw
)
688 struct e1000_phy_info
*phy
= &hw
->phy
;
693 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
698 hw_dbg(hw
, "Phy info is only valid if link is up\n");
699 return -E1000_ERR_CONFIG
;
702 ret_val
= e1e_rphy(hw
, IFE_PHY_SPECIAL_CONTROL
, &data
);
705 phy
->polarity_correction
= (!(data
& IFE_PSC_AUTO_POLARITY_DISABLE
));
707 if (phy
->polarity_correction
) {
708 ret_val
= e1000_check_polarity_ife_ich8lan(hw
);
712 /* Polarity is forced */
713 phy
->cable_polarity
= (data
& IFE_PSC_FORCE_POLARITY
)
714 ? e1000_rev_polarity_reversed
715 : e1000_rev_polarity_normal
;
718 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
722 phy
->is_mdix
= (data
& IFE_PMC_MDIX_STATUS
);
724 /* The following parameters are undefined for 10/100 operation. */
725 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
726 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
727 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
733 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
734 * @hw: pointer to the HW structure
736 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
737 * This is a function pointer entry point called by drivers
738 * or other shared routines.
740 static s32
e1000_get_phy_info_ich8lan(struct e1000_hw
*hw
)
742 switch (hw
->phy
.type
) {
744 return e1000_get_phy_info_ife_ich8lan(hw
);
746 case e1000_phy_igp_3
:
748 return e1000e_get_phy_info_igp(hw
);
754 return -E1000_ERR_PHY_TYPE
;
758 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
759 * @hw: pointer to the HW structure
761 * Polarity is determined on the polarity reversal feature being enabled.
762 * This function is only called by other family-specific
765 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
)
767 struct e1000_phy_info
*phy
= &hw
->phy
;
769 u16 phy_data
, offset
, mask
;
772 * Polarity is determined based on the reversal feature being enabled.
774 if (phy
->polarity_correction
) {
775 offset
= IFE_PHY_EXTENDED_STATUS_CONTROL
;
776 mask
= IFE_PESC_POLARITY_REVERSED
;
778 offset
= IFE_PHY_SPECIAL_CONTROL
;
779 mask
= IFE_PSC_FORCE_POLARITY
;
782 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
785 phy
->cable_polarity
= (phy_data
& mask
)
786 ? e1000_rev_polarity_reversed
787 : e1000_rev_polarity_normal
;
793 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
794 * @hw: pointer to the HW structure
795 * @active: TRUE to enable LPLU, FALSE to disable
797 * Sets the LPLU D0 state according to the active flag. When
798 * activating LPLU this function also disables smart speed
799 * and vice versa. LPLU will not be activated unless the
800 * device autonegotiation advertisement meets standards of
801 * either 10 or 10/100 or 10/100/1000 at all duplexes.
802 * This is a function pointer entry point only called by
803 * PHY setup routines.
805 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
807 struct e1000_phy_info
*phy
= &hw
->phy
;
812 if (phy
->type
== e1000_phy_ife
)
815 phy_ctrl
= er32(PHY_CTRL
);
818 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
819 ew32(PHY_CTRL
, phy_ctrl
);
822 * Call gig speed drop workaround on LPLU before accessing
825 if ((hw
->mac
.type
== e1000_ich8lan
) &&
826 (hw
->phy
.type
== e1000_phy_igp_3
))
827 e1000e_gig_downshift_workaround_ich8lan(hw
);
829 /* When LPLU is enabled, we should disable SmartSpeed */
830 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
831 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
832 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
836 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
837 ew32(PHY_CTRL
, phy_ctrl
);
840 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
841 * during Dx states where the power conservation is most
842 * important. During driver activity we should enable
843 * SmartSpeed, so performance is maintained.
845 if (phy
->smart_speed
== e1000_smart_speed_on
) {
846 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
851 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
852 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
856 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
857 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
862 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
863 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
874 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
875 * @hw: pointer to the HW structure
876 * @active: TRUE to enable LPLU, FALSE to disable
878 * Sets the LPLU D3 state according to the active flag. When
879 * activating LPLU this function also disables smart speed
880 * and vice versa. LPLU will not be activated unless the
881 * device autonegotiation advertisement meets standards of
882 * either 10 or 10/100 or 10/100/1000 at all duplexes.
883 * This is a function pointer entry point only called by
884 * PHY setup routines.
886 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
888 struct e1000_phy_info
*phy
= &hw
->phy
;
893 phy_ctrl
= er32(PHY_CTRL
);
896 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
897 ew32(PHY_CTRL
, phy_ctrl
);
899 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
900 * during Dx states where the power conservation is most
901 * important. During driver activity we should enable
902 * SmartSpeed, so performance is maintained.
904 if (phy
->smart_speed
== e1000_smart_speed_on
) {
905 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
910 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
911 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
915 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
916 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
921 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
922 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
927 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
928 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
929 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
930 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
931 ew32(PHY_CTRL
, phy_ctrl
);
934 * Call gig speed drop workaround on LPLU before accessing
937 if ((hw
->mac
.type
== e1000_ich8lan
) &&
938 (hw
->phy
.type
== e1000_phy_igp_3
))
939 e1000e_gig_downshift_workaround_ich8lan(hw
);
941 /* When LPLU is enabled, we should disable SmartSpeed */
942 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
946 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
947 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
954 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
955 * @hw: pointer to the HW structure
956 * @bank: pointer to the variable that returns the active bank
958 * Reads signature byte from the NVM using the flash access registers.
960 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
962 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
963 /* flash bank size is in words */
964 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
965 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
966 u8 bank_high_byte
= 0;
968 if (hw
->mac
.type
!= e1000_ich10lan
) {
969 if (er32(EECD
) & E1000_EECD_SEC1VAL
)
975 * Make sure the signature for bank 0 is valid,
976 * if not check for bank1
978 e1000_read_flash_byte_ich8lan(hw
, act_offset
, &bank_high_byte
);
979 if ((bank_high_byte
& 0xC0) == 0x80) {
983 * find if segment 1 is valid by verifying
984 * bit 15:14 = 10b in word 0x13
986 e1000_read_flash_byte_ich8lan(hw
,
987 act_offset
+ bank1_offset
,
990 /* bank1 has a valid signature equivalent to SEC1V */
991 if ((bank_high_byte
& 0xC0) == 0x80) {
994 hw_dbg(hw
, "ERROR: EEPROM not present\n");
995 return -E1000_ERR_NVM
;
1004 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1005 * @hw: pointer to the HW structure
1006 * @offset: The offset (in bytes) of the word(s) to read.
1007 * @words: Size of data to read in words
1008 * @data: Pointer to the word(s) to read at offset.
1010 * Reads a word(s) from the NVM using the flash access registers.
1012 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1015 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1016 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1022 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1024 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1025 return -E1000_ERR_NVM
;
1028 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1032 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1036 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
1037 act_offset
+= offset
;
1039 for (i
= 0; i
< words
; i
++) {
1040 if ((dev_spec
->shadow_ram
) &&
1041 (dev_spec
->shadow_ram
[offset
+i
].modified
)) {
1042 data
[i
] = dev_spec
->shadow_ram
[offset
+i
].value
;
1044 ret_val
= e1000_read_flash_word_ich8lan(hw
,
1053 e1000_release_swflag_ich8lan(hw
);
1059 * e1000_flash_cycle_init_ich8lan - Initialize flash
1060 * @hw: pointer to the HW structure
1062 * This function does initial flash setup so that a new read/write/erase cycle
1065 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
1067 union ich8_hws_flash_status hsfsts
;
1068 s32 ret_val
= -E1000_ERR_NVM
;
1071 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1073 /* Check if the flash descriptor is valid */
1074 if (hsfsts
.hsf_status
.fldesvalid
== 0) {
1075 hw_dbg(hw
, "Flash descriptor invalid. "
1076 "SW Sequencing must be used.");
1077 return -E1000_ERR_NVM
;
1080 /* Clear FCERR and DAEL in hw status by writing 1 */
1081 hsfsts
.hsf_status
.flcerr
= 1;
1082 hsfsts
.hsf_status
.dael
= 1;
1084 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1087 * Either we should have a hardware SPI cycle in progress
1088 * bit to check against, in order to start a new cycle or
1089 * FDONE bit should be changed in the hardware so that it
1090 * is 1 after hardware reset, which can then be used as an
1091 * indication whether a cycle is in progress or has been
1095 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1097 * There is no cycle running at present,
1098 * so we can start a cycle
1099 * Begin by setting Flash Cycle Done.
1101 hsfsts
.hsf_status
.flcdone
= 1;
1102 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1106 * otherwise poll for sometime so the current
1107 * cycle has a chance to end before giving up.
1109 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
1110 hsfsts
.regval
= __er16flash(hw
, ICH_FLASH_HSFSTS
);
1111 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1119 * Successful in waiting for previous cycle to timeout,
1120 * now set the Flash Cycle Done.
1122 hsfsts
.hsf_status
.flcdone
= 1;
1123 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1125 hw_dbg(hw
, "Flash controller busy, cannot get access");
1133 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1134 * @hw: pointer to the HW structure
1135 * @timeout: maximum time to wait for completion
1137 * This function starts a flash cycle and waits for its completion.
1139 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
1141 union ich8_hws_flash_ctrl hsflctl
;
1142 union ich8_hws_flash_status hsfsts
;
1143 s32 ret_val
= -E1000_ERR_NVM
;
1146 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1147 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1148 hsflctl
.hsf_ctrl
.flcgo
= 1;
1149 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1151 /* wait till FDONE bit is set to 1 */
1153 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1154 if (hsfsts
.hsf_status
.flcdone
== 1)
1157 } while (i
++ < timeout
);
1159 if (hsfsts
.hsf_status
.flcdone
== 1 && hsfsts
.hsf_status
.flcerr
== 0)
1166 * e1000_read_flash_word_ich8lan - Read word from flash
1167 * @hw: pointer to the HW structure
1168 * @offset: offset to data location
1169 * @data: pointer to the location for storing the data
1171 * Reads the flash word at offset into data. Offset is converted
1172 * to bytes before read.
1174 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1177 /* Must convert offset into bytes. */
1180 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
1184 * e1000_read_flash_byte_ich8lan - Read byte from flash
1185 * @hw: pointer to the HW structure
1186 * @offset: The offset of the byte to read.
1187 * @data: Pointer to a byte to store the value read.
1189 * Reads a single byte from the NVM using the flash access registers.
1191 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1197 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
1207 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1208 * @hw: pointer to the HW structure
1209 * @offset: The offset (in bytes) of the byte or word to read.
1210 * @size: Size of data to read, 1=byte 2=word
1211 * @data: Pointer to the word to store the value read.
1213 * Reads a byte or word from the NVM using the flash access registers.
1215 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1218 union ich8_hws_flash_status hsfsts
;
1219 union ich8_hws_flash_ctrl hsflctl
;
1220 u32 flash_linear_addr
;
1222 s32 ret_val
= -E1000_ERR_NVM
;
1225 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1226 return -E1000_ERR_NVM
;
1228 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1229 hw
->nvm
.flash_base_addr
;
1234 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1238 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1239 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1240 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
1241 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
1242 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1244 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1246 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1247 ICH_FLASH_READ_COMMAND_TIMEOUT
);
1250 * Check if FCERR is set to 1, if set to 1, clear it
1251 * and try the whole sequence a few more times, else
1252 * read in (shift in) the Flash Data0, the order is
1253 * least significant byte first msb to lsb
1256 flash_data
= er32flash(ICH_FLASH_FDATA0
);
1258 *data
= (u8
)(flash_data
& 0x000000FF);
1259 } else if (size
== 2) {
1260 *data
= (u16
)(flash_data
& 0x0000FFFF);
1265 * If we've gotten here, then things are probably
1266 * completely hosed, but if the error condition is
1267 * detected, it won't hurt to give it another try...
1268 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1270 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1271 if (hsfsts
.hsf_status
.flcerr
== 1) {
1272 /* Repeat for some time before giving up. */
1274 } else if (hsfsts
.hsf_status
.flcdone
== 0) {
1275 hw_dbg(hw
, "Timeout error - flash cycle "
1276 "did not complete.");
1280 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1286 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1287 * @hw: pointer to the HW structure
1288 * @offset: The offset (in bytes) of the word(s) to write.
1289 * @words: Size of data to write in words
1290 * @data: Pointer to the word(s) to write at offset.
1292 * Writes a byte or word to the NVM using the flash access registers.
1294 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1297 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1298 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1302 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1304 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1305 return -E1000_ERR_NVM
;
1308 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1312 for (i
= 0; i
< words
; i
++) {
1313 dev_spec
->shadow_ram
[offset
+i
].modified
= 1;
1314 dev_spec
->shadow_ram
[offset
+i
].value
= data
[i
];
1317 e1000_release_swflag_ich8lan(hw
);
1323 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1324 * @hw: pointer to the HW structure
1326 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1327 * which writes the checksum to the shadow ram. The changes in the shadow
1328 * ram are then committed to the EEPROM by processing each bank at a time
1329 * checking for the modified bit and writing only the pending changes.
1330 * After a successful commit, the shadow ram is cleared and is ready for
1333 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1335 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1336 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1337 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
1341 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
1345 if (nvm
->type
!= e1000_nvm_flash_sw
)
1348 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1353 * We're writing to the opposite bank so if we're on bank 1,
1354 * write to bank 0 etc. We also need to erase the segment that
1355 * is going to be written
1357 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1362 new_bank_offset
= nvm
->flash_bank_size
;
1363 old_bank_offset
= 0;
1364 e1000_erase_flash_bank_ich8lan(hw
, 1);
1366 old_bank_offset
= nvm
->flash_bank_size
;
1367 new_bank_offset
= 0;
1368 e1000_erase_flash_bank_ich8lan(hw
, 0);
1371 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1373 * Determine whether to write the value stored
1374 * in the other NVM bank or a modified value stored
1377 if (dev_spec
->shadow_ram
[i
].modified
) {
1378 data
= dev_spec
->shadow_ram
[i
].value
;
1380 e1000_read_flash_word_ich8lan(hw
,
1381 i
+ old_bank_offset
,
1386 * If the word is 0x13, then make sure the signature bits
1387 * (15:14) are 11b until the commit has completed.
1388 * This will allow us to write 10b which indicates the
1389 * signature is valid. We want to do this after the write
1390 * has completed so that we don't mark the segment valid
1391 * while the write is still in progress
1393 if (i
== E1000_ICH_NVM_SIG_WORD
)
1394 data
|= E1000_ICH_NVM_SIG_MASK
;
1396 /* Convert offset to bytes. */
1397 act_offset
= (i
+ new_bank_offset
) << 1;
1400 /* Write the bytes to the new bank. */
1401 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1408 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1416 * Don't bother writing the segment valid bits if sector
1417 * programming failed.
1420 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1421 hw_dbg(hw
, "Flash commit failed.\n");
1422 e1000_release_swflag_ich8lan(hw
);
1427 * Finally validate the new segment by setting bit 15:14
1428 * to 10b in word 0x13 , this can be done without an
1429 * erase as well since these bits are 11 to start with
1430 * and we need to change bit 14 to 0b
1432 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
1433 e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
1435 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1439 e1000_release_swflag_ich8lan(hw
);
1444 * And invalidate the previously valid segment by setting
1445 * its signature word (0x13) high_byte to 0b. This can be
1446 * done without an erase because flash erase sets all bits
1447 * to 1's. We can write 1's to 0's without an erase
1449 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
1450 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
1452 e1000_release_swflag_ich8lan(hw
);
1456 /* Great! Everything worked, we can now clear the cached entries. */
1457 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1458 dev_spec
->shadow_ram
[i
].modified
= 0;
1459 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
1462 e1000_release_swflag_ich8lan(hw
);
1465 * Reload the EEPROM, or else modifications will not appear
1466 * until after the next adapter reset.
1468 e1000e_reload_nvm(hw
);
1475 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1476 * @hw: pointer to the HW structure
1478 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1479 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1480 * calculated, in which case we need to calculate the checksum and set bit 6.
1482 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1488 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1489 * needs to be fixed. This bit is an indication that the NVM
1490 * was prepared by OEM software and did not calculate the
1491 * checksum...a likely scenario.
1493 ret_val
= e1000_read_nvm(hw
, 0x19, 1, &data
);
1497 if ((data
& 0x40) == 0) {
1499 ret_val
= e1000_write_nvm(hw
, 0x19, 1, &data
);
1502 ret_val
= e1000e_update_nvm_checksum(hw
);
1507 return e1000e_validate_nvm_checksum_generic(hw
);
1511 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1512 * @hw: pointer to the HW structure
1514 * To prevent malicious write/erase of the NVM, set it to be read-only
1515 * so that the hardware ignores all write/erase cycles of the NVM via
1516 * the flash control registers. The shadow-ram copy of the NVM will
1517 * still be updated, however any updates to this copy will not stick
1518 * across driver reloads.
1520 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
1522 union ich8_flash_protected_range pr0
;
1523 union ich8_hws_flash_status hsfsts
;
1527 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1531 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
1533 /* Write-protect GbE Sector of NVM */
1534 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
1535 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
1536 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
1537 pr0
.range
.wpe
= true;
1538 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
1541 * Lock down a subset of GbE Flash Control Registers, e.g.
1542 * PR0 to prevent the write-protection from being lifted.
1543 * Once FLOCKDN is set, the registers protected by it cannot
1544 * be written until FLOCKDN is cleared by a hardware reset.
1546 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1547 hsfsts
.hsf_status
.flockdn
= true;
1548 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1550 e1000_release_swflag_ich8lan(hw
);
1554 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1555 * @hw: pointer to the HW structure
1556 * @offset: The offset (in bytes) of the byte/word to read.
1557 * @size: Size of data to read, 1=byte 2=word
1558 * @data: The byte(s) to write to the NVM.
1560 * Writes one/two bytes to the NVM using the flash access registers.
1562 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1565 union ich8_hws_flash_status hsfsts
;
1566 union ich8_hws_flash_ctrl hsflctl
;
1567 u32 flash_linear_addr
;
1572 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
1573 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1574 return -E1000_ERR_NVM
;
1576 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1577 hw
->nvm
.flash_base_addr
;
1582 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1586 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1587 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1588 hsflctl
.hsf_ctrl
.fldbcount
= size
-1;
1589 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
1590 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1592 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1595 flash_data
= (u32
)data
& 0x00FF;
1597 flash_data
= (u32
)data
;
1599 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
1602 * check if FCERR is set to 1 , if set to 1, clear it
1603 * and try the whole sequence a few more times else done
1605 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1606 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
1611 * If we're here, then things are most likely
1612 * completely hosed, but if the error condition
1613 * is detected, it won't hurt to give it another
1614 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1616 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1617 if (hsfsts
.hsf_status
.flcerr
== 1)
1618 /* Repeat for some time before giving up. */
1620 if (hsfsts
.hsf_status
.flcdone
== 0) {
1621 hw_dbg(hw
, "Timeout error - flash cycle "
1622 "did not complete.");
1625 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1631 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1632 * @hw: pointer to the HW structure
1633 * @offset: The index of the byte to read.
1634 * @data: The byte to write to the NVM.
1636 * Writes a single byte to the NVM using the flash access registers.
1638 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1641 u16 word
= (u16
)data
;
1643 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
1647 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1648 * @hw: pointer to the HW structure
1649 * @offset: The offset of the byte to write.
1650 * @byte: The byte to write to the NVM.
1652 * Writes a single byte to the NVM using the flash access registers.
1653 * Goes through a retry algorithm before giving up.
1655 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
1656 u32 offset
, u8 byte
)
1659 u16 program_retries
;
1661 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1665 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
1666 hw_dbg(hw
, "Retrying Byte %2.2X at offset %u\n", byte
, offset
);
1668 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1672 if (program_retries
== 100)
1673 return -E1000_ERR_NVM
;
1679 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1680 * @hw: pointer to the HW structure
1681 * @bank: 0 for first bank, 1 for second bank, etc.
1683 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1684 * bank N is 4096 * N + flash_reg_addr.
1686 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
1688 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1689 union ich8_hws_flash_status hsfsts
;
1690 union ich8_hws_flash_ctrl hsflctl
;
1691 u32 flash_linear_addr
;
1692 /* bank size is in 16bit words - adjust to bytes */
1693 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
1700 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1703 * Determine HW Sector size: Read BERASE bits of hw flash status
1705 * 00: The Hw sector is 256 bytes, hence we need to erase 16
1706 * consecutive sectors. The start index for the nth Hw sector
1707 * can be calculated as = bank * 4096 + n * 256
1708 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1709 * The start index for the nth Hw sector can be calculated
1711 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1712 * (ich9 only, otherwise error condition)
1713 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1715 switch (hsfsts
.hsf_status
.berasesz
) {
1717 /* Hw sector size 256 */
1718 sector_size
= ICH_FLASH_SEG_SIZE_256
;
1719 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
1722 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
1723 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_4K
;
1726 if (hw
->mac
.type
== e1000_ich9lan
) {
1727 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
1728 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_8K
;
1730 return -E1000_ERR_NVM
;
1734 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
1735 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_64K
;
1738 return -E1000_ERR_NVM
;
1741 /* Start with the base address, then add the sector offset. */
1742 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
1743 flash_linear_addr
+= (bank
) ? (sector_size
* iteration
) : 0;
1745 for (j
= 0; j
< iteration
; j
++) {
1748 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1753 * Write a value 11 (block Erase) in Flash
1754 * Cycle field in hw flash control
1756 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1757 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
1758 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1761 * Write the last 24 bits of an index within the
1762 * block into Flash Linear address field in Flash
1765 flash_linear_addr
+= (j
* sector_size
);
1766 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1768 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1769 ICH_FLASH_ERASE_COMMAND_TIMEOUT
);
1774 * Check if FCERR is set to 1. If 1,
1775 * clear it and try the whole sequence
1776 * a few more times else Done
1778 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1779 if (hsfsts
.hsf_status
.flcerr
== 1)
1780 /* repeat for some time before giving up */
1782 else if (hsfsts
.hsf_status
.flcdone
== 0)
1784 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
1791 * e1000_valid_led_default_ich8lan - Set the default LED settings
1792 * @hw: pointer to the HW structure
1793 * @data: Pointer to the LED settings
1795 * Reads the LED default settings from the NVM to data. If the NVM LED
1796 * settings is all 0's or F's, set the LED default to a valid LED default
1799 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
1803 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1805 hw_dbg(hw
, "NVM Read Error\n");
1809 if (*data
== ID_LED_RESERVED_0000
||
1810 *data
== ID_LED_RESERVED_FFFF
)
1811 *data
= ID_LED_DEFAULT_ICH8LAN
;
1817 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1818 * @hw: pointer to the HW structure
1820 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1821 * register, so the the bus width is hard coded.
1823 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
1825 struct e1000_bus_info
*bus
= &hw
->bus
;
1828 ret_val
= e1000e_get_bus_info_pcie(hw
);
1831 * ICH devices are "PCI Express"-ish. They have
1832 * a configuration space, but do not contain
1833 * PCI Express Capability registers, so bus width
1834 * must be hardcoded.
1836 if (bus
->width
== e1000_bus_width_unknown
)
1837 bus
->width
= e1000_bus_width_pcie_x1
;
1843 * e1000_reset_hw_ich8lan - Reset the hardware
1844 * @hw: pointer to the HW structure
1846 * Does a full reset of the hardware which includes a reset of the PHY and
1849 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
1855 * Prevent the PCI-E bus from sticking if there is no TLP connection
1856 * on the last TLP read/write transaction when MAC is reset.
1858 ret_val
= e1000e_disable_pcie_master(hw
);
1860 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
1863 hw_dbg(hw
, "Masking off all interrupts\n");
1864 ew32(IMC
, 0xffffffff);
1867 * Disable the Transmit and Receive units. Then delay to allow
1868 * any pending transactions to complete before we hit the MAC
1869 * with the global reset.
1872 ew32(TCTL
, E1000_TCTL_PSP
);
1877 /* Workaround for ICH8 bit corruption issue in FIFO memory */
1878 if (hw
->mac
.type
== e1000_ich8lan
) {
1879 /* Set Tx and Rx buffer allocation to 8k apiece. */
1880 ew32(PBA
, E1000_PBA_8K
);
1881 /* Set Packet Buffer Size to 16k. */
1882 ew32(PBS
, E1000_PBS_16K
);
1887 if (!e1000_check_reset_block(hw
)) {
1889 * PHY HW reset requires MAC CORE reset at the same
1890 * time to make sure the interface between MAC and the
1891 * external PHY is reset.
1893 ctrl
|= E1000_CTRL_PHY_RST
;
1895 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1896 /* Whether or not the swflag was acquired, we need to reset the part */
1897 hw_dbg(hw
, "Issuing a global reset to ich8lan");
1898 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
1902 /* release the swflag because it is not reset by
1905 e1000_release_swflag_ich8lan(hw
);
1908 ret_val
= e1000e_get_auto_rd_done(hw
);
1911 * When auto config read does not complete, do not
1912 * return with an error. This can happen in situations
1913 * where there is no eeprom and prevents getting link.
1915 hw_dbg(hw
, "Auto Read Done did not complete\n");
1918 ew32(IMC
, 0xffffffff);
1921 kab
= er32(KABGTXD
);
1922 kab
|= E1000_KABGTXD_BGSQLBIAS
;
1929 * e1000_init_hw_ich8lan - Initialize the hardware
1930 * @hw: pointer to the HW structure
1932 * Prepares the hardware for transmit and receive by doing the following:
1933 * - initialize hardware bits
1934 * - initialize LED identification
1935 * - setup receive address registers
1936 * - setup flow control
1937 * - setup transmit descriptors
1938 * - clear statistics
1940 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
1942 struct e1000_mac_info
*mac
= &hw
->mac
;
1943 u32 ctrl_ext
, txdctl
, snoop
;
1947 e1000_initialize_hw_bits_ich8lan(hw
);
1949 /* Initialize identification LED */
1950 ret_val
= e1000e_id_led_init(hw
);
1952 hw_dbg(hw
, "Error initializing identification LED\n");
1956 /* Setup the receive address. */
1957 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
1959 /* Zero out the Multicast HASH table */
1960 hw_dbg(hw
, "Zeroing the MTA\n");
1961 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
1962 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
1964 /* Setup link and flow control */
1965 ret_val
= e1000_setup_link_ich8lan(hw
);
1967 /* Set the transmit descriptor write-back policy for both queues */
1968 txdctl
= er32(TXDCTL(0));
1969 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
1970 E1000_TXDCTL_FULL_TX_DESC_WB
;
1971 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
1972 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
1973 ew32(TXDCTL(0), txdctl
);
1974 txdctl
= er32(TXDCTL(1));
1975 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
1976 E1000_TXDCTL_FULL_TX_DESC_WB
;
1977 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
1978 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
1979 ew32(TXDCTL(1), txdctl
);
1982 * ICH8 has opposite polarity of no_snoop bits.
1983 * By default, we should use snoop behavior.
1985 if (mac
->type
== e1000_ich8lan
)
1986 snoop
= PCIE_ICH8_SNOOP_ALL
;
1988 snoop
= (u32
) ~(PCIE_NO_SNOOP_ALL
);
1989 e1000e_set_pcie_no_snoop(hw
, snoop
);
1991 ctrl_ext
= er32(CTRL_EXT
);
1992 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
1993 ew32(CTRL_EXT
, ctrl_ext
);
1996 * Clear all of the statistics registers (clear on read). It is
1997 * important that we do this after we have tried to establish link
1998 * because the symbol error count will increment wildly if there
2001 e1000_clear_hw_cntrs_ich8lan(hw
);
2006 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2007 * @hw: pointer to the HW structure
2009 * Sets/Clears required hardware bits necessary for correctly setting up the
2010 * hardware for transmit and receive.
2012 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
2016 /* Extended Device Control */
2017 reg
= er32(CTRL_EXT
);
2019 ew32(CTRL_EXT
, reg
);
2021 /* Transmit Descriptor Control 0 */
2022 reg
= er32(TXDCTL(0));
2024 ew32(TXDCTL(0), reg
);
2026 /* Transmit Descriptor Control 1 */
2027 reg
= er32(TXDCTL(1));
2029 ew32(TXDCTL(1), reg
);
2031 /* Transmit Arbitration Control 0 */
2032 reg
= er32(TARC(0));
2033 if (hw
->mac
.type
== e1000_ich8lan
)
2034 reg
|= (1 << 28) | (1 << 29);
2035 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2038 /* Transmit Arbitration Control 1 */
2039 reg
= er32(TARC(1));
2040 if (er32(TCTL
) & E1000_TCTL_MULR
)
2044 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
2048 if (hw
->mac
.type
== e1000_ich8lan
) {
2056 * e1000_setup_link_ich8lan - Setup flow control and link settings
2057 * @hw: pointer to the HW structure
2059 * Determines which flow control settings to use, then configures flow
2060 * control. Calls the appropriate media-specific link configuration
2061 * function. Assuming the adapter has a valid link partner, a valid link
2062 * should be established. Assumes the hardware has previously been reset
2063 * and the transmitter and receiver are not enabled.
2065 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
2069 if (e1000_check_reset_block(hw
))
2073 * ICH parts do not have a word in the NVM to determine
2074 * the default flow control setting, so we explicitly
2077 if (hw
->fc
.type
== e1000_fc_default
)
2078 hw
->fc
.type
= e1000_fc_full
;
2080 hw
->fc
.original_type
= hw
->fc
.type
;
2082 hw_dbg(hw
, "After fix-ups FlowControl is now = %x\n", hw
->fc
.type
);
2084 /* Continue to configure the copper link. */
2085 ret_val
= e1000_setup_copper_link_ich8lan(hw
);
2089 ew32(FCTTV
, hw
->fc
.pause_time
);
2091 return e1000e_set_fc_watermarks(hw
);
2095 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2096 * @hw: pointer to the HW structure
2098 * Configures the kumeran interface to the PHY to wait the appropriate time
2099 * when polling the PHY, then call the generic setup_copper_link to finish
2100 * configuring the copper link.
2102 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
2109 ctrl
|= E1000_CTRL_SLU
;
2110 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
2114 * Set the mac to wait the maximum time between each iteration
2115 * and increase the max iterations when polling the phy;
2116 * this fixes erroneous timeouts at 10Mbps.
2118 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 4), 0xFFFF);
2121 ret_val
= e1000e_read_kmrn_reg(hw
, GG82563_REG(0x34, 9), ®_data
);
2125 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 9), reg_data
);
2129 if (hw
->phy
.type
== e1000_phy_igp_3
) {
2130 ret_val
= e1000e_copper_link_setup_igp(hw
);
2133 } else if (hw
->phy
.type
== e1000_phy_bm
) {
2134 ret_val
= e1000e_copper_link_setup_m88(hw
);
2139 if (hw
->phy
.type
== e1000_phy_ife
) {
2140 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, ®_data
);
2144 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
2146 switch (hw
->phy
.mdix
) {
2148 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
2151 reg_data
|= IFE_PMC_FORCE_MDIX
;
2155 reg_data
|= IFE_PMC_AUTO_MDIX
;
2158 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, reg_data
);
2162 return e1000e_setup_copper_link(hw
);
2166 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2167 * @hw: pointer to the HW structure
2168 * @speed: pointer to store current link speed
2169 * @duplex: pointer to store the current link duplex
2171 * Calls the generic get_speed_and_duplex to retrieve the current link
2172 * information and then calls the Kumeran lock loss workaround for links at
2175 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
2180 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
2184 if ((hw
->mac
.type
== e1000_ich8lan
) &&
2185 (hw
->phy
.type
== e1000_phy_igp_3
) &&
2186 (*speed
== SPEED_1000
)) {
2187 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
2194 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2195 * @hw: pointer to the HW structure
2197 * Work-around for 82566 Kumeran PCS lock loss:
2198 * On link status change (i.e. PCI reset, speed change) and link is up and
2200 * 0) if workaround is optionally disabled do nothing
2201 * 1) wait 1ms for Kumeran link to come up
2202 * 2) check Kumeran Diagnostic register PCS lock loss bit
2203 * 3) if not set the link is locked (all is good), otherwise...
2205 * 5) repeat up to 10 times
2206 * Note: this is only called for IGP3 copper when speed is 1gb.
2208 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
2210 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2216 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
2220 * Make sure link is up before proceeding. If not just return.
2221 * Attempting this while link is negotiating fouled up link
2224 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
2228 for (i
= 0; i
< 10; i
++) {
2229 /* read once to clear */
2230 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2233 /* and again to get new status */
2234 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2238 /* check for PCS lock */
2239 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
2242 /* Issue PHY reset */
2243 e1000_phy_hw_reset(hw
);
2246 /* Disable GigE link negotiation */
2247 phy_ctrl
= er32(PHY_CTRL
);
2248 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2249 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2250 ew32(PHY_CTRL
, phy_ctrl
);
2253 * Call gig speed drop workaround on Gig disable before accessing
2256 e1000e_gig_downshift_workaround_ich8lan(hw
);
2258 /* unable to acquire PCS lock */
2259 return -E1000_ERR_PHY
;
2263 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2264 * @hw: pointer to the HW structure
2265 * @state: boolean value used to set the current Kumeran workaround state
2267 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2268 * /disabled - FALSE).
2270 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
2273 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2275 if (hw
->mac
.type
!= e1000_ich8lan
) {
2276 hw_dbg(hw
, "Workaround applies to ICH8 only.\n");
2280 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
2284 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2285 * @hw: pointer to the HW structure
2287 * Workaround for 82566 power-down on D3 entry:
2288 * 1) disable gigabit link
2289 * 2) write VR power-down enable
2291 * Continue if successful, else issue LCD reset and repeat
2293 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
2299 if (hw
->phy
.type
!= e1000_phy_igp_3
)
2302 /* Try the workaround twice (if needed) */
2305 reg
= er32(PHY_CTRL
);
2306 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2307 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2308 ew32(PHY_CTRL
, reg
);
2311 * Call gig speed drop workaround on Gig disable before
2312 * accessing any PHY registers
2314 if (hw
->mac
.type
== e1000_ich8lan
)
2315 e1000e_gig_downshift_workaround_ich8lan(hw
);
2317 /* Write VR power-down enable */
2318 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2319 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2320 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
2322 /* Read it back and test */
2323 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2324 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2325 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
2328 /* Issue PHY reset and repeat at most one more time */
2330 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
2336 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2337 * @hw: pointer to the HW structure
2339 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2340 * LPLU, Gig disable, MDIC PHY reset):
2341 * 1) Set Kumeran Near-end loopback
2342 * 2) Clear Kumeran Near-end loopback
2343 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2345 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
2350 if ((hw
->mac
.type
!= e1000_ich8lan
) ||
2351 (hw
->phy
.type
!= e1000_phy_igp_3
))
2354 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2358 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2359 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2363 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2364 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2369 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2370 * @hw: pointer to the HW structure
2372 * During S0 to Sx transition, it is possible the link remains at gig
2373 * instead of negotiating to a lower speed. Before going to Sx, set
2374 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2377 * Should only be called for ICH9 and ICH10 devices.
2379 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw
*hw
)
2383 if ((hw
->mac
.type
== e1000_ich10lan
) ||
2384 (hw
->mac
.type
== e1000_ich9lan
)) {
2385 phy_ctrl
= er32(PHY_CTRL
);
2386 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
|
2387 E1000_PHY_CTRL_GBE_DISABLE
;
2388 ew32(PHY_CTRL
, phy_ctrl
);
2395 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2396 * @hw: pointer to the HW structure
2398 * Return the LED back to the default configuration.
2400 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
2402 if (hw
->phy
.type
== e1000_phy_ife
)
2403 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
2405 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
2410 * e1000_led_on_ich8lan - Turn LEDs on
2411 * @hw: pointer to the HW structure
2415 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
2417 if (hw
->phy
.type
== e1000_phy_ife
)
2418 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2419 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
2421 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
2426 * e1000_led_off_ich8lan - Turn LEDs off
2427 * @hw: pointer to the HW structure
2429 * Turn off the LEDs.
2431 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
2433 if (hw
->phy
.type
== e1000_phy_ife
)
2434 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2435 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_OFF
));
2437 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
2442 * e1000_get_cfg_done_ich8lan - Read config done bit
2443 * @hw: pointer to the HW structure
2445 * Read the management control register for the config done bit for
2446 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2447 * to read the config done bit, so an error is *ONLY* logged and returns
2448 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2449 * would not be able to be reset or change link.
2451 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
2455 e1000e_get_cfg_done(hw
);
2457 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2458 if (hw
->mac
.type
!= e1000_ich10lan
) {
2459 if (((er32(EECD
) & E1000_EECD_PRES
) == 0) &&
2460 (hw
->phy
.type
== e1000_phy_igp_3
)) {
2461 e1000e_phy_init_script_igp3(hw
);
2464 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
2465 /* Maybe we should do a basic PHY config */
2466 hw_dbg(hw
, "EEPROM not present\n");
2467 return -E1000_ERR_CONFIG
;
2475 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2476 * @hw: pointer to the HW structure
2478 * Clears hardware counters specific to the silicon family and calls
2479 * clear_hw_cntrs_generic to clear all general purpose counters.
2481 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
2485 e1000e_clear_hw_cntrs_base(hw
);
2487 temp
= er32(ALGNERRC
);
2488 temp
= er32(RXERRC
);
2490 temp
= er32(CEXTERR
);
2492 temp
= er32(TSCTFC
);
2494 temp
= er32(MGTPRC
);
2495 temp
= er32(MGTPDC
);
2496 temp
= er32(MGTPTC
);
2499 temp
= er32(ICRXOC
);
2503 static struct e1000_mac_operations ich8_mac_ops
= {
2504 .check_mng_mode
= e1000_check_mng_mode_ich8lan
,
2505 .check_for_link
= e1000e_check_for_copper_link
,
2506 .cleanup_led
= e1000_cleanup_led_ich8lan
,
2507 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
2508 .get_bus_info
= e1000_get_bus_info_ich8lan
,
2509 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
2510 .led_on
= e1000_led_on_ich8lan
,
2511 .led_off
= e1000_led_off_ich8lan
,
2512 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
2513 .reset_hw
= e1000_reset_hw_ich8lan
,
2514 .init_hw
= e1000_init_hw_ich8lan
,
2515 .setup_link
= e1000_setup_link_ich8lan
,
2516 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
2519 static struct e1000_phy_operations ich8_phy_ops
= {
2520 .acquire_phy
= e1000_acquire_swflag_ich8lan
,
2521 .check_reset_block
= e1000_check_reset_block_ich8lan
,
2523 .force_speed_duplex
= e1000_phy_force_speed_duplex_ich8lan
,
2524 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
2525 .get_cable_length
= e1000e_get_cable_length_igp_2
,
2526 .get_phy_info
= e1000_get_phy_info_ich8lan
,
2527 .read_phy_reg
= e1000e_read_phy_reg_igp
,
2528 .release_phy
= e1000_release_swflag_ich8lan
,
2529 .reset_phy
= e1000_phy_hw_reset_ich8lan
,
2530 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
2531 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
2532 .write_phy_reg
= e1000e_write_phy_reg_igp
,
2535 static struct e1000_nvm_operations ich8_nvm_ops
= {
2536 .acquire_nvm
= e1000_acquire_swflag_ich8lan
,
2537 .read_nvm
= e1000_read_nvm_ich8lan
,
2538 .release_nvm
= e1000_release_swflag_ich8lan
,
2539 .update_nvm
= e1000_update_nvm_checksum_ich8lan
,
2540 .valid_led_default
= e1000_valid_led_default_ich8lan
,
2541 .validate_nvm
= e1000_validate_nvm_checksum_ich8lan
,
2542 .write_nvm
= e1000_write_nvm_ich8lan
,
2545 struct e1000_info e1000_ich8_info
= {
2546 .mac
= e1000_ich8lan
,
2547 .flags
= FLAG_HAS_WOL
2549 | FLAG_RX_CSUM_ENABLED
2550 | FLAG_HAS_CTRLEXT_ON_LOAD
2555 .get_variants
= e1000_get_variants_ich8lan
,
2556 .mac_ops
= &ich8_mac_ops
,
2557 .phy_ops
= &ich8_phy_ops
,
2558 .nvm_ops
= &ich8_nvm_ops
,
2561 struct e1000_info e1000_ich9_info
= {
2562 .mac
= e1000_ich9lan
,
2563 .flags
= FLAG_HAS_JUMBO_FRAMES
2566 | FLAG_RX_CSUM_ENABLED
2567 | FLAG_HAS_CTRLEXT_ON_LOAD
2573 .get_variants
= e1000_get_variants_ich8lan
,
2574 .mac_ops
= &ich8_mac_ops
,
2575 .phy_ops
= &ich8_phy_ops
,
2576 .nvm_ops
= &ich8_nvm_ops
,
2579 struct e1000_info e1000_ich10_info
= {
2580 .mac
= e1000_ich10lan
,
2581 .flags
= FLAG_HAS_JUMBO_FRAMES
2584 | FLAG_RX_CSUM_ENABLED
2585 | FLAG_HAS_CTRLEXT_ON_LOAD
2591 .get_variants
= e1000_get_variants_ich8lan
,
2592 .mac_ops
= &ich8_mac_ops
,
2593 .phy_ops
= &ich8_phy_ops
,
2594 .nvm_ops
= &ich8_nvm_ops
,