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drm/nv50: Improve PGRAPH interrupt handling.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / nouveau / nouveau_state.c
blobf4ea3e61c094048336f6ac89d34860957fab0132
1 /*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <linux/swab.h>
27 #include "drmP.h"
28 #include "drm.h"
29 #include "drm_sarea.h"
30 #include "drm_crtc_helper.h"
31 #include <linux/vgaarb.h>
32
33 #include "nouveau_drv.h"
34 #include "nouveau_drm.h"
35 #include "nv50_display.h"
36
37 static void nouveau_stub_takedown(struct drm_device *dev) {}
38
39 static int nouveau_init_engine_ptrs(struct drm_device *dev)
40 {
41 struct drm_nouveau_private *dev_priv = dev->dev_private;
42 struct nouveau_engine *engine = &dev_priv->engine;
43
44 switch (dev_priv->chipset & 0xf0) {
45 case 0x00:
46 engine->instmem.init = nv04_instmem_init;
47 engine->instmem.takedown = nv04_instmem_takedown;
48 engine->instmem.suspend = nv04_instmem_suspend;
49 engine->instmem.resume = nv04_instmem_resume;
50 engine->instmem.populate = nv04_instmem_populate;
51 engine->instmem.clear = nv04_instmem_clear;
52 engine->instmem.bind = nv04_instmem_bind;
53 engine->instmem.unbind = nv04_instmem_unbind;
54 engine->instmem.prepare_access = nv04_instmem_prepare_access;
55 engine->instmem.finish_access = nv04_instmem_finish_access;
56 engine->mc.init = nv04_mc_init;
57 engine->mc.takedown = nv04_mc_takedown;
58 engine->timer.init = nv04_timer_init;
59 engine->timer.read = nv04_timer_read;
60 engine->timer.takedown = nv04_timer_takedown;
61 engine->fb.init = nv04_fb_init;
62 engine->fb.takedown = nv04_fb_takedown;
63 engine->graph.grclass = nv04_graph_grclass;
64 engine->graph.init = nv04_graph_init;
65 engine->graph.takedown = nv04_graph_takedown;
66 engine->graph.fifo_access = nv04_graph_fifo_access;
67 engine->graph.channel = nv04_graph_channel;
68 engine->graph.create_context = nv04_graph_create_context;
69 engine->graph.destroy_context = nv04_graph_destroy_context;
70 engine->graph.load_context = nv04_graph_load_context;
71 engine->graph.unload_context = nv04_graph_unload_context;
72 engine->fifo.channels = 16;
73 engine->fifo.init = nv04_fifo_init;
74 engine->fifo.takedown = nouveau_stub_takedown;
75 engine->fifo.disable = nv04_fifo_disable;
76 engine->fifo.enable = nv04_fifo_enable;
77 engine->fifo.reassign = nv04_fifo_reassign;
78 engine->fifo.cache_flush = nv04_fifo_cache_flush;
79 engine->fifo.cache_pull = nv04_fifo_cache_pull;
80 engine->fifo.channel_id = nv04_fifo_channel_id;
81 engine->fifo.create_context = nv04_fifo_create_context;
82 engine->fifo.destroy_context = nv04_fifo_destroy_context;
83 engine->fifo.load_context = nv04_fifo_load_context;
84 engine->fifo.unload_context = nv04_fifo_unload_context;
85 break;
86 case 0x10:
87 engine->instmem.init = nv04_instmem_init;
88 engine->instmem.takedown = nv04_instmem_takedown;
89 engine->instmem.suspend = nv04_instmem_suspend;
90 engine->instmem.resume = nv04_instmem_resume;
91 engine->instmem.populate = nv04_instmem_populate;
92 engine->instmem.clear = nv04_instmem_clear;
93 engine->instmem.bind = nv04_instmem_bind;
94 engine->instmem.unbind = nv04_instmem_unbind;
95 engine->instmem.prepare_access = nv04_instmem_prepare_access;
96 engine->instmem.finish_access = nv04_instmem_finish_access;
97 engine->mc.init = nv04_mc_init;
98 engine->mc.takedown = nv04_mc_takedown;
99 engine->timer.init = nv04_timer_init;
100 engine->timer.read = nv04_timer_read;
101 engine->timer.takedown = nv04_timer_takedown;
102 engine->fb.init = nv10_fb_init;
103 engine->fb.takedown = nv10_fb_takedown;
104 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
105 engine->graph.grclass = nv10_graph_grclass;
106 engine->graph.init = nv10_graph_init;
107 engine->graph.takedown = nv10_graph_takedown;
108 engine->graph.channel = nv10_graph_channel;
109 engine->graph.create_context = nv10_graph_create_context;
110 engine->graph.destroy_context = nv10_graph_destroy_context;
111 engine->graph.fifo_access = nv04_graph_fifo_access;
112 engine->graph.load_context = nv10_graph_load_context;
113 engine->graph.unload_context = nv10_graph_unload_context;
114 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
115 engine->fifo.channels = 32;
116 engine->fifo.init = nv10_fifo_init;
117 engine->fifo.takedown = nouveau_stub_takedown;
118 engine->fifo.disable = nv04_fifo_disable;
119 engine->fifo.enable = nv04_fifo_enable;
120 engine->fifo.reassign = nv04_fifo_reassign;
121 engine->fifo.cache_flush = nv04_fifo_cache_flush;
122 engine->fifo.cache_pull = nv04_fifo_cache_pull;
123 engine->fifo.channel_id = nv10_fifo_channel_id;
124 engine->fifo.create_context = nv10_fifo_create_context;
125 engine->fifo.destroy_context = nv10_fifo_destroy_context;
126 engine->fifo.load_context = nv10_fifo_load_context;
127 engine->fifo.unload_context = nv10_fifo_unload_context;
128 break;
129 case 0x20:
130 engine->instmem.init = nv04_instmem_init;
131 engine->instmem.takedown = nv04_instmem_takedown;
132 engine->instmem.suspend = nv04_instmem_suspend;
133 engine->instmem.resume = nv04_instmem_resume;
134 engine->instmem.populate = nv04_instmem_populate;
135 engine->instmem.clear = nv04_instmem_clear;
136 engine->instmem.bind = nv04_instmem_bind;
137 engine->instmem.unbind = nv04_instmem_unbind;
138 engine->instmem.prepare_access = nv04_instmem_prepare_access;
139 engine->instmem.finish_access = nv04_instmem_finish_access;
140 engine->mc.init = nv04_mc_init;
141 engine->mc.takedown = nv04_mc_takedown;
142 engine->timer.init = nv04_timer_init;
143 engine->timer.read = nv04_timer_read;
144 engine->timer.takedown = nv04_timer_takedown;
145 engine->fb.init = nv10_fb_init;
146 engine->fb.takedown = nv10_fb_takedown;
147 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
148 engine->graph.grclass = nv20_graph_grclass;
149 engine->graph.init = nv20_graph_init;
150 engine->graph.takedown = nv20_graph_takedown;
151 engine->graph.channel = nv10_graph_channel;
152 engine->graph.create_context = nv20_graph_create_context;
153 engine->graph.destroy_context = nv20_graph_destroy_context;
154 engine->graph.fifo_access = nv04_graph_fifo_access;
155 engine->graph.load_context = nv20_graph_load_context;
156 engine->graph.unload_context = nv20_graph_unload_context;
157 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
158 engine->fifo.channels = 32;
159 engine->fifo.init = nv10_fifo_init;
160 engine->fifo.takedown = nouveau_stub_takedown;
161 engine->fifo.disable = nv04_fifo_disable;
162 engine->fifo.enable = nv04_fifo_enable;
163 engine->fifo.reassign = nv04_fifo_reassign;
164 engine->fifo.cache_flush = nv04_fifo_cache_flush;
165 engine->fifo.cache_pull = nv04_fifo_cache_pull;
166 engine->fifo.channel_id = nv10_fifo_channel_id;
167 engine->fifo.create_context = nv10_fifo_create_context;
168 engine->fifo.destroy_context = nv10_fifo_destroy_context;
169 engine->fifo.load_context = nv10_fifo_load_context;
170 engine->fifo.unload_context = nv10_fifo_unload_context;
171 break;
172 case 0x30:
173 engine->instmem.init = nv04_instmem_init;
174 engine->instmem.takedown = nv04_instmem_takedown;
175 engine->instmem.suspend = nv04_instmem_suspend;
176 engine->instmem.resume = nv04_instmem_resume;
177 engine->instmem.populate = nv04_instmem_populate;
178 engine->instmem.clear = nv04_instmem_clear;
179 engine->instmem.bind = nv04_instmem_bind;
180 engine->instmem.unbind = nv04_instmem_unbind;
181 engine->instmem.prepare_access = nv04_instmem_prepare_access;
182 engine->instmem.finish_access = nv04_instmem_finish_access;
183 engine->mc.init = nv04_mc_init;
184 engine->mc.takedown = nv04_mc_takedown;
185 engine->timer.init = nv04_timer_init;
186 engine->timer.read = nv04_timer_read;
187 engine->timer.takedown = nv04_timer_takedown;
188 engine->fb.init = nv10_fb_init;
189 engine->fb.takedown = nv10_fb_takedown;
190 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
191 engine->graph.grclass = nv30_graph_grclass;
192 engine->graph.init = nv30_graph_init;
193 engine->graph.takedown = nv20_graph_takedown;
194 engine->graph.fifo_access = nv04_graph_fifo_access;
195 engine->graph.channel = nv10_graph_channel;
196 engine->graph.create_context = nv20_graph_create_context;
197 engine->graph.destroy_context = nv20_graph_destroy_context;
198 engine->graph.load_context = nv20_graph_load_context;
199 engine->graph.unload_context = nv20_graph_unload_context;
200 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
201 engine->fifo.channels = 32;
202 engine->fifo.init = nv10_fifo_init;
203 engine->fifo.takedown = nouveau_stub_takedown;
204 engine->fifo.disable = nv04_fifo_disable;
205 engine->fifo.enable = nv04_fifo_enable;
206 engine->fifo.reassign = nv04_fifo_reassign;
207 engine->fifo.cache_flush = nv04_fifo_cache_flush;
208 engine->fifo.cache_pull = nv04_fifo_cache_pull;
209 engine->fifo.channel_id = nv10_fifo_channel_id;
210 engine->fifo.create_context = nv10_fifo_create_context;
211 engine->fifo.destroy_context = nv10_fifo_destroy_context;
212 engine->fifo.load_context = nv10_fifo_load_context;
213 engine->fifo.unload_context = nv10_fifo_unload_context;
214 break;
215 case 0x40:
216 case 0x60:
217 engine->instmem.init = nv04_instmem_init;
218 engine->instmem.takedown = nv04_instmem_takedown;
219 engine->instmem.suspend = nv04_instmem_suspend;
220 engine->instmem.resume = nv04_instmem_resume;
221 engine->instmem.populate = nv04_instmem_populate;
222 engine->instmem.clear = nv04_instmem_clear;
223 engine->instmem.bind = nv04_instmem_bind;
224 engine->instmem.unbind = nv04_instmem_unbind;
225 engine->instmem.prepare_access = nv04_instmem_prepare_access;
226 engine->instmem.finish_access = nv04_instmem_finish_access;
227 engine->mc.init = nv40_mc_init;
228 engine->mc.takedown = nv40_mc_takedown;
229 engine->timer.init = nv04_timer_init;
230 engine->timer.read = nv04_timer_read;
231 engine->timer.takedown = nv04_timer_takedown;
232 engine->fb.init = nv40_fb_init;
233 engine->fb.takedown = nv40_fb_takedown;
234 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
235 engine->graph.grclass = nv40_graph_grclass;
236 engine->graph.init = nv40_graph_init;
237 engine->graph.takedown = nv40_graph_takedown;
238 engine->graph.fifo_access = nv04_graph_fifo_access;
239 engine->graph.channel = nv40_graph_channel;
240 engine->graph.create_context = nv40_graph_create_context;
241 engine->graph.destroy_context = nv40_graph_destroy_context;
242 engine->graph.load_context = nv40_graph_load_context;
243 engine->graph.unload_context = nv40_graph_unload_context;
244 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
245 engine->fifo.channels = 32;
246 engine->fifo.init = nv40_fifo_init;
247 engine->fifo.takedown = nouveau_stub_takedown;
248 engine->fifo.disable = nv04_fifo_disable;
249 engine->fifo.enable = nv04_fifo_enable;
250 engine->fifo.reassign = nv04_fifo_reassign;
251 engine->fifo.cache_flush = nv04_fifo_cache_flush;
252 engine->fifo.cache_pull = nv04_fifo_cache_pull;
253 engine->fifo.channel_id = nv10_fifo_channel_id;
254 engine->fifo.create_context = nv40_fifo_create_context;
255 engine->fifo.destroy_context = nv40_fifo_destroy_context;
256 engine->fifo.load_context = nv40_fifo_load_context;
257 engine->fifo.unload_context = nv40_fifo_unload_context;
258 break;
259 case 0x50:
260 case 0x80: /* gotta love NVIDIA's consistency.. */
261 case 0x90:
262 case 0xA0:
263 engine->instmem.init = nv50_instmem_init;
264 engine->instmem.takedown = nv50_instmem_takedown;
265 engine->instmem.suspend = nv50_instmem_suspend;
266 engine->instmem.resume = nv50_instmem_resume;
267 engine->instmem.populate = nv50_instmem_populate;
268 engine->instmem.clear = nv50_instmem_clear;
269 engine->instmem.bind = nv50_instmem_bind;
270 engine->instmem.unbind = nv50_instmem_unbind;
271 engine->instmem.prepare_access = nv50_instmem_prepare_access;
272 engine->instmem.finish_access = nv50_instmem_finish_access;
273 engine->mc.init = nv50_mc_init;
274 engine->mc.takedown = nv50_mc_takedown;
275 engine->timer.init = nv04_timer_init;
276 engine->timer.read = nv04_timer_read;
277 engine->timer.takedown = nv04_timer_takedown;
278 engine->fb.init = nv50_fb_init;
279 engine->fb.takedown = nv50_fb_takedown;
280 engine->graph.grclass = nv50_graph_grclass;
281 engine->graph.init = nv50_graph_init;
282 engine->graph.takedown = nv50_graph_takedown;
283 engine->graph.fifo_access = nv50_graph_fifo_access;
284 engine->graph.channel = nv50_graph_channel;
285 engine->graph.create_context = nv50_graph_create_context;
286 engine->graph.destroy_context = nv50_graph_destroy_context;
287 engine->graph.load_context = nv50_graph_load_context;
288 engine->graph.unload_context = nv50_graph_unload_context;
289 engine->fifo.channels = 128;
290 engine->fifo.init = nv50_fifo_init;
291 engine->fifo.takedown = nv50_fifo_takedown;
292 engine->fifo.disable = nv04_fifo_disable;
293 engine->fifo.enable = nv04_fifo_enable;
294 engine->fifo.reassign = nv04_fifo_reassign;
295 engine->fifo.channel_id = nv50_fifo_channel_id;
296 engine->fifo.create_context = nv50_fifo_create_context;
297 engine->fifo.destroy_context = nv50_fifo_destroy_context;
298 engine->fifo.load_context = nv50_fifo_load_context;
299 engine->fifo.unload_context = nv50_fifo_unload_context;
300 break;
301 default:
302 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
303 return 1;
304 }
305
306 return 0;
307 }
308
309 static unsigned int
310 nouveau_vga_set_decode(void *priv, bool state)
311 {
312 struct drm_device *dev = priv;
313 struct drm_nouveau_private *dev_priv = dev->dev_private;
314
315 if (dev_priv->chipset >= 0x40)
316 nv_wr32(dev, 0x88054, state);
317 else
318 nv_wr32(dev, 0x1854, state);
319
320 if (state)
321 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
322 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
323 else
324 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
325 }
326
327 static int
328 nouveau_card_init_channel(struct drm_device *dev)
329 {
330 struct drm_nouveau_private *dev_priv = dev->dev_private;
331 struct nouveau_gpuobj *gpuobj;
332 int ret;
333
334 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
335 (struct drm_file *)-2,
336 NvDmaFB, NvDmaTT);
337 if (ret)
338 return ret;
339
340 gpuobj = NULL;
341 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
342 0, nouveau_mem_fb_amount(dev),
343 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
344 &gpuobj);
345 if (ret)
346 goto out_err;
347
348 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
349 gpuobj, NULL);
350 if (ret)
351 goto out_err;
352
353 gpuobj = NULL;
354 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
355 dev_priv->gart_info.aper_size,
356 NV_DMA_ACCESS_RW, &gpuobj, NULL);
357 if (ret)
358 goto out_err;
359
360 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
361 gpuobj, NULL);
362 if (ret)
363 goto out_err;
364
365 return 0;
366 out_err:
367 nouveau_gpuobj_del(dev, &gpuobj);
368 nouveau_channel_free(dev_priv->channel);
369 dev_priv->channel = NULL;
370 return ret;
371 }
372
373 int
374 nouveau_card_init(struct drm_device *dev)
375 {
376 struct drm_nouveau_private *dev_priv = dev->dev_private;
377 struct nouveau_engine *engine;
378 int ret;
379
380 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
381
382 if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
383 return 0;
384
385 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
386
387 /* Initialise internal driver API hooks */
388 ret = nouveau_init_engine_ptrs(dev);
389 if (ret)
390 goto out;
391 engine = &dev_priv->engine;
392 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
393 spin_lock_init(&dev_priv->context_switch_lock);
394
395 /* Parse BIOS tables / Run init tables if card not POSTed */
396 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
397 ret = nouveau_bios_init(dev);
398 if (ret)
399 goto out;
400 }
401
402 ret = nouveau_gpuobj_early_init(dev);
403 if (ret)
404 goto out_bios;
405
406 /* Initialise instance memory, must happen before mem_init so we
407 * know exactly how much VRAM we're able to use for "normal"
408 * purposes.
409 */
410 ret = engine->instmem.init(dev);
411 if (ret)
412 goto out_gpuobj_early;
413
414 /* Setup the memory manager */
415 ret = nouveau_mem_init(dev);
416 if (ret)
417 goto out_instmem;
418
419 ret = nouveau_gpuobj_init(dev);
420 if (ret)
421 goto out_mem;
422
423 /* PMC */
424 ret = engine->mc.init(dev);
425 if (ret)
426 goto out_gpuobj;
427
428 /* PTIMER */
429 ret = engine->timer.init(dev);
430 if (ret)
431 goto out_mc;
432
433 /* PFB */
434 ret = engine->fb.init(dev);
435 if (ret)
436 goto out_timer;
437
438 if (nouveau_noaccel)
439 engine->graph.accel_blocked = true;
440 else {
441 /* PGRAPH */
442 ret = engine->graph.init(dev);
443 if (ret)
444 goto out_fb;
445
446 /* PFIFO */
447 ret = engine->fifo.init(dev);
448 if (ret)
449 goto out_graph;
450 }
451
452 /* this call irq_preinstall, register irq handler and
453 * call irq_postinstall
454 */
455 ret = drm_irq_install(dev);
456 if (ret)
457 goto out_fifo;
458
459 ret = drm_vblank_init(dev, 0);
460 if (ret)
461 goto out_irq;
462
463 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
464
465 if (!engine->graph.accel_blocked) {
466 ret = nouveau_card_init_channel(dev);
467 if (ret)
468 goto out_irq;
469 }
470
471 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
472 if (dev_priv->card_type >= NV_50)
473 ret = nv50_display_create(dev);
474 else
475 ret = nv04_display_create(dev);
476 if (ret)
477 goto out_irq;
478 }
479
480 ret = nouveau_backlight_init(dev);
481 if (ret)
482 NV_ERROR(dev, "Error %d registering backlight\n", ret);
483
484 dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
485
486 if (drm_core_check_feature(dev, DRIVER_MODESET))
487 drm_helper_initial_config(dev);
488
489 return 0;
490
491 out_irq:
492 drm_irq_uninstall(dev);
493 out_fifo:
494 if (!nouveau_noaccel)
495 engine->fifo.takedown(dev);
496 out_graph:
497 if (!nouveau_noaccel)
498 engine->graph.takedown(dev);
499 out_fb:
500 engine->fb.takedown(dev);
501 out_timer:
502 engine->timer.takedown(dev);
503 out_mc:
504 engine->mc.takedown(dev);
505 out_gpuobj:
506 nouveau_gpuobj_takedown(dev);
507 out_mem:
508 nouveau_mem_close(dev);
509 out_instmem:
510 engine->instmem.takedown(dev);
511 out_gpuobj_early:
512 nouveau_gpuobj_late_takedown(dev);
513 out_bios:
514 nouveau_bios_takedown(dev);
515 out:
516 vga_client_register(dev->pdev, NULL, NULL, NULL);
517 return ret;
518 }
519
520 static void nouveau_card_takedown(struct drm_device *dev)
521 {
522 struct drm_nouveau_private *dev_priv = dev->dev_private;
523 struct nouveau_engine *engine = &dev_priv->engine;
524
525 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
526
527 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
528 nouveau_backlight_exit(dev);
529
530 if (dev_priv->channel) {
531 nouveau_channel_free(dev_priv->channel);
532 dev_priv->channel = NULL;
533 }
534
535 if (!nouveau_noaccel) {
536 engine->fifo.takedown(dev);
537 engine->graph.takedown(dev);
538 }
539 engine->fb.takedown(dev);
540 engine->timer.takedown(dev);
541 engine->mc.takedown(dev);
542
543 mutex_lock(&dev->struct_mutex);
544 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
545 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
546 mutex_unlock(&dev->struct_mutex);
547 nouveau_sgdma_takedown(dev);
548
549 nouveau_gpuobj_takedown(dev);
550 nouveau_mem_close(dev);
551 engine->instmem.takedown(dev);
552
553 if (drm_core_check_feature(dev, DRIVER_MODESET))
554 drm_irq_uninstall(dev);
555
556 nouveau_gpuobj_late_takedown(dev);
557 nouveau_bios_takedown(dev);
558
559 vga_client_register(dev->pdev, NULL, NULL, NULL);
560
561 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
562 }
563 }
564
565 /* here a client dies, release the stuff that was allocated for its
566 * file_priv */
567 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
568 {
569 nouveau_channel_cleanup(dev, file_priv);
570 }
571
572 /* first module load, setup the mmio/fb mapping */
573 /* KMS: we need mmio at load time, not when the first drm client opens. */
574 int nouveau_firstopen(struct drm_device *dev)
575 {
576 return 0;
577 }
578
579 /* if we have an OF card, copy vbios to RAMIN */
580 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
581 {
582 #if defined(__powerpc__)
583 int size, i;
584 const uint32_t *bios;
585 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
586 if (!dn) {
587 NV_INFO(dev, "Unable to get the OF node\n");
588 return;
589 }
590
591 bios = of_get_property(dn, "NVDA,BMP", &size);
592 if (bios) {
593 for (i = 0; i < size; i += 4)
594 nv_wi32(dev, i, bios[i/4]);
595 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
596 } else {
597 NV_INFO(dev, "Unable to get the OF bios\n");
598 }
599 #endif
600 }
601
602 int nouveau_load(struct drm_device *dev, unsigned long flags)
603 {
604 struct drm_nouveau_private *dev_priv;
605 uint32_t reg0;
606 resource_size_t mmio_start_offs;
607
608 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
609 if (!dev_priv)
610 return -ENOMEM;
611 dev->dev_private = dev_priv;
612 dev_priv->dev = dev;
613
614 dev_priv->flags = flags & NOUVEAU_FLAGS;
615 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
616
617 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
618 dev->pci_vendor, dev->pci_device, dev->pdev->class);
619
620 dev_priv->acpi_dsm = nouveau_dsm_probe(dev);
621
622 if (dev_priv->acpi_dsm)
623 nouveau_hybrid_setup(dev);
624
625 dev_priv->wq = create_workqueue("nouveau");
626 if (!dev_priv->wq)
627 return -EINVAL;
628
629 /* resource 0 is mmio regs */
630 /* resource 1 is linear FB */
631 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
632 /* resource 6 is bios */
633
634 /* map the mmio regs */
635 mmio_start_offs = pci_resource_start(dev->pdev, 0);
636 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
637 if (!dev_priv->mmio) {
638 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
639 "Please report your setup to " DRIVER_EMAIL "\n");
640 return -EINVAL;
641 }
642 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
643 (unsigned long long)mmio_start_offs);
644
645 #ifdef __BIG_ENDIAN
646 /* Put the card in BE mode if it's not */
647 if (nv_rd32(dev, NV03_PMC_BOOT_1))
648 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
649
650 DRM_MEMORYBARRIER();
651 #endif
652
653 /* Time to determine the card architecture */
654 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
655
656 /* We're dealing with >=NV10 */
657 if ((reg0 & 0x0f000000) > 0) {
658 /* Bit 27-20 contain the architecture in hex */
659 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
660 /* NV04 or NV05 */
661 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
662 if (reg0 & 0x00f00000)
663 dev_priv->chipset = 0x05;
664 else
665 dev_priv->chipset = 0x04;
666 } else
667 dev_priv->chipset = 0xff;
668
669 switch (dev_priv->chipset & 0xf0) {
670 case 0x00:
671 case 0x10:
672 case 0x20:
673 case 0x30:
674 dev_priv->card_type = dev_priv->chipset & 0xf0;
675 break;
676 case 0x40:
677 case 0x60:
678 dev_priv->card_type = NV_40;
679 break;
680 case 0x50:
681 case 0x80:
682 case 0x90:
683 case 0xa0:
684 dev_priv->card_type = NV_50;
685 break;
686 default:
687 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
688 return -EINVAL;
689 }
690
691 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
692 dev_priv->card_type, reg0);
693
694 /* map larger RAMIN aperture on NV40 cards */
695 dev_priv->ramin = NULL;
696 if (dev_priv->card_type >= NV_40) {
697 int ramin_bar = 2;
698 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
699 ramin_bar = 3;
700
701 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
702 dev_priv->ramin = ioremap(
703 pci_resource_start(dev->pdev, ramin_bar),
704 dev_priv->ramin_size);
705 if (!dev_priv->ramin) {
706 NV_ERROR(dev, "Failed to init RAMIN mapping, "
707 "limited instance memory available\n");
708 }
709 }
710
711 /* On older cards (or if the above failed), create a map covering
712 * the BAR0 PRAMIN aperture */
713 if (!dev_priv->ramin) {
714 dev_priv->ramin_size = 1 * 1024 * 1024;
715 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
716 dev_priv->ramin_size);
717 if (!dev_priv->ramin) {
718 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
719 return -ENOMEM;
720 }
721 }
722
723 nouveau_OF_copy_vbios_to_ramin(dev);
724
725 /* Special flags */
726 if (dev->pci_device == 0x01a0)
727 dev_priv->flags |= NV_NFORCE;
728 else if (dev->pci_device == 0x01f0)
729 dev_priv->flags |= NV_NFORCE2;
730
731 /* For kernel modesetting, init card now and bring up fbcon */
732 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
733 int ret = nouveau_card_init(dev);
734 if (ret)
735 return ret;
736 }
737
738 return 0;
739 }
740
741 static void nouveau_close(struct drm_device *dev)
742 {
743 struct drm_nouveau_private *dev_priv = dev->dev_private;
744
745 /* In the case of an error dev_priv may not be allocated yet */
746 if (dev_priv)
747 nouveau_card_takedown(dev);
748 }
749
750 /* KMS: we need mmio at load time, not when the first drm client opens. */
751 void nouveau_lastclose(struct drm_device *dev)
752 {
753 if (drm_core_check_feature(dev, DRIVER_MODESET))
754 return;
755
756 nouveau_close(dev);
757 }
758
759 int nouveau_unload(struct drm_device *dev)
760 {
761 struct drm_nouveau_private *dev_priv = dev->dev_private;
762
763 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
764 if (dev_priv->card_type >= NV_50)
765 nv50_display_destroy(dev);
766 else
767 nv04_display_destroy(dev);
768 nouveau_close(dev);
769 }
770
771 iounmap(dev_priv->mmio);
772 iounmap(dev_priv->ramin);
773
774 kfree(dev_priv);
775 dev->dev_private = NULL;
776 return 0;
777 }
778
779 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
780 struct drm_file *file_priv)
781 {
782 struct drm_nouveau_private *dev_priv = dev->dev_private;
783 struct drm_nouveau_getparam *getparam = data;
784
785 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
786
787 switch (getparam->param) {
788 case NOUVEAU_GETPARAM_CHIPSET_ID:
789 getparam->value = dev_priv->chipset;
790 break;
791 case NOUVEAU_GETPARAM_PCI_VENDOR:
792 getparam->value = dev->pci_vendor;
793 break;
794 case NOUVEAU_GETPARAM_PCI_DEVICE:
795 getparam->value = dev->pci_device;
796 break;
797 case NOUVEAU_GETPARAM_BUS_TYPE:
798 if (drm_device_is_agp(dev))
799 getparam->value = NV_AGP;
800 else if (drm_device_is_pcie(dev))
801 getparam->value = NV_PCIE;
802 else
803 getparam->value = NV_PCI;
804 break;
805 case NOUVEAU_GETPARAM_FB_PHYSICAL:
806 getparam->value = dev_priv->fb_phys;
807 break;
808 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
809 getparam->value = dev_priv->gart_info.aper_base;
810 break;
811 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
812 if (dev->sg) {
813 getparam->value = (unsigned long)dev->sg->virtual;
814 } else {
815 NV_ERROR(dev, "Requested PCIGART address, "
816 "while no PCIGART was created\n");
817 return -EINVAL;
818 }
819 break;
820 case NOUVEAU_GETPARAM_FB_SIZE:
821 getparam->value = dev_priv->fb_available_size;
822 break;
823 case NOUVEAU_GETPARAM_AGP_SIZE:
824 getparam->value = dev_priv->gart_info.aper_size;
825 break;
826 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
827 getparam->value = dev_priv->vm_vram_base;
828 break;
829 case NOUVEAU_GETPARAM_GRAPH_UNITS:
830 /* NV40 and NV50 versions are quite different, but register
831 * address is the same. User is supposed to know the card
832 * family anyway... */
833 if (dev_priv->chipset >= 0x40) {
834 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
835 break;
836 }
837 /* FALLTHRU */
838 default:
839 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
840 return -EINVAL;
841 }
842
843 return 0;
844 }
845
846 int
847 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
848 struct drm_file *file_priv)
849 {
850 struct drm_nouveau_setparam *setparam = data;
851
852 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
853
854 switch (setparam->param) {
855 default:
856 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
857 return -EINVAL;
858 }
859
860 return 0;
861 }
862
863 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
864 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
865 uint32_t reg, uint32_t mask, uint32_t val)
866 {
867 struct drm_nouveau_private *dev_priv = dev->dev_private;
868 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
869 uint64_t start = ptimer->read(dev);
870
871 do {
872 if ((nv_rd32(dev, reg) & mask) == val)
873 return true;
874 } while (ptimer->read(dev) - start < timeout);
875
876 return false;
877 }
878
879 /* Waits for PGRAPH to go completely idle */
880 bool nouveau_wait_for_idle(struct drm_device *dev)
881 {
882 if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
883 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
884 nv_rd32(dev, NV04_PGRAPH_STATUS));
885 return false;
886 }
887
888 return true;
889 }
890
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree