drivers/spi/spi_sh_msiof.c

   1 /*
   2  * SuperH MSIOF SPI Master Interface
   3  *
   4  * Copyright (c) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/bitmap.h>
  13 #include <linux/clk.h>
  14 #include <linux/completion.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/kernel.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24
  25 #include <linux/spi/sh_msiof.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/spi/spi_bitbang.h>
  28
  29 #include <asm/unaligned.h>
  30
  31 struct sh_msiof_spi_priv {
  32         struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */
  33         void __iomem *mapbase;
  34         struct clk *clk;
  35         struct platform_device *pdev;
  36         struct sh_msiof_spi_info *info;
  37         struct completion done;
  38         unsigned long flags;
  39         int tx_fifo_size;
  40         int rx_fifo_size;
  41 };
  42
  43 #define TMDR1   0x00
  44 #define TMDR2   0x04
  45 #define TMDR3   0x08
  46 #define RMDR1   0x10
  47 #define RMDR2   0x14
  48 #define RMDR3   0x18
  49 #define TSCR    0x20
  50 #define RSCR    0x22
  51 #define CTR     0x28
  52 #define FCTR    0x30
  53 #define STR     0x40
  54 #define IER     0x44
  55 #define TDR1    0x48
  56 #define TDR2    0x4c
  57 #define TFDR    0x50
  58 #define RDR1    0x58
  59 #define RDR2    0x5c
  60 #define RFDR    0x60
  61
  62 #define CTR_TSCKE (1 << 15)
  63 #define CTR_TFSE  (1 << 14)
  64 #define CTR_TXE   (1 << 9)
  65 #define CTR_RXE   (1 << 8)
  66
  67 #define STR_TEOF  (1 << 23)
  68 #define STR_REOF  (1 << 7)
  69
  70 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
  71 {
  72         switch (reg_offs) {
  73         case TSCR:
  74         case RSCR:
  75                 return ioread16(p->mapbase + reg_offs);
  76         default:
  77                 return ioread32(p->mapbase + reg_offs);
  78         }
  79 }
  80
  81 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
  82                            u32 value)
  83 {
  84         switch (reg_offs) {
  85         case TSCR:
  86         case RSCR:
  87                 iowrite16(value, p->mapbase + reg_offs);
  88                 break;
  89         default:
  90                 iowrite32(value, p->mapbase + reg_offs);
  91                 break;
  92         }
  93 }
  94
  95 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
  96                                     u32 clr, u32 set)
  97 {
  98         u32 mask = clr | set;
  99         u32 data;
 100         int k;
 101
 102         data = sh_msiof_read(p, CTR);
 103         data &= ~clr;
 104         data |= set;
 105         sh_msiof_write(p, CTR, data);
 106
 107         for (k = 100; k > 0; k--) {
 108                 if ((sh_msiof_read(p, CTR) & mask) == set)
 109                         break;
 110
 111                 udelay(10);
 112         }
 113
 114         return k > 0 ? 0 : -ETIMEDOUT;
 115 }
 116
 117 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
 118 {
 119         struct sh_msiof_spi_priv *p = data;
 120
 121         /* just disable the interrupt and wake up */
 122         sh_msiof_write(p, IER, 0);
 123         complete(&p->done);
 124
 125         return IRQ_HANDLED;
 126 }
 127
 128 static struct {
 129         unsigned short div;
 130         unsigned short scr;
 131 } const sh_msiof_spi_clk_table[] = {
 132         { 1, 0x0007 },
 133         { 2, 0x0000 },
 134         { 4, 0x0001 },
 135         { 8, 0x0002 },
 136         { 16, 0x0003 },
 137         { 32, 0x0004 },
 138         { 64, 0x1f00 },
 139         { 128, 0x1f01 },
 140         { 256, 0x1f02 },
 141         { 512, 0x1f03 },
 142         { 1024, 0x1f04 },
 143 };
 144
 145 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
 146                                       unsigned long parent_rate,
 147                                       unsigned long spi_hz)
 148 {
 149         unsigned long div = 1024;
 150         size_t k;
 151
 152         if (!WARN_ON(!spi_hz || !parent_rate))
 153                 div = parent_rate / spi_hz;
 154
 155         /* TODO: make more fine grained */
 156
 157         for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
 158                 if (sh_msiof_spi_clk_table[k].div >= div)
 159                         break;
 160         }
 161
 162         k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
 163
 164         sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
 165         sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
 166 }
 167
 168 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
 169                                       u32 cpol, u32 cpha,
 170                                       u32 tx_hi_z, u32 lsb_first)
 171 {
 172         u32 tmp;
 173         int edge;
 174
 175         /*
 176          * CPOL CPHA     TSCKIZ RSCKIZ TEDG REDG
 177          *    0    0         10     10    1    1
 178          *    0    1         10     10    0    0
 179          *    1    0         11     11    0    0
 180          *    1    1         11     11    1    1
 181          */
 182         sh_msiof_write(p, FCTR, 0);
 183         sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24));
 184         sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24));
 185
 186         tmp = 0xa0000000;
 187         tmp |= cpol << 30; /* TSCKIZ */
 188         tmp |= cpol << 28; /* RSCKIZ */
 189
 190         edge = cpol ^ !cpha;
 191
 192         tmp |= edge << 27; /* TEDG */
 193         tmp |= edge << 26; /* REDG */
 194         tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */
 195         sh_msiof_write(p, CTR, tmp);
 196 }
 197
 198 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
 199                                        const void *tx_buf, void *rx_buf,
 200                                        u32 bits, u32 words)
 201 {
 202         u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16);
 203
 204         if (tx_buf)
 205                 sh_msiof_write(p, TMDR2, dr2);
 206         else
 207                 sh_msiof_write(p, TMDR2, dr2 | 1);
 208
 209         if (rx_buf)
 210                 sh_msiof_write(p, RMDR2, dr2);
 211
 212         sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
 213 }
 214
 215 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
 216 {
 217         sh_msiof_write(p, STR, sh_msiof_read(p, STR));
 218 }
 219
 220 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
 221                                       const void *tx_buf, int words, int fs)
 222 {
 223         const u8 *buf_8 = tx_buf;
 224         int k;
 225
 226         for (k = 0; k < words; k++)
 227                 sh_msiof_write(p, TFDR, buf_8[k] << fs);
 228 }
 229
 230 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
 231                                        const void *tx_buf, int words, int fs)
 232 {
 233         const u16 *buf_16 = tx_buf;
 234         int k;
 235
 236         for (k = 0; k < words; k++)
 237                 sh_msiof_write(p, TFDR, buf_16[k] << fs);
 238 }
 239
 240 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
 241                                         const void *tx_buf, int words, int fs)
 242 {
 243         const u16 *buf_16 = tx_buf;
 244         int k;
 245
 246         for (k = 0; k < words; k++)
 247                 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
 248 }
 249
 250 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
 251                                        const void *tx_buf, int words, int fs)
 252 {
 253         const u32 *buf_32 = tx_buf;
 254         int k;
 255
 256         for (k = 0; k < words; k++)
 257                 sh_msiof_write(p, TFDR, buf_32[k] << fs);
 258 }
 259
 260 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
 261                                         const void *tx_buf, int words, int fs)
 262 {
 263         const u32 *buf_32 = tx_buf;
 264         int k;
 265
 266         for (k = 0; k < words; k++)
 267                 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
 268 }
 269
 270 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
 271                                         const void *tx_buf, int words, int fs)
 272 {
 273         const u32 *buf_32 = tx_buf;
 274         int k;
 275
 276         for (k = 0; k < words; k++)
 277                 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
 278 }
 279
 280 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
 281                                          const void *tx_buf, int words, int fs)
 282 {
 283         const u32 *buf_32 = tx_buf;
 284         int k;
 285
 286         for (k = 0; k < words; k++)
 287                 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
 288 }
 289
 290 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
 291                                      void *rx_buf, int words, int fs)
 292 {
 293         u8 *buf_8 = rx_buf;
 294         int k;
 295
 296         for (k = 0; k < words; k++)
 297                 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
 298 }
 299
 300 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
 301                                       void *rx_buf, int words, int fs)
 302 {
 303         u16 *buf_16 = rx_buf;
 304         int k;
 305
 306         for (k = 0; k < words; k++)
 307                 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
 308 }
 309
 310 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
 311                                        void *rx_buf, int words, int fs)
 312 {
 313         u16 *buf_16 = rx_buf;
 314         int k;
 315
 316         for (k = 0; k < words; k++)
 317                 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
 318 }
 319
 320 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
 321                                       void *rx_buf, int words, int fs)
 322 {
 323         u32 *buf_32 = rx_buf;
 324         int k;
 325
 326         for (k = 0; k < words; k++)
 327                 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
 328 }
 329
 330 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
 331                                        void *rx_buf, int words, int fs)
 332 {
 333         u32 *buf_32 = rx_buf;
 334         int k;
 335
 336         for (k = 0; k < words; k++)
 337                 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
 338 }
 339
 340 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
 341                                        void *rx_buf, int words, int fs)
 342 {
 343         u32 *buf_32 = rx_buf;
 344         int k;
 345
 346         for (k = 0; k < words; k++)
 347                 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
 348 }
 349
 350 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
 351                                        void *rx_buf, int words, int fs)
 352 {
 353         u32 *buf_32 = rx_buf;
 354         int k;
 355
 356         for (k = 0; k < words; k++)
 357                 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
 358 }
 359
 360 static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t)
 361 {
 362         int bits;
 363
 364         bits = t ? t->bits_per_word : 0;
 365         if (!bits)
 366                 bits = spi->bits_per_word;
 367         return bits;
 368 }
 369
 370 static unsigned long sh_msiof_spi_hz(struct spi_device *spi,
 371                                      struct spi_transfer *t)
 372 {
 373         unsigned long hz;
 374
 375         hz = t ? t->speed_hz : 0;
 376         if (!hz)
 377                 hz = spi->max_speed_hz;
 378         return hz;
 379 }
 380
 381 static int sh_msiof_spi_setup_transfer(struct spi_device *spi,
 382                                        struct spi_transfer *t)
 383 {
 384         int bits;
 385
 386         /* noting to check hz values against since parent clock is disabled */
 387
 388         bits = sh_msiof_spi_bits(spi, t);
 389         if (bits < 8)
 390                 return -EINVAL;
 391         if (bits > 32)
 392                 return -EINVAL;
 393
 394         return spi_bitbang_setup_transfer(spi, t);
 395 }
 396
 397 static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
 398 {
 399         struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
 400         int value;
 401
 402         /* chip select is active low unless SPI_CS_HIGH is set */
 403         if (spi->mode & SPI_CS_HIGH)
 404                 value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0;
 405         else
 406                 value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1;
 407
 408         if (is_on == BITBANG_CS_ACTIVE) {
 409                 if (!test_and_set_bit(0, &p->flags)) {
 410                         pm_runtime_get_sync(&p->pdev->dev);
 411                         clk_enable(p->clk);
 412                 }
 413
 414                 /* Configure pins before asserting CS */
 415                 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
 416                                           !!(spi->mode & SPI_CPHA),
 417                                           !!(spi->mode & SPI_3WIRE),
 418                                           !!(spi->mode & SPI_LSB_FIRST));
 419         }
 420
 421         /* use spi->controller data for CS (same strategy as spi_gpio) */
 422         gpio_set_value((unsigned)spi->controller_data, value);
 423
 424         if (is_on == BITBANG_CS_INACTIVE) {
 425                 if (test_and_clear_bit(0, &p->flags)) {
 426                         clk_disable(p->clk);
 427                         pm_runtime_put(&p->pdev->dev);
 428                 }
 429         }
 430 }
 431
 432 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
 433                                   void (*tx_fifo)(struct sh_msiof_spi_priv *,
 434                                                   const void *, int, int),
 435                                   void (*rx_fifo)(struct sh_msiof_spi_priv *,
 436                                                   void *, int, int),
 437                                   const void *tx_buf, void *rx_buf,
 438                                   int words, int bits)
 439 {
 440         int fifo_shift;
 441         int ret;
 442
 443         /* limit maximum word transfer to rx/tx fifo size */
 444         if (tx_buf)
 445                 words = min_t(int, words, p->tx_fifo_size);
 446         if (rx_buf)
 447                 words = min_t(int, words, p->rx_fifo_size);
 448
 449         /* the fifo contents need shifting */
 450         fifo_shift = 32 - bits;
 451
 452         /* setup msiof transfer mode registers */
 453         sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
 454
 455         /* write tx fifo */
 456         if (tx_buf)
 457                 tx_fifo(p, tx_buf, words, fifo_shift);
 458
 459         /* setup clock and rx/tx signals */
 460         ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
 461         if (rx_buf)
 462                 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
 463         ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
 464
 465         /* start by setting frame bit */
 466         INIT_COMPLETION(p->done);
 467         ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
 468         if (ret) {
 469                 dev_err(&p->pdev->dev, "failed to start hardware\n");
 470                 goto err;
 471         }
 472
 473         /* wait for tx fifo to be emptied / rx fifo to be filled */
 474         wait_for_completion(&p->done);
 475
 476         /* read rx fifo */
 477         if (rx_buf)
 478                 rx_fifo(p, rx_buf, words, fifo_shift);
 479
 480         /* clear status bits */
 481         sh_msiof_reset_str(p);
 482
 483         /* shut down frame, tx/tx and clock signals */
 484         ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
 485         ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
 486         if (rx_buf)
 487                 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
 488         ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
 489         if (ret) {
 490                 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
 491                 goto err;
 492         }
 493
 494         return words;
 495
 496  err:
 497         sh_msiof_write(p, IER, 0);
 498         return ret;
 499 }
 500
 501 static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
 502 {
 503         struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
 504         void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
 505         void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
 506         int bits;
 507         int bytes_per_word;
 508         int bytes_done;
 509         int words;
 510         int n;
 511         bool swab;
 512
 513         bits = sh_msiof_spi_bits(spi, t);
 514
 515         if (bits <= 8 && t->len > 15 && !(t->len & 3)) {
 516                 bits = 32;
 517                 swab = true;
 518         } else {
 519                 swab = false;
 520         }
 521
 522         /* setup bytes per word and fifo read/write functions */
 523         if (bits <= 8) {
 524                 bytes_per_word = 1;
 525                 tx_fifo = sh_msiof_spi_write_fifo_8;
 526                 rx_fifo = sh_msiof_spi_read_fifo_8;
 527         } else if (bits <= 16) {
 528                 bytes_per_word = 2;
 529                 if ((unsigned long)t->tx_buf & 0x01)
 530                         tx_fifo = sh_msiof_spi_write_fifo_16u;
 531                 else
 532                         tx_fifo = sh_msiof_spi_write_fifo_16;
 533
 534                 if ((unsigned long)t->rx_buf & 0x01)
 535                         rx_fifo = sh_msiof_spi_read_fifo_16u;
 536                 else
 537                         rx_fifo = sh_msiof_spi_read_fifo_16;
 538         } else if (swab) {
 539                 bytes_per_word = 4;
 540                 if ((unsigned long)t->tx_buf & 0x03)
 541                         tx_fifo = sh_msiof_spi_write_fifo_s32u;
 542                 else
 543                         tx_fifo = sh_msiof_spi_write_fifo_s32;
 544
 545                 if ((unsigned long)t->rx_buf & 0x03)
 546                         rx_fifo = sh_msiof_spi_read_fifo_s32u;
 547                 else
 548                         rx_fifo = sh_msiof_spi_read_fifo_s32;
 549         } else {
 550                 bytes_per_word = 4;
 551                 if ((unsigned long)t->tx_buf & 0x03)
 552                         tx_fifo = sh_msiof_spi_write_fifo_32u;
 553                 else
 554                         tx_fifo = sh_msiof_spi_write_fifo_32;
 555
 556                 if ((unsigned long)t->rx_buf & 0x03)
 557                         rx_fifo = sh_msiof_spi_read_fifo_32u;
 558                 else
 559                         rx_fifo = sh_msiof_spi_read_fifo_32;
 560         }
 561
 562         /* setup clocks (clock already enabled in chipselect()) */
 563         sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk),
 564                                   sh_msiof_spi_hz(spi, t));
 565
 566         /* transfer in fifo sized chunks */
 567         words = t->len / bytes_per_word;
 568         bytes_done = 0;
 569
 570         while (bytes_done < t->len) {
 571                 void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL;
 572                 const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL;
 573                 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo,
 574                                            tx_buf,
 575                                            rx_buf,
 576                                            words, bits);
 577                 if (n < 0)
 578                         break;
 579
 580                 bytes_done += n * bytes_per_word;
 581                 words -= n;
 582         }
 583
 584         return bytes_done;
 585 }
 586
 587 static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
 588                                   u32 word, u8 bits)
 589 {
 590         BUG(); /* unused but needed by bitbang code */
 591         return 0;
 592 }
 593
 594 static int sh_msiof_spi_probe(struct platform_device *pdev)
 595 {
 596         struct resource *r;
 597         struct spi_master *master;
 598         struct sh_msiof_spi_priv *p;
 599         char clk_name[16];
 600         int i;
 601         int ret;
 602
 603         master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
 604         if (master == NULL) {
 605                 dev_err(&pdev->dev, "failed to allocate spi master\n");
 606                 ret = -ENOMEM;
 607                 goto err0;
 608         }
 609
 610         p = spi_master_get_devdata(master);
 611
 612         platform_set_drvdata(pdev, p);
 613         p->info = pdev->dev.platform_data;
 614         init_completion(&p->done);
 615
 616         snprintf(clk_name, sizeof(clk_name), "msiof%d", pdev->id);
 617         p->clk = clk_get(&pdev->dev, clk_name);
 618         if (IS_ERR(p->clk)) {
 619                 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
 620                 ret = PTR_ERR(p->clk);
 621                 goto err1;
 622         }
 623
 624         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 625         i = platform_get_irq(pdev, 0);
 626         if (!r || i < 0) {
 627                 dev_err(&pdev->dev, "cannot get platform resources\n");
 628                 ret = -ENOENT;
 629                 goto err2;
 630         }
 631         p->mapbase = ioremap_nocache(r->start, resource_size(r));
 632         if (!p->mapbase) {
 633                 dev_err(&pdev->dev, "unable to ioremap\n");
 634                 ret = -ENXIO;
 635                 goto err2;
 636         }
 637
 638         ret = request_irq(i, sh_msiof_spi_irq, IRQF_DISABLED,
 639                           dev_name(&pdev->dev), p);
 640         if (ret) {
 641                 dev_err(&pdev->dev, "unable to request irq\n");
 642                 goto err3;
 643         }
 644
 645         p->pdev = pdev;
 646         pm_runtime_enable(&pdev->dev);
 647
 648         /* The standard version of MSIOF use 64 word FIFOs */
 649         p->tx_fifo_size = 64;
 650         p->rx_fifo_size = 64;
 651
 652         /* Platform data may override FIFO sizes */
 653         if (p->info->tx_fifo_override)
 654                 p->tx_fifo_size = p->info->tx_fifo_override;
 655         if (p->info->rx_fifo_override)
 656                 p->rx_fifo_size = p->info->rx_fifo_override;
 657
 658         /* init master and bitbang code */
 659         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 660         master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
 661         master->flags = 0;
 662         master->bus_num = pdev->id;
 663         master->num_chipselect = p->info->num_chipselect;
 664         master->setup = spi_bitbang_setup;
 665         master->cleanup = spi_bitbang_cleanup;
 666
 667         p->bitbang.master = master;
 668         p->bitbang.chipselect = sh_msiof_spi_chipselect;
 669         p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer;
 670         p->bitbang.txrx_bufs = sh_msiof_spi_txrx;
 671         p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word;
 672         p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word;
 673         p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word;
 674         p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word;
 675
 676         ret = spi_bitbang_start(&p->bitbang);
 677         if (ret == 0)
 678                 return 0;
 679
 680         pm_runtime_disable(&pdev->dev);
 681  err3:
 682         iounmap(p->mapbase);
 683  err2:
 684         clk_put(p->clk);
 685  err1:
 686         spi_master_put(master);
 687  err0:
 688         return ret;
 689 }
 690
 691 static int sh_msiof_spi_remove(struct platform_device *pdev)
 692 {
 693         struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
 694         int ret;
 695
 696         ret = spi_bitbang_stop(&p->bitbang);
 697         if (!ret) {
 698                 pm_runtime_disable(&pdev->dev);
 699                 free_irq(platform_get_irq(pdev, 0), p);
 700                 iounmap(p->mapbase);
 701                 clk_put(p->clk);
 702                 spi_master_put(p->bitbang.master);
 703         }
 704         return ret;
 705 }
 706
 707 static int sh_msiof_spi_runtime_nop(struct device *dev)
 708 {
 709         /* Runtime PM callback shared between ->runtime_suspend()
 710          * and ->runtime_resume(). Simply returns success.
 711          *
 712          * This driver re-initializes all registers after
 713          * pm_runtime_get_sync() anyway so there is no need
 714          * to save and restore registers here.
 715          */
 716         return 0;
 717 }
 718
 719 static struct dev_pm_ops sh_msiof_spi_dev_pm_ops = {
 720         .runtime_suspend = sh_msiof_spi_runtime_nop,
 721         .runtime_resume = sh_msiof_spi_runtime_nop,
 722 };
 723
 724 static struct platform_driver sh_msiof_spi_drv = {
 725         .probe          = sh_msiof_spi_probe,
 726         .remove         = sh_msiof_spi_remove,
 727         .driver         = {
 728                 .name           = "spi_sh_msiof",
 729                 .owner          = THIS_MODULE,
 730                 .pm             = &sh_msiof_spi_dev_pm_ops,
 731         },
 732 };
 733
 734 static int __init sh_msiof_spi_init(void)
 735 {
 736         return platform_driver_register(&sh_msiof_spi_drv);
 737 }
 738 module_init(sh_msiof_spi_init);
 739
 740 static void __exit sh_msiof_spi_exit(void)
 741 {
 742         platform_driver_unregister(&sh_msiof_spi_drv);
 743 }
 744 module_exit(sh_msiof_spi_exit);
 745
 746 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
 747 MODULE_AUTHOR("Magnus Damm");
 748 MODULE_LICENSE("GPL v2");
 749 MODULE_ALIAS("platform:spi_sh_msiof");