iwlwifi: use paged Rx
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
blob5c43d7c43b30f8d98cef49fc63bbe6a38ccf513d
1 /******************************************************************************
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <net/mac80211.h>
32 #include "iwl-eeprom.h"
33 #include "iwl-dev.h"
34 #include "iwl-core.h"
35 #include "iwl-sta.h"
36 #include "iwl-io.h"
37 #include "iwl-helpers.h"
39 static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
59 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
60 struct iwl_dma_ptr *ptr, size_t size)
62 ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
63 if (!ptr->addr)
64 return -ENOMEM;
65 ptr->size = size;
66 return 0;
69 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
70 struct iwl_dma_ptr *ptr)
72 if (unlikely(!ptr->addr))
73 return;
75 pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
76 memset(ptr, 0, sizeof(*ptr));
79 /**
80 * iwl_txq_update_write_ptr - Send new write index to hardware
82 int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
84 u32 reg = 0;
85 int ret = 0;
86 int txq_id = txq->q.id;
88 if (txq->need_update == 0)
89 return ret;
91 /* if we're trying to save power */
92 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
93 /* wake up nic if it's powered down ...
94 * uCode will wake up, and interrupt us again, so next
95 * time we'll skip this part. */
96 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
98 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
99 IWL_DEBUG_INFO(priv, "Requesting wakeup, GP1 = 0x%x\n", reg);
100 iwl_set_bit(priv, CSR_GP_CNTRL,
101 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
102 return ret;
105 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
106 txq->q.write_ptr | (txq_id << 8));
108 /* else not in power-save mode, uCode will never sleep when we're
109 * trying to tx (during RFKILL, we're not trying to tx). */
110 } else
111 iwl_write32(priv, HBUS_TARG_WRPTR,
112 txq->q.write_ptr | (txq_id << 8));
114 txq->need_update = 0;
116 return ret;
118 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
122 * iwl_tx_queue_free - Deallocate DMA queue.
123 * @txq: Transmit queue to deallocate.
125 * Empty queue by removing and destroying all BD's.
126 * Free all buffers.
127 * 0-fill, but do not free "txq" descriptor structure.
129 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
131 struct iwl_tx_queue *txq = &priv->txq[txq_id];
132 struct iwl_queue *q = &txq->q;
133 struct pci_dev *dev = priv->pci_dev;
134 int i, len;
136 if (q->n_bd == 0)
137 return;
139 /* first, empty all BD's */
140 for (; q->write_ptr != q->read_ptr;
141 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
142 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
144 len = sizeof(struct iwl_device_cmd) * q->n_window;
146 /* De-alloc array of command/tx buffers */
147 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
148 kfree(txq->cmd[i]);
150 /* De-alloc circular buffer of TFDs */
151 if (txq->q.n_bd)
152 pci_free_consistent(dev, priv->hw_params.tfd_size *
153 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
155 /* De-alloc array of per-TFD driver data */
156 kfree(txq->txb);
157 txq->txb = NULL;
159 /* deallocate arrays */
160 kfree(txq->cmd);
161 kfree(txq->meta);
162 txq->cmd = NULL;
163 txq->meta = NULL;
165 /* 0-fill queue descriptor structure */
166 memset(txq, 0, sizeof(*txq));
168 EXPORT_SYMBOL(iwl_tx_queue_free);
171 * iwl_cmd_queue_free - Deallocate DMA queue.
172 * @txq: Transmit queue to deallocate.
174 * Empty queue by removing and destroying all BD's.
175 * Free all buffers.
176 * 0-fill, but do not free "txq" descriptor structure.
178 void iwl_cmd_queue_free(struct iwl_priv *priv)
180 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
181 struct iwl_queue *q = &txq->q;
182 struct pci_dev *dev = priv->pci_dev;
183 int i, len;
185 if (q->n_bd == 0)
186 return;
188 len = sizeof(struct iwl_device_cmd) * q->n_window;
189 len += IWL_MAX_SCAN_SIZE;
191 /* De-alloc array of command/tx buffers */
192 for (i = 0; i <= TFD_CMD_SLOTS; i++)
193 kfree(txq->cmd[i]);
195 /* De-alloc circular buffer of TFDs */
196 if (txq->q.n_bd)
197 pci_free_consistent(dev, priv->hw_params.tfd_size *
198 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
200 /* deallocate arrays */
201 kfree(txq->cmd);
202 kfree(txq->meta);
203 txq->cmd = NULL;
204 txq->meta = NULL;
206 /* 0-fill queue descriptor structure */
207 memset(txq, 0, sizeof(*txq));
209 EXPORT_SYMBOL(iwl_cmd_queue_free);
211 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
212 * DMA services
214 * Theory of operation
216 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
217 * of buffer descriptors, each of which points to one or more data buffers for
218 * the device to read from or fill. Driver and device exchange status of each
219 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
220 * entries in each circular buffer, to protect against confusing empty and full
221 * queue states.
223 * The device reads or writes the data in the queues via the device's several
224 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
226 * For Tx queue, there are low mark and high mark limits. If, after queuing
227 * the packet for Tx, free space become < low mark, Tx queue stopped. When
228 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
229 * Tx queue resumed.
231 * See more detailed info in iwl-4965-hw.h.
232 ***************************************************/
234 int iwl_queue_space(const struct iwl_queue *q)
236 int s = q->read_ptr - q->write_ptr;
238 if (q->read_ptr > q->write_ptr)
239 s -= q->n_bd;
241 if (s <= 0)
242 s += q->n_window;
243 /* keep some reserve to not confuse empty and full situations */
244 s -= 2;
245 if (s < 0)
246 s = 0;
247 return s;
249 EXPORT_SYMBOL(iwl_queue_space);
253 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
255 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
256 int count, int slots_num, u32 id)
258 q->n_bd = count;
259 q->n_window = slots_num;
260 q->id = id;
262 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
263 * and iwl_queue_dec_wrap are broken. */
264 BUG_ON(!is_power_of_2(count));
266 /* slots_num must be power-of-two size, otherwise
267 * get_cmd_index is broken. */
268 BUG_ON(!is_power_of_2(slots_num));
270 q->low_mark = q->n_window / 4;
271 if (q->low_mark < 4)
272 q->low_mark = 4;
274 q->high_mark = q->n_window / 8;
275 if (q->high_mark < 2)
276 q->high_mark = 2;
278 q->write_ptr = q->read_ptr = 0;
280 return 0;
284 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
286 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
287 struct iwl_tx_queue *txq, u32 id)
289 struct pci_dev *dev = priv->pci_dev;
290 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
292 /* Driver private data, only for Tx (not command) queues,
293 * not shared with device. */
294 if (id != IWL_CMD_QUEUE_NUM) {
295 txq->txb = kmalloc(sizeof(txq->txb[0]) *
296 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
297 if (!txq->txb) {
298 IWL_ERR(priv, "kmalloc for auxiliary BD "
299 "structures failed\n");
300 goto error;
302 } else {
303 txq->txb = NULL;
306 /* Circular buffer of transmit frame descriptors (TFDs),
307 * shared with device */
308 txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr);
310 if (!txq->tfds) {
311 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
312 goto error;
314 txq->q.id = id;
316 return 0;
318 error:
319 kfree(txq->txb);
320 txq->txb = NULL;
322 return -ENOMEM;
326 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
328 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
329 int slots_num, u32 txq_id)
331 int i, len;
332 int ret;
333 int actual_slots = slots_num;
336 * Alloc buffer array for commands (Tx or other types of commands).
337 * For the command queue (#4), allocate command space + one big
338 * command for scan, since scan command is very huge; the system will
339 * not have two scans at the same time, so only one is needed.
340 * For normal Tx queues (all other queues), no super-size command
341 * space is needed.
343 if (txq_id == IWL_CMD_QUEUE_NUM)
344 actual_slots++;
346 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
347 GFP_KERNEL);
348 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
349 GFP_KERNEL);
351 if (!txq->meta || !txq->cmd)
352 goto out_free_arrays;
354 len = sizeof(struct iwl_device_cmd);
355 for (i = 0; i < actual_slots; i++) {
356 /* only happens for cmd queue */
357 if (i == slots_num)
358 len += IWL_MAX_SCAN_SIZE;
360 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
361 if (!txq->cmd[i])
362 goto err;
365 /* Alloc driver data array and TFD circular buffer */
366 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
367 if (ret)
368 goto err;
370 txq->need_update = 0;
372 /* aggregation TX queues will get their ID when aggregation begins */
373 if (txq_id <= IWL_TX_FIFO_AC3)
374 txq->swq_id = txq_id;
376 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
377 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
378 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
380 /* Initialize queue's high/low-water marks, and head/tail indexes */
381 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
383 /* Tell device where to find queue */
384 priv->cfg->ops->lib->txq_init(priv, txq);
386 return 0;
387 err:
388 for (i = 0; i < actual_slots; i++)
389 kfree(txq->cmd[i]);
390 out_free_arrays:
391 kfree(txq->meta);
392 kfree(txq->cmd);
394 return -ENOMEM;
396 EXPORT_SYMBOL(iwl_tx_queue_init);
399 * iwl_hw_txq_ctx_free - Free TXQ Context
401 * Destroy all TX DMA queues and structures
403 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
405 int txq_id;
407 /* Tx queues */
408 if (priv->txq)
409 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
410 txq_id++)
411 if (txq_id == IWL_CMD_QUEUE_NUM)
412 iwl_cmd_queue_free(priv);
413 else
414 iwl_tx_queue_free(priv, txq_id);
415 iwl_free_dma_ptr(priv, &priv->kw);
417 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
419 /* free tx queue structure */
420 iwl_free_txq_mem(priv);
422 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
425 * iwl_txq_ctx_reset - Reset TX queue context
426 * Destroys all DMA structures and initialize them again
428 * @param priv
429 * @return error code
431 int iwl_txq_ctx_reset(struct iwl_priv *priv)
433 int ret = 0;
434 int txq_id, slots_num;
435 unsigned long flags;
437 /* Free all tx/cmd queues and keep-warm buffer */
438 iwl_hw_txq_ctx_free(priv);
440 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
441 priv->hw_params.scd_bc_tbls_size);
442 if (ret) {
443 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
444 goto error_bc_tbls;
446 /* Alloc keep-warm buffer */
447 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
448 if (ret) {
449 IWL_ERR(priv, "Keep Warm allocation failed\n");
450 goto error_kw;
453 /* allocate tx queue structure */
454 ret = iwl_alloc_txq_mem(priv);
455 if (ret)
456 goto error;
458 spin_lock_irqsave(&priv->lock, flags);
460 /* Turn off all Tx DMA fifos */
461 priv->cfg->ops->lib->txq_set_sched(priv, 0);
463 /* Tell NIC where to find the "keep warm" buffer */
464 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
466 spin_unlock_irqrestore(&priv->lock, flags);
468 /* Alloc and init all Tx queues, including the command queue (#4) */
469 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
470 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
471 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
472 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
473 txq_id);
474 if (ret) {
475 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
476 goto error;
480 return ret;
482 error:
483 iwl_hw_txq_ctx_free(priv);
484 iwl_free_dma_ptr(priv, &priv->kw);
485 error_kw:
486 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
487 error_bc_tbls:
488 return ret;
492 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
494 void iwl_txq_ctx_stop(struct iwl_priv *priv)
496 int ch;
497 unsigned long flags;
499 /* Turn off all Tx DMA fifos */
500 spin_lock_irqsave(&priv->lock, flags);
502 priv->cfg->ops->lib->txq_set_sched(priv, 0);
504 /* Stop each Tx DMA channel, and wait for it to be idle */
505 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
506 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
507 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
508 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
509 1000);
511 spin_unlock_irqrestore(&priv->lock, flags);
513 /* Deallocate memory for all Tx queues */
514 iwl_hw_txq_ctx_free(priv);
516 EXPORT_SYMBOL(iwl_txq_ctx_stop);
519 * handle build REPLY_TX command notification.
521 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
522 struct iwl_tx_cmd *tx_cmd,
523 struct ieee80211_tx_info *info,
524 struct ieee80211_hdr *hdr,
525 u8 std_id)
527 __le16 fc = hdr->frame_control;
528 __le32 tx_flags = tx_cmd->tx_flags;
530 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
531 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
532 tx_flags |= TX_CMD_FLG_ACK_MSK;
533 if (ieee80211_is_mgmt(fc))
534 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
535 if (ieee80211_is_probe_resp(fc) &&
536 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
537 tx_flags |= TX_CMD_FLG_TSF_MSK;
538 } else {
539 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
540 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
543 if (ieee80211_is_back_req(fc))
544 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
547 tx_cmd->sta_id = std_id;
548 if (ieee80211_has_morefrags(fc))
549 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
551 if (ieee80211_is_data_qos(fc)) {
552 u8 *qc = ieee80211_get_qos_ctl(hdr);
553 tx_cmd->tid_tspec = qc[0] & 0xf;
554 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
555 } else {
556 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
559 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
561 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
562 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
564 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
565 if (ieee80211_is_mgmt(fc)) {
566 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
567 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
568 else
569 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
570 } else {
571 tx_cmd->timeout.pm_frame_timeout = 0;
574 tx_cmd->driver_txop = 0;
575 tx_cmd->tx_flags = tx_flags;
576 tx_cmd->next_frame_len = 0;
579 #define RTS_HCCA_RETRY_LIMIT 3
580 #define RTS_DFAULT_RETRY_LIMIT 60
582 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
583 struct iwl_tx_cmd *tx_cmd,
584 struct ieee80211_tx_info *info,
585 __le16 fc, int is_hcca)
587 u32 rate_flags;
588 int rate_idx;
589 u8 rts_retry_limit;
590 u8 data_retry_limit;
591 u8 rate_plcp;
593 /* Set retry limit on DATA packets and Probe Responses*/
594 if (ieee80211_is_probe_resp(fc))
595 data_retry_limit = 3;
596 else
597 data_retry_limit = IWL_DEFAULT_TX_RETRY;
598 tx_cmd->data_retry_limit = data_retry_limit;
600 /* Set retry limit on RTS packets */
601 rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT :
602 RTS_DFAULT_RETRY_LIMIT;
603 if (data_retry_limit < rts_retry_limit)
604 rts_retry_limit = data_retry_limit;
605 tx_cmd->rts_retry_limit = rts_retry_limit;
607 /* DATA packets will use the uCode station table for rate/antenna
608 * selection */
609 if (ieee80211_is_data(fc)) {
610 tx_cmd->initial_rate_index = 0;
611 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
612 return;
616 * If the current TX rate stored in mac80211 has the MCS bit set, it's
617 * not really a TX rate. Thus, we use the lowest supported rate for
618 * this band. Also use the lowest supported rate if the stored rate
619 * index is invalid.
621 rate_idx = info->control.rates[0].idx;
622 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
623 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
624 rate_idx = rate_lowest_index(&priv->bands[info->band],
625 info->control.sta);
626 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
627 if (info->band == IEEE80211_BAND_5GHZ)
628 rate_idx += IWL_FIRST_OFDM_RATE;
629 /* Get PLCP rate for tx_cmd->rate_n_flags */
630 rate_plcp = iwl_rates[rate_idx].plcp;
631 /* Zero out flags for this packet */
632 rate_flags = 0;
634 /* Set CCK flag as needed */
635 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
636 rate_flags |= RATE_MCS_CCK_MSK;
638 /* Set up RTS and CTS flags for certain packets */
639 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
640 case cpu_to_le16(IEEE80211_STYPE_AUTH):
641 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
642 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
643 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
644 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
645 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
646 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
648 break;
649 default:
650 break;
653 /* Set up antennas */
654 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
655 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
657 /* Set the rate in the TX cmd */
658 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
661 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
662 struct ieee80211_tx_info *info,
663 struct iwl_tx_cmd *tx_cmd,
664 struct sk_buff *skb_frag,
665 int sta_id)
667 struct ieee80211_key_conf *keyconf = info->control.hw_key;
669 switch (keyconf->alg) {
670 case ALG_CCMP:
671 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
672 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
673 if (info->flags & IEEE80211_TX_CTL_AMPDU)
674 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
675 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
676 break;
678 case ALG_TKIP:
679 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
680 ieee80211_get_tkip_key(keyconf, skb_frag,
681 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
682 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
683 break;
685 case ALG_WEP:
686 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
687 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
689 if (keyconf->keylen == WEP_KEY_LEN_128)
690 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
692 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
694 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
695 "with key %d\n", keyconf->keyidx);
696 break;
698 default:
699 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
700 break;
705 * start REPLY_TX command process
707 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
709 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
710 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
711 struct iwl_tx_queue *txq;
712 struct iwl_queue *q;
713 struct iwl_device_cmd *out_cmd;
714 struct iwl_cmd_meta *out_meta;
715 struct iwl_tx_cmd *tx_cmd;
716 int swq_id, txq_id;
717 dma_addr_t phys_addr;
718 dma_addr_t txcmd_phys;
719 dma_addr_t scratch_phys;
720 u16 len, len_org, firstlen, secondlen;
721 u16 seq_number = 0;
722 __le16 fc;
723 u8 hdr_len;
724 u8 sta_id;
725 u8 wait_write_ptr = 0;
726 u8 tid = 0;
727 u8 *qc = NULL;
728 unsigned long flags;
729 int ret;
731 spin_lock_irqsave(&priv->lock, flags);
732 if (iwl_is_rfkill(priv)) {
733 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
734 goto drop_unlock;
737 fc = hdr->frame_control;
739 #ifdef CONFIG_IWLWIFI_DEBUG
740 if (ieee80211_is_auth(fc))
741 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
742 else if (ieee80211_is_assoc_req(fc))
743 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
744 else if (ieee80211_is_reassoc_req(fc))
745 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
746 #endif
748 /* drop all non-injected data frame if we are not associated */
749 if (ieee80211_is_data(fc) &&
750 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
751 (!iwl_is_associated(priv) ||
752 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
753 !priv->assoc_station_added)) {
754 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
755 goto drop_unlock;
758 hdr_len = ieee80211_hdrlen(fc);
760 /* Find (or create) index into station table for destination station */
761 if (info->flags & IEEE80211_TX_CTL_INJECTED)
762 sta_id = priv->hw_params.bcast_sta_id;
763 else
764 sta_id = iwl_get_sta_id(priv, hdr);
765 if (sta_id == IWL_INVALID_STATION) {
766 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
767 hdr->addr1);
768 goto drop_unlock;
771 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
773 txq_id = skb_get_queue_mapping(skb);
774 if (ieee80211_is_data_qos(fc)) {
775 qc = ieee80211_get_qos_ctl(hdr);
776 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
777 if (unlikely(tid >= MAX_TID_COUNT))
778 goto drop_unlock;
779 seq_number = priv->stations[sta_id].tid[tid].seq_number;
780 seq_number &= IEEE80211_SCTL_SEQ;
781 hdr->seq_ctrl = hdr->seq_ctrl &
782 cpu_to_le16(IEEE80211_SCTL_FRAG);
783 hdr->seq_ctrl |= cpu_to_le16(seq_number);
784 seq_number += 0x10;
785 /* aggregation is on for this <sta,tid> */
786 if (info->flags & IEEE80211_TX_CTL_AMPDU)
787 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
790 txq = &priv->txq[txq_id];
791 swq_id = txq->swq_id;
792 q = &txq->q;
794 if (unlikely(iwl_queue_space(q) < q->high_mark))
795 goto drop_unlock;
797 if (ieee80211_is_data_qos(fc))
798 priv->stations[sta_id].tid[tid].tfds_in_queue++;
800 /* Set up driver data for this TFD */
801 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
802 txq->txb[q->write_ptr].skb[0] = skb;
804 /* Set up first empty entry in queue's array of Tx/cmd buffers */
805 out_cmd = txq->cmd[q->write_ptr];
806 out_meta = &txq->meta[q->write_ptr];
807 tx_cmd = &out_cmd->cmd.tx;
808 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
809 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
812 * Set up the Tx-command (not MAC!) header.
813 * Store the chosen Tx queue and TFD index within the sequence field;
814 * after Tx, uCode's Tx response will return this value so driver can
815 * locate the frame within the tx queue and do post-tx processing.
817 out_cmd->hdr.cmd = REPLY_TX;
818 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
819 INDEX_TO_SEQ(q->write_ptr)));
821 /* Copy MAC header from skb into command buffer */
822 memcpy(tx_cmd->hdr, hdr, hdr_len);
825 /* Total # bytes to be transmitted */
826 len = (u16)skb->len;
827 tx_cmd->len = cpu_to_le16(len);
829 if (info->control.hw_key)
830 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
832 /* TODO need this for burst mode later on */
833 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
834 iwl_dbg_log_tx_data_frame(priv, len, hdr);
836 /* set is_hcca to 0; it probably will never be implemented */
837 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0);
839 iwl_update_stats(priv, true, fc, len);
841 * Use the first empty entry in this queue's command buffer array
842 * to contain the Tx command and MAC header concatenated together
843 * (payload data will be in another buffer).
844 * Size of this varies, due to varying MAC header length.
845 * If end is not dword aligned, we'll have 2 extra bytes at the end
846 * of the MAC header (device reads on dword boundaries).
847 * We'll tell device about this padding later.
849 len = sizeof(struct iwl_tx_cmd) +
850 sizeof(struct iwl_cmd_header) + hdr_len;
852 len_org = len;
853 firstlen = len = (len + 3) & ~3;
855 if (len_org != len)
856 len_org = 1;
857 else
858 len_org = 0;
860 /* Tell NIC about any 2-byte padding after MAC header */
861 if (len_org)
862 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
864 /* Physical address of this Tx command's header (not MAC header!),
865 * within command buffer array. */
866 txcmd_phys = pci_map_single(priv->pci_dev,
867 &out_cmd->hdr, len,
868 PCI_DMA_BIDIRECTIONAL);
869 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
870 pci_unmap_len_set(out_meta, len, len);
871 /* Add buffer containing Tx command and MAC(!) header to TFD's
872 * first entry */
873 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
874 txcmd_phys, len, 1, 0);
876 if (!ieee80211_has_morefrags(hdr->frame_control)) {
877 txq->need_update = 1;
878 if (qc)
879 priv->stations[sta_id].tid[tid].seq_number = seq_number;
880 } else {
881 wait_write_ptr = 1;
882 txq->need_update = 0;
885 /* Set up TFD's 2nd entry to point directly to remainder of skb,
886 * if any (802.11 null frames have no payload). */
887 secondlen = len = skb->len - hdr_len;
888 if (len) {
889 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
890 len, PCI_DMA_TODEVICE);
891 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
892 phys_addr, len,
893 0, 0);
896 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
897 offsetof(struct iwl_tx_cmd, scratch);
899 len = sizeof(struct iwl_tx_cmd) +
900 sizeof(struct iwl_cmd_header) + hdr_len;
901 /* take back ownership of DMA buffer to enable update */
902 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
903 len, PCI_DMA_BIDIRECTIONAL);
904 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
905 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
907 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
908 le16_to_cpu(out_cmd->hdr.sequence));
909 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
910 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
911 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
913 /* Set up entry for this TFD in Tx byte-count array */
914 if (info->flags & IEEE80211_TX_CTL_AMPDU)
915 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
916 le16_to_cpu(tx_cmd->len));
918 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
919 len, PCI_DMA_BIDIRECTIONAL);
921 trace_iwlwifi_dev_tx(priv,
922 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
923 sizeof(struct iwl_tfd),
924 &out_cmd->hdr, firstlen,
925 skb->data + hdr_len, secondlen);
927 /* Tell device the write index *just past* this latest filled TFD */
928 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
929 ret = iwl_txq_update_write_ptr(priv, txq);
930 spin_unlock_irqrestore(&priv->lock, flags);
932 if (ret)
933 return ret;
935 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
936 if (wait_write_ptr) {
937 spin_lock_irqsave(&priv->lock, flags);
938 txq->need_update = 1;
939 iwl_txq_update_write_ptr(priv, txq);
940 spin_unlock_irqrestore(&priv->lock, flags);
941 } else {
942 iwl_stop_queue(priv, txq->swq_id);
946 return 0;
948 drop_unlock:
949 spin_unlock_irqrestore(&priv->lock, flags);
950 return -1;
952 EXPORT_SYMBOL(iwl_tx_skb);
954 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
957 * iwl_enqueue_hcmd - enqueue a uCode command
958 * @priv: device private data point
959 * @cmd: a point to the ucode command structure
961 * The function returns < 0 values to indicate the operation is
962 * failed. On success, it turns the index (> 0) of command in the
963 * command queue.
965 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
967 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
968 struct iwl_queue *q = &txq->q;
969 struct iwl_device_cmd *out_cmd;
970 struct iwl_cmd_meta *out_meta;
971 dma_addr_t phys_addr;
972 unsigned long flags;
973 int len, ret;
974 u32 idx;
975 u16 fix_size;
977 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
978 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
980 /* If any of the command structures end up being larger than
981 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
982 * we will need to increase the size of the TFD entries */
983 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
984 !(cmd->flags & CMD_SIZE_HUGE));
986 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
987 IWL_DEBUG_INFO(priv, "Not sending command - RF/CT KILL\n");
988 return -EIO;
991 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
992 IWL_ERR(priv, "No space for Tx\n");
993 if (iwl_within_ct_kill_margin(priv))
994 iwl_tt_enter_ct_kill(priv);
995 else {
996 IWL_ERR(priv, "Restarting adapter due to queue full\n");
997 queue_work(priv->workqueue, &priv->restart);
999 return -ENOSPC;
1002 spin_lock_irqsave(&priv->hcmd_lock, flags);
1004 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
1005 out_cmd = txq->cmd[idx];
1006 out_meta = &txq->meta[idx];
1008 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1009 out_meta->flags = cmd->flags;
1010 if (cmd->flags & CMD_WANT_SKB)
1011 out_meta->source = cmd;
1012 if (cmd->flags & CMD_ASYNC)
1013 out_meta->callback = cmd->callback;
1015 out_cmd->hdr.cmd = cmd->id;
1016 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1018 /* At this point, the out_cmd now has all of the incoming cmd
1019 * information */
1021 out_cmd->hdr.flags = 0;
1022 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1023 INDEX_TO_SEQ(q->write_ptr));
1024 if (cmd->flags & CMD_SIZE_HUGE)
1025 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
1026 len = sizeof(struct iwl_device_cmd);
1027 len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0;
1030 #ifdef CONFIG_IWLWIFI_DEBUG
1031 switch (out_cmd->hdr.cmd) {
1032 case REPLY_TX_LINK_QUALITY_CMD:
1033 case SENSITIVITY_CMD:
1034 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
1035 "%d bytes at %d[%d]:%d\n",
1036 get_cmd_string(out_cmd->hdr.cmd),
1037 out_cmd->hdr.cmd,
1038 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1039 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1040 break;
1041 default:
1042 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
1043 "%d bytes at %d[%d]:%d\n",
1044 get_cmd_string(out_cmd->hdr.cmd),
1045 out_cmd->hdr.cmd,
1046 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1047 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1049 #endif
1050 txq->need_update = 1;
1052 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1053 /* Set up entry in queue's byte count circular buffer */
1054 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1056 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
1057 fix_size, PCI_DMA_BIDIRECTIONAL);
1058 pci_unmap_addr_set(out_meta, mapping, phys_addr);
1059 pci_unmap_len_set(out_meta, len, fix_size);
1061 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
1063 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
1064 phys_addr, fix_size, 1,
1065 U32_PAD(cmd->len));
1067 /* Increment and update queue's write index */
1068 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1069 ret = iwl_txq_update_write_ptr(priv, txq);
1071 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1072 return ret ? ret : idx;
1075 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1077 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1078 struct iwl_queue *q = &txq->q;
1079 struct iwl_tx_info *tx_info;
1080 int nfreed = 0;
1082 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1083 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1084 "is out of range [0-%d] %d %d.\n", txq_id,
1085 index, q->n_bd, q->write_ptr, q->read_ptr);
1086 return 0;
1089 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1090 q->read_ptr != index;
1091 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1093 tx_info = &txq->txb[txq->q.read_ptr];
1094 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1095 tx_info->skb[0] = NULL;
1097 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1098 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1100 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1101 nfreed++;
1103 return nfreed;
1105 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1109 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1111 * When FW advances 'R' index, all entries between old and new 'R' index
1112 * need to be reclaimed. As result, some free space forms. If there is
1113 * enough free space (> low mark), wake the stack that feeds us.
1115 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1116 int idx, int cmd_idx)
1118 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1119 struct iwl_queue *q = &txq->q;
1120 int nfreed = 0;
1122 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1123 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1124 "is out of range [0-%d] %d %d.\n", txq_id,
1125 idx, q->n_bd, q->write_ptr, q->read_ptr);
1126 return;
1129 pci_unmap_single(priv->pci_dev,
1130 pci_unmap_addr(&txq->meta[cmd_idx], mapping),
1131 pci_unmap_len(&txq->meta[cmd_idx], len),
1132 PCI_DMA_BIDIRECTIONAL);
1134 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1135 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1137 if (nfreed++ > 0) {
1138 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1139 q->write_ptr, q->read_ptr);
1140 queue_work(priv->workqueue, &priv->restart);
1147 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1148 * @rxb: Rx buffer to reclaim
1150 * If an Rx buffer has an async callback associated with it the callback
1151 * will be executed. The attached skb (if present) will only be freed
1152 * if the callback returns 1
1154 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1156 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1157 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1158 int txq_id = SEQ_TO_QUEUE(sequence);
1159 int index = SEQ_TO_INDEX(sequence);
1160 int cmd_index;
1161 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1162 struct iwl_device_cmd *cmd;
1163 struct iwl_cmd_meta *meta;
1165 /* If a Tx command is being handled and it isn't in the actual
1166 * command queue then there a command routing bug has been introduced
1167 * in the queue management code. */
1168 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1169 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1170 txq_id, sequence,
1171 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1172 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1173 iwl_print_hex_error(priv, pkt, 32);
1174 return;
1177 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1178 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1179 meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index];
1181 /* Input error checking is done when commands are added to queue. */
1182 if (meta->flags & CMD_WANT_SKB) {
1183 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
1184 rxb->page = NULL;
1185 } else if (meta->callback)
1186 meta->callback(priv, cmd, pkt);
1188 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1190 if (!(meta->flags & CMD_ASYNC)) {
1191 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1192 wake_up_interruptible(&priv->wait_command_queue);
1195 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1198 * Find first available (lowest unused) Tx Queue, mark it "active".
1199 * Called only when finding queue for aggregation.
1200 * Should never return anything < 7, because they should already
1201 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1203 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1205 int txq_id;
1207 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1208 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1209 return txq_id;
1210 return -1;
1213 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1215 int sta_id;
1216 int tx_fifo;
1217 int txq_id;
1218 int ret;
1219 unsigned long flags;
1220 struct iwl_tid_data *tid_data;
1222 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1223 tx_fifo = default_tid_to_tx_fifo[tid];
1224 else
1225 return -EINVAL;
1227 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1228 __func__, ra, tid);
1230 sta_id = iwl_find_station(priv, ra);
1231 if (sta_id == IWL_INVALID_STATION) {
1232 IWL_ERR(priv, "Start AGG on invalid station\n");
1233 return -ENXIO;
1235 if (unlikely(tid >= MAX_TID_COUNT))
1236 return -EINVAL;
1238 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1239 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1240 return -ENXIO;
1243 txq_id = iwl_txq_ctx_activate_free(priv);
1244 if (txq_id == -1) {
1245 IWL_ERR(priv, "No free aggregation queue available\n");
1246 return -ENXIO;
1249 spin_lock_irqsave(&priv->sta_lock, flags);
1250 tid_data = &priv->stations[sta_id].tid[tid];
1251 *ssn = SEQ_TO_SN(tid_data->seq_number);
1252 tid_data->agg.txq_id = txq_id;
1253 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id);
1254 spin_unlock_irqrestore(&priv->sta_lock, flags);
1256 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1257 sta_id, tid, *ssn);
1258 if (ret)
1259 return ret;
1261 if (tid_data->tfds_in_queue == 0) {
1262 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1263 tid_data->agg.state = IWL_AGG_ON;
1264 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1265 } else {
1266 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1267 tid_data->tfds_in_queue);
1268 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1270 return ret;
1272 EXPORT_SYMBOL(iwl_tx_agg_start);
1274 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1276 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1277 struct iwl_tid_data *tid_data;
1278 int ret, write_ptr, read_ptr;
1279 unsigned long flags;
1281 if (!ra) {
1282 IWL_ERR(priv, "ra = NULL\n");
1283 return -EINVAL;
1286 if (unlikely(tid >= MAX_TID_COUNT))
1287 return -EINVAL;
1289 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1290 tx_fifo_id = default_tid_to_tx_fifo[tid];
1291 else
1292 return -EINVAL;
1294 sta_id = iwl_find_station(priv, ra);
1296 if (sta_id == IWL_INVALID_STATION) {
1297 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1298 return -ENXIO;
1301 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1302 IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n");
1304 tid_data = &priv->stations[sta_id].tid[tid];
1305 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1306 txq_id = tid_data->agg.txq_id;
1307 write_ptr = priv->txq[txq_id].q.write_ptr;
1308 read_ptr = priv->txq[txq_id].q.read_ptr;
1310 /* The queue is not empty */
1311 if (write_ptr != read_ptr) {
1312 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1313 priv->stations[sta_id].tid[tid].agg.state =
1314 IWL_EMPTYING_HW_QUEUE_DELBA;
1315 return 0;
1318 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1319 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1321 spin_lock_irqsave(&priv->lock, flags);
1322 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1323 tx_fifo_id);
1324 spin_unlock_irqrestore(&priv->lock, flags);
1326 if (ret)
1327 return ret;
1329 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1331 return 0;
1333 EXPORT_SYMBOL(iwl_tx_agg_stop);
1335 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1337 struct iwl_queue *q = &priv->txq[txq_id].q;
1338 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1339 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1341 switch (priv->stations[sta_id].tid[tid].agg.state) {
1342 case IWL_EMPTYING_HW_QUEUE_DELBA:
1343 /* We are reclaiming the last packet of the */
1344 /* aggregated HW queue */
1345 if ((txq_id == tid_data->agg.txq_id) &&
1346 (q->read_ptr == q->write_ptr)) {
1347 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1348 int tx_fifo = default_tid_to_tx_fifo[tid];
1349 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1350 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1351 ssn, tx_fifo);
1352 tid_data->agg.state = IWL_AGG_OFF;
1353 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1355 break;
1356 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1357 /* We are reclaiming the last packet of the queue */
1358 if (tid_data->tfds_in_queue == 0) {
1359 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1360 tid_data->agg.state = IWL_AGG_ON;
1361 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1363 break;
1365 return 0;
1367 EXPORT_SYMBOL(iwl_txq_check_empty);
1370 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1372 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1373 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1375 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1376 struct iwl_ht_agg *agg,
1377 struct iwl_compressed_ba_resp *ba_resp)
1380 int i, sh, ack;
1381 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1382 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1383 u64 bitmap;
1384 int successes = 0;
1385 struct ieee80211_tx_info *info;
1387 if (unlikely(!agg->wait_for_ba)) {
1388 IWL_ERR(priv, "Received BA when not expected\n");
1389 return -EINVAL;
1392 /* Mark that the expected block-ack response arrived */
1393 agg->wait_for_ba = 0;
1394 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1396 /* Calculate shift to align block-ack bits with our Tx window bits */
1397 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1398 if (sh < 0) /* tbw something is wrong with indices */
1399 sh += 0x100;
1401 /* don't use 64-bit values for now */
1402 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1404 if (agg->frame_count > (64 - sh)) {
1405 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1406 return -1;
1409 /* check for success or failure according to the
1410 * transmitted bitmap and block-ack bitmap */
1411 bitmap &= agg->bitmap;
1413 /* For each frame attempted in aggregation,
1414 * update driver's record of tx frame's status. */
1415 for (i = 0; i < agg->frame_count ; i++) {
1416 ack = bitmap & (1ULL << i);
1417 successes += !!ack;
1418 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1419 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1420 agg->start_idx + i);
1423 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1424 memset(&info->status, 0, sizeof(info->status));
1425 info->flags |= IEEE80211_TX_STAT_ACK;
1426 info->flags |= IEEE80211_TX_STAT_AMPDU;
1427 info->status.ampdu_ack_map = successes;
1428 info->status.ampdu_ack_len = agg->frame_count;
1429 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1431 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1433 return 0;
1437 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1439 * Handles block-acknowledge notification from device, which reports success
1440 * of frames sent via aggregation.
1442 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1443 struct iwl_rx_mem_buffer *rxb)
1445 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1446 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1447 struct iwl_tx_queue *txq = NULL;
1448 struct iwl_ht_agg *agg;
1449 int index;
1450 int sta_id;
1451 int tid;
1453 /* "flow" corresponds to Tx queue */
1454 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1456 /* "ssn" is start of block-ack Tx window, corresponds to index
1457 * (in Tx queue's circular buffer) of first TFD/frame in window */
1458 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1460 if (scd_flow >= priv->hw_params.max_txq_num) {
1461 IWL_ERR(priv,
1462 "BUG_ON scd_flow is bigger than number of queues\n");
1463 return;
1466 txq = &priv->txq[scd_flow];
1467 sta_id = ba_resp->sta_id;
1468 tid = ba_resp->tid;
1469 agg = &priv->stations[sta_id].tid[tid].agg;
1471 /* Find index just before block-ack window */
1472 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1474 /* TODO: Need to get this copy more safely - now good for debug */
1476 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1477 "sta_id = %d\n",
1478 agg->wait_for_ba,
1479 (u8 *) &ba_resp->sta_addr_lo32,
1480 ba_resp->sta_id);
1481 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1482 "%d, scd_ssn = %d\n",
1483 ba_resp->tid,
1484 ba_resp->seq_ctl,
1485 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1486 ba_resp->scd_flow,
1487 ba_resp->scd_ssn);
1488 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1489 agg->start_idx,
1490 (unsigned long long)agg->bitmap);
1492 /* Update driver's record of ACK vs. not for each frame in window */
1493 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1495 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1496 * block-ack window (we assume that they've been successfully
1497 * transmitted ... if not, it's too late anyway). */
1498 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1499 /* calculate mac80211 ampdu sw queue to wake */
1500 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1501 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1503 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1504 priv->mac80211_registered &&
1505 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1506 iwl_wake_queue(priv, txq->swq_id);
1508 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1511 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1513 #ifdef CONFIG_IWLWIFI_DEBUG
1514 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1516 const char *iwl_get_tx_fail_reason(u32 status)
1518 switch (status & TX_STATUS_MSK) {
1519 case TX_STATUS_SUCCESS:
1520 return "SUCCESS";
1521 TX_STATUS_ENTRY(SHORT_LIMIT);
1522 TX_STATUS_ENTRY(LONG_LIMIT);
1523 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1524 TX_STATUS_ENTRY(MGMNT_ABORT);
1525 TX_STATUS_ENTRY(NEXT_FRAG);
1526 TX_STATUS_ENTRY(LIFE_EXPIRE);
1527 TX_STATUS_ENTRY(DEST_PS);
1528 TX_STATUS_ENTRY(ABORTED);
1529 TX_STATUS_ENTRY(BT_RETRY);
1530 TX_STATUS_ENTRY(STA_INVALID);
1531 TX_STATUS_ENTRY(FRAG_DROPPED);
1532 TX_STATUS_ENTRY(TID_DISABLE);
1533 TX_STATUS_ENTRY(FRAME_FLUSHED);
1534 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1535 TX_STATUS_ENTRY(TX_LOCKED);
1536 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1539 return "UNKNOWN";
1541 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1542 #endif /* CONFIG_IWLWIFI_DEBUG */