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iwlwifi: use paged Rx
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
blob17555c7c1d6797e7c5034bc1948f6cc7b9af1e69
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
38
39 #include "iwl-eeprom.h"
40 #include "iwl-dev.h"
41 #include "iwl-core.h"
42 #include "iwl-io.h"
43 #include "iwl-sta.h"
44 #include "iwl-helpers.h"
45 #include "iwl-agn-led.h"
46 #include "iwl-5000-hw.h"
47 #include "iwl-6000-hw.h"
48
49 /* Highest firmware API version supported */
50 #define IWL5000_UCODE_API_MAX 2
51 #define IWL5150_UCODE_API_MAX 2
52
53 /* Lowest firmware API version supported */
54 #define IWL5000_UCODE_API_MIN 1
55 #define IWL5150_UCODE_API_MIN 1
56
57 #define IWL5000_FW_PRE "iwlwifi-5000-"
58 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
59 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
60
61 #define IWL5150_FW_PRE "iwlwifi-5150-"
62 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
63 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
64
65 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
66 IWL_TX_FIFO_AC3,
67 IWL_TX_FIFO_AC2,
68 IWL_TX_FIFO_AC1,
69 IWL_TX_FIFO_AC0,
70 IWL50_CMD_FIFO_NUM,
71 IWL_TX_FIFO_HCCA_1,
72 IWL_TX_FIFO_HCCA_2
73 };
74
75 int iwl5000_apm_init(struct iwl_priv *priv)
76 {
77 int ret = 0;
78
79 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
80 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
81
82 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
83 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
84 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
85
86 /* Set FH wait threshold to maximum (HW error during stress W/A) */
87 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
88
89 /* enable HAP INTA to move device L1a -> L0s */
90 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
91 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
92
93 if (priv->cfg->need_pll_cfg)
94 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
95
96 /* set "initialization complete" bit to move adapter
97 * D0U* --> D0A* state */
98 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
99
100 /* wait for clock stabilization */
101 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
102 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
103 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
104 if (ret < 0) {
105 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
106 return ret;
107 }
108
109 /* enable DMA */
110 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
111
112 udelay(20);
113
114 /* disable L1-Active */
115 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
116 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
117
118 return ret;
119 }
120
121 /* NIC configuration for 5000 series */
122 void iwl5000_nic_config(struct iwl_priv *priv)
123 {
124 unsigned long flags;
125 u16 radio_cfg;
126 u16 lctl;
127
128 spin_lock_irqsave(&priv->lock, flags);
129
130 lctl = iwl_pcie_link_ctl(priv);
131
132 /* HW bug W/A */
133 /* L1-ASPM is enabled by BIOS */
134 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
135 /* L1-APSM enabled: disable L0S */
136 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
137 else
138 /* L1-ASPM disabled: enable L0S */
139 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
140
141 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
142
143 /* write radio config values to register */
144 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
145 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
146 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
147 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
148 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
149
150 /* set CSR_HW_CONFIG_REG for uCode use */
151 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
152 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
153 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
154
155 /* W/A : NIC is stuck in a reset state after Early PCIe power off
156 * (PCIe power is lost before PERST# is asserted),
157 * causing ME FW to lose ownership and not being able to obtain it back.
158 */
159 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
160 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
161 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
162
163
164 spin_unlock_irqrestore(&priv->lock, flags);
165 }
166
167
168 /*
169 * EEPROM
170 */
171 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
172 {
173 u16 offset = 0;
174
175 if ((address & INDIRECT_ADDRESS) == 0)
176 return address;
177
178 switch (address & INDIRECT_TYPE_MSK) {
179 case INDIRECT_HOST:
180 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
181 break;
182 case INDIRECT_GENERAL:
183 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
184 break;
185 case INDIRECT_REGULATORY:
186 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
187 break;
188 case INDIRECT_CALIBRATION:
189 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
190 break;
191 case INDIRECT_PROCESS_ADJST:
192 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
193 break;
194 case INDIRECT_OTHERS:
195 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
196 break;
197 default:
198 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
199 address & INDIRECT_TYPE_MSK);
200 break;
201 }
202
203 /* translate the offset from words to byte */
204 return (address & ADDRESS_MSK) + (offset << 1);
205 }
206
207 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
208 {
209 struct iwl_eeprom_calib_hdr {
210 u8 version;
211 u8 pa_type;
212 u16 voltage;
213 } *hdr;
214
215 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
216 EEPROM_5000_CALIB_ALL);
217 return hdr->version;
218
219 }
220
221 static void iwl5000_gain_computation(struct iwl_priv *priv,
222 u32 average_noise[NUM_RX_CHAINS],
223 u16 min_average_noise_antenna_i,
224 u32 min_average_noise,
225 u8 default_chain)
226 {
227 int i;
228 s32 delta_g;
229 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
230
231 /*
232 * Find Gain Code for the chains based on "default chain"
233 */
234 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
235 if ((data->disconn_array[i])) {
236 data->delta_gain_code[i] = 0;
237 continue;
238 }
239 delta_g = (1000 * ((s32)average_noise[0] -
240 (s32)average_noise[i])) / 1500;
241 /* bound gain by 2 bits value max, 3rd bit is sign */
242 data->delta_gain_code[i] =
243 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
244
245 if (delta_g < 0)
246 /* set negative sign */
247 data->delta_gain_code[i] |= (1 << 2);
248 }
249
250 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
251 data->delta_gain_code[1], data->delta_gain_code[2]);
252
253 if (!data->radio_write) {
254 struct iwl_calib_chain_noise_gain_cmd cmd;
255
256 memset(&cmd, 0, sizeof(cmd));
257
258 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
259 cmd.hdr.first_group = 0;
260 cmd.hdr.groups_num = 1;
261 cmd.hdr.data_valid = 1;
262 cmd.delta_gain_1 = data->delta_gain_code[1];
263 cmd.delta_gain_2 = data->delta_gain_code[2];
264 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
265 sizeof(cmd), &cmd, NULL);
266
267 data->radio_write = 1;
268 data->state = IWL_CHAIN_NOISE_CALIBRATED;
269 }
270
271 data->chain_noise_a = 0;
272 data->chain_noise_b = 0;
273 data->chain_noise_c = 0;
274 data->chain_signal_a = 0;
275 data->chain_signal_b = 0;
276 data->chain_signal_c = 0;
277 data->beacon_count = 0;
278 }
279
280 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
281 {
282 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
283 int ret;
284
285 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
286 struct iwl_calib_chain_noise_reset_cmd cmd;
287 memset(&cmd, 0, sizeof(cmd));
288
289 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
290 cmd.hdr.first_group = 0;
291 cmd.hdr.groups_num = 1;
292 cmd.hdr.data_valid = 1;
293 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
294 sizeof(cmd), &cmd);
295 if (ret)
296 IWL_ERR(priv,
297 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
298 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
299 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
300 }
301 }
302
303 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
304 __le32 *tx_flags)
305 {
306 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
307 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
308 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
309 else
310 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
311 }
312
313 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
314 .min_nrg_cck = 95,
315 .max_nrg_cck = 0, /* not used, set to 0 */
316 .auto_corr_min_ofdm = 90,
317 .auto_corr_min_ofdm_mrc = 170,
318 .auto_corr_min_ofdm_x1 = 120,
319 .auto_corr_min_ofdm_mrc_x1 = 240,
320
321 .auto_corr_max_ofdm = 120,
322 .auto_corr_max_ofdm_mrc = 210,
323 .auto_corr_max_ofdm_x1 = 155,
324 .auto_corr_max_ofdm_mrc_x1 = 290,
325
326 .auto_corr_min_cck = 125,
327 .auto_corr_max_cck = 200,
328 .auto_corr_min_cck_mrc = 170,
329 .auto_corr_max_cck_mrc = 400,
330 .nrg_th_cck = 95,
331 .nrg_th_ofdm = 95,
332
333 .barker_corr_th_min = 190,
334 .barker_corr_th_min_mrc = 390,
335 .nrg_th_cca = 62,
336 };
337
338 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
339 .min_nrg_cck = 95,
340 .max_nrg_cck = 0, /* not used, set to 0 */
341 .auto_corr_min_ofdm = 90,
342 .auto_corr_min_ofdm_mrc = 170,
343 .auto_corr_min_ofdm_x1 = 105,
344 .auto_corr_min_ofdm_mrc_x1 = 220,
345
346 .auto_corr_max_ofdm = 120,
347 .auto_corr_max_ofdm_mrc = 210,
348 /* max = min for performance bug in 5150 DSP */
349 .auto_corr_max_ofdm_x1 = 105,
350 .auto_corr_max_ofdm_mrc_x1 = 220,
351
352 .auto_corr_min_cck = 125,
353 .auto_corr_max_cck = 200,
354 .auto_corr_min_cck_mrc = 170,
355 .auto_corr_max_cck_mrc = 400,
356 .nrg_th_cck = 95,
357 .nrg_th_ofdm = 95,
358
359 .barker_corr_th_min = 190,
360 .barker_corr_th_min_mrc = 390,
361 .nrg_th_cca = 62,
362 };
363
364 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
365 size_t offset)
366 {
367 u32 address = eeprom_indirect_address(priv, offset);
368 BUG_ON(address >= priv->cfg->eeprom_size);
369 return &priv->eeprom[address];
370 }
371
372 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
373 {
374 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
375 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
376 iwl_temp_calib_to_offset(priv);
377
378 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
379 }
380
381 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
382 {
383 /* want Celsius */
384 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
385 }
386
387 /*
388 * Calibration
389 */
390 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
391 {
392 struct iwl_calib_xtal_freq_cmd cmd;
393 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
394
395 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
396 cmd.hdr.first_group = 0;
397 cmd.hdr.groups_num = 1;
398 cmd.hdr.data_valid = 1;
399 cmd.cap_pin1 = (u8)xtal_calib[0];
400 cmd.cap_pin2 = (u8)xtal_calib[1];
401 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
402 (u8 *)&cmd, sizeof(cmd));
403 }
404
405 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
406 {
407 struct iwl_calib_cfg_cmd calib_cfg_cmd;
408 struct iwl_host_cmd cmd = {
409 .id = CALIBRATION_CFG_CMD,
410 .len = sizeof(struct iwl_calib_cfg_cmd),
411 .data = &calib_cfg_cmd,
412 };
413
414 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
415 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
416 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
417 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
418 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
419
420 return iwl_send_cmd(priv, &cmd);
421 }
422
423 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
424 struct iwl_rx_mem_buffer *rxb)
425 {
426 struct iwl_rx_packet *pkt = rxb_addr(rxb);
427 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
428 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
429 int index;
430
431 /* reduce the size of the length field itself */
432 len -= 4;
433
434 /* Define the order in which the results will be sent to the runtime
435 * uCode. iwl_send_calib_results sends them in a row according to their
436 * index. We sort them here */
437 switch (hdr->op_code) {
438 case IWL_PHY_CALIBRATE_DC_CMD:
439 index = IWL_CALIB_DC;
440 break;
441 case IWL_PHY_CALIBRATE_LO_CMD:
442 index = IWL_CALIB_LO;
443 break;
444 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
445 index = IWL_CALIB_TX_IQ;
446 break;
447 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
448 index = IWL_CALIB_TX_IQ_PERD;
449 break;
450 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
451 index = IWL_CALIB_BASE_BAND;
452 break;
453 default:
454 IWL_ERR(priv, "Unknown calibration notification %d\n",
455 hdr->op_code);
456 return;
457 }
458 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
459 }
460
461 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
462 struct iwl_rx_mem_buffer *rxb)
463 {
464 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
465 queue_work(priv->workqueue, &priv->restart);
466 }
467
468 /*
469 * ucode
470 */
471 static int iwl5000_load_section(struct iwl_priv *priv,
472 struct fw_desc *image,
473 u32 dst_addr)
474 {
475 dma_addr_t phy_addr = image->p_addr;
476 u32 byte_cnt = image->len;
477
478 iwl_write_direct32(priv,
479 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
480 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
481
482 iwl_write_direct32(priv,
483 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
484
485 iwl_write_direct32(priv,
486 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
487 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
488
489 iwl_write_direct32(priv,
490 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
491 (iwl_get_dma_hi_addr(phy_addr)
492 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
493
494 iwl_write_direct32(priv,
495 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
496 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
497 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
498 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
499
500 iwl_write_direct32(priv,
501 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
502 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
503 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
504 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
505
506 return 0;
507 }
508
509 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
510 struct fw_desc *inst_image,
511 struct fw_desc *data_image)
512 {
513 int ret = 0;
514
515 ret = iwl5000_load_section(priv, inst_image,
516 IWL50_RTC_INST_LOWER_BOUND);
517 if (ret)
518 return ret;
519
520 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
521 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
522 priv->ucode_write_complete, 5 * HZ);
523 if (ret == -ERESTARTSYS) {
524 IWL_ERR(priv, "Could not load the INST uCode section due "
525 "to interrupt\n");
526 return ret;
527 }
528 if (!ret) {
529 IWL_ERR(priv, "Could not load the INST uCode section\n");
530 return -ETIMEDOUT;
531 }
532
533 priv->ucode_write_complete = 0;
534
535 ret = iwl5000_load_section(
536 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
537 if (ret)
538 return ret;
539
540 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
541
542 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
543 priv->ucode_write_complete, 5 * HZ);
544 if (ret == -ERESTARTSYS) {
545 IWL_ERR(priv, "Could not load the INST uCode section due "
546 "to interrupt\n");
547 return ret;
548 } else if (!ret) {
549 IWL_ERR(priv, "Could not load the DATA uCode section\n");
550 return -ETIMEDOUT;
551 } else
552 ret = 0;
553
554 priv->ucode_write_complete = 0;
555
556 return ret;
557 }
558
559 int iwl5000_load_ucode(struct iwl_priv *priv)
560 {
561 int ret = 0;
562
563 /* check whether init ucode should be loaded, or rather runtime ucode */
564 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
565 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
566 ret = iwl5000_load_given_ucode(priv,
567 &priv->ucode_init, &priv->ucode_init_data);
568 if (!ret) {
569 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
570 priv->ucode_type = UCODE_INIT;
571 }
572 } else {
573 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
574 "Loading runtime ucode...\n");
575 ret = iwl5000_load_given_ucode(priv,
576 &priv->ucode_code, &priv->ucode_data);
577 if (!ret) {
578 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
579 priv->ucode_type = UCODE_RT;
580 }
581 }
582
583 return ret;
584 }
585
586 void iwl5000_init_alive_start(struct iwl_priv *priv)
587 {
588 int ret = 0;
589
590 /* Check alive response for "valid" sign from uCode */
591 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
592 /* We had an error bringing up the hardware, so take it
593 * all the way back down so we can try again */
594 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
595 goto restart;
596 }
597
598 /* initialize uCode was loaded... verify inst image.
599 * This is a paranoid check, because we would not have gotten the
600 * "initialize" alive if code weren't properly loaded. */
601 if (iwl_verify_ucode(priv)) {
602 /* Runtime instruction load was bad;
603 * take it all the way back down so we can try again */
604 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
605 goto restart;
606 }
607
608 iwl_clear_stations_table(priv);
609 ret = priv->cfg->ops->lib->alive_notify(priv);
610 if (ret) {
611 IWL_WARN(priv,
612 "Could not complete ALIVE transition: %d\n", ret);
613 goto restart;
614 }
615
616 iwl5000_send_calib_cfg(priv);
617 return;
618
619 restart:
620 /* real restart (first load init_ucode) */
621 queue_work(priv->workqueue, &priv->restart);
622 }
623
624 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
625 int txq_id, u32 index)
626 {
627 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
628 (index & 0xff) | (txq_id << 8));
629 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
630 }
631
632 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
633 struct iwl_tx_queue *txq,
634 int tx_fifo_id, int scd_retry)
635 {
636 int txq_id = txq->q.id;
637 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
638
639 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
640 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
641 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
642 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
643 IWL50_SCD_QUEUE_STTS_REG_MSK);
644
645 txq->sched_retry = scd_retry;
646
647 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
648 active ? "Activate" : "Deactivate",
649 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
650 }
651
652 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
653 {
654 struct iwl_wimax_coex_cmd coex_cmd;
655
656 memset(&coex_cmd, 0, sizeof(coex_cmd));
657
658 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
659 sizeof(coex_cmd), &coex_cmd);
660 }
661
662 int iwl5000_alive_notify(struct iwl_priv *priv)
663 {
664 u32 a;
665 unsigned long flags;
666 int i, chan;
667 u32 reg_val;
668
669 spin_lock_irqsave(&priv->lock, flags);
670
671 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
672 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
673 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
674 a += 4)
675 iwl_write_targ_mem(priv, a, 0);
676 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
677 a += 4)
678 iwl_write_targ_mem(priv, a, 0);
679 for (; a < priv->scd_base_addr +
680 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
681 iwl_write_targ_mem(priv, a, 0);
682
683 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
684 priv->scd_bc_tbls.dma >> 10);
685
686 /* Enable DMA channel */
687 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
688 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
689 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
690 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
691
692 /* Update FH chicken bits */
693 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
694 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
695 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
696
697 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
698 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
699 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
700
701 /* initiate the queues */
702 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
703 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
704 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
705 iwl_write_targ_mem(priv, priv->scd_base_addr +
706 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
707 iwl_write_targ_mem(priv, priv->scd_base_addr +
708 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
709 sizeof(u32),
710 ((SCD_WIN_SIZE <<
711 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
712 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
713 ((SCD_FRAME_LIMIT <<
714 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
715 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
716 }
717
718 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
719 IWL_MASK(0, priv->hw_params.max_txq_num));
720
721 /* Activate all Tx DMA/FIFO channels */
722 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
723
724 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
725
726 /* map qos queues to fifos one-to-one */
727 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
728 int ac = iwl5000_default_queue_to_tx_fifo[i];
729 iwl_txq_ctx_activate(priv, i);
730 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
731 }
732 /* TODO - need to initialize those FIFOs inside the loop above,
733 * not only mark them as active */
734 iwl_txq_ctx_activate(priv, 4);
735 iwl_txq_ctx_activate(priv, 7);
736 iwl_txq_ctx_activate(priv, 8);
737 iwl_txq_ctx_activate(priv, 9);
738
739 spin_unlock_irqrestore(&priv->lock, flags);
740
741
742 iwl5000_send_wimax_coex(priv);
743
744 iwl5000_set_Xtal_calib(priv);
745 iwl_send_calib_results(priv);
746
747 return 0;
748 }
749
750 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
751 {
752 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
753 priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
754 priv->cfg->num_of_queues =
755 priv->cfg->mod_params->num_of_queues;
756
757 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
758 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
759 priv->hw_params.scd_bc_tbls_size =
760 priv->cfg->num_of_queues *
761 sizeof(struct iwl5000_scd_bc_tbl);
762 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
763 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
764 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
765
766 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
767 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
768
769 priv->hw_params.max_bsm_size = 0;
770 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
771 BIT(IEEE80211_BAND_5GHZ);
772 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
773
774 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
775 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
776 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
777 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
778
779 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
780 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
781
782 /* Set initial sensitivity parameters */
783 /* Set initial calibration set */
784 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
785 case CSR_HW_REV_TYPE_5150:
786 priv->hw_params.sens = &iwl5150_sensitivity;
787 priv->hw_params.calib_init_cfg =
788 BIT(IWL_CALIB_DC) |
789 BIT(IWL_CALIB_LO) |
790 BIT(IWL_CALIB_TX_IQ) |
791 BIT(IWL_CALIB_BASE_BAND);
792
793 break;
794 default:
795 priv->hw_params.sens = &iwl5000_sensitivity;
796 priv->hw_params.calib_init_cfg =
797 BIT(IWL_CALIB_XTAL) |
798 BIT(IWL_CALIB_LO) |
799 BIT(IWL_CALIB_TX_IQ) |
800 BIT(IWL_CALIB_TX_IQ_PERD) |
801 BIT(IWL_CALIB_BASE_BAND);
802 break;
803 }
804
805 return 0;
806 }
807
808 /**
809 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
810 */
811 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
812 struct iwl_tx_queue *txq,
813 u16 byte_cnt)
814 {
815 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
816 int write_ptr = txq->q.write_ptr;
817 int txq_id = txq->q.id;
818 u8 sec_ctl = 0;
819 u8 sta_id = 0;
820 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
821 __le16 bc_ent;
822
823 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
824
825 if (txq_id != IWL_CMD_QUEUE_NUM) {
826 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
827 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
828
829 switch (sec_ctl & TX_CMD_SEC_MSK) {
830 case TX_CMD_SEC_CCM:
831 len += CCMP_MIC_LEN;
832 break;
833 case TX_CMD_SEC_TKIP:
834 len += TKIP_ICV_LEN;
835 break;
836 case TX_CMD_SEC_WEP:
837 len += WEP_IV_LEN + WEP_ICV_LEN;
838 break;
839 }
840 }
841
842 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
843
844 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
845
846 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
847 scd_bc_tbl[txq_id].
848 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
849 }
850
851 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
852 struct iwl_tx_queue *txq)
853 {
854 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
855 int txq_id = txq->q.id;
856 int read_ptr = txq->q.read_ptr;
857 u8 sta_id = 0;
858 __le16 bc_ent;
859
860 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
861
862 if (txq_id != IWL_CMD_QUEUE_NUM)
863 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
864
865 bc_ent = cpu_to_le16(1 | (sta_id << 12));
866 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
867
868 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
869 scd_bc_tbl[txq_id].
870 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
871 }
872
873 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
874 u16 txq_id)
875 {
876 u32 tbl_dw_addr;
877 u32 tbl_dw;
878 u16 scd_q2ratid;
879
880 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
881
882 tbl_dw_addr = priv->scd_base_addr +
883 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
884
885 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
886
887 if (txq_id & 0x1)
888 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
889 else
890 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
891
892 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
893
894 return 0;
895 }
896 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
897 {
898 /* Simply stop the queue, but don't change any configuration;
899 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
900 iwl_write_prph(priv,
901 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
902 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
903 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
904 }
905
906 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
907 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
908 {
909 unsigned long flags;
910 u16 ra_tid;
911
912 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
913 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
914 <= txq_id)) {
915 IWL_WARN(priv,
916 "queue number out of range: %d, must be %d to %d\n",
917 txq_id, IWL50_FIRST_AMPDU_QUEUE,
918 IWL50_FIRST_AMPDU_QUEUE +
919 priv->cfg->num_of_ampdu_queues - 1);
920 return -EINVAL;
921 }
922
923 ra_tid = BUILD_RAxTID(sta_id, tid);
924
925 /* Modify device's station table to Tx this TID */
926 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
927
928 spin_lock_irqsave(&priv->lock, flags);
929
930 /* Stop this Tx queue before configuring it */
931 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
932
933 /* Map receiver-address / traffic-ID to this queue */
934 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
935
936 /* Set this queue as a chain-building queue */
937 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
938
939 /* enable aggregations for the queue */
940 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
941
942 /* Place first TFD at index corresponding to start sequence number.
943 * Assumes that ssn_idx is valid (!= 0xFFF) */
944 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
945 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
946 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
947
948 /* Set up Tx window size and frame limit for this queue */
949 iwl_write_targ_mem(priv, priv->scd_base_addr +
950 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
951 sizeof(u32),
952 ((SCD_WIN_SIZE <<
953 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
954 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
955 ((SCD_FRAME_LIMIT <<
956 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
957 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
958
959 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
960
961 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
962 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
963
964 spin_unlock_irqrestore(&priv->lock, flags);
965
966 return 0;
967 }
968
969 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
970 u16 ssn_idx, u8 tx_fifo)
971 {
972 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
973 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
974 <= txq_id)) {
975 IWL_ERR(priv,
976 "queue number out of range: %d, must be %d to %d\n",
977 txq_id, IWL50_FIRST_AMPDU_QUEUE,
978 IWL50_FIRST_AMPDU_QUEUE +
979 priv->cfg->num_of_ampdu_queues - 1);
980 return -EINVAL;
981 }
982
983 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
984
985 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
986
987 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
988 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
989 /* supposes that ssn_idx is valid (!= 0xFFF) */
990 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
991
992 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
993 iwl_txq_ctx_deactivate(priv, txq_id);
994 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
995
996 return 0;
997 }
998
999 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1000 {
1001 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1002 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1003 memcpy(addsta, cmd, size);
1004 /* resrved in 5000 */
1005 addsta->rate_n_flags = cpu_to_le16(0);
1006 return size;
1007 }
1008
1009
1010 /*
1011 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1012 * must be called under priv->lock and mac access
1013 */
1014 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1015 {
1016 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1017 }
1018
1019
1020 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1021 {
1022 return le32_to_cpup((__le32 *)&tx_resp->status +
1023 tx_resp->frame_count) & MAX_SN;
1024 }
1025
1026 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1027 struct iwl_ht_agg *agg,
1028 struct iwl5000_tx_resp *tx_resp,
1029 int txq_id, u16 start_idx)
1030 {
1031 u16 status;
1032 struct agg_tx_status *frame_status = &tx_resp->status;
1033 struct ieee80211_tx_info *info = NULL;
1034 struct ieee80211_hdr *hdr = NULL;
1035 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1036 int i, sh, idx;
1037 u16 seq;
1038
1039 if (agg->wait_for_ba)
1040 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1041
1042 agg->frame_count = tx_resp->frame_count;
1043 agg->start_idx = start_idx;
1044 agg->rate_n_flags = rate_n_flags;
1045 agg->bitmap = 0;
1046
1047 /* # frames attempted by Tx command */
1048 if (agg->frame_count == 1) {
1049 /* Only one frame was attempted; no block-ack will arrive */
1050 status = le16_to_cpu(frame_status[0].status);
1051 idx = start_idx;
1052
1053 /* FIXME: code repetition */
1054 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1055 agg->frame_count, agg->start_idx, idx);
1056
1057 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1058 info->status.rates[0].count = tx_resp->failure_frame + 1;
1059 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1060 info->flags |= iwl_is_tx_success(status) ?
1061 IEEE80211_TX_STAT_ACK : 0;
1062 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1063
1064 /* FIXME: code repetition end */
1065
1066 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1067 status & 0xff, tx_resp->failure_frame);
1068 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1069
1070 agg->wait_for_ba = 0;
1071 } else {
1072 /* Two or more frames were attempted; expect block-ack */
1073 u64 bitmap = 0;
1074 int start = agg->start_idx;
1075
1076 /* Construct bit-map of pending frames within Tx window */
1077 for (i = 0; i < agg->frame_count; i++) {
1078 u16 sc;
1079 status = le16_to_cpu(frame_status[i].status);
1080 seq = le16_to_cpu(frame_status[i].sequence);
1081 idx = SEQ_TO_INDEX(seq);
1082 txq_id = SEQ_TO_QUEUE(seq);
1083
1084 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1085 AGG_TX_STATE_ABORT_MSK))
1086 continue;
1087
1088 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1089 agg->frame_count, txq_id, idx);
1090
1091 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1092 if (!hdr) {
1093 IWL_ERR(priv,
1094 "BUG_ON idx doesn't point to valid skb"
1095 " idx=%d, txq_id=%d\n", idx, txq_id);
1096 return -1;
1097 }
1098
1099 sc = le16_to_cpu(hdr->seq_ctrl);
1100 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1101 IWL_ERR(priv,
1102 "BUG_ON idx doesn't match seq control"
1103 " idx=%d, seq_idx=%d, seq=%d\n",
1104 idx, SEQ_TO_SN(sc),
1105 hdr->seq_ctrl);
1106 return -1;
1107 }
1108
1109 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1110 i, idx, SEQ_TO_SN(sc));
1111
1112 sh = idx - start;
1113 if (sh > 64) {
1114 sh = (start - idx) + 0xff;
1115 bitmap = bitmap << sh;
1116 sh = 0;
1117 start = idx;
1118 } else if (sh < -64)
1119 sh = 0xff - (start - idx);
1120 else if (sh < 0) {
1121 sh = start - idx;
1122 start = idx;
1123 bitmap = bitmap << sh;
1124 sh = 0;
1125 }
1126 bitmap |= 1ULL << sh;
1127 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1128 start, (unsigned long long)bitmap);
1129 }
1130
1131 agg->bitmap = bitmap;
1132 agg->start_idx = start;
1133 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1134 agg->frame_count, agg->start_idx,
1135 (unsigned long long)agg->bitmap);
1136
1137 if (bitmap)
1138 agg->wait_for_ba = 1;
1139 }
1140 return 0;
1141 }
1142
1143 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1144 struct iwl_rx_mem_buffer *rxb)
1145 {
1146 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1147 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1148 int txq_id = SEQ_TO_QUEUE(sequence);
1149 int index = SEQ_TO_INDEX(sequence);
1150 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1151 struct ieee80211_tx_info *info;
1152 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1153 u32 status = le16_to_cpu(tx_resp->status.status);
1154 int tid;
1155 int sta_id;
1156 int freed;
1157
1158 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1159 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1160 "is out of range [0-%d] %d %d\n", txq_id,
1161 index, txq->q.n_bd, txq->q.write_ptr,
1162 txq->q.read_ptr);
1163 return;
1164 }
1165
1166 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1167 memset(&info->status, 0, sizeof(info->status));
1168
1169 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1170 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1171
1172 if (txq->sched_retry) {
1173 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1174 struct iwl_ht_agg *agg = NULL;
1175
1176 agg = &priv->stations[sta_id].tid[tid].agg;
1177
1178 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1179
1180 /* check if BAR is needed */
1181 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1182 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1183
1184 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1185 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1186 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1187 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1188 scd_ssn , index, txq_id, txq->swq_id);
1189
1190 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1191 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1192
1193 if (priv->mac80211_registered &&
1194 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1195 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1196 if (agg->state == IWL_AGG_OFF)
1197 iwl_wake_queue(priv, txq_id);
1198 else
1199 iwl_wake_queue(priv, txq->swq_id);
1200 }
1201 }
1202 } else {
1203 BUG_ON(txq_id != txq->swq_id);
1204
1205 info->status.rates[0].count = tx_resp->failure_frame + 1;
1206 info->flags |= iwl_is_tx_success(status) ?
1207 IEEE80211_TX_STAT_ACK : 0;
1208 iwl_hwrate_to_tx_control(priv,
1209 le32_to_cpu(tx_resp->rate_n_flags),
1210 info);
1211
1212 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1213 "0x%x retries %d\n",
1214 txq_id,
1215 iwl_get_tx_fail_reason(status), status,
1216 le32_to_cpu(tx_resp->rate_n_flags),
1217 tx_resp->failure_frame);
1218
1219 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1220 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1221 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1222
1223 if (priv->mac80211_registered &&
1224 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1225 iwl_wake_queue(priv, txq_id);
1226 }
1227
1228 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1229 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1230
1231 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1232 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1233 }
1234
1235 /* Currently 5000 is the superset of everything */
1236 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1237 {
1238 return len;
1239 }
1240
1241 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1242 {
1243 /* in 5000 the tx power calibration is done in uCode */
1244 priv->disable_tx_power_cal = 1;
1245 }
1246
1247 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1248 {
1249 /* init calibration handlers */
1250 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1251 iwl5000_rx_calib_result;
1252 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1253 iwl5000_rx_calib_complete;
1254 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1255 }
1256
1257
1258 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1259 {
1260 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1261 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1262 }
1263
1264 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1265 {
1266 int ret = 0;
1267 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1268 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1269 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1270
1271 if ((rxon1->flags == rxon2->flags) &&
1272 (rxon1->filter_flags == rxon2->filter_flags) &&
1273 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1274 (rxon1->ofdm_ht_single_stream_basic_rates ==
1275 rxon2->ofdm_ht_single_stream_basic_rates) &&
1276 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1277 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1278 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1279 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1280 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1281 (rxon1->rx_chain == rxon2->rx_chain) &&
1282 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1283 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1284 return 0;
1285 }
1286
1287 rxon_assoc.flags = priv->staging_rxon.flags;
1288 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1289 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1290 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1291 rxon_assoc.reserved1 = 0;
1292 rxon_assoc.reserved2 = 0;
1293 rxon_assoc.reserved3 = 0;
1294 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1295 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1296 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1297 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1298 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1299 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1300 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1301 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1302
1303 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1304 sizeof(rxon_assoc), &rxon_assoc, NULL);
1305 if (ret)
1306 return ret;
1307
1308 return ret;
1309 }
1310 int iwl5000_send_tx_power(struct iwl_priv *priv)
1311 {
1312 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1313 u8 tx_ant_cfg_cmd;
1314
1315 /* half dBm need to multiply */
1316 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1317 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1318 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1319
1320 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1321 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1322 else
1323 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1324
1325 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1326 sizeof(tx_power_cmd), &tx_power_cmd,
1327 NULL);
1328 }
1329
1330 void iwl5000_temperature(struct iwl_priv *priv)
1331 {
1332 /* store temperature from statistics (in Celsius) */
1333 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1334 iwl_tt_handler(priv);
1335 }
1336
1337 static void iwl5150_temperature(struct iwl_priv *priv)
1338 {
1339 u32 vt = 0;
1340 s32 offset = iwl_temp_calib_to_offset(priv);
1341
1342 vt = le32_to_cpu(priv->statistics.general.temperature);
1343 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1344 /* now vt hold the temperature in Kelvin */
1345 priv->temperature = KELVIN_TO_CELSIUS(vt);
1346 iwl_tt_handler(priv);
1347 }
1348
1349 /* Calc max signal level (dBm) among 3 possible receivers */
1350 int iwl5000_calc_rssi(struct iwl_priv *priv,
1351 struct iwl_rx_phy_res *rx_resp)
1352 {
1353 /* data from PHY/DSP regarding signal strength, etc.,
1354 * contents are always there, not configurable by host
1355 */
1356 struct iwl5000_non_cfg_phy *ncphy =
1357 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1358 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1359 u8 agc;
1360
1361 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1362 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1363
1364 /* Find max rssi among 3 possible receivers.
1365 * These values are measured by the digital signal processor (DSP).
1366 * They should stay fairly constant even as the signal strength varies,
1367 * if the radio's automatic gain control (AGC) is working right.
1368 * AGC value (see below) will provide the "interesting" info.
1369 */
1370 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1371 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1372 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1373 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1374 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1375
1376 max_rssi = max_t(u32, rssi_a, rssi_b);
1377 max_rssi = max_t(u32, max_rssi, rssi_c);
1378
1379 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1380 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1381
1382 /* dBm = max_rssi dB - agc dB - constant.
1383 * Higher AGC (higher radio gain) means lower signal. */
1384 return max_rssi - agc - IWL49_RSSI_OFFSET;
1385 }
1386
1387 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1388 {
1389 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1390 .valid = cpu_to_le32(valid_tx_ant),
1391 };
1392
1393 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1394 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1395 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1396 sizeof(struct iwl_tx_ant_config_cmd),
1397 &tx_ant_cmd);
1398 } else {
1399 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1400 return -EOPNOTSUPP;
1401 }
1402 }
1403
1404
1405 #define IWL5000_UCODE_GET(item) \
1406 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1407 u32 api_ver) \
1408 { \
1409 if (api_ver <= 2) \
1410 return le32_to_cpu(ucode->u.v1.item); \
1411 return le32_to_cpu(ucode->u.v2.item); \
1412 }
1413
1414 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1415 {
1416 if (api_ver <= 2)
1417 return UCODE_HEADER_SIZE(1);
1418 return UCODE_HEADER_SIZE(2);
1419 }
1420
1421 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1422 u32 api_ver)
1423 {
1424 if (api_ver <= 2)
1425 return 0;
1426 return le32_to_cpu(ucode->u.v2.build);
1427 }
1428
1429 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1430 u32 api_ver)
1431 {
1432 if (api_ver <= 2)
1433 return (u8 *) ucode->u.v1.data;
1434 return (u8 *) ucode->u.v2.data;
1435 }
1436
1437 IWL5000_UCODE_GET(inst_size);
1438 IWL5000_UCODE_GET(data_size);
1439 IWL5000_UCODE_GET(init_size);
1440 IWL5000_UCODE_GET(init_data_size);
1441 IWL5000_UCODE_GET(boot_size);
1442
1443 struct iwl_hcmd_ops iwl5000_hcmd = {
1444 .rxon_assoc = iwl5000_send_rxon_assoc,
1445 .commit_rxon = iwl_commit_rxon,
1446 .set_rxon_chain = iwl_set_rxon_chain,
1447 .set_tx_ant = iwl5000_send_tx_ant_config,
1448 };
1449
1450 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1451 .get_hcmd_size = iwl5000_get_hcmd_size,
1452 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1453 .gain_computation = iwl5000_gain_computation,
1454 .chain_noise_reset = iwl5000_chain_noise_reset,
1455 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1456 .calc_rssi = iwl5000_calc_rssi,
1457 };
1458
1459 struct iwl_ucode_ops iwl5000_ucode = {
1460 .get_header_size = iwl5000_ucode_get_header_size,
1461 .get_build = iwl5000_ucode_get_build,
1462 .get_inst_size = iwl5000_ucode_get_inst_size,
1463 .get_data_size = iwl5000_ucode_get_data_size,
1464 .get_init_size = iwl5000_ucode_get_init_size,
1465 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1466 .get_boot_size = iwl5000_ucode_get_boot_size,
1467 .get_data = iwl5000_ucode_get_data,
1468 };
1469
1470 struct iwl_lib_ops iwl5000_lib = {
1471 .set_hw_params = iwl5000_hw_set_hw_params,
1472 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1473 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1474 .txq_set_sched = iwl5000_txq_set_sched,
1475 .txq_agg_enable = iwl5000_txq_agg_enable,
1476 .txq_agg_disable = iwl5000_txq_agg_disable,
1477 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1478 .txq_free_tfd = iwl_hw_txq_free_tfd,
1479 .txq_init = iwl_hw_tx_queue_init,
1480 .rx_handler_setup = iwl5000_rx_handler_setup,
1481 .setup_deferred_work = iwl5000_setup_deferred_work,
1482 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1483 .dump_nic_event_log = iwl_dump_nic_event_log,
1484 .dump_nic_error_log = iwl_dump_nic_error_log,
1485 .load_ucode = iwl5000_load_ucode,
1486 .init_alive_start = iwl5000_init_alive_start,
1487 .alive_notify = iwl5000_alive_notify,
1488 .send_tx_power = iwl5000_send_tx_power,
1489 .update_chain_flags = iwl_update_chain_flags,
1490 .apm_ops = {
1491 .init = iwl5000_apm_init,
1492 .stop = iwl_apm_stop,
1493 .config = iwl5000_nic_config,
1494 .set_pwr_src = iwl_set_pwr_src,
1495 },
1496 .eeprom_ops = {
1497 .regulatory_bands = {
1498 EEPROM_5000_REG_BAND_1_CHANNELS,
1499 EEPROM_5000_REG_BAND_2_CHANNELS,
1500 EEPROM_5000_REG_BAND_3_CHANNELS,
1501 EEPROM_5000_REG_BAND_4_CHANNELS,
1502 EEPROM_5000_REG_BAND_5_CHANNELS,
1503 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1504 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1505 },
1506 .verify_signature = iwlcore_eeprom_verify_signature,
1507 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1508 .release_semaphore = iwlcore_eeprom_release_semaphore,
1509 .calib_version = iwl5000_eeprom_calib_version,
1510 .query_addr = iwl5000_eeprom_query_addr,
1511 },
1512 .post_associate = iwl_post_associate,
1513 .isr = iwl_isr_ict,
1514 .config_ap = iwl_config_ap,
1515 .temp_ops = {
1516 .temperature = iwl5000_temperature,
1517 .set_ct_kill = iwl5000_set_ct_threshold,
1518 },
1519 };
1520
1521 static struct iwl_lib_ops iwl5150_lib = {
1522 .set_hw_params = iwl5000_hw_set_hw_params,
1523 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1524 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1525 .txq_set_sched = iwl5000_txq_set_sched,
1526 .txq_agg_enable = iwl5000_txq_agg_enable,
1527 .txq_agg_disable = iwl5000_txq_agg_disable,
1528 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1529 .txq_free_tfd = iwl_hw_txq_free_tfd,
1530 .txq_init = iwl_hw_tx_queue_init,
1531 .rx_handler_setup = iwl5000_rx_handler_setup,
1532 .setup_deferred_work = iwl5000_setup_deferred_work,
1533 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1534 .dump_nic_event_log = iwl_dump_nic_event_log,
1535 .dump_nic_error_log = iwl_dump_nic_error_log,
1536 .load_ucode = iwl5000_load_ucode,
1537 .init_alive_start = iwl5000_init_alive_start,
1538 .alive_notify = iwl5000_alive_notify,
1539 .send_tx_power = iwl5000_send_tx_power,
1540 .update_chain_flags = iwl_update_chain_flags,
1541 .apm_ops = {
1542 .init = iwl5000_apm_init,
1543 .stop = iwl_apm_stop,
1544 .config = iwl5000_nic_config,
1545 .set_pwr_src = iwl_set_pwr_src,
1546 },
1547 .eeprom_ops = {
1548 .regulatory_bands = {
1549 EEPROM_5000_REG_BAND_1_CHANNELS,
1550 EEPROM_5000_REG_BAND_2_CHANNELS,
1551 EEPROM_5000_REG_BAND_3_CHANNELS,
1552 EEPROM_5000_REG_BAND_4_CHANNELS,
1553 EEPROM_5000_REG_BAND_5_CHANNELS,
1554 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1555 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1556 },
1557 .verify_signature = iwlcore_eeprom_verify_signature,
1558 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1559 .release_semaphore = iwlcore_eeprom_release_semaphore,
1560 .calib_version = iwl5000_eeprom_calib_version,
1561 .query_addr = iwl5000_eeprom_query_addr,
1562 },
1563 .post_associate = iwl_post_associate,
1564 .isr = iwl_isr_ict,
1565 .config_ap = iwl_config_ap,
1566 .temp_ops = {
1567 .temperature = iwl5150_temperature,
1568 .set_ct_kill = iwl5150_set_ct_threshold,
1569 },
1570 };
1571
1572 static struct iwl_ops iwl5000_ops = {
1573 .ucode = &iwl5000_ucode,
1574 .lib = &iwl5000_lib,
1575 .hcmd = &iwl5000_hcmd,
1576 .utils = &iwl5000_hcmd_utils,
1577 .led = &iwlagn_led_ops,
1578 };
1579
1580 static struct iwl_ops iwl5150_ops = {
1581 .ucode = &iwl5000_ucode,
1582 .lib = &iwl5150_lib,
1583 .hcmd = &iwl5000_hcmd,
1584 .utils = &iwl5000_hcmd_utils,
1585 .led = &iwlagn_led_ops,
1586 };
1587
1588 struct iwl_mod_params iwl50_mod_params = {
1589 .amsdu_size_8K = 1,
1590 .restart_fw = 1,
1591 /* the rest are 0 by default */
1592 };
1593
1594
1595 struct iwl_cfg iwl5300_agn_cfg = {
1596 .name = "5300AGN",
1597 .fw_name_pre = IWL5000_FW_PRE,
1598 .ucode_api_max = IWL5000_UCODE_API_MAX,
1599 .ucode_api_min = IWL5000_UCODE_API_MIN,
1600 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1601 .ops = &iwl5000_ops,
1602 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1603 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1604 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1605 .num_of_queues = IWL50_NUM_QUEUES,
1606 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1607 .mod_params = &iwl50_mod_params,
1608 .valid_tx_ant = ANT_ABC,
1609 .valid_rx_ant = ANT_ABC,
1610 .need_pll_cfg = true,
1611 .ht_greenfield_support = true,
1612 .led_compensation = 51,
1613 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1614 };
1615
1616 struct iwl_cfg iwl5100_bg_cfg = {
1617 .name = "5100BG",
1618 .fw_name_pre = IWL5000_FW_PRE,
1619 .ucode_api_max = IWL5000_UCODE_API_MAX,
1620 .ucode_api_min = IWL5000_UCODE_API_MIN,
1621 .sku = IWL_SKU_G,
1622 .ops = &iwl5000_ops,
1623 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1624 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1625 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1626 .num_of_queues = IWL50_NUM_QUEUES,
1627 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1628 .mod_params = &iwl50_mod_params,
1629 .valid_tx_ant = ANT_B,
1630 .valid_rx_ant = ANT_AB,
1631 .need_pll_cfg = true,
1632 .ht_greenfield_support = true,
1633 .led_compensation = 51,
1634 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1635 };
1636
1637 struct iwl_cfg iwl5100_abg_cfg = {
1638 .name = "5100ABG",
1639 .fw_name_pre = IWL5000_FW_PRE,
1640 .ucode_api_max = IWL5000_UCODE_API_MAX,
1641 .ucode_api_min = IWL5000_UCODE_API_MIN,
1642 .sku = IWL_SKU_A|IWL_SKU_G,
1643 .ops = &iwl5000_ops,
1644 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1645 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1646 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1647 .num_of_queues = IWL50_NUM_QUEUES,
1648 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1649 .mod_params = &iwl50_mod_params,
1650 .valid_tx_ant = ANT_B,
1651 .valid_rx_ant = ANT_AB,
1652 .need_pll_cfg = true,
1653 .ht_greenfield_support = true,
1654 .led_compensation = 51,
1655 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1656 };
1657
1658 struct iwl_cfg iwl5100_agn_cfg = {
1659 .name = "5100AGN",
1660 .fw_name_pre = IWL5000_FW_PRE,
1661 .ucode_api_max = IWL5000_UCODE_API_MAX,
1662 .ucode_api_min = IWL5000_UCODE_API_MIN,
1663 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1664 .ops = &iwl5000_ops,
1665 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1666 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1667 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1668 .num_of_queues = IWL50_NUM_QUEUES,
1669 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1670 .mod_params = &iwl50_mod_params,
1671 .valid_tx_ant = ANT_B,
1672 .valid_rx_ant = ANT_AB,
1673 .need_pll_cfg = true,
1674 .ht_greenfield_support = true,
1675 .led_compensation = 51,
1676 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1677 };
1678
1679 struct iwl_cfg iwl5350_agn_cfg = {
1680 .name = "5350AGN",
1681 .fw_name_pre = IWL5000_FW_PRE,
1682 .ucode_api_max = IWL5000_UCODE_API_MAX,
1683 .ucode_api_min = IWL5000_UCODE_API_MIN,
1684 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1685 .ops = &iwl5000_ops,
1686 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1687 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1688 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1689 .num_of_queues = IWL50_NUM_QUEUES,
1690 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1691 .mod_params = &iwl50_mod_params,
1692 .valid_tx_ant = ANT_ABC,
1693 .valid_rx_ant = ANT_ABC,
1694 .need_pll_cfg = true,
1695 .ht_greenfield_support = true,
1696 .led_compensation = 51,
1697 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1698 };
1699
1700 struct iwl_cfg iwl5150_agn_cfg = {
1701 .name = "5150AGN",
1702 .fw_name_pre = IWL5150_FW_PRE,
1703 .ucode_api_max = IWL5150_UCODE_API_MAX,
1704 .ucode_api_min = IWL5150_UCODE_API_MIN,
1705 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1706 .ops = &iwl5150_ops,
1707 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1708 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1709 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1710 .num_of_queues = IWL50_NUM_QUEUES,
1711 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1712 .mod_params = &iwl50_mod_params,
1713 .valid_tx_ant = ANT_A,
1714 .valid_rx_ant = ANT_AB,
1715 .need_pll_cfg = true,
1716 .ht_greenfield_support = true,
1717 .led_compensation = 51,
1718 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1719 };
1720
1721 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1722 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1723
1724 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1725 MODULE_PARM_DESC(swcrypto50,
1726 "using software crypto engine (default 0 [hardware])\n");
1727 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1728 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1729 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1730 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1731 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1732 int, S_IRUGO);
1733 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1734 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1735 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree