arch/arm/mach-tegra/timer.c

   1 /*
   2  * arch/arch/mach-tegra/timer.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/time.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/clockchips.h>
  26 #include <linux/clocksource.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29
  30 #include <asm/mach/time.h>
  31 #include <asm/localtimer.h>
  32 #include <asm/sched_clock.h>
  33
  34 #include <mach/iomap.h>
  35 #include <mach/irqs.h>
  36 #include <mach/suspend.h>
  37
  38 #include "board.h"
  39 #include "clock.h"
  40
  41 #define TIMERUS_CNTR_1US 0x10
  42 #define TIMERUS_USEC_CFG 0x14
  43 #define TIMERUS_CNTR_FREEZE 0x4c
  44
  45 #define TIMER1_BASE 0x0
  46 #define TIMER2_BASE 0x8
  47 #define TIMER3_BASE 0x50
  48 #define TIMER4_BASE 0x58
  49
  50 #define TIMER_PTV 0x0
  51 #define TIMER_PCR 0x4
  52
  53 struct tegra_timer;
  54
  55 static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
  56
  57 #define timer_writel(value, reg) \
  58         __raw_writel(value, (u32)timer_reg_base + (reg))
  59 #define timer_readl(reg) \
  60         __raw_readl((u32)timer_reg_base + (reg))
  61
  62 static int tegra_timer_set_next_event(unsigned long cycles,
  63                                          struct clock_event_device *evt)
  64 {
  65         u32 reg;
  66
  67         reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
  68         timer_writel(reg, TIMER3_BASE + TIMER_PTV);
  69
  70         return 0;
  71 }
  72
  73 static void tegra_timer_set_mode(enum clock_event_mode mode,
  74                                     struct clock_event_device *evt)
  75 {
  76         u32 reg;
  77
  78         timer_writel(0, TIMER3_BASE + TIMER_PTV);
  79
  80         switch (mode) {
  81         case CLOCK_EVT_MODE_PERIODIC:
  82                 reg = 0xC0000000 | ((1000000/HZ)-1);
  83                 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
  84                 break;
  85         case CLOCK_EVT_MODE_ONESHOT:
  86                 break;
  87         case CLOCK_EVT_MODE_UNUSED:
  88         case CLOCK_EVT_MODE_SHUTDOWN:
  89         case CLOCK_EVT_MODE_RESUME:
  90                 break;
  91         }
  92 }
  93
  94 static cycle_t tegra_clocksource_read(struct clocksource *cs)
  95 {
  96         return timer_readl(TIMERUS_CNTR_1US);
  97 }
  98
  99 static struct clock_event_device tegra_clockevent = {
 100         .name           = "timer0",
 101         .rating         = 300,
 102         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 103         .set_next_event = tegra_timer_set_next_event,
 104         .set_mode       = tegra_timer_set_mode,
 105 };
 106
 107 static struct clocksource tegra_clocksource = {
 108         .name   = "timer_us",
 109         .rating = 300,
 110         .read   = tegra_clocksource_read,
 111         .mask   = CLOCKSOURCE_MASK(32),
 112         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 113 };
 114
 115 static DEFINE_CLOCK_DATA(cd);
 116
 117 /*
 118  * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60).
 119  * This gives a resolution of about 1us and a wrap period of about 1h11min.
 120  */
 121 #define SC_MULT         4194304000u
 122 #define SC_SHIFT        22
 123
 124 unsigned long long notrace sched_clock(void)
 125 {
 126         u32 cyc = timer_readl(TIMERUS_CNTR_1US);
 127         return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
 128 }
 129
 130 static void notrace tegra_update_sched_clock(void)
 131 {
 132         u32 cyc = timer_readl(TIMERUS_CNTR_1US);
 133         update_sched_clock(&cd, cyc, (u32)~0);
 134 }
 135
 136 static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
 137 {
 138         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 139         timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
 140         evt->event_handler(evt);
 141         return IRQ_HANDLED;
 142 }
 143
 144 static struct irqaction tegra_timer_irq = {
 145         .name           = "timer0",
 146         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
 147         .handler        = tegra_timer_interrupt,
 148         .dev_id         = &tegra_clockevent,
 149         .irq            = INT_TMR3,
 150 };
 151
 152 static void __init tegra_init_timer(void)
 153 {
 154         unsigned long rate = clk_measure_input_freq();
 155         int ret;
 156
 157 #ifdef CONFIG_HAVE_ARM_TWD
 158         twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
 159 #endif
 160
 161         switch (rate) {
 162         case 12000000:
 163                 timer_writel(0x000b, TIMERUS_USEC_CFG);
 164                 break;
 165         case 13000000:
 166                 timer_writel(0x000c, TIMERUS_USEC_CFG);
 167                 break;
 168         case 19200000:
 169                 timer_writel(0x045f, TIMERUS_USEC_CFG);
 170                 break;
 171         case 26000000:
 172                 timer_writel(0x0019, TIMERUS_USEC_CFG);
 173                 break;
 174         default:
 175                 WARN(1, "Unknown clock rate");
 176         }
 177
 178         init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
 179                                1000000, SC_MULT, SC_SHIFT);
 180
 181         if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
 182                 printk(KERN_ERR "Failed to register clocksource\n");
 183                 BUG();
 184         }
 185
 186         ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
 187         if (ret) {
 188                 printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
 189                 BUG();
 190         }
 191
 192         clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
 193         tegra_clockevent.max_delta_ns =
 194                 clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
 195         tegra_clockevent.min_delta_ns =
 196                 clockevent_delta2ns(0x1, &tegra_clockevent);
 197         tegra_clockevent.cpumask = cpu_all_mask;
 198         tegra_clockevent.irq = tegra_timer_irq.irq;
 199         clockevents_register_device(&tegra_clockevent);
 200
 201         return;
 202 }
 203
 204 struct sys_timer tegra_timer = {
 205         .init = tegra_init_timer,
 206 };