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USB: fsl_udc_core: support device mode of MPC5121E DR USB Controller
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / gadget / fsl_udc_core.c
blob28b3a9f25f3b92383cdeb6954072d7ffc57c060c
1 /*
2 * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Author: Li Yang <leoli@freescale.com>
5 * Jiang Bo <tanya.jiang@freescale.com>
6 *
7 * Description:
8 * Freescale high-speed USB SOC DR module device controller driver.
9 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
10 * The driver is previously named as mpc_udc. Based on bare board
11 * code from Dave Liu and Shlomi Gridish.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19 #undef VERBOSE
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/ioport.h>
24 #include <linux/types.h>
25 #include <linux/errno.h>
26 #include <linux/slab.h>
27 #include <linux/init.h>
28 #include <linux/list.h>
29 #include <linux/interrupt.h>
30 #include <linux/proc_fs.h>
31 #include <linux/mm.h>
32 #include <linux/moduleparam.h>
33 #include <linux/device.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/otg.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/platform_device.h>
39 #include <linux/fsl_devices.h>
40 #include <linux/dmapool.h>
41 #include <linux/delay.h>
42
43 #include <asm/byteorder.h>
44 #include <asm/io.h>
45 #include <asm/system.h>
46 #include <asm/unaligned.h>
47 #include <asm/dma.h>
48 #include <asm/cacheflush.h>
49
50 #include "fsl_usb2_udc.h"
51
52 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
53 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
54 #define DRIVER_VERSION "Apr 20, 2007"
55
56 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
57
58 static const char driver_name[] = "fsl-usb2-udc";
59 static const char driver_desc[] = DRIVER_DESC;
60
61 static struct usb_dr_device *dr_regs;
62 #ifndef CONFIG_ARCH_MXC
63 static struct usb_sys_interface *usb_sys_regs;
64 #endif
65
66 /* it is initialized in probe() */
67 static struct fsl_udc *udc_controller = NULL;
68
69 static const struct usb_endpoint_descriptor
70 fsl_ep0_desc = {
71 .bLength = USB_DT_ENDPOINT_SIZE,
72 .bDescriptorType = USB_DT_ENDPOINT,
73 .bEndpointAddress = 0,
74 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
75 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
76 };
77
78 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
79
80 #ifdef CONFIG_PPC32
81 /*
82 * On some SoCs, the USB controller registers can be big or little endian,
83 * depending on the version of the chip. In order to be able to run the
84 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
85 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
86 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
87 * call through those pointers. Platform code for SoCs that have BE USB
88 * registers should set pdata->big_endian_mmio flag.
89 *
90 * This also applies to controller-to-cpu accessors for the USB descriptors,
91 * since their endianness is also SoC dependant. Platform code for SoCs that
92 * have BE USB descriptors should set pdata->big_endian_desc flag.
93 */
94 static u32 _fsl_readl_be(const unsigned __iomem *p)
95 {
96 return in_be32(p);
97 }
98
99 static u32 _fsl_readl_le(const unsigned __iomem *p)
100 {
101 return in_le32(p);
102 }
103
104 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
105 {
106 out_be32(p, v);
107 }
108
109 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
110 {
111 out_le32(p, v);
112 }
113
114 static u32 (*_fsl_readl)(const unsigned __iomem *p);
115 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
116
117 #define fsl_readl(p) (*_fsl_readl)((p))
118 #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
119
120 static inline u32 cpu_to_hc32(const u32 x)
121 {
122 return udc_controller->pdata->big_endian_desc
123 ? (__force u32)cpu_to_be32(x)
124 : (__force u32)cpu_to_le32(x);
125 }
126
127 static inline u32 hc32_to_cpu(const u32 x)
128 {
129 return udc_controller->pdata->big_endian_desc
130 ? be32_to_cpu((__force __be32)x)
131 : le32_to_cpu((__force __le32)x);
132 }
133 #else /* !CONFIG_PPC32 */
134 #define fsl_readl(addr) readl(addr)
135 #define fsl_writel(val32, addr) writel(val32, addr)
136 #define cpu_to_hc32(x) cpu_to_le32(x)
137 #define hc32_to_cpu(x) le32_to_cpu(x)
138 #endif /* CONFIG_PPC32 */
139
140 /********************************************************************
141 * Internal Used Function
142 ********************************************************************/
143 /*-----------------------------------------------------------------
144 * done() - retire a request; caller blocked irqs
145 * @status : request status to be set, only works when
146 * request is still in progress.
147 *--------------------------------------------------------------*/
148 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
149 {
150 struct fsl_udc *udc = NULL;
151 unsigned char stopped = ep->stopped;
152 struct ep_td_struct *curr_td, *next_td;
153 int j;
154
155 udc = (struct fsl_udc *)ep->udc;
156 /* Removed the req from fsl_ep->queue */
157 list_del_init(&req->queue);
158
159 /* req.status should be set as -EINPROGRESS in ep_queue() */
160 if (req->req.status == -EINPROGRESS)
161 req->req.status = status;
162 else
163 status = req->req.status;
164
165 /* Free dtd for the request */
166 next_td = req->head;
167 for (j = 0; j < req->dtd_count; j++) {
168 curr_td = next_td;
169 if (j != req->dtd_count - 1) {
170 next_td = curr_td->next_td_virt;
171 }
172 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
173 }
174
175 if (req->mapped) {
176 dma_unmap_single(ep->udc->gadget.dev.parent,
177 req->req.dma, req->req.length,
178 ep_is_in(ep)
179 ? DMA_TO_DEVICE
180 : DMA_FROM_DEVICE);
181 req->req.dma = DMA_ADDR_INVALID;
182 req->mapped = 0;
183 } else
184 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
185 req->req.dma, req->req.length,
186 ep_is_in(ep)
187 ? DMA_TO_DEVICE
188 : DMA_FROM_DEVICE);
189
190 if (status && (status != -ESHUTDOWN))
191 VDBG("complete %s req %p stat %d len %u/%u",
192 ep->ep.name, &req->req, status,
193 req->req.actual, req->req.length);
194
195 ep->stopped = 1;
196
197 spin_unlock(&ep->udc->lock);
198 /* complete() is from gadget layer,
199 * eg fsg->bulk_in_complete() */
200 if (req->req.complete)
201 req->req.complete(&ep->ep, &req->req);
202
203 spin_lock(&ep->udc->lock);
204 ep->stopped = stopped;
205 }
206
207 /*-----------------------------------------------------------------
208 * nuke(): delete all requests related to this ep
209 * called with spinlock held
210 *--------------------------------------------------------------*/
211 static void nuke(struct fsl_ep *ep, int status)
212 {
213 ep->stopped = 1;
214
215 /* Flush fifo */
216 fsl_ep_fifo_flush(&ep->ep);
217
218 /* Whether this eq has request linked */
219 while (!list_empty(&ep->queue)) {
220 struct fsl_req *req = NULL;
221
222 req = list_entry(ep->queue.next, struct fsl_req, queue);
223 done(ep, req, status);
224 }
225 }
226
227 /*------------------------------------------------------------------
228 Internal Hardware related function
229 ------------------------------------------------------------------*/
230
231 static int dr_controller_setup(struct fsl_udc *udc)
232 {
233 unsigned int tmp, portctrl;
234 #ifndef CONFIG_ARCH_MXC
235 unsigned int ctrl;
236 #endif
237 unsigned long timeout;
238 #define FSL_UDC_RESET_TIMEOUT 1000
239
240 /* Config PHY interface */
241 portctrl = fsl_readl(&dr_regs->portsc1);
242 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
243 switch (udc->phy_mode) {
244 case FSL_USB2_PHY_ULPI:
245 portctrl |= PORTSCX_PTS_ULPI;
246 break;
247 case FSL_USB2_PHY_UTMI_WIDE:
248 portctrl |= PORTSCX_PTW_16BIT;
249 /* fall through */
250 case FSL_USB2_PHY_UTMI:
251 portctrl |= PORTSCX_PTS_UTMI;
252 break;
253 case FSL_USB2_PHY_SERIAL:
254 portctrl |= PORTSCX_PTS_FSLS;
255 break;
256 default:
257 return -EINVAL;
258 }
259 fsl_writel(portctrl, &dr_regs->portsc1);
260
261 /* Stop and reset the usb controller */
262 tmp = fsl_readl(&dr_regs->usbcmd);
263 tmp &= ~USB_CMD_RUN_STOP;
264 fsl_writel(tmp, &dr_regs->usbcmd);
265
266 tmp = fsl_readl(&dr_regs->usbcmd);
267 tmp |= USB_CMD_CTRL_RESET;
268 fsl_writel(tmp, &dr_regs->usbcmd);
269
270 /* Wait for reset to complete */
271 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
272 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
273 if (time_after(jiffies, timeout)) {
274 ERR("udc reset timeout!\n");
275 return -ETIMEDOUT;
276 }
277 cpu_relax();
278 }
279
280 /* Set the controller as device mode */
281 tmp = fsl_readl(&dr_regs->usbmode);
282 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
283 tmp |= USB_MODE_CTRL_MODE_DEVICE;
284 /* Disable Setup Lockout */
285 tmp |= USB_MODE_SETUP_LOCK_OFF;
286 if (udc->pdata->es)
287 tmp |= USB_MODE_ES;
288 fsl_writel(tmp, &dr_regs->usbmode);
289
290 /* Clear the setup status */
291 fsl_writel(0, &dr_regs->usbsts);
292
293 tmp = udc->ep_qh_dma;
294 tmp &= USB_EP_LIST_ADDRESS_MASK;
295 fsl_writel(tmp, &dr_regs->endpointlistaddr);
296
297 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
298 udc->ep_qh, (int)tmp,
299 fsl_readl(&dr_regs->endpointlistaddr));
300
301 /* Config control enable i/o output, cpu endian register */
302 #ifndef CONFIG_ARCH_MXC
303 if (udc->pdata->have_sysif_regs) {
304 ctrl = __raw_readl(&usb_sys_regs->control);
305 ctrl |= USB_CTRL_IOENB;
306 __raw_writel(ctrl, &usb_sys_regs->control);
307 }
308 #endif
309
310 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
311 /* Turn on cache snooping hardware, since some PowerPC platforms
312 * wholly rely on hardware to deal with cache coherent. */
313
314 if (udc->pdata->have_sysif_regs) {
315 /* Setup Snooping for all the 4GB space */
316 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
317 __raw_writel(tmp, &usb_sys_regs->snoop1);
318 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
319 __raw_writel(tmp, &usb_sys_regs->snoop2);
320 }
321 #endif
322
323 return 0;
324 }
325
326 /* Enable DR irq and set controller to run state */
327 static void dr_controller_run(struct fsl_udc *udc)
328 {
329 u32 temp;
330
331 /* Enable DR irq reg */
332 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
333 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
334 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
335
336 fsl_writel(temp, &dr_regs->usbintr);
337
338 /* Clear stopped bit */
339 udc->stopped = 0;
340
341 /* Set the controller as device mode */
342 temp = fsl_readl(&dr_regs->usbmode);
343 temp |= USB_MODE_CTRL_MODE_DEVICE;
344 fsl_writel(temp, &dr_regs->usbmode);
345
346 /* Set controller to Run */
347 temp = fsl_readl(&dr_regs->usbcmd);
348 temp |= USB_CMD_RUN_STOP;
349 fsl_writel(temp, &dr_regs->usbcmd);
350 }
351
352 static void dr_controller_stop(struct fsl_udc *udc)
353 {
354 unsigned int tmp;
355
356 /* disable all INTR */
357 fsl_writel(0, &dr_regs->usbintr);
358
359 /* Set stopped bit for isr */
360 udc->stopped = 1;
361
362 /* disable IO output */
363 /* usb_sys_regs->control = 0; */
364
365 /* set controller to Stop */
366 tmp = fsl_readl(&dr_regs->usbcmd);
367 tmp &= ~USB_CMD_RUN_STOP;
368 fsl_writel(tmp, &dr_regs->usbcmd);
369 }
370
371 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
372 unsigned char ep_type)
373 {
374 unsigned int tmp_epctrl = 0;
375
376 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
377 if (dir) {
378 if (ep_num)
379 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
380 tmp_epctrl |= EPCTRL_TX_ENABLE;
381 tmp_epctrl |= ((unsigned int)(ep_type)
382 << EPCTRL_TX_EP_TYPE_SHIFT);
383 } else {
384 if (ep_num)
385 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
386 tmp_epctrl |= EPCTRL_RX_ENABLE;
387 tmp_epctrl |= ((unsigned int)(ep_type)
388 << EPCTRL_RX_EP_TYPE_SHIFT);
389 }
390
391 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
392 }
393
394 static void
395 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
396 {
397 u32 tmp_epctrl = 0;
398
399 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
400
401 if (value) {
402 /* set the stall bit */
403 if (dir)
404 tmp_epctrl |= EPCTRL_TX_EP_STALL;
405 else
406 tmp_epctrl |= EPCTRL_RX_EP_STALL;
407 } else {
408 /* clear the stall bit and reset data toggle */
409 if (dir) {
410 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
411 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
412 } else {
413 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
414 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
415 }
416 }
417 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
418 }
419
420 /* Get stall status of a specific ep
421 Return: 0: not stalled; 1:stalled */
422 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
423 {
424 u32 epctrl;
425
426 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
427 if (dir)
428 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
429 else
430 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
431 }
432
433 /********************************************************************
434 Internal Structure Build up functions
435 ********************************************************************/
436
437 /*------------------------------------------------------------------
438 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
439 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
440 * @mult: Mult field
441 ------------------------------------------------------------------*/
442 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
443 unsigned char dir, unsigned char ep_type,
444 unsigned int max_pkt_len,
445 unsigned int zlt, unsigned char mult)
446 {
447 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
448 unsigned int tmp = 0;
449
450 /* set the Endpoint Capabilites in QH */
451 switch (ep_type) {
452 case USB_ENDPOINT_XFER_CONTROL:
453 /* Interrupt On Setup (IOS). for control ep */
454 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
455 | EP_QUEUE_HEAD_IOS;
456 break;
457 case USB_ENDPOINT_XFER_ISOC:
458 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
459 | (mult << EP_QUEUE_HEAD_MULT_POS);
460 break;
461 case USB_ENDPOINT_XFER_BULK:
462 case USB_ENDPOINT_XFER_INT:
463 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
464 break;
465 default:
466 VDBG("error ep type is %d", ep_type);
467 return;
468 }
469 if (zlt)
470 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
471
472 p_QH->max_pkt_length = cpu_to_hc32(tmp);
473 p_QH->next_dtd_ptr = 1;
474 p_QH->size_ioc_int_sts = 0;
475 }
476
477 /* Setup qh structure and ep register for ep0. */
478 static void ep0_setup(struct fsl_udc *udc)
479 {
480 /* the intialization of an ep includes: fields in QH, Regs,
481 * fsl_ep struct */
482 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
483 USB_MAX_CTRL_PAYLOAD, 0, 0);
484 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
485 USB_MAX_CTRL_PAYLOAD, 0, 0);
486 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
487 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
488
489 return;
490
491 }
492
493 /***********************************************************************
494 Endpoint Management Functions
495 ***********************************************************************/
496
497 /*-------------------------------------------------------------------------
498 * when configurations are set, or when interface settings change
499 * for example the do_set_interface() in gadget layer,
500 * the driver will enable or disable the relevant endpoints
501 * ep0 doesn't use this routine. It is always enabled.
502 -------------------------------------------------------------------------*/
503 static int fsl_ep_enable(struct usb_ep *_ep,
504 const struct usb_endpoint_descriptor *desc)
505 {
506 struct fsl_udc *udc = NULL;
507 struct fsl_ep *ep = NULL;
508 unsigned short max = 0;
509 unsigned char mult = 0, zlt;
510 int retval = -EINVAL;
511 unsigned long flags = 0;
512
513 ep = container_of(_ep, struct fsl_ep, ep);
514
515 /* catch various bogus parameters */
516 if (!_ep || !desc || ep->desc
517 || (desc->bDescriptorType != USB_DT_ENDPOINT))
518 return -EINVAL;
519
520 udc = ep->udc;
521
522 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
523 return -ESHUTDOWN;
524
525 max = le16_to_cpu(desc->wMaxPacketSize);
526
527 /* Disable automatic zlp generation. Driver is responsible to indicate
528 * explicitly through req->req.zero. This is needed to enable multi-td
529 * request. */
530 zlt = 1;
531
532 /* Assume the max packet size from gadget is always correct */
533 switch (desc->bmAttributes & 0x03) {
534 case USB_ENDPOINT_XFER_CONTROL:
535 case USB_ENDPOINT_XFER_BULK:
536 case USB_ENDPOINT_XFER_INT:
537 /* mult = 0. Execute N Transactions as demonstrated by
538 * the USB variable length packet protocol where N is
539 * computed using the Maximum Packet Length (dQH) and
540 * the Total Bytes field (dTD) */
541 mult = 0;
542 break;
543 case USB_ENDPOINT_XFER_ISOC:
544 /* Calculate transactions needed for high bandwidth iso */
545 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
546 max = max & 0x7ff; /* bit 0~10 */
547 /* 3 transactions at most */
548 if (mult > 3)
549 goto en_done;
550 break;
551 default:
552 goto en_done;
553 }
554
555 spin_lock_irqsave(&udc->lock, flags);
556 ep->ep.maxpacket = max;
557 ep->desc = desc;
558 ep->stopped = 0;
559
560 /* Controller related setup */
561 /* Init EPx Queue Head (Ep Capabilites field in QH
562 * according to max, zlt, mult) */
563 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
564 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
565 ? USB_SEND : USB_RECV),
566 (unsigned char) (desc->bmAttributes
567 & USB_ENDPOINT_XFERTYPE_MASK),
568 max, zlt, mult);
569
570 /* Init endpoint ctrl register */
571 dr_ep_setup((unsigned char) ep_index(ep),
572 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
573 ? USB_SEND : USB_RECV),
574 (unsigned char) (desc->bmAttributes
575 & USB_ENDPOINT_XFERTYPE_MASK));
576
577 spin_unlock_irqrestore(&udc->lock, flags);
578 retval = 0;
579
580 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
581 ep->desc->bEndpointAddress & 0x0f,
582 (desc->bEndpointAddress & USB_DIR_IN)
583 ? "in" : "out", max);
584 en_done:
585 return retval;
586 }
587
588 /*---------------------------------------------------------------------
589 * @ep : the ep being unconfigured. May not be ep0
590 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
591 *---------------------------------------------------------------------*/
592 static int fsl_ep_disable(struct usb_ep *_ep)
593 {
594 struct fsl_udc *udc = NULL;
595 struct fsl_ep *ep = NULL;
596 unsigned long flags = 0;
597 u32 epctrl;
598 int ep_num;
599
600 ep = container_of(_ep, struct fsl_ep, ep);
601 if (!_ep || !ep->desc) {
602 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
603 return -EINVAL;
604 }
605
606 /* disable ep on controller */
607 ep_num = ep_index(ep);
608 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
609 if (ep_is_in(ep))
610 epctrl &= ~EPCTRL_TX_ENABLE;
611 else
612 epctrl &= ~EPCTRL_RX_ENABLE;
613 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
614
615 udc = (struct fsl_udc *)ep->udc;
616 spin_lock_irqsave(&udc->lock, flags);
617
618 /* nuke all pending requests (does flush) */
619 nuke(ep, -ESHUTDOWN);
620
621 ep->desc = NULL;
622 ep->stopped = 1;
623 spin_unlock_irqrestore(&udc->lock, flags);
624
625 VDBG("disabled %s OK", _ep->name);
626 return 0;
627 }
628
629 /*---------------------------------------------------------------------
630 * allocate a request object used by this endpoint
631 * the main operation is to insert the req->queue to the eq->queue
632 * Returns the request, or null if one could not be allocated
633 *---------------------------------------------------------------------*/
634 static struct usb_request *
635 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
636 {
637 struct fsl_req *req = NULL;
638
639 req = kzalloc(sizeof *req, gfp_flags);
640 if (!req)
641 return NULL;
642
643 req->req.dma = DMA_ADDR_INVALID;
644 INIT_LIST_HEAD(&req->queue);
645
646 return &req->req;
647 }
648
649 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
650 {
651 struct fsl_req *req = NULL;
652
653 req = container_of(_req, struct fsl_req, req);
654
655 if (_req)
656 kfree(req);
657 }
658
659 /*-------------------------------------------------------------------------*/
660 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
661 {
662 int i = ep_index(ep) * 2 + ep_is_in(ep);
663 u32 temp, bitmask, tmp_stat;
664 struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
665
666 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
667 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
668
669 bitmask = ep_is_in(ep)
670 ? (1 << (ep_index(ep) + 16))
671 : (1 << (ep_index(ep)));
672
673 /* check if the pipe is empty */
674 if (!(list_empty(&ep->queue))) {
675 /* Add td to the end */
676 struct fsl_req *lastreq;
677 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
678 lastreq->tail->next_td_ptr =
679 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
680 /* Read prime bit, if 1 goto done */
681 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
682 goto out;
683
684 do {
685 /* Set ATDTW bit in USBCMD */
686 temp = fsl_readl(&dr_regs->usbcmd);
687 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
688
689 /* Read correct status bit */
690 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
691
692 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
693
694 /* Write ATDTW bit to 0 */
695 temp = fsl_readl(&dr_regs->usbcmd);
696 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
697
698 if (tmp_stat)
699 goto out;
700 }
701
702 /* Write dQH next pointer and terminate bit to 0 */
703 temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
704 dQH->next_dtd_ptr = cpu_to_hc32(temp);
705
706 /* Clear active and halt bit */
707 temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
708 | EP_QUEUE_HEAD_STATUS_HALT));
709 dQH->size_ioc_int_sts &= temp;
710
711 /* Ensure that updates to the QH will occur before priming. */
712 wmb();
713
714 /* Prime endpoint by writing 1 to ENDPTPRIME */
715 temp = ep_is_in(ep)
716 ? (1 << (ep_index(ep) + 16))
717 : (1 << (ep_index(ep)));
718 fsl_writel(temp, &dr_regs->endpointprime);
719 out:
720 return;
721 }
722
723 /* Fill in the dTD structure
724 * @req: request that the transfer belongs to
725 * @length: return actually data length of the dTD
726 * @dma: return dma address of the dTD
727 * @is_last: return flag if it is the last dTD of the request
728 * return: pointer to the built dTD */
729 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
730 dma_addr_t *dma, int *is_last)
731 {
732 u32 swap_temp;
733 struct ep_td_struct *dtd;
734
735 /* how big will this transfer be? */
736 *length = min(req->req.length - req->req.actual,
737 (unsigned)EP_MAX_LENGTH_TRANSFER);
738
739 dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
740 if (dtd == NULL)
741 return dtd;
742
743 dtd->td_dma = *dma;
744 /* Clear reserved field */
745 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
746 swap_temp &= ~DTD_RESERVED_FIELDS;
747 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
748
749 /* Init all of buffer page pointers */
750 swap_temp = (u32) (req->req.dma + req->req.actual);
751 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
752 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
753 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
754 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
755 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
756
757 req->req.actual += *length;
758
759 /* zlp is needed if req->req.zero is set */
760 if (req->req.zero) {
761 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
762 *is_last = 1;
763 else
764 *is_last = 0;
765 } else if (req->req.length == req->req.actual)
766 *is_last = 1;
767 else
768 *is_last = 0;
769
770 if ((*is_last) == 0)
771 VDBG("multi-dtd request!");
772 /* Fill in the transfer size; set active bit */
773 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
774
775 /* Enable interrupt for the last dtd of a request */
776 if (*is_last && !req->req.no_interrupt)
777 swap_temp |= DTD_IOC;
778
779 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
780
781 mb();
782
783 VDBG("length = %d address= 0x%x", *length, (int)*dma);
784
785 return dtd;
786 }
787
788 /* Generate dtd chain for a request */
789 static int fsl_req_to_dtd(struct fsl_req *req)
790 {
791 unsigned count;
792 int is_last;
793 int is_first =1;
794 struct ep_td_struct *last_dtd = NULL, *dtd;
795 dma_addr_t dma;
796
797 do {
798 dtd = fsl_build_dtd(req, &count, &dma, &is_last);
799 if (dtd == NULL)
800 return -ENOMEM;
801
802 if (is_first) {
803 is_first = 0;
804 req->head = dtd;
805 } else {
806 last_dtd->next_td_ptr = cpu_to_hc32(dma);
807 last_dtd->next_td_virt = dtd;
808 }
809 last_dtd = dtd;
810
811 req->dtd_count++;
812 } while (!is_last);
813
814 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
815
816 req->tail = dtd;
817
818 return 0;
819 }
820
821 /* queues (submits) an I/O request to an endpoint */
822 static int
823 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
824 {
825 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
826 struct fsl_req *req = container_of(_req, struct fsl_req, req);
827 struct fsl_udc *udc;
828 unsigned long flags;
829
830 /* catch various bogus parameters */
831 if (!_req || !req->req.complete || !req->req.buf
832 || !list_empty(&req->queue)) {
833 VDBG("%s, bad params", __func__);
834 return -EINVAL;
835 }
836 if (unlikely(!_ep || !ep->desc)) {
837 VDBG("%s, bad ep", __func__);
838 return -EINVAL;
839 }
840 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
841 if (req->req.length > ep->ep.maxpacket)
842 return -EMSGSIZE;
843 }
844
845 udc = ep->udc;
846 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
847 return -ESHUTDOWN;
848
849 req->ep = ep;
850
851 /* map virtual address to hardware */
852 if (req->req.dma == DMA_ADDR_INVALID) {
853 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
854 req->req.buf,
855 req->req.length, ep_is_in(ep)
856 ? DMA_TO_DEVICE
857 : DMA_FROM_DEVICE);
858 req->mapped = 1;
859 } else {
860 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
861 req->req.dma, req->req.length,
862 ep_is_in(ep)
863 ? DMA_TO_DEVICE
864 : DMA_FROM_DEVICE);
865 req->mapped = 0;
866 }
867
868 req->req.status = -EINPROGRESS;
869 req->req.actual = 0;
870 req->dtd_count = 0;
871
872 spin_lock_irqsave(&udc->lock, flags);
873
874 /* build dtds and push them to device queue */
875 if (!fsl_req_to_dtd(req)) {
876 fsl_queue_td(ep, req);
877 } else {
878 spin_unlock_irqrestore(&udc->lock, flags);
879 return -ENOMEM;
880 }
881
882 /* Update ep0 state */
883 if ((ep_index(ep) == 0))
884 udc->ep0_state = DATA_STATE_XMIT;
885
886 /* irq handler advances the queue */
887 if (req != NULL)
888 list_add_tail(&req->queue, &ep->queue);
889 spin_unlock_irqrestore(&udc->lock, flags);
890
891 return 0;
892 }
893
894 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
895 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
896 {
897 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
898 struct fsl_req *req;
899 unsigned long flags;
900 int ep_num, stopped, ret = 0;
901 u32 epctrl;
902
903 if (!_ep || !_req)
904 return -EINVAL;
905
906 spin_lock_irqsave(&ep->udc->lock, flags);
907 stopped = ep->stopped;
908
909 /* Stop the ep before we deal with the queue */
910 ep->stopped = 1;
911 ep_num = ep_index(ep);
912 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
913 if (ep_is_in(ep))
914 epctrl &= ~EPCTRL_TX_ENABLE;
915 else
916 epctrl &= ~EPCTRL_RX_ENABLE;
917 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
918
919 /* make sure it's actually queued on this endpoint */
920 list_for_each_entry(req, &ep->queue, queue) {
921 if (&req->req == _req)
922 break;
923 }
924 if (&req->req != _req) {
925 ret = -EINVAL;
926 goto out;
927 }
928
929 /* The request is in progress, or completed but not dequeued */
930 if (ep->queue.next == &req->queue) {
931 _req->status = -ECONNRESET;
932 fsl_ep_fifo_flush(_ep); /* flush current transfer */
933
934 /* The request isn't the last request in this ep queue */
935 if (req->queue.next != &ep->queue) {
936 struct ep_queue_head *qh;
937 struct fsl_req *next_req;
938
939 qh = ep->qh;
940 next_req = list_entry(req->queue.next, struct fsl_req,
941 queue);
942
943 /* Point the QH to the first TD of next request */
944 fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
945 }
946
947 /* The request hasn't been processed, patch up the TD chain */
948 } else {
949 struct fsl_req *prev_req;
950
951 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
952 fsl_writel(fsl_readl(&req->tail->next_td_ptr),
953 &prev_req->tail->next_td_ptr);
954
955 }
956
957 done(ep, req, -ECONNRESET);
958
959 /* Enable EP */
960 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
961 if (ep_is_in(ep))
962 epctrl |= EPCTRL_TX_ENABLE;
963 else
964 epctrl |= EPCTRL_RX_ENABLE;
965 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
966 ep->stopped = stopped;
967
968 spin_unlock_irqrestore(&ep->udc->lock, flags);
969 return ret;
970 }
971
972 /*-------------------------------------------------------------------------*/
973
974 /*-----------------------------------------------------------------
975 * modify the endpoint halt feature
976 * @ep: the non-isochronous endpoint being stalled
977 * @value: 1--set halt 0--clear halt
978 * Returns zero, or a negative error code.
979 *----------------------------------------------------------------*/
980 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
981 {
982 struct fsl_ep *ep = NULL;
983 unsigned long flags = 0;
984 int status = -EOPNOTSUPP; /* operation not supported */
985 unsigned char ep_dir = 0, ep_num = 0;
986 struct fsl_udc *udc = NULL;
987
988 ep = container_of(_ep, struct fsl_ep, ep);
989 udc = ep->udc;
990 if (!_ep || !ep->desc) {
991 status = -EINVAL;
992 goto out;
993 }
994
995 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
996 status = -EOPNOTSUPP;
997 goto out;
998 }
999
1000 /* Attempt to halt IN ep will fail if any transfer requests
1001 * are still queue */
1002 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1003 status = -EAGAIN;
1004 goto out;
1005 }
1006
1007 status = 0;
1008 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1009 ep_num = (unsigned char)(ep_index(ep));
1010 spin_lock_irqsave(&ep->udc->lock, flags);
1011 dr_ep_change_stall(ep_num, ep_dir, value);
1012 spin_unlock_irqrestore(&ep->udc->lock, flags);
1013
1014 if (ep_index(ep) == 0) {
1015 udc->ep0_state = WAIT_FOR_SETUP;
1016 udc->ep0_dir = 0;
1017 }
1018 out:
1019 VDBG(" %s %s halt stat %d", ep->ep.name,
1020 value ? "set" : "clear", status);
1021
1022 return status;
1023 }
1024
1025 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1026 {
1027 struct fsl_ep *ep;
1028 struct fsl_udc *udc;
1029 int size = 0;
1030 u32 bitmask;
1031 struct ep_queue_head *d_qh;
1032
1033 ep = container_of(_ep, struct fsl_ep, ep);
1034 if (!_ep || (!ep->desc && ep_index(ep) != 0))
1035 return -ENODEV;
1036
1037 udc = (struct fsl_udc *)ep->udc;
1038
1039 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1040 return -ESHUTDOWN;
1041
1042 d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
1043
1044 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1045 (1 << (ep_index(ep)));
1046
1047 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1048 size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1049 >> DTD_LENGTH_BIT_POS;
1050
1051 pr_debug("%s %u\n", __func__, size);
1052 return size;
1053 }
1054
1055 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1056 {
1057 struct fsl_ep *ep;
1058 int ep_num, ep_dir;
1059 u32 bits;
1060 unsigned long timeout;
1061 #define FSL_UDC_FLUSH_TIMEOUT 1000
1062
1063 if (!_ep) {
1064 return;
1065 } else {
1066 ep = container_of(_ep, struct fsl_ep, ep);
1067 if (!ep->desc)
1068 return;
1069 }
1070 ep_num = ep_index(ep);
1071 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1072
1073 if (ep_num == 0)
1074 bits = (1 << 16) | 1;
1075 else if (ep_dir == USB_SEND)
1076 bits = 1 << (16 + ep_num);
1077 else
1078 bits = 1 << ep_num;
1079
1080 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1081 do {
1082 fsl_writel(bits, &dr_regs->endptflush);
1083
1084 /* Wait until flush complete */
1085 while (fsl_readl(&dr_regs->endptflush)) {
1086 if (time_after(jiffies, timeout)) {
1087 ERR("ep flush timeout\n");
1088 return;
1089 }
1090 cpu_relax();
1091 }
1092 /* See if we need to flush again */
1093 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1094 }
1095
1096 static struct usb_ep_ops fsl_ep_ops = {
1097 .enable = fsl_ep_enable,
1098 .disable = fsl_ep_disable,
1099
1100 .alloc_request = fsl_alloc_request,
1101 .free_request = fsl_free_request,
1102
1103 .queue = fsl_ep_queue,
1104 .dequeue = fsl_ep_dequeue,
1105
1106 .set_halt = fsl_ep_set_halt,
1107 .fifo_status = fsl_ep_fifo_status,
1108 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1109 };
1110
1111 /*-------------------------------------------------------------------------
1112 Gadget Driver Layer Operations
1113 -------------------------------------------------------------------------*/
1114
1115 /*----------------------------------------------------------------------
1116 * Get the current frame number (from DR frame_index Reg )
1117 *----------------------------------------------------------------------*/
1118 static int fsl_get_frame(struct usb_gadget *gadget)
1119 {
1120 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1121 }
1122
1123 /*-----------------------------------------------------------------------
1124 * Tries to wake up the host connected to this gadget
1125 -----------------------------------------------------------------------*/
1126 static int fsl_wakeup(struct usb_gadget *gadget)
1127 {
1128 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1129 u32 portsc;
1130
1131 /* Remote wakeup feature not enabled by host */
1132 if (!udc->remote_wakeup)
1133 return -ENOTSUPP;
1134
1135 portsc = fsl_readl(&dr_regs->portsc1);
1136 /* not suspended? */
1137 if (!(portsc & PORTSCX_PORT_SUSPEND))
1138 return 0;
1139 /* trigger force resume */
1140 portsc |= PORTSCX_PORT_FORCE_RESUME;
1141 fsl_writel(portsc, &dr_regs->portsc1);
1142 return 0;
1143 }
1144
1145 static int can_pullup(struct fsl_udc *udc)
1146 {
1147 return udc->driver && udc->softconnect && udc->vbus_active;
1148 }
1149
1150 /* Notify controller that VBUS is powered, Called by whatever
1151 detects VBUS sessions */
1152 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1153 {
1154 struct fsl_udc *udc;
1155 unsigned long flags;
1156
1157 udc = container_of(gadget, struct fsl_udc, gadget);
1158 spin_lock_irqsave(&udc->lock, flags);
1159 VDBG("VBUS %s", is_active ? "on" : "off");
1160 udc->vbus_active = (is_active != 0);
1161 if (can_pullup(udc))
1162 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1163 &dr_regs->usbcmd);
1164 else
1165 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1166 &dr_regs->usbcmd);
1167 spin_unlock_irqrestore(&udc->lock, flags);
1168 return 0;
1169 }
1170
1171 /* constrain controller's VBUS power usage
1172 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1173 * reporting how much power the device may consume. For example, this
1174 * could affect how quickly batteries are recharged.
1175 *
1176 * Returns zero on success, else negative errno.
1177 */
1178 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1179 {
1180 struct fsl_udc *udc;
1181
1182 udc = container_of(gadget, struct fsl_udc, gadget);
1183 if (udc->transceiver)
1184 return otg_set_power(udc->transceiver, mA);
1185 return -ENOTSUPP;
1186 }
1187
1188 /* Change Data+ pullup status
1189 * this func is used by usb_gadget_connect/disconnet
1190 */
1191 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1192 {
1193 struct fsl_udc *udc;
1194
1195 udc = container_of(gadget, struct fsl_udc, gadget);
1196 udc->softconnect = (is_on != 0);
1197 if (can_pullup(udc))
1198 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1199 &dr_regs->usbcmd);
1200 else
1201 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1202 &dr_regs->usbcmd);
1203
1204 return 0;
1205 }
1206
1207 /* defined in gadget.h */
1208 static struct usb_gadget_ops fsl_gadget_ops = {
1209 .get_frame = fsl_get_frame,
1210 .wakeup = fsl_wakeup,
1211 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1212 .vbus_session = fsl_vbus_session,
1213 .vbus_draw = fsl_vbus_draw,
1214 .pullup = fsl_pullup,
1215 };
1216
1217 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1218 on new transaction */
1219 static void ep0stall(struct fsl_udc *udc)
1220 {
1221 u32 tmp;
1222
1223 /* must set tx and rx to stall at the same time */
1224 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1225 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1226 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1227 udc->ep0_state = WAIT_FOR_SETUP;
1228 udc->ep0_dir = 0;
1229 }
1230
1231 /* Prime a status phase for ep0 */
1232 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1233 {
1234 struct fsl_req *req = udc->status_req;
1235 struct fsl_ep *ep;
1236
1237 if (direction == EP_DIR_IN)
1238 udc->ep0_dir = USB_DIR_IN;
1239 else
1240 udc->ep0_dir = USB_DIR_OUT;
1241
1242 ep = &udc->eps[0];
1243 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1244
1245 req->ep = ep;
1246 req->req.length = 0;
1247 req->req.status = -EINPROGRESS;
1248 req->req.actual = 0;
1249 req->req.complete = NULL;
1250 req->dtd_count = 0;
1251
1252 if (fsl_req_to_dtd(req) == 0)
1253 fsl_queue_td(ep, req);
1254 else
1255 return -ENOMEM;
1256
1257 list_add_tail(&req->queue, &ep->queue);
1258
1259 return 0;
1260 }
1261
1262 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1263 {
1264 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1265
1266 if (ep->name)
1267 nuke(ep, -ESHUTDOWN);
1268 }
1269
1270 /*
1271 * ch9 Set address
1272 */
1273 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1274 {
1275 /* Save the new address to device struct */
1276 udc->device_address = (u8) value;
1277 /* Update usb state */
1278 udc->usb_state = USB_STATE_ADDRESS;
1279 /* Status phase */
1280 if (ep0_prime_status(udc, EP_DIR_IN))
1281 ep0stall(udc);
1282 }
1283
1284 /*
1285 * ch9 Get status
1286 */
1287 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1288 u16 index, u16 length)
1289 {
1290 u16 tmp = 0; /* Status, cpu endian */
1291 struct fsl_req *req;
1292 struct fsl_ep *ep;
1293
1294 ep = &udc->eps[0];
1295
1296 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1297 /* Get device status */
1298 tmp = 1 << USB_DEVICE_SELF_POWERED;
1299 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1300 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1301 /* Get interface status */
1302 /* We don't have interface information in udc driver */
1303 tmp = 0;
1304 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1305 /* Get endpoint status */
1306 struct fsl_ep *target_ep;
1307
1308 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1309
1310 /* stall if endpoint doesn't exist */
1311 if (!target_ep->desc)
1312 goto stall;
1313 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1314 << USB_ENDPOINT_HALT;
1315 }
1316
1317 udc->ep0_dir = USB_DIR_IN;
1318 /* Borrow the per device status_req */
1319 req = udc->status_req;
1320 /* Fill in the reqest structure */
1321 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1322
1323 /* flush cache for the req buffer */
1324 flush_dcache_range((u32)req->req.buf, (u32)req->req.buf + 8);
1325
1326 req->ep = ep;
1327 req->req.length = 2;
1328 req->req.status = -EINPROGRESS;
1329 req->req.actual = 0;
1330 req->req.complete = NULL;
1331 req->dtd_count = 0;
1332
1333 /* prime the data phase */
1334 if ((fsl_req_to_dtd(req) == 0))
1335 fsl_queue_td(ep, req);
1336 else /* no mem */
1337 goto stall;
1338
1339 list_add_tail(&req->queue, &ep->queue);
1340 udc->ep0_state = DATA_STATE_XMIT;
1341 return;
1342 stall:
1343 ep0stall(udc);
1344 }
1345
1346 static void setup_received_irq(struct fsl_udc *udc,
1347 struct usb_ctrlrequest *setup)
1348 {
1349 u16 wValue = le16_to_cpu(setup->wValue);
1350 u16 wIndex = le16_to_cpu(setup->wIndex);
1351 u16 wLength = le16_to_cpu(setup->wLength);
1352
1353 udc_reset_ep_queue(udc, 0);
1354
1355 /* We process some stardard setup requests here */
1356 switch (setup->bRequest) {
1357 case USB_REQ_GET_STATUS:
1358 /* Data+Status phase from udc */
1359 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1360 != (USB_DIR_IN | USB_TYPE_STANDARD))
1361 break;
1362 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1363 return;
1364
1365 case USB_REQ_SET_ADDRESS:
1366 /* Status phase from udc */
1367 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1368 | USB_RECIP_DEVICE))
1369 break;
1370 ch9setaddress(udc, wValue, wIndex, wLength);
1371 return;
1372
1373 case USB_REQ_CLEAR_FEATURE:
1374 case USB_REQ_SET_FEATURE:
1375 /* Status phase from udc */
1376 {
1377 int rc = -EOPNOTSUPP;
1378 u16 ptc = 0;
1379
1380 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1381 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1382 int pipe = get_pipe_by_windex(wIndex);
1383 struct fsl_ep *ep;
1384
1385 if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1386 break;
1387 ep = get_ep_by_pipe(udc, pipe);
1388
1389 spin_unlock(&udc->lock);
1390 rc = fsl_ep_set_halt(&ep->ep,
1391 (setup->bRequest == USB_REQ_SET_FEATURE)
1392 ? 1 : 0);
1393 spin_lock(&udc->lock);
1394
1395 } else if ((setup->bRequestType & (USB_RECIP_MASK
1396 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1397 | USB_TYPE_STANDARD)) {
1398 /* Note: The driver has not include OTG support yet.
1399 * This will be set when OTG support is added */
1400 if (wValue == USB_DEVICE_TEST_MODE)
1401 ptc = wIndex >> 8;
1402 else if (gadget_is_otg(&udc->gadget)) {
1403 if (setup->bRequest ==
1404 USB_DEVICE_B_HNP_ENABLE)
1405 udc->gadget.b_hnp_enable = 1;
1406 else if (setup->bRequest ==
1407 USB_DEVICE_A_HNP_SUPPORT)
1408 udc->gadget.a_hnp_support = 1;
1409 else if (setup->bRequest ==
1410 USB_DEVICE_A_ALT_HNP_SUPPORT)
1411 udc->gadget.a_alt_hnp_support = 1;
1412 }
1413 rc = 0;
1414 } else
1415 break;
1416
1417 if (rc == 0) {
1418 if (ep0_prime_status(udc, EP_DIR_IN))
1419 ep0stall(udc);
1420 }
1421 if (ptc) {
1422 u32 tmp;
1423
1424 mdelay(10);
1425 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1426 fsl_writel(tmp, &dr_regs->portsc1);
1427 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1428 }
1429
1430 return;
1431 }
1432
1433 default:
1434 break;
1435 }
1436
1437 /* Requests handled by gadget */
1438 if (wLength) {
1439 /* Data phase from gadget, status phase from udc */
1440 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1441 ? USB_DIR_IN : USB_DIR_OUT;
1442 spin_unlock(&udc->lock);
1443 if (udc->driver->setup(&udc->gadget,
1444 &udc->local_setup_buff) < 0)
1445 ep0stall(udc);
1446 spin_lock(&udc->lock);
1447 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1448 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1449 } else {
1450 /* No data phase, IN status from gadget */
1451 udc->ep0_dir = USB_DIR_IN;
1452 spin_unlock(&udc->lock);
1453 if (udc->driver->setup(&udc->gadget,
1454 &udc->local_setup_buff) < 0)
1455 ep0stall(udc);
1456 spin_lock(&udc->lock);
1457 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1458 }
1459 }
1460
1461 /* Process request for Data or Status phase of ep0
1462 * prime status phase if needed */
1463 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1464 struct fsl_req *req)
1465 {
1466 if (udc->usb_state == USB_STATE_ADDRESS) {
1467 /* Set the new address */
1468 u32 new_address = (u32) udc->device_address;
1469 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1470 &dr_regs->deviceaddr);
1471 }
1472
1473 done(ep0, req, 0);
1474
1475 switch (udc->ep0_state) {
1476 case DATA_STATE_XMIT:
1477 /* receive status phase */
1478 if (ep0_prime_status(udc, EP_DIR_OUT))
1479 ep0stall(udc);
1480 break;
1481 case DATA_STATE_RECV:
1482 /* send status phase */
1483 if (ep0_prime_status(udc, EP_DIR_IN))
1484 ep0stall(udc);
1485 break;
1486 case WAIT_FOR_OUT_STATUS:
1487 udc->ep0_state = WAIT_FOR_SETUP;
1488 break;
1489 case WAIT_FOR_SETUP:
1490 ERR("Unexpect ep0 packets\n");
1491 break;
1492 default:
1493 ep0stall(udc);
1494 break;
1495 }
1496 }
1497
1498 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1499 * being corrupted by another incoming setup packet */
1500 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1501 {
1502 u32 temp;
1503 struct ep_queue_head *qh;
1504 struct fsl_usb2_platform_data *pdata = udc->pdata;
1505
1506 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1507
1508 /* Clear bit in ENDPTSETUPSTAT */
1509 temp = fsl_readl(&dr_regs->endptsetupstat);
1510 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1511
1512 /* while a hazard exists when setup package arrives */
1513 do {
1514 /* Set Setup Tripwire */
1515 temp = fsl_readl(&dr_regs->usbcmd);
1516 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1517
1518 /* Copy the setup packet to local buffer */
1519 if (pdata->le_setup_buf) {
1520 u32 *p = (u32 *)buffer_ptr;
1521 u32 *s = (u32 *)qh->setup_buffer;
1522
1523 /* Convert little endian setup buffer to CPU endian */
1524 *p++ = le32_to_cpu(*s++);
1525 *p = le32_to_cpu(*s);
1526 } else {
1527 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1528 }
1529 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1530
1531 /* Clear Setup Tripwire */
1532 temp = fsl_readl(&dr_regs->usbcmd);
1533 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1534 }
1535
1536 /* process-ep_req(): free the completed Tds for this req */
1537 static int process_ep_req(struct fsl_udc *udc, int pipe,
1538 struct fsl_req *curr_req)
1539 {
1540 struct ep_td_struct *curr_td;
1541 int td_complete, actual, remaining_length, j, tmp;
1542 int status = 0;
1543 int errors = 0;
1544 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1545 int direction = pipe % 2;
1546
1547 curr_td = curr_req->head;
1548 td_complete = 0;
1549 actual = curr_req->req.length;
1550
1551 for (j = 0; j < curr_req->dtd_count; j++) {
1552 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1553 & DTD_PACKET_SIZE)
1554 >> DTD_LENGTH_BIT_POS;
1555 actual -= remaining_length;
1556
1557 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1558 if (errors & DTD_ERROR_MASK) {
1559 if (errors & DTD_STATUS_HALTED) {
1560 ERR("dTD error %08x QH=%d\n", errors, pipe);
1561 /* Clear the errors and Halt condition */
1562 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1563 tmp &= ~errors;
1564 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1565 status = -EPIPE;
1566 /* FIXME: continue with next queued TD? */
1567
1568 break;
1569 }
1570 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1571 VDBG("Transfer overflow");
1572 status = -EPROTO;
1573 break;
1574 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1575 VDBG("ISO error");
1576 status = -EILSEQ;
1577 break;
1578 } else
1579 ERR("Unknown error has occurred (0x%x)!\n",
1580 errors);
1581
1582 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1583 & DTD_STATUS_ACTIVE) {
1584 VDBG("Request not complete");
1585 status = REQ_UNCOMPLETE;
1586 return status;
1587 } else if (remaining_length) {
1588 if (direction) {
1589 VDBG("Transmit dTD remaining length not zero");
1590 status = -EPROTO;
1591 break;
1592 } else {
1593 td_complete++;
1594 break;
1595 }
1596 } else {
1597 td_complete++;
1598 VDBG("dTD transmitted successful");
1599 }
1600
1601 if (j != curr_req->dtd_count - 1)
1602 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1603 }
1604
1605 if (status)
1606 return status;
1607
1608 curr_req->req.actual = actual;
1609
1610 return 0;
1611 }
1612
1613 /* Process a DTD completion interrupt */
1614 static void dtd_complete_irq(struct fsl_udc *udc)
1615 {
1616 u32 bit_pos;
1617 int i, ep_num, direction, bit_mask, status;
1618 struct fsl_ep *curr_ep;
1619 struct fsl_req *curr_req, *temp_req;
1620
1621 /* Clear the bits in the register */
1622 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1623 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1624
1625 if (!bit_pos)
1626 return;
1627
1628 for (i = 0; i < udc->max_ep * 2; i++) {
1629 ep_num = i >> 1;
1630 direction = i % 2;
1631
1632 bit_mask = 1 << (ep_num + 16 * direction);
1633
1634 if (!(bit_pos & bit_mask))
1635 continue;
1636
1637 curr_ep = get_ep_by_pipe(udc, i);
1638
1639 /* If the ep is configured */
1640 if (curr_ep->name == NULL) {
1641 WARNING("Invalid EP?");
1642 continue;
1643 }
1644
1645 /* process the req queue until an uncomplete request */
1646 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1647 queue) {
1648 status = process_ep_req(udc, i, curr_req);
1649
1650 VDBG("status of process_ep_req= %d, ep = %d",
1651 status, ep_num);
1652 if (status == REQ_UNCOMPLETE)
1653 break;
1654 /* write back status to req */
1655 curr_req->req.status = status;
1656
1657 if (ep_num == 0) {
1658 ep0_req_complete(udc, curr_ep, curr_req);
1659 break;
1660 } else
1661 done(curr_ep, curr_req, status);
1662 }
1663 }
1664 }
1665
1666 /* Process a port change interrupt */
1667 static void port_change_irq(struct fsl_udc *udc)
1668 {
1669 u32 speed;
1670
1671 /* Bus resetting is finished */
1672 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
1673 /* Get the speed */
1674 speed = (fsl_readl(&dr_regs->portsc1)
1675 & PORTSCX_PORT_SPEED_MASK);
1676 switch (speed) {
1677 case PORTSCX_PORT_SPEED_HIGH:
1678 udc->gadget.speed = USB_SPEED_HIGH;
1679 break;
1680 case PORTSCX_PORT_SPEED_FULL:
1681 udc->gadget.speed = USB_SPEED_FULL;
1682 break;
1683 case PORTSCX_PORT_SPEED_LOW:
1684 udc->gadget.speed = USB_SPEED_LOW;
1685 break;
1686 default:
1687 udc->gadget.speed = USB_SPEED_UNKNOWN;
1688 break;
1689 }
1690 }
1691
1692 /* Update USB state */
1693 if (!udc->resume_state)
1694 udc->usb_state = USB_STATE_DEFAULT;
1695 }
1696
1697 /* Process suspend interrupt */
1698 static void suspend_irq(struct fsl_udc *udc)
1699 {
1700 udc->resume_state = udc->usb_state;
1701 udc->usb_state = USB_STATE_SUSPENDED;
1702
1703 /* report suspend to the driver, serial.c does not support this */
1704 if (udc->driver->suspend)
1705 udc->driver->suspend(&udc->gadget);
1706 }
1707
1708 static void bus_resume(struct fsl_udc *udc)
1709 {
1710 udc->usb_state = udc->resume_state;
1711 udc->resume_state = 0;
1712
1713 /* report resume to the driver, serial.c does not support this */
1714 if (udc->driver->resume)
1715 udc->driver->resume(&udc->gadget);
1716 }
1717
1718 /* Clear up all ep queues */
1719 static int reset_queues(struct fsl_udc *udc)
1720 {
1721 u8 pipe;
1722
1723 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1724 udc_reset_ep_queue(udc, pipe);
1725
1726 /* report disconnect; the driver is already quiesced */
1727 spin_unlock(&udc->lock);
1728 udc->driver->disconnect(&udc->gadget);
1729 spin_lock(&udc->lock);
1730
1731 return 0;
1732 }
1733
1734 /* Process reset interrupt */
1735 static void reset_irq(struct fsl_udc *udc)
1736 {
1737 u32 temp;
1738 unsigned long timeout;
1739
1740 /* Clear the device address */
1741 temp = fsl_readl(&dr_regs->deviceaddr);
1742 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1743
1744 udc->device_address = 0;
1745
1746 /* Clear usb state */
1747 udc->resume_state = 0;
1748 udc->ep0_dir = 0;
1749 udc->ep0_state = WAIT_FOR_SETUP;
1750 udc->remote_wakeup = 0; /* default to 0 on reset */
1751 udc->gadget.b_hnp_enable = 0;
1752 udc->gadget.a_hnp_support = 0;
1753 udc->gadget.a_alt_hnp_support = 0;
1754
1755 /* Clear all the setup token semaphores */
1756 temp = fsl_readl(&dr_regs->endptsetupstat);
1757 fsl_writel(temp, &dr_regs->endptsetupstat);
1758
1759 /* Clear all the endpoint complete status bits */
1760 temp = fsl_readl(&dr_regs->endptcomplete);
1761 fsl_writel(temp, &dr_regs->endptcomplete);
1762
1763 timeout = jiffies + 100;
1764 while (fsl_readl(&dr_regs->endpointprime)) {
1765 /* Wait until all endptprime bits cleared */
1766 if (time_after(jiffies, timeout)) {
1767 ERR("Timeout for reset\n");
1768 break;
1769 }
1770 cpu_relax();
1771 }
1772
1773 /* Write 1s to the flush register */
1774 fsl_writel(0xffffffff, &dr_regs->endptflush);
1775
1776 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1777 VDBG("Bus reset");
1778 /* Reset all the queues, include XD, dTD, EP queue
1779 * head and TR Queue */
1780 reset_queues(udc);
1781 udc->usb_state = USB_STATE_DEFAULT;
1782 } else {
1783 VDBG("Controller reset");
1784 /* initialize usb hw reg except for regs for EP, not
1785 * touch usbintr reg */
1786 dr_controller_setup(udc);
1787
1788 /* Reset all internal used Queues */
1789 reset_queues(udc);
1790
1791 ep0_setup(udc);
1792
1793 /* Enable DR IRQ reg, Set Run bit, change udc state */
1794 dr_controller_run(udc);
1795 udc->usb_state = USB_STATE_ATTACHED;
1796 }
1797 }
1798
1799 /*
1800 * USB device controller interrupt handler
1801 */
1802 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1803 {
1804 struct fsl_udc *udc = _udc;
1805 u32 irq_src;
1806 irqreturn_t status = IRQ_NONE;
1807 unsigned long flags;
1808
1809 /* Disable ISR for OTG host mode */
1810 if (udc->stopped)
1811 return IRQ_NONE;
1812 spin_lock_irqsave(&udc->lock, flags);
1813 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1814 /* Clear notification bits */
1815 fsl_writel(irq_src, &dr_regs->usbsts);
1816
1817 /* VDBG("irq_src [0x%8x]", irq_src); */
1818
1819 /* Need to resume? */
1820 if (udc->usb_state == USB_STATE_SUSPENDED)
1821 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1822 bus_resume(udc);
1823
1824 /* USB Interrupt */
1825 if (irq_src & USB_STS_INT) {
1826 VDBG("Packet int");
1827 /* Setup package, we only support ep0 as control ep */
1828 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1829 tripwire_handler(udc, 0,
1830 (u8 *) (&udc->local_setup_buff));
1831 setup_received_irq(udc, &udc->local_setup_buff);
1832 status = IRQ_HANDLED;
1833 }
1834
1835 /* completion of dtd */
1836 if (fsl_readl(&dr_regs->endptcomplete)) {
1837 dtd_complete_irq(udc);
1838 status = IRQ_HANDLED;
1839 }
1840 }
1841
1842 /* SOF (for ISO transfer) */
1843 if (irq_src & USB_STS_SOF) {
1844 status = IRQ_HANDLED;
1845 }
1846
1847 /* Port Change */
1848 if (irq_src & USB_STS_PORT_CHANGE) {
1849 port_change_irq(udc);
1850 status = IRQ_HANDLED;
1851 }
1852
1853 /* Reset Received */
1854 if (irq_src & USB_STS_RESET) {
1855 reset_irq(udc);
1856 status = IRQ_HANDLED;
1857 }
1858
1859 /* Sleep Enable (Suspend) */
1860 if (irq_src & USB_STS_SUSPEND) {
1861 suspend_irq(udc);
1862 status = IRQ_HANDLED;
1863 }
1864
1865 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1866 VDBG("Error IRQ %x", irq_src);
1867 }
1868
1869 spin_unlock_irqrestore(&udc->lock, flags);
1870 return status;
1871 }
1872
1873 /*----------------------------------------------------------------*
1874 * Hook to gadget drivers
1875 * Called by initialization code of gadget drivers
1876 *----------------------------------------------------------------*/
1877 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1878 int (*bind)(struct usb_gadget *))
1879 {
1880 int retval = -ENODEV;
1881 unsigned long flags = 0;
1882
1883 if (!udc_controller)
1884 return -ENODEV;
1885
1886 if (!driver || (driver->speed != USB_SPEED_FULL
1887 && driver->speed != USB_SPEED_HIGH)
1888 || !bind || !driver->disconnect || !driver->setup)
1889 return -EINVAL;
1890
1891 if (udc_controller->driver)
1892 return -EBUSY;
1893
1894 /* lock is needed but whether should use this lock or another */
1895 spin_lock_irqsave(&udc_controller->lock, flags);
1896
1897 driver->driver.bus = NULL;
1898 /* hook up the driver */
1899 udc_controller->driver = driver;
1900 udc_controller->gadget.dev.driver = &driver->driver;
1901 spin_unlock_irqrestore(&udc_controller->lock, flags);
1902
1903 /* bind udc driver to gadget driver */
1904 retval = bind(&udc_controller->gadget);
1905 if (retval) {
1906 VDBG("bind to %s --> %d", driver->driver.name, retval);
1907 udc_controller->gadget.dev.driver = NULL;
1908 udc_controller->driver = NULL;
1909 goto out;
1910 }
1911
1912 /* Enable DR IRQ reg and Set usbcmd reg Run bit */
1913 dr_controller_run(udc_controller);
1914 udc_controller->usb_state = USB_STATE_ATTACHED;
1915 udc_controller->ep0_state = WAIT_FOR_SETUP;
1916 udc_controller->ep0_dir = 0;
1917 printk(KERN_INFO "%s: bind to driver %s\n",
1918 udc_controller->gadget.name, driver->driver.name);
1919
1920 out:
1921 if (retval)
1922 printk(KERN_WARNING "gadget driver register failed %d\n",
1923 retval);
1924 return retval;
1925 }
1926 EXPORT_SYMBOL(usb_gadget_probe_driver);
1927
1928 /* Disconnect from gadget driver */
1929 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1930 {
1931 struct fsl_ep *loop_ep;
1932 unsigned long flags;
1933
1934 if (!udc_controller)
1935 return -ENODEV;
1936
1937 if (!driver || driver != udc_controller->driver || !driver->unbind)
1938 return -EINVAL;
1939
1940 if (udc_controller->transceiver)
1941 otg_set_peripheral(udc_controller->transceiver, NULL);
1942
1943 /* stop DR, disable intr */
1944 dr_controller_stop(udc_controller);
1945
1946 /* in fact, no needed */
1947 udc_controller->usb_state = USB_STATE_ATTACHED;
1948 udc_controller->ep0_state = WAIT_FOR_SETUP;
1949 udc_controller->ep0_dir = 0;
1950
1951 /* stand operation */
1952 spin_lock_irqsave(&udc_controller->lock, flags);
1953 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
1954 nuke(&udc_controller->eps[0], -ESHUTDOWN);
1955 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
1956 ep.ep_list)
1957 nuke(loop_ep, -ESHUTDOWN);
1958 spin_unlock_irqrestore(&udc_controller->lock, flags);
1959
1960 /* report disconnect; the controller is already quiesced */
1961 driver->disconnect(&udc_controller->gadget);
1962
1963 /* unbind gadget and unhook driver. */
1964 driver->unbind(&udc_controller->gadget);
1965 udc_controller->gadget.dev.driver = NULL;
1966 udc_controller->driver = NULL;
1967
1968 printk(KERN_WARNING "unregistered gadget driver '%s'\n",
1969 driver->driver.name);
1970 return 0;
1971 }
1972 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1973
1974 /*-------------------------------------------------------------------------
1975 PROC File System Support
1976 -------------------------------------------------------------------------*/
1977 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1978
1979 #include <linux/seq_file.h>
1980
1981 static const char proc_filename[] = "driver/fsl_usb2_udc";
1982
1983 static int fsl_proc_read(char *page, char **start, off_t off, int count,
1984 int *eof, void *_dev)
1985 {
1986 char *buf = page;
1987 char *next = buf;
1988 unsigned size = count;
1989 unsigned long flags;
1990 int t, i;
1991 u32 tmp_reg;
1992 struct fsl_ep *ep = NULL;
1993 struct fsl_req *req;
1994
1995 struct fsl_udc *udc = udc_controller;
1996 if (off != 0)
1997 return 0;
1998
1999 spin_lock_irqsave(&udc->lock, flags);
2000
2001 /* ------basic driver information ---- */
2002 t = scnprintf(next, size,
2003 DRIVER_DESC "\n"
2004 "%s version: %s\n"
2005 "Gadget driver: %s\n\n",
2006 driver_name, DRIVER_VERSION,
2007 udc->driver ? udc->driver->driver.name : "(none)");
2008 size -= t;
2009 next += t;
2010
2011 /* ------ DR Registers ----- */
2012 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2013 t = scnprintf(next, size,
2014 "USBCMD reg:\n"
2015 "SetupTW: %d\n"
2016 "Run/Stop: %s\n\n",
2017 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2018 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2019 size -= t;
2020 next += t;
2021
2022 tmp_reg = fsl_readl(&dr_regs->usbsts);
2023 t = scnprintf(next, size,
2024 "USB Status Reg:\n"
2025 "Dr Suspend: %d Reset Received: %d System Error: %s "
2026 "USB Error Interrupt: %s\n\n",
2027 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2028 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2029 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2030 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2031 size -= t;
2032 next += t;
2033
2034 tmp_reg = fsl_readl(&dr_regs->usbintr);
2035 t = scnprintf(next, size,
2036 "USB Intrrupt Enable Reg:\n"
2037 "Sleep Enable: %d SOF Received Enable: %d "
2038 "Reset Enable: %d\n"
2039 "System Error Enable: %d "
2040 "Port Change Dectected Enable: %d\n"
2041 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2042 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2043 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2044 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2045 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2046 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2047 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2048 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2049 size -= t;
2050 next += t;
2051
2052 tmp_reg = fsl_readl(&dr_regs->frindex);
2053 t = scnprintf(next, size,
2054 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2055 (tmp_reg & USB_FRINDEX_MASKS));
2056 size -= t;
2057 next += t;
2058
2059 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2060 t = scnprintf(next, size,
2061 "USB Device Address Reg: Device Addr is 0x%x\n\n",
2062 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2063 size -= t;
2064 next += t;
2065
2066 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2067 t = scnprintf(next, size,
2068 "USB Endpoint List Address Reg: "
2069 "Device Addr is 0x%x\n\n",
2070 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2071 size -= t;
2072 next += t;
2073
2074 tmp_reg = fsl_readl(&dr_regs->portsc1);
2075 t = scnprintf(next, size,
2076 "USB Port Status&Control Reg:\n"
2077 "Port Transceiver Type : %s Port Speed: %s\n"
2078 "PHY Low Power Suspend: %s Port Reset: %s "
2079 "Port Suspend Mode: %s\n"
2080 "Over-current Change: %s "
2081 "Port Enable/Disable Change: %s\n"
2082 "Port Enabled/Disabled: %s "
2083 "Current Connect Status: %s\n\n", ( {
2084 char *s;
2085 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2086 case PORTSCX_PTS_UTMI:
2087 s = "UTMI"; break;
2088 case PORTSCX_PTS_ULPI:
2089 s = "ULPI "; break;
2090 case PORTSCX_PTS_FSLS:
2091 s = "FS/LS Serial"; break;
2092 default:
2093 s = "None"; break;
2094 }
2095 s;} ), ( {
2096 char *s;
2097 switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
2098 case PORTSCX_PORT_SPEED_FULL:
2099 s = "Full Speed"; break;
2100 case PORTSCX_PORT_SPEED_LOW:
2101 s = "Low Speed"; break;
2102 case PORTSCX_PORT_SPEED_HIGH:
2103 s = "High Speed"; break;
2104 default:
2105 s = "Undefined"; break;
2106 }
2107 s;
2108 } ),
2109 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2110 "Normal PHY mode" : "Low power mode",
2111 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2112 "Not in Reset",
2113 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2114 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2115 "No",
2116 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2117 "Not change",
2118 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2119 "Not correct",
2120 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2121 "Attached" : "Not-Att");
2122 size -= t;
2123 next += t;
2124
2125 tmp_reg = fsl_readl(&dr_regs->usbmode);
2126 t = scnprintf(next, size,
2127 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2128 char *s;
2129 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2130 case USB_MODE_CTRL_MODE_IDLE:
2131 s = "Idle"; break;
2132 case USB_MODE_CTRL_MODE_DEVICE:
2133 s = "Device Controller"; break;
2134 case USB_MODE_CTRL_MODE_HOST:
2135 s = "Host Controller"; break;
2136 default:
2137 s = "None"; break;
2138 }
2139 s;
2140 } ));
2141 size -= t;
2142 next += t;
2143
2144 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2145 t = scnprintf(next, size,
2146 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2147 (tmp_reg & EP_SETUP_STATUS_MASK));
2148 size -= t;
2149 next += t;
2150
2151 for (i = 0; i < udc->max_ep / 2; i++) {
2152 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2153 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2154 i, tmp_reg);
2155 size -= t;
2156 next += t;
2157 }
2158 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2159 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2160 size -= t;
2161 next += t;
2162
2163 #ifndef CONFIG_ARCH_MXC
2164 if (udc->pdata->have_sysif_regs) {
2165 tmp_reg = usb_sys_regs->snoop1;
2166 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2167 size -= t;
2168 next += t;
2169
2170 tmp_reg = usb_sys_regs->control;
2171 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2172 tmp_reg);
2173 size -= t;
2174 next += t;
2175 }
2176 #endif
2177
2178 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2179 ep = &udc->eps[0];
2180 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2181 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2182 size -= t;
2183 next += t;
2184
2185 if (list_empty(&ep->queue)) {
2186 t = scnprintf(next, size, "its req queue is empty\n\n");
2187 size -= t;
2188 next += t;
2189 } else {
2190 list_for_each_entry(req, &ep->queue, queue) {
2191 t = scnprintf(next, size,
2192 "req %p actual 0x%x length 0x%x buf %p\n",
2193 &req->req, req->req.actual,
2194 req->req.length, req->req.buf);
2195 size -= t;
2196 next += t;
2197 }
2198 }
2199 /* other gadget->eplist ep */
2200 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2201 if (ep->desc) {
2202 t = scnprintf(next, size,
2203 "\nFor %s Maxpkt is 0x%x "
2204 "index is 0x%x\n",
2205 ep->ep.name, ep_maxpacket(ep),
2206 ep_index(ep));
2207 size -= t;
2208 next += t;
2209
2210 if (list_empty(&ep->queue)) {
2211 t = scnprintf(next, size,
2212 "its req queue is empty\n\n");
2213 size -= t;
2214 next += t;
2215 } else {
2216 list_for_each_entry(req, &ep->queue, queue) {
2217 t = scnprintf(next, size,
2218 "req %p actual 0x%x length "
2219 "0x%x buf %p\n",
2220 &req->req, req->req.actual,
2221 req->req.length, req->req.buf);
2222 size -= t;
2223 next += t;
2224 } /* end for each_entry of ep req */
2225 } /* end for else */
2226 } /* end for if(ep->queue) */
2227 } /* end (ep->desc) */
2228
2229 spin_unlock_irqrestore(&udc->lock, flags);
2230
2231 *eof = 1;
2232 return count - size;
2233 }
2234
2235 #define create_proc_file() create_proc_read_entry(proc_filename, \
2236 0, NULL, fsl_proc_read, NULL)
2237
2238 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2239
2240 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2241
2242 #define create_proc_file() do {} while (0)
2243 #define remove_proc_file() do {} while (0)
2244
2245 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2246
2247 /*-------------------------------------------------------------------------*/
2248
2249 /* Release udc structures */
2250 static void fsl_udc_release(struct device *dev)
2251 {
2252 complete(udc_controller->done);
2253 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2254 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2255 kfree(udc_controller);
2256 }
2257
2258 /******************************************************************
2259 Internal structure setup functions
2260 *******************************************************************/
2261 /*------------------------------------------------------------------
2262 * init resource for globle controller
2263 * Return the udc handle on success or NULL on failure
2264 ------------------------------------------------------------------*/
2265 static int __init struct_udc_setup(struct fsl_udc *udc,
2266 struct platform_device *pdev)
2267 {
2268 struct fsl_usb2_platform_data *pdata;
2269 size_t size;
2270
2271 pdata = pdev->dev.platform_data;
2272 udc->phy_mode = pdata->phy_mode;
2273
2274 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2275 if (!udc->eps) {
2276 ERR("malloc fsl_ep failed\n");
2277 return -1;
2278 }
2279
2280 /* initialized QHs, take care of alignment */
2281 size = udc->max_ep * sizeof(struct ep_queue_head);
2282 if (size < QH_ALIGNMENT)
2283 size = QH_ALIGNMENT;
2284 else if ((size % QH_ALIGNMENT) != 0) {
2285 size += QH_ALIGNMENT + 1;
2286 size &= ~(QH_ALIGNMENT - 1);
2287 }
2288 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2289 &udc->ep_qh_dma, GFP_KERNEL);
2290 if (!udc->ep_qh) {
2291 ERR("malloc QHs for udc failed\n");
2292 kfree(udc->eps);
2293 return -1;
2294 }
2295
2296 udc->ep_qh_size = size;
2297
2298 /* Initialize ep0 status request structure */
2299 /* FIXME: fsl_alloc_request() ignores ep argument */
2300 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2301 struct fsl_req, req);
2302 /* allocate a small amount of memory to get valid address */
2303 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2304 udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
2305
2306 udc->resume_state = USB_STATE_NOTATTACHED;
2307 udc->usb_state = USB_STATE_POWERED;
2308 udc->ep0_dir = 0;
2309 udc->remote_wakeup = 0; /* default to 0 on reset */
2310
2311 return 0;
2312 }
2313
2314 /*----------------------------------------------------------------
2315 * Setup the fsl_ep struct for eps
2316 * Link fsl_ep->ep to gadget->ep_list
2317 * ep0out is not used so do nothing here
2318 * ep0in should be taken care
2319 *--------------------------------------------------------------*/
2320 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2321 char *name, int link)
2322 {
2323 struct fsl_ep *ep = &udc->eps[index];
2324
2325 ep->udc = udc;
2326 strcpy(ep->name, name);
2327 ep->ep.name = ep->name;
2328
2329 ep->ep.ops = &fsl_ep_ops;
2330 ep->stopped = 0;
2331
2332 /* for ep0: maxP defined in desc
2333 * for other eps, maxP is set by epautoconfig() called by gadget layer
2334 */
2335 ep->ep.maxpacket = (unsigned short) ~0;
2336
2337 /* the queue lists any req for this ep */
2338 INIT_LIST_HEAD(&ep->queue);
2339
2340 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2341 if (link)
2342 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2343 ep->gadget = &udc->gadget;
2344 ep->qh = &udc->ep_qh[index];
2345
2346 return 0;
2347 }
2348
2349 /* Driver probe function
2350 * all intialization operations implemented here except enabling usb_intr reg
2351 * board setup should have been done in the platform code
2352 */
2353 static int __init fsl_udc_probe(struct platform_device *pdev)
2354 {
2355 struct fsl_usb2_platform_data *pdata;
2356 struct resource *res;
2357 int ret = -ENODEV;
2358 unsigned int i;
2359 u32 dccparams;
2360
2361 if (strcmp(pdev->name, driver_name)) {
2362 VDBG("Wrong device");
2363 return -ENODEV;
2364 }
2365
2366 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2367 if (udc_controller == NULL) {
2368 ERR("malloc udc failed\n");
2369 return -ENOMEM;
2370 }
2371
2372 pdata = pdev->dev.platform_data;
2373 udc_controller->pdata = pdata;
2374 spin_lock_init(&udc_controller->lock);
2375 udc_controller->stopped = 1;
2376
2377 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2378 if (!res) {
2379 ret = -ENXIO;
2380 goto err_kfree;
2381 }
2382
2383 if (!request_mem_region(res->start, res->end - res->start + 1,
2384 driver_name)) {
2385 ERR("request mem region for %s failed\n", pdev->name);
2386 ret = -EBUSY;
2387 goto err_kfree;
2388 }
2389
2390 dr_regs = ioremap(res->start, resource_size(res));
2391 if (!dr_regs) {
2392 ret = -ENOMEM;
2393 goto err_release_mem_region;
2394 }
2395
2396 pdata->regs = (void *)dr_regs;
2397
2398 /*
2399 * do platform specific init: check the clock, grab/config pins, etc.
2400 */
2401 if (pdata->init && pdata->init(pdev)) {
2402 ret = -ENODEV;
2403 goto err_iounmap_noclk;
2404 }
2405
2406 /* Set accessors only after pdata->init() ! */
2407 if (pdata->big_endian_mmio) {
2408 _fsl_readl = _fsl_readl_be;
2409 _fsl_writel = _fsl_writel_be;
2410 } else {
2411 _fsl_readl = _fsl_readl_le;
2412 _fsl_writel = _fsl_writel_le;
2413 }
2414
2415 #ifndef CONFIG_ARCH_MXC
2416 if (pdata->have_sysif_regs)
2417 usb_sys_regs = (struct usb_sys_interface *)
2418 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2419 #endif
2420
2421 /* Initialize USB clocks */
2422 ret = fsl_udc_clk_init(pdev);
2423 if (ret < 0)
2424 goto err_iounmap_noclk;
2425
2426 /* Read Device Controller Capability Parameters register */
2427 dccparams = fsl_readl(&dr_regs->dccparams);
2428 if (!(dccparams & DCCPARAMS_DC)) {
2429 ERR("This SOC doesn't support device role\n");
2430 ret = -ENODEV;
2431 goto err_iounmap;
2432 }
2433 /* Get max device endpoints */
2434 /* DEN is bidirectional ep number, max_ep doubles the number */
2435 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2436
2437 udc_controller->irq = platform_get_irq(pdev, 0);
2438 if (!udc_controller->irq) {
2439 ret = -ENODEV;
2440 goto err_iounmap;
2441 }
2442
2443 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2444 driver_name, udc_controller);
2445 if (ret != 0) {
2446 ERR("cannot request irq %d err %d\n",
2447 udc_controller->irq, ret);
2448 goto err_iounmap;
2449 }
2450
2451 /* Initialize the udc structure including QH member and other member */
2452 if (struct_udc_setup(udc_controller, pdev)) {
2453 ERR("Can't initialize udc data structure\n");
2454 ret = -ENOMEM;
2455 goto err_free_irq;
2456 }
2457
2458 /* initialize usb hw reg except for regs for EP,
2459 * leave usbintr reg untouched */
2460 dr_controller_setup(udc_controller);
2461
2462 fsl_udc_clk_finalize(pdev);
2463
2464 /* Setup gadget structure */
2465 udc_controller->gadget.ops = &fsl_gadget_ops;
2466 udc_controller->gadget.is_dualspeed = 1;
2467 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2468 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2469 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2470 udc_controller->gadget.name = driver_name;
2471
2472 /* Setup gadget.dev and register with kernel */
2473 dev_set_name(&udc_controller->gadget.dev, "gadget");
2474 udc_controller->gadget.dev.release = fsl_udc_release;
2475 udc_controller->gadget.dev.parent = &pdev->dev;
2476 ret = device_register(&udc_controller->gadget.dev);
2477 if (ret < 0)
2478 goto err_free_irq;
2479
2480 /* setup QH and epctrl for ep0 */
2481 ep0_setup(udc_controller);
2482
2483 /* setup udc->eps[] for ep0 */
2484 struct_ep_setup(udc_controller, 0, "ep0", 0);
2485 /* for ep0: the desc defined here;
2486 * for other eps, gadget layer called ep_enable with defined desc
2487 */
2488 udc_controller->eps[0].desc = &fsl_ep0_desc;
2489 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2490
2491 /* setup the udc->eps[] for non-control endpoints and link
2492 * to gadget.ep_list */
2493 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2494 char name[14];
2495
2496 sprintf(name, "ep%dout", i);
2497 struct_ep_setup(udc_controller, i * 2, name, 1);
2498 sprintf(name, "ep%din", i);
2499 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2500 }
2501
2502 /* use dma_pool for TD management */
2503 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2504 sizeof(struct ep_td_struct),
2505 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2506 if (udc_controller->td_pool == NULL) {
2507 ret = -ENOMEM;
2508 goto err_unregister;
2509 }
2510 create_proc_file();
2511 return 0;
2512
2513 err_unregister:
2514 device_unregister(&udc_controller->gadget.dev);
2515 err_free_irq:
2516 free_irq(udc_controller->irq, udc_controller);
2517 err_iounmap:
2518 if (pdata->exit)
2519 pdata->exit(pdev);
2520 fsl_udc_clk_release();
2521 err_iounmap_noclk:
2522 iounmap(dr_regs);
2523 err_release_mem_region:
2524 release_mem_region(res->start, res->end - res->start + 1);
2525 err_kfree:
2526 kfree(udc_controller);
2527 udc_controller = NULL;
2528 return ret;
2529 }
2530
2531 /* Driver removal function
2532 * Free resources and finish pending transactions
2533 */
2534 static int __exit fsl_udc_remove(struct platform_device *pdev)
2535 {
2536 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2537 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2538
2539 DECLARE_COMPLETION(done);
2540
2541 if (!udc_controller)
2542 return -ENODEV;
2543 udc_controller->done = &done;
2544
2545 fsl_udc_clk_release();
2546
2547 /* DR has been stopped in usb_gadget_unregister_driver() */
2548 remove_proc_file();
2549
2550 /* Free allocated memory */
2551 kfree(udc_controller->status_req->req.buf);
2552 kfree(udc_controller->status_req);
2553 kfree(udc_controller->eps);
2554
2555 dma_pool_destroy(udc_controller->td_pool);
2556 free_irq(udc_controller->irq, udc_controller);
2557 iounmap(dr_regs);
2558 release_mem_region(res->start, res->end - res->start + 1);
2559
2560 device_unregister(&udc_controller->gadget.dev);
2561 /* free udc --wait for the release() finished */
2562 wait_for_completion(&done);
2563
2564 /*
2565 * do platform specific un-initialization:
2566 * release iomux pins, etc.
2567 */
2568 if (pdata->exit)
2569 pdata->exit(pdev);
2570
2571 return 0;
2572 }
2573
2574 /*-----------------------------------------------------------------
2575 * Modify Power management attributes
2576 * Used by OTG statemachine to disable gadget temporarily
2577 -----------------------------------------------------------------*/
2578 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2579 {
2580 dr_controller_stop(udc_controller);
2581 return 0;
2582 }
2583
2584 /*-----------------------------------------------------------------
2585 * Invoked on USB resume. May be called in_interrupt.
2586 * Here we start the DR controller and enable the irq
2587 *-----------------------------------------------------------------*/
2588 static int fsl_udc_resume(struct platform_device *pdev)
2589 {
2590 /* Enable DR irq reg and set controller Run */
2591 if (udc_controller->stopped) {
2592 dr_controller_setup(udc_controller);
2593 dr_controller_run(udc_controller);
2594 }
2595 udc_controller->usb_state = USB_STATE_ATTACHED;
2596 udc_controller->ep0_state = WAIT_FOR_SETUP;
2597 udc_controller->ep0_dir = 0;
2598 return 0;
2599 }
2600
2601 /*-------------------------------------------------------------------------
2602 Register entry point for the peripheral controller driver
2603 --------------------------------------------------------------------------*/
2604
2605 static struct platform_driver udc_driver = {
2606 .remove = __exit_p(fsl_udc_remove),
2607 /* these suspend and resume are not usb suspend and resume */
2608 .suspend = fsl_udc_suspend,
2609 .resume = fsl_udc_resume,
2610 .driver = {
2611 .name = (char *)driver_name,
2612 .owner = THIS_MODULE,
2613 },
2614 };
2615
2616 static int __init udc_init(void)
2617 {
2618 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2619 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2620 }
2621
2622 module_init(udc_init);
2623
2624 static void __exit udc_exit(void)
2625 {
2626 platform_driver_unregister(&udc_driver);
2627 printk(KERN_WARNING "%s unregistered\n", driver_desc);
2628 }
2629
2630 module_exit(udc_exit);
2631
2632 MODULE_DESCRIPTION(DRIVER_DESC);
2633 MODULE_AUTHOR(DRIVER_AUTHOR);
2634 MODULE_LICENSE("GPL");
2635 MODULE_ALIAS("platform:fsl-usb2-udc");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree