2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/sysdev.h>
27 #include <linux/module.h>
28 #include <linux/ioport.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
35 #include <asm/mach_apic.h>
38 #include <asm/proto.h>
39 #include <asm/timex.h>
45 int apic_runs_main_timer
;
46 int apic_calibrate_pmtmr __initdata
;
48 int disable_apic_timer __initdata
;
50 /* Local APIC timer works in C2? */
51 int local_apic_timer_c2_ok
;
52 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
54 static struct resource
*ioapic_resources
;
55 static struct resource lapic_resource
= {
57 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
61 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
62 * IPIs in place of local APIC timers
64 static cpumask_t timer_interrupt_broadcast_ipi_mask
;
66 /* Using APIC to generate smp_local_timer_interrupt? */
67 int using_apic_timer __read_mostly
= 0;
69 static void apic_pm_activate(void);
71 void enable_NMI_through_LVT0 (void * dummy
)
75 v
= APIC_DM_NMI
; /* unmask and set to NMI */
76 apic_write(APIC_LVT0
, v
);
81 unsigned int v
, maxlvt
;
83 v
= apic_read(APIC_LVR
);
84 maxlvt
= GET_APIC_MAXLVT(v
);
89 * 'what should we do if we get a hw irq event on an illegal vector'.
90 * each architecture has to answer this themselves.
92 void ack_bad_irq(unsigned int irq
)
94 printk("unexpected IRQ trap at vector %02x\n", irq
);
96 * Currently unexpected vectors happen only on SMP and APIC.
97 * We _must_ ack these because every local APIC has only N
98 * irq slots per priority level, and a 'hanging, unacked' IRQ
99 * holds up an irq slot - in excessive cases (when multiple
100 * unexpected vectors occur) that might lock up the APIC
102 * But don't ack when the APIC is disabled. -AK
108 void clear_local_APIC(void)
113 maxlvt
= get_maxlvt();
116 * Masking an LVT entry can trigger a local APIC error
117 * if the vector is zero. Mask LVTERR first to prevent this.
120 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
121 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
124 * Careful: we have to set masks only first to deassert
125 * any level-triggered sources.
127 v
= apic_read(APIC_LVTT
);
128 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
129 v
= apic_read(APIC_LVT0
);
130 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
131 v
= apic_read(APIC_LVT1
);
132 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
134 v
= apic_read(APIC_LVTPC
);
135 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
139 * Clean APIC state for other OSs:
141 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
142 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
143 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
145 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
147 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
148 apic_write(APIC_ESR
, 0);
152 void disconnect_bsp_APIC(int virt_wire_setup
)
154 /* Go back to Virtual Wire compatibility mode */
157 /* For the spurious interrupt use vector F, and enable it */
158 value
= apic_read(APIC_SPIV
);
159 value
&= ~APIC_VECTOR_MASK
;
160 value
|= APIC_SPIV_APIC_ENABLED
;
162 apic_write(APIC_SPIV
, value
);
164 if (!virt_wire_setup
) {
165 /* For LVT0 make it edge triggered, active high, external and enabled */
166 value
= apic_read(APIC_LVT0
);
167 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
168 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
169 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
170 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
171 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
172 apic_write(APIC_LVT0
, value
);
175 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
178 /* For LVT1 make it edge triggered, active high, nmi and enabled */
179 value
= apic_read(APIC_LVT1
);
180 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
181 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
182 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
183 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
184 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
185 apic_write(APIC_LVT1
, value
);
188 void disable_local_APIC(void)
195 * Disable APIC (implies clearing of registers
198 value
= apic_read(APIC_SPIV
);
199 value
&= ~APIC_SPIV_APIC_ENABLED
;
200 apic_write(APIC_SPIV
, value
);
204 * This is to verify that we're looking at a real local APIC.
205 * Check these against your board if the CPUs aren't getting
206 * started for no apparent reason.
208 int __init
verify_local_APIC(void)
210 unsigned int reg0
, reg1
;
213 * The version register is read-only in a real APIC.
215 reg0
= apic_read(APIC_LVR
);
216 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
217 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
218 reg1
= apic_read(APIC_LVR
);
219 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
222 * The two version reads above should print the same
223 * numbers. If the second one is different, then we
224 * poke at a non-APIC.
230 * Check if the version looks reasonably.
232 reg1
= GET_APIC_VERSION(reg0
);
233 if (reg1
== 0x00 || reg1
== 0xff)
236 if (reg1
< 0x02 || reg1
== 0xff)
240 * The ID register is read/write in a real APIC.
242 reg0
= apic_read(APIC_ID
);
243 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
244 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
245 reg1
= apic_read(APIC_ID
);
246 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
247 apic_write(APIC_ID
, reg0
);
248 if (reg1
!= (reg0
^ APIC_ID_MASK
))
252 * The next two are just to see if we have sane values.
253 * They're only really relevant if we're in Virtual Wire
254 * compatibility mode, but most boxes are anymore.
256 reg0
= apic_read(APIC_LVT0
);
257 apic_printk(APIC_DEBUG
,"Getting LVT0: %x\n", reg0
);
258 reg1
= apic_read(APIC_LVT1
);
259 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
264 void __init
sync_Arb_IDs(void)
266 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
267 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
268 if (ver
>= 0x14) /* P4 or higher */
274 apic_wait_icr_idle();
276 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
277 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
282 * An initial setup of the virtual wire mode.
284 void __init
init_bsp_APIC(void)
289 * Don't do the setup now if we have a SMP BIOS as the
290 * through-I/O-APIC virtual wire mode might be active.
292 if (smp_found_config
|| !cpu_has_apic
)
295 value
= apic_read(APIC_LVR
);
298 * Do not trust the local APIC being empty at bootup.
305 value
= apic_read(APIC_SPIV
);
306 value
&= ~APIC_VECTOR_MASK
;
307 value
|= APIC_SPIV_APIC_ENABLED
;
308 value
|= APIC_SPIV_FOCUS_DISABLED
;
309 value
|= SPURIOUS_APIC_VECTOR
;
310 apic_write(APIC_SPIV
, value
);
313 * Set up the virtual wire mode.
315 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
317 apic_write(APIC_LVT1
, value
);
320 void __cpuinit
setup_local_APIC (void)
322 unsigned int value
, maxlvt
;
325 value
= apic_read(APIC_LVR
);
327 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
330 * Double-check whether this APIC is really registered.
331 * This is meaningless in clustered apic mode, so we skip it.
333 if (!apic_id_registered())
337 * Intel recommends to set DFR, LDR and TPR before enabling
338 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
339 * document number 292116). So here it goes...
344 * Set Task Priority to 'accept all'. We never change this
347 value
= apic_read(APIC_TASKPRI
);
348 value
&= ~APIC_TPRI_MASK
;
349 apic_write(APIC_TASKPRI
, value
);
352 * After a crash, we no longer service the interrupts and a pending
353 * interrupt from previous kernel might still have ISR bit set.
355 * Most probably by now CPU has serviced that pending interrupt and
356 * it might not have done the ack_APIC_irq() because it thought,
357 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
358 * does not clear the ISR bit and cpu thinks it has already serivced
359 * the interrupt. Hence a vector might get locked. It was noticed
360 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
362 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
363 value
= apic_read(APIC_ISR
+ i
*0x10);
364 for (j
= 31; j
>= 0; j
--) {
371 * Now that we are all set up, enable the APIC
373 value
= apic_read(APIC_SPIV
);
374 value
&= ~APIC_VECTOR_MASK
;
378 value
|= APIC_SPIV_APIC_ENABLED
;
380 /* We always use processor focus */
383 * Set spurious IRQ vector
385 value
|= SPURIOUS_APIC_VECTOR
;
386 apic_write(APIC_SPIV
, value
);
391 * set up through-local-APIC on the BP's LINT0. This is not
392 * strictly necessary in pure symmetric-IO mode, but sometimes
393 * we delegate interrupts to the 8259A.
396 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
398 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
399 if (!smp_processor_id() && !value
) {
400 value
= APIC_DM_EXTINT
;
401 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", smp_processor_id());
403 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
404 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", smp_processor_id());
406 apic_write(APIC_LVT0
, value
);
409 * only the BP should see the LINT1 NMI signal, obviously.
411 if (!smp_processor_id())
414 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
415 apic_write(APIC_LVT1
, value
);
419 maxlvt
= get_maxlvt();
420 oldvalue
= apic_read(APIC_ESR
);
421 value
= ERROR_APIC_VECTOR
; // enables sending errors
422 apic_write(APIC_LVTERR
, value
);
424 * spec says clear errors after enabling vector.
427 apic_write(APIC_ESR
, 0);
428 value
= apic_read(APIC_ESR
);
429 if (value
!= oldvalue
)
430 apic_printk(APIC_VERBOSE
,
431 "ESR value after enabling vector: %08x, after %08x\n",
435 nmi_watchdog_default();
436 setup_apic_nmi_watchdog(NULL
);
443 /* 'active' is true if the local APIC was enabled by us and
444 not the BIOS; this signifies that we are also responsible
445 for disabling it before entering apm/acpi suspend */
447 /* r/w apic fields */
448 unsigned int apic_id
;
449 unsigned int apic_taskpri
;
450 unsigned int apic_ldr
;
451 unsigned int apic_dfr
;
452 unsigned int apic_spiv
;
453 unsigned int apic_lvtt
;
454 unsigned int apic_lvtpc
;
455 unsigned int apic_lvt0
;
456 unsigned int apic_lvt1
;
457 unsigned int apic_lvterr
;
458 unsigned int apic_tmict
;
459 unsigned int apic_tdcr
;
460 unsigned int apic_thmr
;
463 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
468 if (!apic_pm_state
.active
)
471 maxlvt
= get_maxlvt();
473 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
474 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
475 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
476 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
477 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
478 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
480 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
481 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
482 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
483 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
484 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
485 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
486 #ifdef CONFIG_X86_MCE_INTEL
488 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
490 local_irq_save(flags
);
491 disable_local_APIC();
492 local_irq_restore(flags
);
496 static int lapic_resume(struct sys_device
*dev
)
502 if (!apic_pm_state
.active
)
505 maxlvt
= get_maxlvt();
507 local_irq_save(flags
);
508 rdmsr(MSR_IA32_APICBASE
, l
, h
);
509 l
&= ~MSR_IA32_APICBASE_BASE
;
510 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
511 wrmsr(MSR_IA32_APICBASE
, l
, h
);
512 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
513 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
514 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
515 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
516 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
517 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
518 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
519 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
520 #ifdef CONFIG_X86_MCE_INTEL
522 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
525 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
526 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
527 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
528 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
529 apic_write(APIC_ESR
, 0);
531 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
532 apic_write(APIC_ESR
, 0);
534 local_irq_restore(flags
);
538 static struct sysdev_class lapic_sysclass
= {
539 set_kset_name("lapic"),
540 .resume
= lapic_resume
,
541 .suspend
= lapic_suspend
,
544 static struct sys_device device_lapic
= {
546 .cls
= &lapic_sysclass
,
549 static void __cpuinit
apic_pm_activate(void)
551 apic_pm_state
.active
= 1;
554 static int __init
init_lapic_sysfs(void)
559 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
560 error
= sysdev_class_register(&lapic_sysclass
);
562 error
= sysdev_register(&device_lapic
);
565 device_initcall(init_lapic_sysfs
);
567 #else /* CONFIG_PM */
569 static void apic_pm_activate(void) { }
571 #endif /* CONFIG_PM */
573 static int __init
apic_set_verbosity(char *str
)
576 skip_ioapic_setup
= 0;
580 if (strcmp("debug", str
) == 0)
581 apic_verbosity
= APIC_DEBUG
;
582 else if (strcmp("verbose", str
) == 0)
583 apic_verbosity
= APIC_VERBOSE
;
585 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
586 " use apic=verbose or apic=debug\n", str
);
592 early_param("apic", apic_set_verbosity
);
595 * Detect and enable local APICs on non-SMP boards.
596 * Original code written by Keir Fraser.
597 * On AMD64 we trust the BIOS - if it says no APIC it is likely
598 * not correctly set up (usually the APIC timer won't work etc.)
601 static int __init
detect_init_APIC (void)
604 printk(KERN_INFO
"No local APIC present\n");
608 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
613 #ifdef CONFIG_X86_IO_APIC
614 static struct resource
* __init
ioapic_setup_resources(void)
616 #define IOAPIC_RESOURCE_NAME_SIZE 11
618 struct resource
*res
;
625 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
628 mem
= alloc_bootmem(n
);
633 mem
+= sizeof(struct resource
) * nr_ioapics
;
635 for (i
= 0; i
< nr_ioapics
; i
++) {
637 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
638 sprintf(mem
, "IOAPIC %u", i
);
639 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
643 ioapic_resources
= res
;
648 static int __init
ioapic_insert_resources(void)
651 struct resource
*r
= ioapic_resources
;
654 printk("IO APIC resources could be not be allocated.\n");
658 for (i
= 0; i
< nr_ioapics
; i
++) {
659 insert_resource(&iomem_resource
, r
);
666 /* Insert the IO APIC resources after PCI initialization has occured to handle
667 * IO APICS that are mapped in on a BAR in PCI space. */
668 late_initcall(ioapic_insert_resources
);
671 void __init
init_apic_mappings(void)
673 unsigned long apic_phys
;
676 * If no local APIC can be found then set up a fake all
677 * zeroes page to simulate the local APIC and another
678 * one for the IO-APIC.
680 if (!smp_found_config
&& detect_init_APIC()) {
681 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
682 apic_phys
= __pa(apic_phys
);
684 apic_phys
= mp_lapic_addr
;
686 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
688 apic_printk(APIC_VERBOSE
,"mapped APIC to %16lx (%16lx)\n", APIC_BASE
, apic_phys
);
690 /* Put local APIC into the resource map. */
691 lapic_resource
.start
= apic_phys
;
692 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
693 insert_resource(&iomem_resource
, &lapic_resource
);
696 * Fetch the APIC ID of the BSP in case we have a
697 * default configuration (or the MP table is broken).
699 boot_cpu_id
= GET_APIC_ID(apic_read(APIC_ID
));
702 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
704 struct resource
*ioapic_res
;
706 ioapic_res
= ioapic_setup_resources();
707 for (i
= 0; i
< nr_ioapics
; i
++) {
708 if (smp_found_config
) {
709 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
711 ioapic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
712 ioapic_phys
= __pa(ioapic_phys
);
714 set_fixmap_nocache(idx
, ioapic_phys
);
715 apic_printk(APIC_VERBOSE
,"mapped IOAPIC to %016lx (%016lx)\n",
716 __fix_to_virt(idx
), ioapic_phys
);
719 if (ioapic_res
!= NULL
) {
720 ioapic_res
->start
= ioapic_phys
;
721 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
729 * This function sets up the local APIC timer, with a timeout of
730 * 'clocks' APIC bus clock. During calibration we actually call
731 * this function twice on the boot CPU, once with a bogus timeout
732 * value, second time for real. The other (noncalibrating) CPUs
733 * call this function only once, with the real, calibrated value.
735 * We do reads before writes even if unnecessary, to get around the
736 * P5 APIC double write bug.
739 #define APIC_DIVISOR 16
741 static void __setup_APIC_LVTT(unsigned int clocks
)
743 unsigned int lvtt_value
, tmp_value
;
744 int cpu
= smp_processor_id();
746 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
748 if (cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
))
749 lvtt_value
|= APIC_LVT_MASKED
;
751 apic_write(APIC_LVTT
, lvtt_value
);
756 tmp_value
= apic_read(APIC_TDCR
);
757 apic_write(APIC_TDCR
, (tmp_value
758 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
761 apic_write(APIC_TMICT
, clocks
/APIC_DIVISOR
);
764 static void setup_APIC_timer(unsigned int clocks
)
768 local_irq_save(flags
);
770 /* wait for irq slice */
771 if (hpet_address
&& hpet_use_timer
) {
772 int trigger
= hpet_readl(HPET_T0_CMP
);
773 while (hpet_readl(HPET_COUNTER
) >= trigger
)
775 while (hpet_readl(HPET_COUNTER
) < trigger
)
781 c2
|= inb_p(0x40) << 8;
786 c2
|= inb_p(0x40) << 8;
787 } while (c2
- c1
< 300);
789 __setup_APIC_LVTT(clocks
);
790 /* Turn off PIT interrupt if we use APIC timer as main timer.
791 Only works with the PM timer right now
792 TBD fix it for HPET too. */
793 if ((pmtmr_ioport
!= 0) &&
794 smp_processor_id() == boot_cpu_id
&&
795 apic_runs_main_timer
== 1 &&
796 !cpu_isset(boot_cpu_id
, timer_interrupt_broadcast_ipi_mask
)) {
797 stop_timer_interrupt();
798 apic_runs_main_timer
++;
800 local_irq_restore(flags
);
804 * In this function we calibrate APIC bus clocks to the external
805 * timer. Unfortunately we cannot use jiffies and the timer irq
806 * to calibrate, since some later bootup code depends on getting
807 * the first irq? Ugh.
809 * We want to do the calibration only once since we
810 * want to have local timer irqs syncron. CPUs connected
811 * by the same APIC bus have the very same bus frequency.
812 * And we want to have irqs off anyways, no accidental
816 #define TICK_COUNT 100000000
818 static int __init
calibrate_APIC_clock(void)
820 int apic
, apic_start
, tsc
, tsc_start
;
823 * Put whatever arbitrary (but long enough) timeout
824 * value into the APIC clock, we just want to get the
825 * counter running for calibration.
827 __setup_APIC_LVTT(1000000000);
829 apic_start
= apic_read(APIC_TMCCT
);
830 #ifdef CONFIG_X86_PM_TIMER
831 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
832 pmtimer_wait(5000); /* 5ms wait */
833 apic
= apic_read(APIC_TMCCT
);
834 result
= (apic_start
- apic
) * 1000L / 5;
841 apic
= apic_read(APIC_TMCCT
);
843 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
844 (apic
- apic_start
) < TICK_COUNT
);
846 result
= (apic_start
- apic
) * 1000L * cpu_khz
/
849 printk("result %d\n", result
);
852 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
853 result
/ 1000 / 1000, result
/ 1000 % 1000);
855 return result
* APIC_DIVISOR
/ HZ
;
858 static unsigned int calibration_result
;
860 void __init
setup_boot_APIC_clock (void)
862 if (disable_apic_timer
) {
863 printk(KERN_INFO
"Disabling APIC timer\n");
867 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
868 using_apic_timer
= 1;
872 calibration_result
= calibrate_APIC_clock();
874 * Now set up the timer for real.
876 setup_APIC_timer(calibration_result
);
881 void __cpuinit
setup_secondary_APIC_clock(void)
883 local_irq_disable(); /* FIXME: Do we need this? --RR */
884 setup_APIC_timer(calibration_result
);
888 void disable_APIC_timer(void)
890 if (using_apic_timer
) {
893 v
= apic_read(APIC_LVTT
);
895 * When an illegal vector value (0-15) is written to an LVT
896 * entry and delivery mode is Fixed, the APIC may signal an
897 * illegal vector error, with out regard to whether the mask
898 * bit is set or whether an interrupt is actually seen on input.
900 * Boot sequence might call this function when the LVTT has
901 * '0' vector value. So make sure vector field is set to
904 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
905 apic_write(APIC_LVTT
, v
);
909 void enable_APIC_timer(void)
911 int cpu
= smp_processor_id();
913 if (using_apic_timer
&&
914 !cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
917 v
= apic_read(APIC_LVTT
);
918 apic_write(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
922 void switch_APIC_timer_to_ipi(void *cpumask
)
924 cpumask_t mask
= *(cpumask_t
*)cpumask
;
925 int cpu
= smp_processor_id();
927 if (cpu_isset(cpu
, mask
) &&
928 !cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
929 disable_APIC_timer();
930 cpu_set(cpu
, timer_interrupt_broadcast_ipi_mask
);
933 EXPORT_SYMBOL(switch_APIC_timer_to_ipi
);
935 void smp_send_timer_broadcast_ipi(void)
939 cpus_and(mask
, cpu_online_map
, timer_interrupt_broadcast_ipi_mask
);
940 if (!cpus_empty(mask
)) {
941 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
945 void switch_ipi_to_APIC_timer(void *cpumask
)
947 cpumask_t mask
= *(cpumask_t
*)cpumask
;
948 int cpu
= smp_processor_id();
950 if (cpu_isset(cpu
, mask
) &&
951 cpu_isset(cpu
, timer_interrupt_broadcast_ipi_mask
)) {
952 cpu_clear(cpu
, timer_interrupt_broadcast_ipi_mask
);
956 EXPORT_SYMBOL(switch_ipi_to_APIC_timer
);
958 int setup_profiling_timer(unsigned int multiplier
)
963 void setup_APIC_extened_lvt(unsigned char lvt_off
, unsigned char vector
,
964 unsigned char msg_type
, unsigned char mask
)
966 unsigned long reg
= (lvt_off
<< 4) + K8_APIC_EXT_LVT_BASE
;
967 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
974 * Local timer interrupt handler. It does both profiling and
975 * process statistics/rescheduling.
977 * We do profiling in every local tick, statistics/rescheduling
978 * happen only every 'profiling multiplier' ticks. The default
979 * multiplier is 1 and it can be changed by writing the new multiplier
980 * value into /proc/profile.
983 void smp_local_timer_interrupt(void)
985 profile_tick(CPU_PROFILING
);
987 update_process_times(user_mode(get_irq_regs()));
989 if (apic_runs_main_timer
> 1 && smp_processor_id() == boot_cpu_id
)
990 main_timer_handler();
992 * We take the 'long' return path, and there every subsystem
993 * grabs the appropriate locks (kernel lock/ irq lock).
995 * We might want to decouple profiling from the 'long path',
996 * and do the profiling totally in assembly.
998 * Currently this isn't too much of an issue (performance wise),
999 * we can take more than 100K local irqs per second on a 100 MHz P5.
1004 * Local APIC timer interrupt. This is the most natural way for doing
1005 * local interrupts, but local timer interrupts can be emulated by
1006 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1008 * [ if a single-CPU system runs an SMP kernel then we call the local
1009 * interrupt as well. Thus we cannot inline the local irq ... ]
1011 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1013 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1016 * the NMI deadlock-detector uses this.
1018 add_pda(apic_timer_irqs
, 1);
1021 * NOTE! We'd better ACK the irq immediately,
1022 * because timer handling can be slow.
1026 * update_process_times() expects us to have done irq_enter().
1027 * Besides, if we don't timer interrupts ignore the global
1028 * interrupt lock, which is the WrongThing (tm) to do.
1032 smp_local_timer_interrupt();
1034 set_irq_regs(old_regs
);
1038 * apic_is_clustered_box() -- Check if we can expect good TSC
1040 * Thus far, the major user of this is IBM's Summit2 series:
1042 * Clustered boxes may have unsynced TSC problems if they are
1043 * multi-chassis. Use available data to take a good guess.
1044 * If in doubt, go HPET.
1046 __cpuinit
int apic_is_clustered_box(void)
1048 int i
, clusters
, zeros
;
1050 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1052 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1054 for (i
= 0; i
< NR_CPUS
; i
++) {
1055 id
= bios_cpu_apicid
[i
];
1056 if (id
!= BAD_APICID
)
1057 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1060 /* Problem: Partially populated chassis may not have CPUs in some of
1061 * the APIC clusters they have been allocated. Only present CPUs have
1062 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1063 * clusters are allocated sequentially, count zeros only if they are
1068 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1069 if (test_bit(i
, clustermap
)) {
1070 clusters
+= 1 + zeros
;
1077 * If clusters > 2, then should be multi-chassis.
1078 * May have to revisit this when multi-core + hyperthreaded CPUs come
1079 * out, but AFAIK this will work even for them.
1081 return (clusters
> 2);
1085 * This interrupt should _never_ happen with our APIC/SMP architecture
1087 asmlinkage
void smp_spurious_interrupt(void)
1093 * Check if this really is a spurious interrupt and ACK it
1094 * if it is a vectored one. Just in case...
1095 * Spurious interrupts should not be ACKed.
1097 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1098 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1102 static unsigned long last_warning
;
1103 static unsigned long skipped
;
1105 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1106 if (time_before(last_warning
+30*HZ
,jiffies
)) {
1107 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, %ld skipped.\n",
1108 smp_processor_id(), skipped
);
1109 last_warning
= jiffies
;
1119 * This interrupt should never happen with our APIC/SMP architecture
1122 asmlinkage
void smp_error_interrupt(void)
1128 /* First tickle the hardware, only then report what went on. -- REW */
1129 v
= apic_read(APIC_ESR
);
1130 apic_write(APIC_ESR
, 0);
1131 v1
= apic_read(APIC_ESR
);
1133 atomic_inc(&irq_err_count
);
1135 /* Here is what the APIC error bits mean:
1138 2: Send accept error
1139 3: Receive accept error
1141 5: Send illegal vector
1142 6: Received illegal vector
1143 7: Illegal register address
1145 printk (KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1146 smp_processor_id(), v
, v1
);
1153 * This initializes the IO-APIC and APIC hardware if this is
1156 int __init
APIC_init_uniprocessor (void)
1159 printk(KERN_INFO
"Apic disabled\n");
1162 if (!cpu_has_apic
) {
1164 printk(KERN_INFO
"Apic disabled by BIOS\n");
1168 verify_local_APIC();
1170 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_id
);
1171 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_id
));
1175 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1179 setup_boot_APIC_clock();
1180 check_nmi_watchdog();
1184 static __init
int setup_disableapic(char *str
)
1187 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1190 early_param("disableapic", setup_disableapic
);
1192 /* same as disableapic, for compatibility */
1193 static __init
int setup_nolapic(char *str
)
1195 return setup_disableapic(str
);
1197 early_param("nolapic", setup_nolapic
);
1199 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1201 local_apic_timer_c2_ok
= 1;
1204 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1206 static __init
int setup_noapictimer(char *str
)
1208 if (str
[0] != ' ' && str
[0] != 0)
1210 disable_apic_timer
= 1;
1214 static __init
int setup_apicmaintimer(char *str
)
1216 apic_runs_main_timer
= 1;
1220 __setup("apicmaintimer", setup_apicmaintimer
);
1222 static __init
int setup_noapicmaintimer(char *str
)
1224 apic_runs_main_timer
= -1;
1227 __setup("noapicmaintimer", setup_noapicmaintimer
);
1229 static __init
int setup_apicpmtimer(char *s
)
1231 apic_calibrate_pmtmr
= 1;
1233 return setup_apicmaintimer(NULL
);
1235 __setup("apicpmtimer", setup_apicpmtimer
);
1237 __setup("noapictimer", setup_noapictimer
);