omap: Add new interface omap_get_die_id
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-omap2 / id.c
blobd079ccfa294e50d0b7ae2a514a0acf7ffabd5c28
1 /*
2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
22 #include <asm/cputype.h>
24 #include <plat/common.h>
25 #include <plat/control.h>
26 #include <plat/cpu.h>
28 #include <mach/id.h>
30 static struct omap_chip_id omap_chip;
31 static unsigned int omap_revision;
33 u32 omap3_features;
35 unsigned int omap_rev(void)
37 return omap_revision;
39 EXPORT_SYMBOL(omap_rev);
41 /**
42 * omap_chip_is - test whether currently running OMAP matches a chip type
43 * @oc: omap_chip_t to test against
45 * Test whether the currently-running OMAP chip matches the supplied
46 * chip type 'oc'. Returns 1 upon a match; 0 upon failure.
48 int omap_chip_is(struct omap_chip_id oci)
50 return (oci.oc & omap_chip.oc) ? 1 : 0;
52 EXPORT_SYMBOL(omap_chip_is);
54 int omap_type(void)
56 u32 val = 0;
58 if (cpu_is_omap24xx()) {
59 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
60 } else if (cpu_is_omap34xx()) {
61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
62 } else if (cpu_is_omap44xx()) {
63 val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
64 } else {
65 pr_err("Cannot detect omap type!\n");
66 goto out;
69 val &= OMAP2_DEVICETYPE_MASK;
70 val >>= 8;
72 out:
73 return val;
75 EXPORT_SYMBOL(omap_type);
78 /*----------------------------------------------------------------------------*/
80 #define OMAP_TAP_IDCODE 0x0204
81 #define OMAP_TAP_DIE_ID_0 0x0218
82 #define OMAP_TAP_DIE_ID_1 0x021C
83 #define OMAP_TAP_DIE_ID_2 0x0220
84 #define OMAP_TAP_DIE_ID_3 0x0224
86 #define read_tap_reg(reg) __raw_readl(tap_base + (reg))
88 struct omap_id {
89 u16 hawkeye; /* Silicon type (Hawkeye id) */
90 u8 dev; /* Device type from production_id reg */
91 u32 type; /* Combined type id copied to omap_revision */
94 /* Register values to detect the OMAP version */
95 static struct omap_id omap_ids[] __initdata = {
96 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
97 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
98 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
99 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
100 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
101 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
104 static void __iomem *tap_base;
105 static u16 tap_prod_id;
107 void omap_get_die_id(struct omap_die_id *odi)
109 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
110 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
111 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
112 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
115 static void __init omap24xx_check_revision(void)
117 int i, j;
118 u32 idcode, prod_id;
119 u16 hawkeye;
120 u8 dev_type, rev;
122 idcode = read_tap_reg(OMAP_TAP_IDCODE);
123 prod_id = read_tap_reg(tap_prod_id);
124 hawkeye = (idcode >> 12) & 0xffff;
125 rev = (idcode >> 28) & 0x0f;
126 dev_type = (prod_id >> 16) & 0x0f;
128 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
129 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
130 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
131 read_tap_reg(OMAP_TAP_DIE_ID_0));
132 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
133 read_tap_reg(OMAP_TAP_DIE_ID_1),
134 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
135 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
136 read_tap_reg(OMAP_TAP_DIE_ID_2));
137 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
138 read_tap_reg(OMAP_TAP_DIE_ID_3));
139 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
140 prod_id, dev_type);
142 /* Check hawkeye ids */
143 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
144 if (hawkeye == omap_ids[i].hawkeye)
145 break;
148 if (i == ARRAY_SIZE(omap_ids)) {
149 printk(KERN_ERR "Unknown OMAP CPU id\n");
150 return;
153 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
154 if (dev_type == omap_ids[j].dev)
155 break;
158 if (j == ARRAY_SIZE(omap_ids)) {
159 printk(KERN_ERR "Unknown OMAP device type. "
160 "Handling it as OMAP%04x\n",
161 omap_ids[i].type >> 16);
162 j = i;
165 pr_info("OMAP%04x", omap_rev() >> 16);
166 if ((omap_rev() >> 8) & 0x0f)
167 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
168 pr_info("\n");
171 #define OMAP3_CHECK_FEATURE(status,feat) \
172 if (((status & OMAP3_ ##feat## _MASK) \
173 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
174 omap3_features |= OMAP3_HAS_ ##feat; \
177 static void __init omap3_check_features(void)
179 u32 status;
181 omap3_features = 0;
183 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
185 OMAP3_CHECK_FEATURE(status, L2CACHE);
186 OMAP3_CHECK_FEATURE(status, IVA);
187 OMAP3_CHECK_FEATURE(status, SGX);
188 OMAP3_CHECK_FEATURE(status, NEON);
189 OMAP3_CHECK_FEATURE(status, ISP);
190 if (cpu_is_omap3630())
191 omap3_features |= OMAP3_HAS_192MHZ_CLK;
192 if (!cpu_is_omap3505() && !cpu_is_omap3517())
193 omap3_features |= OMAP3_HAS_IO_WAKEUP;
196 * TODO: Get additional info (where applicable)
197 * e.g. Size of L2 cache.
201 static void __init omap3_check_revision(void)
203 u32 cpuid, idcode;
204 u16 hawkeye;
205 u8 rev;
207 omap_chip.oc = CHIP_IS_OMAP3430;
210 * We cannot access revision registers on ES1.0.
211 * If the processor type is Cortex-A8 and the revision is 0x0
212 * it means its Cortex r0p0 which is 3430 ES1.0.
214 cpuid = read_cpuid(CPUID_ID);
215 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
216 omap_revision = OMAP3430_REV_ES1_0;
217 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
218 return;
222 * Detection for 34xx ES2.0 and above can be done with just
223 * hawkeye and rev. See TRM 1.5.2 Device Identification.
224 * Note that rev does not map directly to our defined processor
225 * revision numbers as ES1.0 uses value 0.
227 idcode = read_tap_reg(OMAP_TAP_IDCODE);
228 hawkeye = (idcode >> 12) & 0xffff;
229 rev = (idcode >> 28) & 0xff;
231 switch (hawkeye) {
232 case 0xb7ae:
233 /* Handle 34xx/35xx devices */
234 switch (rev) {
235 case 0: /* Take care of early samples */
236 case 1:
237 omap_revision = OMAP3430_REV_ES2_0;
238 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
239 break;
240 case 2:
241 omap_revision = OMAP3430_REV_ES2_1;
242 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
243 break;
244 case 3:
245 omap_revision = OMAP3430_REV_ES3_0;
246 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
247 break;
248 case 4:
249 omap_revision = OMAP3430_REV_ES3_1;
250 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
251 break;
252 case 7:
253 /* FALLTHROUGH */
254 default:
255 /* Use the latest known revision as default */
256 omap_revision = OMAP3430_REV_ES3_1_2;
258 /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
259 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
261 break;
262 case 0xb868:
263 /* Handle OMAP35xx/AM35xx devices
265 * Set the device to be OMAP3505 here. Actual device
266 * is identified later based on the features.
268 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
270 omap_revision = OMAP3505_REV(rev);
271 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
272 break;
273 case 0xb891:
274 /* FALLTHROUGH */
275 default:
276 /* Unknown default to latest silicon rev as default*/
277 omap_revision = OMAP3630_REV_ES1_0;
278 omap_chip.oc |= CHIP_IS_OMAP3630ES1;
282 static void __init omap4_check_revision(void)
284 u32 idcode;
285 u16 hawkeye;
286 u8 rev;
287 char *rev_name = "ES1.0";
290 * The IC rev detection is done with hawkeye and rev.
291 * Note that rev does not map directly to defined processor
292 * revision numbers as ES1.0 uses value 0.
294 idcode = read_tap_reg(OMAP_TAP_IDCODE);
295 hawkeye = (idcode >> 12) & 0xffff;
296 rev = (idcode >> 28) & 0xff;
298 if ((hawkeye == 0xb852) && (rev == 0x0)) {
299 omap_revision = OMAP4430_REV_ES1_0;
300 omap_chip.oc |= CHIP_IS_OMAP4430ES1;
301 pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
302 return;
305 pr_err("Unknown OMAP4 CPU id\n");
308 #define OMAP3_SHOW_FEATURE(feat) \
309 if (omap3_has_ ##feat()) \
310 printk(#feat" ");
312 static void __init omap3_cpuinfo(void)
314 u8 rev = GET_OMAP_REVISION();
315 char cpu_name[16], cpu_rev[16];
317 /* OMAP3430 and OMAP3530 are assumed to be same.
319 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
320 * on available features. Upon detection, update the CPU id
321 * and CPU class bits.
323 if (cpu_is_omap3630()) {
324 strcpy(cpu_name, "OMAP3630");
325 } else if (cpu_is_omap3505()) {
327 * AM35xx devices
329 if (omap3_has_sgx()) {
330 omap_revision = OMAP3517_REV(rev);
331 strcpy(cpu_name, "AM3517");
332 } else {
333 /* Already set in omap3_check_revision() */
334 strcpy(cpu_name, "AM3505");
336 } else if (omap3_has_iva() && omap3_has_sgx()) {
337 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
338 strcpy(cpu_name, "OMAP3430/3530");
339 } else if (omap3_has_iva()) {
340 omap_revision = OMAP3525_REV(rev);
341 strcpy(cpu_name, "OMAP3525");
342 } else if (omap3_has_sgx()) {
343 omap_revision = OMAP3515_REV(rev);
344 strcpy(cpu_name, "OMAP3515");
345 } else {
346 omap_revision = OMAP3503_REV(rev);
347 strcpy(cpu_name, "OMAP3503");
350 switch (rev) {
351 case OMAP_REVBITS_00:
352 strcpy(cpu_rev, "1.0");
353 break;
354 case OMAP_REVBITS_10:
355 strcpy(cpu_rev, "2.0");
356 break;
357 case OMAP_REVBITS_20:
358 strcpy(cpu_rev, "2.1");
359 break;
360 case OMAP_REVBITS_30:
361 strcpy(cpu_rev, "3.0");
362 break;
363 case OMAP_REVBITS_40:
364 /* FALLTHROUGH */
365 default:
366 /* Use the latest known revision as default */
367 strcpy(cpu_rev, "3.1");
370 /* Print verbose information */
371 pr_info("%s ES%s (", cpu_name, cpu_rev);
373 OMAP3_SHOW_FEATURE(l2cache);
374 OMAP3_SHOW_FEATURE(iva);
375 OMAP3_SHOW_FEATURE(sgx);
376 OMAP3_SHOW_FEATURE(neon);
377 OMAP3_SHOW_FEATURE(isp);
378 OMAP3_SHOW_FEATURE(192mhz_clk);
380 printk(")\n");
384 * Try to detect the exact revision of the omap we're running on
386 void __init omap2_check_revision(void)
389 * At this point we have an idea about the processor revision set
390 * earlier with omap2_set_globals_tap().
392 if (cpu_is_omap24xx()) {
393 omap24xx_check_revision();
394 } else if (cpu_is_omap34xx()) {
395 omap3_check_revision();
396 omap3_check_features();
397 omap3_cpuinfo();
398 return;
399 } else if (cpu_is_omap44xx()) {
400 omap4_check_revision();
401 return;
402 } else {
403 pr_err("OMAP revision unknown, please fix!\n");
407 * OK, now we know the exact revision. Initialize omap_chip bits
408 * for powerdowmain and clockdomain code.
410 if (cpu_is_omap243x()) {
411 /* Currently only supports 2430ES2.1 and 2430-all */
412 omap_chip.oc |= CHIP_IS_OMAP2430;
413 return;
414 } else if (cpu_is_omap242x()) {
415 /* Currently only supports 2420ES2.1.1 and 2420-all */
416 omap_chip.oc |= CHIP_IS_OMAP2420;
417 return;
420 pr_err("Uninitialized omap_chip, please fix!\n");
424 * Set up things for map_io and processor detection later on. Gets called
425 * pretty much first thing from board init. For multi-omap, this gets
426 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
427 * detect the exact revision later on in omap2_detect_revision() once map_io
428 * is done.
430 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
432 omap_revision = omap2_globals->class;
433 tap_base = omap2_globals->tap;
435 if (cpu_is_omap34xx())
436 tap_prod_id = 0x0210;
437 else
438 tap_prod_id = 0x0208;