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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath9k / hw.c
blob60e55d8c510ba2efe3692a1fe498bf477373ec21
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
88 {
89 int i;
90
91 BUG_ON(timeout < AH_TIME_QUANTUM);
92
93 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
94 if ((REG_READ(ah, reg) & mask) == val)
95 return true;
96
97 udelay(AH_TIME_QUANTUM);
98 }
99
100 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
102 timeout, reg, REG_READ(ah, reg), mask, val);
103
104 return false;
105 }
106
107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
108 {
109 u32 retval;
110 int i;
111
112 for (i = 0, retval = 0; i < n; i++) {
113 retval = (retval << 1) | (val & 1);
114 val >>= 1;
115 }
116 return retval;
117 }
118
119 bool ath9k_get_channel_edges(struct ath_hw *ah,
120 u16 flags, u16 *low,
121 u16 *high)
122 {
123 struct ath9k_hw_capabilities *pCap = &ah->caps;
124
125 if (flags & CHANNEL_5GHZ) {
126 *low = pCap->low_5ghz_chan;
127 *high = pCap->high_5ghz_chan;
128 return true;
129 }
130 if ((flags & CHANNEL_2GHZ)) {
131 *low = pCap->low_2ghz_chan;
132 *high = pCap->high_2ghz_chan;
133 return true;
134 }
135 return false;
136 }
137
138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
139 struct ath_rate_table *rates,
140 u32 frameLen, u16 rateix,
141 bool shortPreamble)
142 {
143 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
144 u32 kbps;
145
146 kbps = rates->info[rateix].ratekbps;
147
148 if (kbps == 0)
149 return 0;
150
151 switch (rates->info[rateix].phy) {
152 case WLAN_RC_PHY_CCK:
153 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
154 if (shortPreamble && rates->info[rateix].short_preamble)
155 phyTime >>= 1;
156 numBits = frameLen << 3;
157 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
158 break;
159 case WLAN_RC_PHY_OFDM:
160 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
161 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
162 numBits = OFDM_PLCP_BITS + (frameLen << 3);
163 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
164 txTime = OFDM_SIFS_TIME_QUARTER
165 + OFDM_PREAMBLE_TIME_QUARTER
166 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
167 } else if (ah->curchan &&
168 IS_CHAN_HALF_RATE(ah->curchan)) {
169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME_HALF +
173 OFDM_PREAMBLE_TIME_HALF
174 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
175 } else {
176 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
177 numBits = OFDM_PLCP_BITS + (frameLen << 3);
178 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
179 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
180 + (numSymbols * OFDM_SYMBOL_TIME);
181 }
182 break;
183 default:
184 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
185 "Unknown phy %u (rate ix %u)\n",
186 rates->info[rateix].phy, rateix);
187 txTime = 0;
188 break;
189 }
190
191 return txTime;
192 }
193
194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
195 struct ath9k_channel *chan,
196 struct chan_centers *centers)
197 {
198 int8_t extoff;
199
200 if (!IS_CHAN_HT40(chan)) {
201 centers->ctl_center = centers->ext_center =
202 centers->synth_center = chan->channel;
203 return;
204 }
205
206 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
207 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
208 centers->synth_center =
209 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
210 extoff = 1;
211 } else {
212 centers->synth_center =
213 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
214 extoff = -1;
215 }
216
217 centers->ctl_center =
218 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
219 centers->ext_center =
220 centers->synth_center + (extoff *
221 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
222 HT40_CHANNEL_CENTER_SHIFT : 15));
223 }
224
225 /******************/
226 /* Chip Revisions */
227 /******************/
228
229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
230 {
231 u32 val;
232
233 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
234
235 if (val == 0xFF) {
236 val = REG_READ(ah, AR_SREV);
237 ah->hw_version.macVersion =
238 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
239 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
240 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
241 } else {
242 if (!AR_SREV_9100(ah))
243 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
244
245 ah->hw_version.macRev = val & AR_SREV_REVISION;
246
247 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
248 ah->is_pciexpress = true;
249 }
250 }
251
252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
253 {
254 u32 val;
255 int i;
256
257 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
258
259 for (i = 0; i < 8; i++)
260 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
261 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
262 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
263
264 return ath9k_hw_reverse_bits(val, 8);
265 }
266
267 /************************************/
268 /* HW Attach, Detach, Init Routines */
269 /************************************/
270
271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
272 {
273 if (AR_SREV_9100(ah))
274 return;
275
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
285
286 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
287 }
288
289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
290 {
291 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
292 u32 regHold[2];
293 u32 patternData[4] = { 0x55555555,
294 0xaaaaaaaa,
295 0x66666666,
296 0x99999999 };
297 int i, j;
298
299 for (i = 0; i < 2; i++) {
300 u32 addr = regAddr[i];
301 u32 wrData, rdData;
302
303 regHold[i] = REG_READ(ah, addr);
304 for (j = 0; j < 0x100; j++) {
305 wrData = (j << 16) | j;
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (rdData != wrData) {
309 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
312 addr, wrData, rdData);
313 return false;
314 }
315 }
316 for (j = 0; j < 4; j++) {
317 wrData = patternData[j];
318 REG_WRITE(ah, addr, wrData);
319 rdData = REG_READ(ah, addr);
320 if (wrData != rdData) {
321 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
322 "address test failed "
323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
324 addr, wrData, rdData);
325 return false;
326 }
327 }
328 REG_WRITE(ah, regAddr[i], regHold[i]);
329 }
330 udelay(100);
331
332 return true;
333 }
334
335 static const char *ath9k_hw_devname(u16 devid)
336 {
337 switch (devid) {
338 case AR5416_DEVID_PCI:
339 return "Atheros 5416";
340 case AR5416_DEVID_PCIE:
341 return "Atheros 5418";
342 case AR9160_DEVID_PCI:
343 return "Atheros 9160";
344 case AR5416_AR9100_DEVID:
345 return "Atheros 9100";
346 case AR9280_DEVID_PCI:
347 case AR9280_DEVID_PCIE:
348 return "Atheros 9280";
349 case AR9285_DEVID_PCIE:
350 return "Atheros 9285";
351 }
352
353 return NULL;
354 }
355
356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
357 {
358 int i;
359
360 ah->config.dma_beacon_response_time = 2;
361 ah->config.sw_beacon_response_time = 10;
362 ah->config.additional_swba_backoff = 0;
363 ah->config.ack_6mb = 0x0;
364 ah->config.cwm_ignore_extcca = 0;
365 ah->config.pcie_powersave_enable = 0;
366 ah->config.pcie_l1skp_enable = 0;
367 ah->config.pcie_clock_req = 0;
368 ah->config.pcie_power_reset = 0x100;
369 ah->config.pcie_restore = 0;
370 ah->config.pcie_waen = 0;
371 ah->config.analog_shiftreg = 1;
372 ah->config.ht_enable = 1;
373 ah->config.ofdm_trig_low = 200;
374 ah->config.ofdm_trig_high = 500;
375 ah->config.cck_trig_high = 200;
376 ah->config.cck_trig_low = 100;
377 ah->config.enable_ani = 1;
378 ah->config.noise_immunity_level = 4;
379 ah->config.ofdm_weaksignal_det = 1;
380 ah->config.cck_weaksignal_thr = 0;
381 ah->config.spur_immunity_level = 2;
382 ah->config.firstep_level = 0;
383 ah->config.rssi_thr_high = 40;
384 ah->config.rssi_thr_low = 7;
385 ah->config.diversity_control = 0;
386 ah->config.antenna_switch_swap = 0;
387
388 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
389 ah->config.spurchans[i][0] = AR_NO_SPUR;
390 ah->config.spurchans[i][1] = AR_NO_SPUR;
391 }
392
393 ah->config.intr_mitigation = 1;
394
395 /*
396 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
397 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
398 * This means we use it for all AR5416 devices, and the few
399 * minor PCI AR9280 devices out there.
400 *
401 * Serialization is required because these devices do not handle
402 * well the case of two concurrent reads/writes due to the latency
403 * involved. During one read/write another read/write can be issued
404 * on another CPU while the previous read/write may still be working
405 * on our hardware, if we hit this case the hardware poops in a loop.
406 * We prevent this by serializing reads and writes.
407 *
408 * This issue is not present on PCI-Express devices or pre-AR5416
409 * devices (legacy, 802.11abg).
410 */
411 if (num_possible_cpus() > 1)
412 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
413 }
414
415 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
416 int *status)
417 {
418 struct ath_hw *ah;
419
420 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
421 if (ah == NULL) {
422 DPRINTF(sc, ATH_DBG_FATAL,
423 "Cannot allocate memory for state block\n");
424 *status = -ENOMEM;
425 return NULL;
426 }
427
428 ah->ah_sc = sc;
429 ah->hw_version.magic = AR5416_MAGIC;
430 ah->regulatory.country_code = CTRY_DEFAULT;
431 ah->hw_version.devid = devid;
432 ah->hw_version.subvendorid = 0;
433
434 ah->ah_flags = 0;
435 if ((devid == AR5416_AR9100_DEVID))
436 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
437 if (!AR_SREV_9100(ah))
438 ah->ah_flags = AH_USE_EEPROM;
439
440 ah->regulatory.power_limit = MAX_RATE_POWER;
441 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
442 ah->atim_window = 0;
443 ah->diversity_control = ah->config.diversity_control;
444 ah->antenna_switch_swap =
445 ah->config.antenna_switch_swap;
446 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
447 ah->beacon_interval = 100;
448 ah->enable_32kHz_clock = DONT_USE_32KHZ;
449 ah->slottime = (u32) -1;
450 ah->acktimeout = (u32) -1;
451 ah->ctstimeout = (u32) -1;
452 ah->globaltxtimeout = (u32) -1;
453
454 ah->gbeacon_rate = 0;
455
456 return ah;
457 }
458
459 static int ath9k_hw_rfattach(struct ath_hw *ah)
460 {
461 bool rfStatus = false;
462 int ecode = 0;
463
464 rfStatus = ath9k_hw_init_rf(ah, &ecode);
465 if (!rfStatus) {
466 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
467 "RF setup failed, status %u\n", ecode);
468 return ecode;
469 }
470
471 return 0;
472 }
473
474 static int ath9k_hw_rf_claim(struct ath_hw *ah)
475 {
476 u32 val;
477
478 REG_WRITE(ah, AR_PHY(0), 0x00000007);
479
480 val = ath9k_hw_get_radiorev(ah);
481 switch (val & AR_RADIO_SREV_MAJOR) {
482 case 0:
483 val = AR_RAD5133_SREV_MAJOR;
484 break;
485 case AR_RAD5133_SREV_MAJOR:
486 case AR_RAD5122_SREV_MAJOR:
487 case AR_RAD2133_SREV_MAJOR:
488 case AR_RAD2122_SREV_MAJOR:
489 break;
490 default:
491 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
492 "5G Radio Chip Rev 0x%02X is not "
493 "supported by this driver\n",
494 ah->hw_version.analog5GhzRev);
495 return -EOPNOTSUPP;
496 }
497
498 ah->hw_version.analog5GhzRev = val;
499
500 return 0;
501 }
502
503 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
504 {
505 u32 sum;
506 int i;
507 u16 eeval;
508
509 sum = 0;
510 for (i = 0; i < 3; i++) {
511 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
512 sum += eeval;
513 ah->macaddr[2 * i] = eeval >> 8;
514 ah->macaddr[2 * i + 1] = eeval & 0xff;
515 }
516 if (sum == 0 || sum == 0xffff * 3) {
517 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
518 "mac address read failed: %pM\n",
519 ah->macaddr);
520 return -EADDRNOTAVAIL;
521 }
522
523 return 0;
524 }
525
526 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
527 {
528 u32 rxgain_type;
529
530 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
531 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
532
533 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
534 INIT_INI_ARRAY(&ah->iniModesRxGain,
535 ar9280Modes_backoff_13db_rxgain_9280_2,
536 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
537 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
538 INIT_INI_ARRAY(&ah->iniModesRxGain,
539 ar9280Modes_backoff_23db_rxgain_9280_2,
540 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
541 else
542 INIT_INI_ARRAY(&ah->iniModesRxGain,
543 ar9280Modes_original_rxgain_9280_2,
544 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
545 } else {
546 INIT_INI_ARRAY(&ah->iniModesRxGain,
547 ar9280Modes_original_rxgain_9280_2,
548 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
549 }
550 }
551
552 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
553 {
554 u32 txgain_type;
555
556 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
557 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
558
559 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
560 INIT_INI_ARRAY(&ah->iniModesTxGain,
561 ar9280Modes_high_power_tx_gain_9280_2,
562 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
563 else
564 INIT_INI_ARRAY(&ah->iniModesTxGain,
565 ar9280Modes_original_tx_gain_9280_2,
566 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
567 } else {
568 INIT_INI_ARRAY(&ah->iniModesTxGain,
569 ar9280Modes_original_tx_gain_9280_2,
570 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
571 }
572 }
573
574 static int ath9k_hw_post_attach(struct ath_hw *ah)
575 {
576 int ecode;
577
578 if (!ath9k_hw_chip_test(ah)) {
579 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
580 "hardware self-test failed\n");
581 return -ENODEV;
582 }
583
584 ecode = ath9k_hw_rf_claim(ah);
585 if (ecode != 0)
586 return ecode;
587
588 ecode = ath9k_hw_eeprom_attach(ah);
589 if (ecode != 0)
590 return ecode;
591 ecode = ath9k_hw_rfattach(ah);
592 if (ecode != 0)
593 return ecode;
594
595 if (!AR_SREV_9100(ah)) {
596 ath9k_hw_ani_setup(ah);
597 ath9k_hw_ani_attach(ah);
598 }
599
600 return 0;
601 }
602
603 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
604 int *status)
605 {
606 struct ath_hw *ah;
607 int ecode;
608 u32 i, j;
609
610 ah = ath9k_hw_newstate(devid, sc, status);
611 if (ah == NULL)
612 return NULL;
613
614 ath9k_hw_set_defaults(ah);
615
616 if (ah->config.intr_mitigation != 0)
617 ah->intr_mitigation = true;
618
619 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
620 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
621 ecode = -EIO;
622 goto bad;
623 }
624
625 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
626 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
627 ecode = -EIO;
628 goto bad;
629 }
630
631 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
632 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
633 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
634 ah->config.serialize_regmode =
635 SER_REG_MODE_ON;
636 } else {
637 ah->config.serialize_regmode =
638 SER_REG_MODE_OFF;
639 }
640 }
641
642 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
643 ah->config.serialize_regmode);
644
645 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
646 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
647 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
648 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
649 DPRINTF(sc, ATH_DBG_RESET,
650 "Mac Chip Rev 0x%02x.%x is not supported by "
651 "this driver\n", ah->hw_version.macVersion,
652 ah->hw_version.macRev);
653 ecode = -EOPNOTSUPP;
654 goto bad;
655 }
656
657 if (AR_SREV_9100(ah)) {
658 ah->iq_caldata.calData = &iq_cal_multi_sample;
659 ah->supp_cals = IQ_MISMATCH_CAL;
660 ah->is_pciexpress = false;
661 }
662 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
663
664 if (AR_SREV_9160_10_OR_LATER(ah)) {
665 if (AR_SREV_9280_10_OR_LATER(ah)) {
666 ah->iq_caldata.calData = &iq_cal_single_sample;
667 ah->adcgain_caldata.calData =
668 &adc_gain_cal_single_sample;
669 ah->adcdc_caldata.calData =
670 &adc_dc_cal_single_sample;
671 ah->adcdc_calinitdata.calData =
672 &adc_init_dc_cal;
673 } else {
674 ah->iq_caldata.calData = &iq_cal_multi_sample;
675 ah->adcgain_caldata.calData =
676 &adc_gain_cal_multi_sample;
677 ah->adcdc_caldata.calData =
678 &adc_dc_cal_multi_sample;
679 ah->adcdc_calinitdata.calData =
680 &adc_init_dc_cal;
681 }
682 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
683 }
684
685 if (AR_SREV_9160(ah)) {
686 ah->config.enable_ani = 1;
687 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
688 ATH9K_ANI_FIRSTEP_LEVEL);
689 } else {
690 ah->ani_function = ATH9K_ANI_ALL;
691 if (AR_SREV_9280_10_OR_LATER(ah)) {
692 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
693 }
694 }
695
696 DPRINTF(sc, ATH_DBG_RESET,
697 "This Mac Chip Rev 0x%02x.%x is \n",
698 ah->hw_version.macVersion, ah->hw_version.macRev);
699
700 if (AR_SREV_9285_12_OR_LATER(ah)) {
701 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
702 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
703 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
704 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
705
706 if (ah->config.pcie_clock_req) {
707 INIT_INI_ARRAY(&ah->iniPcieSerdes,
708 ar9285PciePhy_clkreq_off_L1_9285_1_2,
709 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
710 } else {
711 INIT_INI_ARRAY(&ah->iniPcieSerdes,
712 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
713 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
714 2);
715 }
716 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
717 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
718 ARRAY_SIZE(ar9285Modes_9285), 6);
719 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
720 ARRAY_SIZE(ar9285Common_9285), 2);
721
722 if (ah->config.pcie_clock_req) {
723 INIT_INI_ARRAY(&ah->iniPcieSerdes,
724 ar9285PciePhy_clkreq_off_L1_9285,
725 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
726 } else {
727 INIT_INI_ARRAY(&ah->iniPcieSerdes,
728 ar9285PciePhy_clkreq_always_on_L1_9285,
729 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
730 }
731 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
732 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
733 ARRAY_SIZE(ar9280Modes_9280_2), 6);
734 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
735 ARRAY_SIZE(ar9280Common_9280_2), 2);
736
737 if (ah->config.pcie_clock_req) {
738 INIT_INI_ARRAY(&ah->iniPcieSerdes,
739 ar9280PciePhy_clkreq_off_L1_9280,
740 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
741 } else {
742 INIT_INI_ARRAY(&ah->iniPcieSerdes,
743 ar9280PciePhy_clkreq_always_on_L1_9280,
744 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
745 }
746 INIT_INI_ARRAY(&ah->iniModesAdditional,
747 ar9280Modes_fast_clock_9280_2,
748 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
749 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
750 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
751 ARRAY_SIZE(ar9280Modes_9280), 6);
752 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
753 ARRAY_SIZE(ar9280Common_9280), 2);
754 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
755 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
756 ARRAY_SIZE(ar5416Modes_9160), 6);
757 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
758 ARRAY_SIZE(ar5416Common_9160), 2);
759 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
760 ARRAY_SIZE(ar5416Bank0_9160), 2);
761 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
762 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
763 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
764 ARRAY_SIZE(ar5416Bank1_9160), 2);
765 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
766 ARRAY_SIZE(ar5416Bank2_9160), 2);
767 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
768 ARRAY_SIZE(ar5416Bank3_9160), 3);
769 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
770 ARRAY_SIZE(ar5416Bank6_9160), 3);
771 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
772 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
773 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
774 ARRAY_SIZE(ar5416Bank7_9160), 2);
775 if (AR_SREV_9160_11(ah)) {
776 INIT_INI_ARRAY(&ah->iniAddac,
777 ar5416Addac_91601_1,
778 ARRAY_SIZE(ar5416Addac_91601_1), 2);
779 } else {
780 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
781 ARRAY_SIZE(ar5416Addac_9160), 2);
782 }
783 } else if (AR_SREV_9100_OR_LATER(ah)) {
784 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
785 ARRAY_SIZE(ar5416Modes_9100), 6);
786 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
787 ARRAY_SIZE(ar5416Common_9100), 2);
788 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
789 ARRAY_SIZE(ar5416Bank0_9100), 2);
790 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
791 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
792 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
793 ARRAY_SIZE(ar5416Bank1_9100), 2);
794 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
795 ARRAY_SIZE(ar5416Bank2_9100), 2);
796 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
797 ARRAY_SIZE(ar5416Bank3_9100), 3);
798 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
799 ARRAY_SIZE(ar5416Bank6_9100), 3);
800 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
801 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
802 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
803 ARRAY_SIZE(ar5416Bank7_9100), 2);
804 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
805 ARRAY_SIZE(ar5416Addac_9100), 2);
806 } else {
807 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
808 ARRAY_SIZE(ar5416Modes), 6);
809 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
810 ARRAY_SIZE(ar5416Common), 2);
811 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
812 ARRAY_SIZE(ar5416Bank0), 2);
813 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
814 ARRAY_SIZE(ar5416BB_RfGain), 3);
815 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
816 ARRAY_SIZE(ar5416Bank1), 2);
817 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
818 ARRAY_SIZE(ar5416Bank2), 2);
819 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
820 ARRAY_SIZE(ar5416Bank3), 3);
821 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
822 ARRAY_SIZE(ar5416Bank6), 3);
823 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
824 ARRAY_SIZE(ar5416Bank6TPC), 3);
825 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
826 ARRAY_SIZE(ar5416Bank7), 2);
827 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
828 ARRAY_SIZE(ar5416Addac), 2);
829 }
830
831 if (ah->is_pciexpress)
832 ath9k_hw_configpcipowersave(ah, 0);
833 else
834 ath9k_hw_disablepcie(ah);
835
836 ecode = ath9k_hw_post_attach(ah);
837 if (ecode != 0)
838 goto bad;
839
840 /* rxgain table */
841 if (AR_SREV_9280_20(ah))
842 ath9k_hw_init_rxgain_ini(ah);
843
844 /* txgain table */
845 if (AR_SREV_9280_20(ah))
846 ath9k_hw_init_txgain_ini(ah);
847
848 if (!ath9k_hw_fill_cap_info(ah)) {
849 DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
850 ecode = -EINVAL;
851 goto bad;
852 }
853
854 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
855 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
856
857 /* EEPROM Fixup */
858 for (i = 0; i < ah->iniModes.ia_rows; i++) {
859 u32 reg = INI_RA(&ah->iniModes, i, 0);
860
861 for (j = 1; j < ah->iniModes.ia_columns; j++) {
862 u32 val = INI_RA(&ah->iniModes, i, j);
863
864 INI_RA(&ah->iniModes, i, j) =
865 ath9k_hw_ini_fixup(ah,
866 &ah->eeprom.def,
867 reg, val);
868 }
869 }
870 }
871
872 ecode = ath9k_hw_init_macaddr(ah);
873 if (ecode != 0) {
874 DPRINTF(sc, ATH_DBG_RESET,
875 "failed initializing mac address\n");
876 goto bad;
877 }
878
879 if (AR_SREV_9285(ah))
880 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
881 else
882 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
883
884 ath9k_init_nfcal_hist_buffer(ah);
885
886 return ah;
887 bad:
888 if (ah)
889 ath9k_hw_detach(ah);
890 if (status)
891 *status = ecode;
892
893 return NULL;
894 }
895
896 static void ath9k_hw_init_bb(struct ath_hw *ah,
897 struct ath9k_channel *chan)
898 {
899 u32 synthDelay;
900
901 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
902 if (IS_CHAN_B(chan))
903 synthDelay = (4 * synthDelay) / 22;
904 else
905 synthDelay /= 10;
906
907 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
908
909 udelay(synthDelay + BASE_ACTIVATE_DELAY);
910 }
911
912 static void ath9k_hw_init_qos(struct ath_hw *ah)
913 {
914 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
915 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
916
917 REG_WRITE(ah, AR_QOS_NO_ACK,
918 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
919 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
920 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
921
922 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
923 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
924 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
925 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
926 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
927 }
928
929 static void ath9k_hw_init_pll(struct ath_hw *ah,
930 struct ath9k_channel *chan)
931 {
932 u32 pll;
933
934 if (AR_SREV_9100(ah)) {
935 if (chan && IS_CHAN_5GHZ(chan))
936 pll = 0x1450;
937 else
938 pll = 0x1458;
939 } else {
940 if (AR_SREV_9280_10_OR_LATER(ah)) {
941 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
942
943 if (chan && IS_CHAN_HALF_RATE(chan))
944 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
945 else if (chan && IS_CHAN_QUARTER_RATE(chan))
946 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
947
948 if (chan && IS_CHAN_5GHZ(chan)) {
949 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
950
951
952 if (AR_SREV_9280_20(ah)) {
953 if (((chan->channel % 20) == 0)
954 || ((chan->channel % 10) == 0))
955 pll = 0x2850;
956 else
957 pll = 0x142c;
958 }
959 } else {
960 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
961 }
962
963 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
964
965 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
966
967 if (chan && IS_CHAN_HALF_RATE(chan))
968 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
969 else if (chan && IS_CHAN_QUARTER_RATE(chan))
970 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
971
972 if (chan && IS_CHAN_5GHZ(chan))
973 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
974 else
975 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
976 } else {
977 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
978
979 if (chan && IS_CHAN_HALF_RATE(chan))
980 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
981 else if (chan && IS_CHAN_QUARTER_RATE(chan))
982 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
983
984 if (chan && IS_CHAN_5GHZ(chan))
985 pll |= SM(0xa, AR_RTC_PLL_DIV);
986 else
987 pll |= SM(0xb, AR_RTC_PLL_DIV);
988 }
989 }
990 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
991
992 udelay(RTC_PLL_SETTLE_DELAY);
993
994 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
995 }
996
997 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
998 {
999 int rx_chainmask, tx_chainmask;
1000
1001 rx_chainmask = ah->rxchainmask;
1002 tx_chainmask = ah->txchainmask;
1003
1004 switch (rx_chainmask) {
1005 case 0x5:
1006 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1007 AR_PHY_SWAP_ALT_CHAIN);
1008 case 0x3:
1009 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1010 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1011 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1012 break;
1013 }
1014 case 0x1:
1015 case 0x2:
1016 case 0x7:
1017 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1018 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1019 break;
1020 default:
1021 break;
1022 }
1023
1024 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1025 if (tx_chainmask == 0x5) {
1026 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1027 AR_PHY_SWAP_ALT_CHAIN);
1028 }
1029 if (AR_SREV_9100(ah))
1030 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1031 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1032 }
1033
1034 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1035 enum nl80211_iftype opmode)
1036 {
1037 ah->mask_reg = AR_IMR_TXERR |
1038 AR_IMR_TXURN |
1039 AR_IMR_RXERR |
1040 AR_IMR_RXORN |
1041 AR_IMR_BCNMISC;
1042
1043 if (ah->intr_mitigation)
1044 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1045 else
1046 ah->mask_reg |= AR_IMR_RXOK;
1047
1048 ah->mask_reg |= AR_IMR_TXOK;
1049
1050 if (opmode == NL80211_IFTYPE_AP)
1051 ah->mask_reg |= AR_IMR_MIB;
1052
1053 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1054 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1055
1056 if (!AR_SREV_9100(ah)) {
1057 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1058 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1059 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1060 }
1061 }
1062
1063 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1064 {
1065 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1066 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1067 ah->acktimeout = (u32) -1;
1068 return false;
1069 } else {
1070 REG_RMW_FIELD(ah, AR_TIME_OUT,
1071 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1072 ah->acktimeout = us;
1073 return true;
1074 }
1075 }
1076
1077 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1078 {
1079 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1080 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1081 ah->ctstimeout = (u32) -1;
1082 return false;
1083 } else {
1084 REG_RMW_FIELD(ah, AR_TIME_OUT,
1085 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1086 ah->ctstimeout = us;
1087 return true;
1088 }
1089 }
1090
1091 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1092 {
1093 if (tu > 0xFFFF) {
1094 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1095 "bad global tx timeout %u\n", tu);
1096 ah->globaltxtimeout = (u32) -1;
1097 return false;
1098 } else {
1099 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1100 ah->globaltxtimeout = tu;
1101 return true;
1102 }
1103 }
1104
1105 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1106 {
1107 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1108 ah->misc_mode);
1109
1110 if (ah->misc_mode != 0)
1111 REG_WRITE(ah, AR_PCU_MISC,
1112 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1113 if (ah->slottime != (u32) -1)
1114 ath9k_hw_setslottime(ah, ah->slottime);
1115 if (ah->acktimeout != (u32) -1)
1116 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1117 if (ah->ctstimeout != (u32) -1)
1118 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1119 if (ah->globaltxtimeout != (u32) -1)
1120 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1121 }
1122
1123 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1124 {
1125 return vendorid == ATHEROS_VENDOR_ID ?
1126 ath9k_hw_devname(devid) : NULL;
1127 }
1128
1129 void ath9k_hw_detach(struct ath_hw *ah)
1130 {
1131 if (!AR_SREV_9100(ah))
1132 ath9k_hw_ani_detach(ah);
1133
1134 ath9k_hw_rfdetach(ah);
1135 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1136 kfree(ah);
1137 }
1138
1139 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1140 {
1141 struct ath_hw *ah = NULL;
1142
1143 switch (devid) {
1144 case AR5416_DEVID_PCI:
1145 case AR5416_DEVID_PCIE:
1146 case AR5416_AR9100_DEVID:
1147 case AR9160_DEVID_PCI:
1148 case AR9280_DEVID_PCI:
1149 case AR9280_DEVID_PCIE:
1150 case AR9285_DEVID_PCIE:
1151 ah = ath9k_hw_do_attach(devid, sc, error);
1152 break;
1153 default:
1154 *error = -ENXIO;
1155 break;
1156 }
1157
1158 return ah;
1159 }
1160
1161 /*******/
1162 /* INI */
1163 /*******/
1164
1165 static void ath9k_hw_override_ini(struct ath_hw *ah,
1166 struct ath9k_channel *chan)
1167 {
1168 /*
1169 * Set the RX_ABORT and RX_DIS and clear if off only after
1170 * RXE is set for MAC. This prevents frames with corrupted
1171 * descriptor status.
1172 */
1173 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1174
1175
1176 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1177 AR_SREV_9280_10_OR_LATER(ah))
1178 return;
1179
1180 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1181 }
1182
1183 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1184 struct ar5416_eeprom_def *pEepData,
1185 u32 reg, u32 value)
1186 {
1187 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1188
1189 switch (ah->hw_version.devid) {
1190 case AR9280_DEVID_PCI:
1191 if (reg == 0x7894) {
1192 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1193 "ini VAL: %x EEPROM: %x\n", value,
1194 (pBase->version & 0xff));
1195
1196 if ((pBase->version & 0xff) > 0x0a) {
1197 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1198 "PWDCLKIND: %d\n",
1199 pBase->pwdclkind);
1200 value &= ~AR_AN_TOP2_PWDCLKIND;
1201 value |= AR_AN_TOP2_PWDCLKIND &
1202 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1203 } else {
1204 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1205 "PWDCLKIND Earlier Rev\n");
1206 }
1207
1208 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1209 "final ini VAL: %x\n", value);
1210 }
1211 break;
1212 }
1213
1214 return value;
1215 }
1216
1217 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1218 struct ar5416_eeprom_def *pEepData,
1219 u32 reg, u32 value)
1220 {
1221 if (ah->eep_map == EEP_MAP_4KBITS)
1222 return value;
1223 else
1224 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1225 }
1226
1227 static void ath9k_olc_init(struct ath_hw *ah)
1228 {
1229 u32 i;
1230
1231 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1232 ah->originalGain[i] =
1233 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1234 AR_PHY_TX_GAIN);
1235 ah->PDADCdelta = 0;
1236 }
1237
1238 static int ath9k_hw_process_ini(struct ath_hw *ah,
1239 struct ath9k_channel *chan,
1240 enum ath9k_ht_macmode macmode)
1241 {
1242 int i, regWrites = 0;
1243 struct ieee80211_channel *channel = chan->chan;
1244 u32 modesIndex, freqIndex;
1245 int status;
1246
1247 switch (chan->chanmode) {
1248 case CHANNEL_A:
1249 case CHANNEL_A_HT20:
1250 modesIndex = 1;
1251 freqIndex = 1;
1252 break;
1253 case CHANNEL_A_HT40PLUS:
1254 case CHANNEL_A_HT40MINUS:
1255 modesIndex = 2;
1256 freqIndex = 1;
1257 break;
1258 case CHANNEL_G:
1259 case CHANNEL_G_HT20:
1260 case CHANNEL_B:
1261 modesIndex = 4;
1262 freqIndex = 2;
1263 break;
1264 case CHANNEL_G_HT40PLUS:
1265 case CHANNEL_G_HT40MINUS:
1266 modesIndex = 3;
1267 freqIndex = 2;
1268 break;
1269
1270 default:
1271 return -EINVAL;
1272 }
1273
1274 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1275 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1276 ah->eep_ops->set_addac(ah, chan);
1277
1278 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1279 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1280 } else {
1281 struct ar5416IniArray temp;
1282 u32 addacSize =
1283 sizeof(u32) * ah->iniAddac.ia_rows *
1284 ah->iniAddac.ia_columns;
1285
1286 memcpy(ah->addac5416_21,
1287 ah->iniAddac.ia_array, addacSize);
1288
1289 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1290
1291 temp.ia_array = ah->addac5416_21;
1292 temp.ia_columns = ah->iniAddac.ia_columns;
1293 temp.ia_rows = ah->iniAddac.ia_rows;
1294 REG_WRITE_ARRAY(&temp, 1, regWrites);
1295 }
1296
1297 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1298
1299 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1300 u32 reg = INI_RA(&ah->iniModes, i, 0);
1301 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1302
1303 REG_WRITE(ah, reg, val);
1304
1305 if (reg >= 0x7800 && reg < 0x78a0
1306 && ah->config.analog_shiftreg) {
1307 udelay(100);
1308 }
1309
1310 DO_DELAY(regWrites);
1311 }
1312
1313 if (AR_SREV_9280(ah))
1314 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1315
1316 if (AR_SREV_9280(ah))
1317 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1318
1319 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1320 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1321 u32 val = INI_RA(&ah->iniCommon, i, 1);
1322
1323 REG_WRITE(ah, reg, val);
1324
1325 if (reg >= 0x7800 && reg < 0x78a0
1326 && ah->config.analog_shiftreg) {
1327 udelay(100);
1328 }
1329
1330 DO_DELAY(regWrites);
1331 }
1332
1333 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1334
1335 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1336 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1337 regWrites);
1338 }
1339
1340 ath9k_hw_override_ini(ah, chan);
1341 ath9k_hw_set_regs(ah, chan, macmode);
1342 ath9k_hw_init_chain_masks(ah);
1343
1344 if (OLC_FOR_AR9280_20_LATER)
1345 ath9k_olc_init(ah);
1346
1347 status = ah->eep_ops->set_txpower(ah, chan,
1348 ath9k_regd_get_ctl(ah, chan),
1349 channel->max_antenna_gain * 2,
1350 channel->max_power * 2,
1351 min((u32) MAX_RATE_POWER,
1352 (u32) ah->regulatory.power_limit));
1353 if (status != 0) {
1354 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1355 "error init'ing transmit power\n");
1356 return -EIO;
1357 }
1358
1359 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1360 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1361 "ar5416SetRfRegs failed\n");
1362 return -EIO;
1363 }
1364
1365 return 0;
1366 }
1367
1368 /****************************************/
1369 /* Reset and Channel Switching Routines */
1370 /****************************************/
1371
1372 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1373 {
1374 u32 rfMode = 0;
1375
1376 if (chan == NULL)
1377 return;
1378
1379 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1380 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1381
1382 if (!AR_SREV_9280_10_OR_LATER(ah))
1383 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1384 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1385
1386 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1387 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1388
1389 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1390 }
1391
1392 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1393 {
1394 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1395 }
1396
1397 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1398 {
1399 u32 regval;
1400
1401 regval = REG_READ(ah, AR_AHB_MODE);
1402 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1403
1404 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1405 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1406
1407 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1408
1409 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1410 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1411
1412 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1413
1414 if (AR_SREV_9285(ah)) {
1415 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1416 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1417 } else {
1418 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1419 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1420 }
1421 }
1422
1423 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1424 {
1425 u32 val;
1426
1427 val = REG_READ(ah, AR_STA_ID1);
1428 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1429 switch (opmode) {
1430 case NL80211_IFTYPE_AP:
1431 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1432 | AR_STA_ID1_KSRCH_MODE);
1433 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1434 break;
1435 case NL80211_IFTYPE_ADHOC:
1436 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1437 | AR_STA_ID1_KSRCH_MODE);
1438 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1439 break;
1440 case NL80211_IFTYPE_STATION:
1441 case NL80211_IFTYPE_MONITOR:
1442 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1443 break;
1444 }
1445 }
1446
1447 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1448 u32 coef_scaled,
1449 u32 *coef_mantissa,
1450 u32 *coef_exponent)
1451 {
1452 u32 coef_exp, coef_man;
1453
1454 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1455 if ((coef_scaled >> coef_exp) & 0x1)
1456 break;
1457
1458 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1459
1460 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1461
1462 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1463 *coef_exponent = coef_exp - 16;
1464 }
1465
1466 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1467 struct ath9k_channel *chan)
1468 {
1469 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1470 u32 clockMhzScaled = 0x64000000;
1471 struct chan_centers centers;
1472
1473 if (IS_CHAN_HALF_RATE(chan))
1474 clockMhzScaled = clockMhzScaled >> 1;
1475 else if (IS_CHAN_QUARTER_RATE(chan))
1476 clockMhzScaled = clockMhzScaled >> 2;
1477
1478 ath9k_hw_get_channel_centers(ah, chan, &centers);
1479 coef_scaled = clockMhzScaled / centers.synth_center;
1480
1481 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1482 &ds_coef_exp);
1483
1484 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1485 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1486 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1487 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1488
1489 coef_scaled = (9 * coef_scaled) / 10;
1490
1491 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1492 &ds_coef_exp);
1493
1494 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1495 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1496 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1497 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1498 }
1499
1500 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1501 {
1502 u32 rst_flags;
1503 u32 tmpReg;
1504
1505 if (AR_SREV_9100(ah)) {
1506 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1507 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1508 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1509 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1510 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1511 }
1512
1513 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1514 AR_RTC_FORCE_WAKE_ON_INT);
1515
1516 if (AR_SREV_9100(ah)) {
1517 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1518 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1519 } else {
1520 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1521 if (tmpReg &
1522 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1523 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1524 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1525 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1526 } else {
1527 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1528 }
1529
1530 rst_flags = AR_RTC_RC_MAC_WARM;
1531 if (type == ATH9K_RESET_COLD)
1532 rst_flags |= AR_RTC_RC_MAC_COLD;
1533 }
1534
1535 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1536 udelay(50);
1537
1538 REG_WRITE(ah, AR_RTC_RC, 0);
1539 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1540 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1541 "RTC stuck in MAC reset\n");
1542 return false;
1543 }
1544
1545 if (!AR_SREV_9100(ah))
1546 REG_WRITE(ah, AR_RC, 0);
1547
1548 ath9k_hw_init_pll(ah, NULL);
1549
1550 if (AR_SREV_9100(ah))
1551 udelay(50);
1552
1553 return true;
1554 }
1555
1556 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1557 {
1558 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1559 AR_RTC_FORCE_WAKE_ON_INT);
1560
1561 REG_WRITE(ah, AR_RTC_RESET, 0);
1562 udelay(2);
1563 REG_WRITE(ah, AR_RTC_RESET, 1);
1564
1565 if (!ath9k_hw_wait(ah,
1566 AR_RTC_STATUS,
1567 AR_RTC_STATUS_M,
1568 AR_RTC_STATUS_ON,
1569 AH_WAIT_TIMEOUT)) {
1570 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1571 return false;
1572 }
1573
1574 ath9k_hw_read_revisions(ah);
1575
1576 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1577 }
1578
1579 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1580 {
1581 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1582 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1583
1584 switch (type) {
1585 case ATH9K_RESET_POWER_ON:
1586 return ath9k_hw_set_reset_power_on(ah);
1587 break;
1588 case ATH9K_RESET_WARM:
1589 case ATH9K_RESET_COLD:
1590 return ath9k_hw_set_reset(ah, type);
1591 break;
1592 default:
1593 return false;
1594 }
1595 }
1596
1597 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1598 enum ath9k_ht_macmode macmode)
1599 {
1600 u32 phymode;
1601 u32 enableDacFifo = 0;
1602
1603 if (AR_SREV_9285_10_OR_LATER(ah))
1604 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1605 AR_PHY_FC_ENABLE_DAC_FIFO);
1606
1607 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1608 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1609
1610 if (IS_CHAN_HT40(chan)) {
1611 phymode |= AR_PHY_FC_DYN2040_EN;
1612
1613 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1614 (chan->chanmode == CHANNEL_G_HT40PLUS))
1615 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1616
1617 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1618 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1619 }
1620 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1621
1622 ath9k_hw_set11nmac2040(ah, macmode);
1623
1624 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1625 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1626 }
1627
1628 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1629 struct ath9k_channel *chan)
1630 {
1631 if (OLC_FOR_AR9280_20_LATER) {
1632 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1633 return false;
1634 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1635 return false;
1636
1637 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1638 return false;
1639
1640 ah->chip_fullsleep = false;
1641 ath9k_hw_init_pll(ah, chan);
1642 ath9k_hw_set_rfmode(ah, chan);
1643
1644 return true;
1645 }
1646
1647 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1648 struct ath9k_channel *chan,
1649 enum ath9k_ht_macmode macmode)
1650 {
1651 struct ieee80211_channel *channel = chan->chan;
1652 u32 synthDelay, qnum;
1653
1654 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1655 if (ath9k_hw_numtxpending(ah, qnum)) {
1656 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1657 "Transmit frames pending on queue %d\n", qnum);
1658 return false;
1659 }
1660 }
1661
1662 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1663 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1664 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1665 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1666 "Could not kill baseband RX\n");
1667 return false;
1668 }
1669
1670 ath9k_hw_set_regs(ah, chan, macmode);
1671
1672 if (AR_SREV_9280_10_OR_LATER(ah)) {
1673 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1674 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1675 "failed to set channel\n");
1676 return false;
1677 }
1678 } else {
1679 if (!(ath9k_hw_set_channel(ah, chan))) {
1680 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1681 "failed to set channel\n");
1682 return false;
1683 }
1684 }
1685
1686 if (ah->eep_ops->set_txpower(ah, chan,
1687 ath9k_regd_get_ctl(ah, chan),
1688 channel->max_antenna_gain * 2,
1689 channel->max_power * 2,
1690 min((u32) MAX_RATE_POWER,
1691 (u32) ah->regulatory.power_limit)) != 0) {
1692 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1693 "error init'ing transmit power\n");
1694 return false;
1695 }
1696
1697 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1698 if (IS_CHAN_B(chan))
1699 synthDelay = (4 * synthDelay) / 22;
1700 else
1701 synthDelay /= 10;
1702
1703 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1704
1705 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1706
1707 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1708 ath9k_hw_set_delta_slope(ah, chan);
1709
1710 if (AR_SREV_9280_10_OR_LATER(ah))
1711 ath9k_hw_9280_spur_mitigate(ah, chan);
1712 else
1713 ath9k_hw_spur_mitigate(ah, chan);
1714
1715 if (!chan->oneTimeCalsDone)
1716 chan->oneTimeCalsDone = true;
1717
1718 return true;
1719 }
1720
1721 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1722 {
1723 int bb_spur = AR_NO_SPUR;
1724 int freq;
1725 int bin, cur_bin;
1726 int bb_spur_off, spur_subchannel_sd;
1727 int spur_freq_sd;
1728 int spur_delta_phase;
1729 int denominator;
1730 int upper, lower, cur_vit_mask;
1731 int tmp, newVal;
1732 int i;
1733 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1734 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1735 };
1736 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1737 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1738 };
1739 int inc[4] = { 0, 100, 0, 0 };
1740 struct chan_centers centers;
1741
1742 int8_t mask_m[123];
1743 int8_t mask_p[123];
1744 int8_t mask_amt;
1745 int tmp_mask;
1746 int cur_bb_spur;
1747 bool is2GHz = IS_CHAN_2GHZ(chan);
1748
1749 memset(&mask_m, 0, sizeof(int8_t) * 123);
1750 memset(&mask_p, 0, sizeof(int8_t) * 123);
1751
1752 ath9k_hw_get_channel_centers(ah, chan, &centers);
1753 freq = centers.synth_center;
1754
1755 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1756 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1757 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1758
1759 if (is2GHz)
1760 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1761 else
1762 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1763
1764 if (AR_NO_SPUR == cur_bb_spur)
1765 break;
1766 cur_bb_spur = cur_bb_spur - freq;
1767
1768 if (IS_CHAN_HT40(chan)) {
1769 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1770 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1771 bb_spur = cur_bb_spur;
1772 break;
1773 }
1774 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1775 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1776 bb_spur = cur_bb_spur;
1777 break;
1778 }
1779 }
1780
1781 if (AR_NO_SPUR == bb_spur) {
1782 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1783 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1784 return;
1785 } else {
1786 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1787 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1788 }
1789
1790 bin = bb_spur * 320;
1791
1792 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1793
1794 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1795 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1796 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1797 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1798 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1799
1800 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1801 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1802 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1803 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1804 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1805 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1806
1807 if (IS_CHAN_HT40(chan)) {
1808 if (bb_spur < 0) {
1809 spur_subchannel_sd = 1;
1810 bb_spur_off = bb_spur + 10;
1811 } else {
1812 spur_subchannel_sd = 0;
1813 bb_spur_off = bb_spur - 10;
1814 }
1815 } else {
1816 spur_subchannel_sd = 0;
1817 bb_spur_off = bb_spur;
1818 }
1819
1820 if (IS_CHAN_HT40(chan))
1821 spur_delta_phase =
1822 ((bb_spur * 262144) /
1823 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1824 else
1825 spur_delta_phase =
1826 ((bb_spur * 524288) /
1827 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1828
1829 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1830 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1831
1832 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1833 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1834 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1835 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1836
1837 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1838 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1839
1840 cur_bin = -6000;
1841 upper = bin + 100;
1842 lower = bin - 100;
1843
1844 for (i = 0; i < 4; i++) {
1845 int pilot_mask = 0;
1846 int chan_mask = 0;
1847 int bp = 0;
1848 for (bp = 0; bp < 30; bp++) {
1849 if ((cur_bin > lower) && (cur_bin < upper)) {
1850 pilot_mask = pilot_mask | 0x1 << bp;
1851 chan_mask = chan_mask | 0x1 << bp;
1852 }
1853 cur_bin += 100;
1854 }
1855 cur_bin += inc[i];
1856 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1857 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1858 }
1859
1860 cur_vit_mask = 6100;
1861 upper = bin + 120;
1862 lower = bin - 120;
1863
1864 for (i = 0; i < 123; i++) {
1865 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1866
1867 /* workaround for gcc bug #37014 */
1868 volatile int tmp_v = abs(cur_vit_mask - bin);
1869
1870 if (tmp_v < 75)
1871 mask_amt = 1;
1872 else
1873 mask_amt = 0;
1874 if (cur_vit_mask < 0)
1875 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1876 else
1877 mask_p[cur_vit_mask / 100] = mask_amt;
1878 }
1879 cur_vit_mask -= 100;
1880 }
1881
1882 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1883 | (mask_m[48] << 26) | (mask_m[49] << 24)
1884 | (mask_m[50] << 22) | (mask_m[51] << 20)
1885 | (mask_m[52] << 18) | (mask_m[53] << 16)
1886 | (mask_m[54] << 14) | (mask_m[55] << 12)
1887 | (mask_m[56] << 10) | (mask_m[57] << 8)
1888 | (mask_m[58] << 6) | (mask_m[59] << 4)
1889 | (mask_m[60] << 2) | (mask_m[61] << 0);
1890 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1891 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1892
1893 tmp_mask = (mask_m[31] << 28)
1894 | (mask_m[32] << 26) | (mask_m[33] << 24)
1895 | (mask_m[34] << 22) | (mask_m[35] << 20)
1896 | (mask_m[36] << 18) | (mask_m[37] << 16)
1897 | (mask_m[48] << 14) | (mask_m[39] << 12)
1898 | (mask_m[40] << 10) | (mask_m[41] << 8)
1899 | (mask_m[42] << 6) | (mask_m[43] << 4)
1900 | (mask_m[44] << 2) | (mask_m[45] << 0);
1901 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1902 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1903
1904 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1905 | (mask_m[18] << 26) | (mask_m[18] << 24)
1906 | (mask_m[20] << 22) | (mask_m[20] << 20)
1907 | (mask_m[22] << 18) | (mask_m[22] << 16)
1908 | (mask_m[24] << 14) | (mask_m[24] << 12)
1909 | (mask_m[25] << 10) | (mask_m[26] << 8)
1910 | (mask_m[27] << 6) | (mask_m[28] << 4)
1911 | (mask_m[29] << 2) | (mask_m[30] << 0);
1912 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1913 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1914
1915 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1916 | (mask_m[2] << 26) | (mask_m[3] << 24)
1917 | (mask_m[4] << 22) | (mask_m[5] << 20)
1918 | (mask_m[6] << 18) | (mask_m[7] << 16)
1919 | (mask_m[8] << 14) | (mask_m[9] << 12)
1920 | (mask_m[10] << 10) | (mask_m[11] << 8)
1921 | (mask_m[12] << 6) | (mask_m[13] << 4)
1922 | (mask_m[14] << 2) | (mask_m[15] << 0);
1923 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1924 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1925
1926 tmp_mask = (mask_p[15] << 28)
1927 | (mask_p[14] << 26) | (mask_p[13] << 24)
1928 | (mask_p[12] << 22) | (mask_p[11] << 20)
1929 | (mask_p[10] << 18) | (mask_p[9] << 16)
1930 | (mask_p[8] << 14) | (mask_p[7] << 12)
1931 | (mask_p[6] << 10) | (mask_p[5] << 8)
1932 | (mask_p[4] << 6) | (mask_p[3] << 4)
1933 | (mask_p[2] << 2) | (mask_p[1] << 0);
1934 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1935 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1936
1937 tmp_mask = (mask_p[30] << 28)
1938 | (mask_p[29] << 26) | (mask_p[28] << 24)
1939 | (mask_p[27] << 22) | (mask_p[26] << 20)
1940 | (mask_p[25] << 18) | (mask_p[24] << 16)
1941 | (mask_p[23] << 14) | (mask_p[22] << 12)
1942 | (mask_p[21] << 10) | (mask_p[20] << 8)
1943 | (mask_p[19] << 6) | (mask_p[18] << 4)
1944 | (mask_p[17] << 2) | (mask_p[16] << 0);
1945 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1946 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1947
1948 tmp_mask = (mask_p[45] << 28)
1949 | (mask_p[44] << 26) | (mask_p[43] << 24)
1950 | (mask_p[42] << 22) | (mask_p[41] << 20)
1951 | (mask_p[40] << 18) | (mask_p[39] << 16)
1952 | (mask_p[38] << 14) | (mask_p[37] << 12)
1953 | (mask_p[36] << 10) | (mask_p[35] << 8)
1954 | (mask_p[34] << 6) | (mask_p[33] << 4)
1955 | (mask_p[32] << 2) | (mask_p[31] << 0);
1956 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1957 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1958
1959 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1960 | (mask_p[59] << 26) | (mask_p[58] << 24)
1961 | (mask_p[57] << 22) | (mask_p[56] << 20)
1962 | (mask_p[55] << 18) | (mask_p[54] << 16)
1963 | (mask_p[53] << 14) | (mask_p[52] << 12)
1964 | (mask_p[51] << 10) | (mask_p[50] << 8)
1965 | (mask_p[49] << 6) | (mask_p[48] << 4)
1966 | (mask_p[47] << 2) | (mask_p[46] << 0);
1967 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1968 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1969 }
1970
1971 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1972 {
1973 int bb_spur = AR_NO_SPUR;
1974 int bin, cur_bin;
1975 int spur_freq_sd;
1976 int spur_delta_phase;
1977 int denominator;
1978 int upper, lower, cur_vit_mask;
1979 int tmp, new;
1980 int i;
1981 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1982 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1983 };
1984 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1985 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1986 };
1987 int inc[4] = { 0, 100, 0, 0 };
1988
1989 int8_t mask_m[123];
1990 int8_t mask_p[123];
1991 int8_t mask_amt;
1992 int tmp_mask;
1993 int cur_bb_spur;
1994 bool is2GHz = IS_CHAN_2GHZ(chan);
1995
1996 memset(&mask_m, 0, sizeof(int8_t) * 123);
1997 memset(&mask_p, 0, sizeof(int8_t) * 123);
1998
1999 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2000 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2001 if (AR_NO_SPUR == cur_bb_spur)
2002 break;
2003 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2004 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2005 bb_spur = cur_bb_spur;
2006 break;
2007 }
2008 }
2009
2010 if (AR_NO_SPUR == bb_spur)
2011 return;
2012
2013 bin = bb_spur * 32;
2014
2015 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2016 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2017 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2018 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2019 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2020
2021 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2022
2023 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2024 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2025 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2026 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2027 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2028 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2029
2030 spur_delta_phase = ((bb_spur * 524288) / 100) &
2031 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2032
2033 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2034 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2035
2036 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2037 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2038 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2039 REG_WRITE(ah, AR_PHY_TIMING11, new);
2040
2041 cur_bin = -6000;
2042 upper = bin + 100;
2043 lower = bin - 100;
2044
2045 for (i = 0; i < 4; i++) {
2046 int pilot_mask = 0;
2047 int chan_mask = 0;
2048 int bp = 0;
2049 for (bp = 0; bp < 30; bp++) {
2050 if ((cur_bin > lower) && (cur_bin < upper)) {
2051 pilot_mask = pilot_mask | 0x1 << bp;
2052 chan_mask = chan_mask | 0x1 << bp;
2053 }
2054 cur_bin += 100;
2055 }
2056 cur_bin += inc[i];
2057 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2058 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2059 }
2060
2061 cur_vit_mask = 6100;
2062 upper = bin + 120;
2063 lower = bin - 120;
2064
2065 for (i = 0; i < 123; i++) {
2066 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2067
2068 /* workaround for gcc bug #37014 */
2069 volatile int tmp_v = abs(cur_vit_mask - bin);
2070
2071 if (tmp_v < 75)
2072 mask_amt = 1;
2073 else
2074 mask_amt = 0;
2075 if (cur_vit_mask < 0)
2076 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2077 else
2078 mask_p[cur_vit_mask / 100] = mask_amt;
2079 }
2080 cur_vit_mask -= 100;
2081 }
2082
2083 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2084 | (mask_m[48] << 26) | (mask_m[49] << 24)
2085 | (mask_m[50] << 22) | (mask_m[51] << 20)
2086 | (mask_m[52] << 18) | (mask_m[53] << 16)
2087 | (mask_m[54] << 14) | (mask_m[55] << 12)
2088 | (mask_m[56] << 10) | (mask_m[57] << 8)
2089 | (mask_m[58] << 6) | (mask_m[59] << 4)
2090 | (mask_m[60] << 2) | (mask_m[61] << 0);
2091 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2092 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2093
2094 tmp_mask = (mask_m[31] << 28)
2095 | (mask_m[32] << 26) | (mask_m[33] << 24)
2096 | (mask_m[34] << 22) | (mask_m[35] << 20)
2097 | (mask_m[36] << 18) | (mask_m[37] << 16)
2098 | (mask_m[48] << 14) | (mask_m[39] << 12)
2099 | (mask_m[40] << 10) | (mask_m[41] << 8)
2100 | (mask_m[42] << 6) | (mask_m[43] << 4)
2101 | (mask_m[44] << 2) | (mask_m[45] << 0);
2102 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2103 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2104
2105 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2106 | (mask_m[18] << 26) | (mask_m[18] << 24)
2107 | (mask_m[20] << 22) | (mask_m[20] << 20)
2108 | (mask_m[22] << 18) | (mask_m[22] << 16)
2109 | (mask_m[24] << 14) | (mask_m[24] << 12)
2110 | (mask_m[25] << 10) | (mask_m[26] << 8)
2111 | (mask_m[27] << 6) | (mask_m[28] << 4)
2112 | (mask_m[29] << 2) | (mask_m[30] << 0);
2113 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2114 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2115
2116 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2117 | (mask_m[2] << 26) | (mask_m[3] << 24)
2118 | (mask_m[4] << 22) | (mask_m[5] << 20)
2119 | (mask_m[6] << 18) | (mask_m[7] << 16)
2120 | (mask_m[8] << 14) | (mask_m[9] << 12)
2121 | (mask_m[10] << 10) | (mask_m[11] << 8)
2122 | (mask_m[12] << 6) | (mask_m[13] << 4)
2123 | (mask_m[14] << 2) | (mask_m[15] << 0);
2124 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2125 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2126
2127 tmp_mask = (mask_p[15] << 28)
2128 | (mask_p[14] << 26) | (mask_p[13] << 24)
2129 | (mask_p[12] << 22) | (mask_p[11] << 20)
2130 | (mask_p[10] << 18) | (mask_p[9] << 16)
2131 | (mask_p[8] << 14) | (mask_p[7] << 12)
2132 | (mask_p[6] << 10) | (mask_p[5] << 8)
2133 | (mask_p[4] << 6) | (mask_p[3] << 4)
2134 | (mask_p[2] << 2) | (mask_p[1] << 0);
2135 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2136 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2137
2138 tmp_mask = (mask_p[30] << 28)
2139 | (mask_p[29] << 26) | (mask_p[28] << 24)
2140 | (mask_p[27] << 22) | (mask_p[26] << 20)
2141 | (mask_p[25] << 18) | (mask_p[24] << 16)
2142 | (mask_p[23] << 14) | (mask_p[22] << 12)
2143 | (mask_p[21] << 10) | (mask_p[20] << 8)
2144 | (mask_p[19] << 6) | (mask_p[18] << 4)
2145 | (mask_p[17] << 2) | (mask_p[16] << 0);
2146 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2147 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2148
2149 tmp_mask = (mask_p[45] << 28)
2150 | (mask_p[44] << 26) | (mask_p[43] << 24)
2151 | (mask_p[42] << 22) | (mask_p[41] << 20)
2152 | (mask_p[40] << 18) | (mask_p[39] << 16)
2153 | (mask_p[38] << 14) | (mask_p[37] << 12)
2154 | (mask_p[36] << 10) | (mask_p[35] << 8)
2155 | (mask_p[34] << 6) | (mask_p[33] << 4)
2156 | (mask_p[32] << 2) | (mask_p[31] << 0);
2157 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2158 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2159
2160 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2161 | (mask_p[59] << 26) | (mask_p[58] << 24)
2162 | (mask_p[57] << 22) | (mask_p[56] << 20)
2163 | (mask_p[55] << 18) | (mask_p[54] << 16)
2164 | (mask_p[53] << 14) | (mask_p[52] << 12)
2165 | (mask_p[51] << 10) | (mask_p[50] << 8)
2166 | (mask_p[49] << 6) | (mask_p[48] << 4)
2167 | (mask_p[47] << 2) | (mask_p[46] << 0);
2168 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2169 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2170 }
2171
2172 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2173 bool bChannelChange)
2174 {
2175 u32 saveLedState;
2176 struct ath_softc *sc = ah->ah_sc;
2177 struct ath9k_channel *curchan = ah->curchan;
2178 u32 saveDefAntenna;
2179 u32 macStaId1;
2180 int i, rx_chainmask, r;
2181
2182 ah->extprotspacing = sc->ht_extprotspacing;
2183 ah->txchainmask = sc->tx_chainmask;
2184 ah->rxchainmask = sc->rx_chainmask;
2185
2186 if (AR_SREV_9285(ah)) {
2187 ah->txchainmask &= 0x1;
2188 ah->rxchainmask &= 0x1;
2189 } else if (AR_SREV_9280(ah)) {
2190 ah->txchainmask &= 0x3;
2191 ah->rxchainmask &= 0x3;
2192 }
2193
2194 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2195 return -EIO;
2196
2197 if (curchan)
2198 ath9k_hw_getnf(ah, curchan);
2199
2200 if (bChannelChange &&
2201 (ah->chip_fullsleep != true) &&
2202 (ah->curchan != NULL) &&
2203 (chan->channel != ah->curchan->channel) &&
2204 ((chan->channelFlags & CHANNEL_ALL) ==
2205 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2206 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2207 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2208
2209 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2210 ath9k_hw_loadnf(ah, ah->curchan);
2211 ath9k_hw_start_nfcal(ah);
2212 return 0;
2213 }
2214 }
2215
2216 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2217 if (saveDefAntenna == 0)
2218 saveDefAntenna = 1;
2219
2220 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2221
2222 saveLedState = REG_READ(ah, AR_CFG_LED) &
2223 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2224 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2225
2226 ath9k_hw_mark_phy_inactive(ah);
2227
2228 if (!ath9k_hw_chip_reset(ah, chan)) {
2229 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2230 return -EINVAL;
2231 }
2232
2233 if (AR_SREV_9280_10_OR_LATER(ah))
2234 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2235
2236 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2237 if (r)
2238 return r;
2239
2240 /* Setup MFP options for CCMP */
2241 if (AR_SREV_9280_20_OR_LATER(ah)) {
2242 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2243 * frames when constructing CCMP AAD. */
2244 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2245 0xc7ff);
2246 ah->sw_mgmt_crypto = false;
2247 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2248 /* Disable hardware crypto for management frames */
2249 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2250 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2251 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2252 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2253 ah->sw_mgmt_crypto = true;
2254 } else
2255 ah->sw_mgmt_crypto = true;
2256
2257 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2258 ath9k_hw_set_delta_slope(ah, chan);
2259
2260 if (AR_SREV_9280_10_OR_LATER(ah))
2261 ath9k_hw_9280_spur_mitigate(ah, chan);
2262 else
2263 ath9k_hw_spur_mitigate(ah, chan);
2264
2265 if (!ah->eep_ops->set_board_values(ah, chan)) {
2266 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2267 "error setting board options\n");
2268 return -EIO;
2269 }
2270
2271 ath9k_hw_decrease_chain_power(ah, chan);
2272
2273 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2274 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2275 | macStaId1
2276 | AR_STA_ID1_RTS_USE_DEF
2277 | (ah->config.
2278 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2279 | ah->sta_id1_defaults);
2280 ath9k_hw_set_operating_mode(ah, ah->opmode);
2281
2282 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2283 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2284
2285 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2286
2287 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2288 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2289 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2290
2291 REG_WRITE(ah, AR_ISR, ~0);
2292
2293 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2294
2295 if (AR_SREV_9280_10_OR_LATER(ah)) {
2296 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2297 return -EIO;
2298 } else {
2299 if (!(ath9k_hw_set_channel(ah, chan)))
2300 return -EIO;
2301 }
2302
2303 for (i = 0; i < AR_NUM_DCU; i++)
2304 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2305
2306 ah->intr_txqs = 0;
2307 for (i = 0; i < ah->caps.total_queues; i++)
2308 ath9k_hw_resettxqueue(ah, i);
2309
2310 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2311 ath9k_hw_init_qos(ah);
2312
2313 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2314 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2315 ath9k_enable_rfkill(ah);
2316 #endif
2317 ath9k_hw_init_user_settings(ah);
2318
2319 REG_WRITE(ah, AR_STA_ID1,
2320 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2321
2322 ath9k_hw_set_dma(ah);
2323
2324 REG_WRITE(ah, AR_OBS, 8);
2325
2326 if (ah->intr_mitigation) {
2327
2328 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2329 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2330 }
2331
2332 ath9k_hw_init_bb(ah, chan);
2333
2334 if (!ath9k_hw_init_cal(ah, chan))
2335 return -EIO;;
2336
2337 rx_chainmask = ah->rxchainmask;
2338 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2339 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2340 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2341 }
2342
2343 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2344
2345 if (AR_SREV_9100(ah)) {
2346 u32 mask;
2347 mask = REG_READ(ah, AR_CFG);
2348 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2349 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2350 "CFG Byte Swap Set 0x%x\n", mask);
2351 } else {
2352 mask =
2353 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2354 REG_WRITE(ah, AR_CFG, mask);
2355 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2356 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2357 }
2358 } else {
2359 #ifdef __BIG_ENDIAN
2360 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2361 #endif
2362 }
2363
2364 return 0;
2365 }
2366
2367 /************************/
2368 /* Key Cache Management */
2369 /************************/
2370
2371 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2372 {
2373 u32 keyType;
2374
2375 if (entry >= ah->caps.keycache_size) {
2376 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2377 "entry %u out of range\n", entry);
2378 return false;
2379 }
2380
2381 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2382
2383 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2384 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2385 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2386 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2387 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2388 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2389 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2390 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2391
2392 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2393 u16 micentry = entry + 64;
2394
2395 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2396 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2397 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2398 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2399
2400 }
2401
2402 if (ah->curchan == NULL)
2403 return true;
2404
2405 return true;
2406 }
2407
2408 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2409 {
2410 u32 macHi, macLo;
2411
2412 if (entry >= ah->caps.keycache_size) {
2413 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2414 "entry %u out of range\n", entry);
2415 return false;
2416 }
2417
2418 if (mac != NULL) {
2419 macHi = (mac[5] << 8) | mac[4];
2420 macLo = (mac[3] << 24) |
2421 (mac[2] << 16) |
2422 (mac[1] << 8) |
2423 mac[0];
2424 macLo >>= 1;
2425 macLo |= (macHi & 1) << 31;
2426 macHi >>= 1;
2427 } else {
2428 macLo = macHi = 0;
2429 }
2430 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2431 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2432
2433 return true;
2434 }
2435
2436 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2437 const struct ath9k_keyval *k,
2438 const u8 *mac)
2439 {
2440 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2441 u32 key0, key1, key2, key3, key4;
2442 u32 keyType;
2443
2444 if (entry >= pCap->keycache_size) {
2445 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2446 "entry %u out of range\n", entry);
2447 return false;
2448 }
2449
2450 switch (k->kv_type) {
2451 case ATH9K_CIPHER_AES_OCB:
2452 keyType = AR_KEYTABLE_TYPE_AES;
2453 break;
2454 case ATH9K_CIPHER_AES_CCM:
2455 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2456 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2457 "AES-CCM not supported by mac rev 0x%x\n",
2458 ah->hw_version.macRev);
2459 return false;
2460 }
2461 keyType = AR_KEYTABLE_TYPE_CCM;
2462 break;
2463 case ATH9K_CIPHER_TKIP:
2464 keyType = AR_KEYTABLE_TYPE_TKIP;
2465 if (ATH9K_IS_MIC_ENABLED(ah)
2466 && entry + 64 >= pCap->keycache_size) {
2467 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2468 "entry %u inappropriate for TKIP\n", entry);
2469 return false;
2470 }
2471 break;
2472 case ATH9K_CIPHER_WEP:
2473 if (k->kv_len < LEN_WEP40) {
2474 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2475 "WEP key length %u too small\n", k->kv_len);
2476 return false;
2477 }
2478 if (k->kv_len <= LEN_WEP40)
2479 keyType = AR_KEYTABLE_TYPE_40;
2480 else if (k->kv_len <= LEN_WEP104)
2481 keyType = AR_KEYTABLE_TYPE_104;
2482 else
2483 keyType = AR_KEYTABLE_TYPE_128;
2484 break;
2485 case ATH9K_CIPHER_CLR:
2486 keyType = AR_KEYTABLE_TYPE_CLR;
2487 break;
2488 default:
2489 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2490 "cipher %u not supported\n", k->kv_type);
2491 return false;
2492 }
2493
2494 key0 = get_unaligned_le32(k->kv_val + 0);
2495 key1 = get_unaligned_le16(k->kv_val + 4);
2496 key2 = get_unaligned_le32(k->kv_val + 6);
2497 key3 = get_unaligned_le16(k->kv_val + 10);
2498 key4 = get_unaligned_le32(k->kv_val + 12);
2499 if (k->kv_len <= LEN_WEP104)
2500 key4 &= 0xff;
2501
2502 /*
2503 * Note: Key cache registers access special memory area that requires
2504 * two 32-bit writes to actually update the values in the internal
2505 * memory. Consequently, the exact order and pairs used here must be
2506 * maintained.
2507 */
2508
2509 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2510 u16 micentry = entry + 64;
2511
2512 /*
2513 * Write inverted key[47:0] first to avoid Michael MIC errors
2514 * on frames that could be sent or received at the same time.
2515 * The correct key will be written in the end once everything
2516 * else is ready.
2517 */
2518 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2519 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2520
2521 /* Write key[95:48] */
2522 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2523 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2524
2525 /* Write key[127:96] and key type */
2526 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2527 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2528
2529 /* Write MAC address for the entry */
2530 (void) ath9k_hw_keysetmac(ah, entry, mac);
2531
2532 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2533 /*
2534 * TKIP uses two key cache entries:
2535 * Michael MIC TX/RX keys in the same key cache entry
2536 * (idx = main index + 64):
2537 * key0 [31:0] = RX key [31:0]
2538 * key1 [15:0] = TX key [31:16]
2539 * key1 [31:16] = reserved
2540 * key2 [31:0] = RX key [63:32]
2541 * key3 [15:0] = TX key [15:0]
2542 * key3 [31:16] = reserved
2543 * key4 [31:0] = TX key [63:32]
2544 */
2545 u32 mic0, mic1, mic2, mic3, mic4;
2546
2547 mic0 = get_unaligned_le32(k->kv_mic + 0);
2548 mic2 = get_unaligned_le32(k->kv_mic + 4);
2549 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2550 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2551 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2552
2553 /* Write RX[31:0] and TX[31:16] */
2554 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2555 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2556
2557 /* Write RX[63:32] and TX[15:0] */
2558 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2559 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2560
2561 /* Write TX[63:32] and keyType(reserved) */
2562 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2563 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2564 AR_KEYTABLE_TYPE_CLR);
2565
2566 } else {
2567 /*
2568 * TKIP uses four key cache entries (two for group
2569 * keys):
2570 * Michael MIC TX/RX keys are in different key cache
2571 * entries (idx = main index + 64 for TX and
2572 * main index + 32 + 96 for RX):
2573 * key0 [31:0] = TX/RX MIC key [31:0]
2574 * key1 [31:0] = reserved
2575 * key2 [31:0] = TX/RX MIC key [63:32]
2576 * key3 [31:0] = reserved
2577 * key4 [31:0] = reserved
2578 *
2579 * Upper layer code will call this function separately
2580 * for TX and RX keys when these registers offsets are
2581 * used.
2582 */
2583 u32 mic0, mic2;
2584
2585 mic0 = get_unaligned_le32(k->kv_mic + 0);
2586 mic2 = get_unaligned_le32(k->kv_mic + 4);
2587
2588 /* Write MIC key[31:0] */
2589 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2590 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2591
2592 /* Write MIC key[63:32] */
2593 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2594 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2595
2596 /* Write TX[63:32] and keyType(reserved) */
2597 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2598 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2599 AR_KEYTABLE_TYPE_CLR);
2600 }
2601
2602 /* MAC address registers are reserved for the MIC entry */
2603 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2604 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2605
2606 /*
2607 * Write the correct (un-inverted) key[47:0] last to enable
2608 * TKIP now that all other registers are set with correct
2609 * values.
2610 */
2611 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2612 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2613 } else {
2614 /* Write key[47:0] */
2615 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2616 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2617
2618 /* Write key[95:48] */
2619 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2620 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2621
2622 /* Write key[127:96] and key type */
2623 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2624 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2625
2626 /* Write MAC address for the entry */
2627 (void) ath9k_hw_keysetmac(ah, entry, mac);
2628 }
2629
2630 return true;
2631 }
2632
2633 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2634 {
2635 if (entry < ah->caps.keycache_size) {
2636 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2637 if (val & AR_KEYTABLE_VALID)
2638 return true;
2639 }
2640 return false;
2641 }
2642
2643 /******************************/
2644 /* Power Management (Chipset) */
2645 /******************************/
2646
2647 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2648 {
2649 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2650 if (setChip) {
2651 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2652 AR_RTC_FORCE_WAKE_EN);
2653 if (!AR_SREV_9100(ah))
2654 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2655
2656 REG_CLR_BIT(ah, (AR_RTC_RESET),
2657 AR_RTC_RESET_EN);
2658 }
2659 }
2660
2661 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2662 {
2663 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2664 if (setChip) {
2665 struct ath9k_hw_capabilities *pCap = &ah->caps;
2666
2667 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2668 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2669 AR_RTC_FORCE_WAKE_ON_INT);
2670 } else {
2671 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2672 AR_RTC_FORCE_WAKE_EN);
2673 }
2674 }
2675 }
2676
2677 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2678 {
2679 u32 val;
2680 int i;
2681
2682 if (setChip) {
2683 if ((REG_READ(ah, AR_RTC_STATUS) &
2684 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2685 if (ath9k_hw_set_reset_reg(ah,
2686 ATH9K_RESET_POWER_ON) != true) {
2687 return false;
2688 }
2689 }
2690 if (AR_SREV_9100(ah))
2691 REG_SET_BIT(ah, AR_RTC_RESET,
2692 AR_RTC_RESET_EN);
2693
2694 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2695 AR_RTC_FORCE_WAKE_EN);
2696 udelay(50);
2697
2698 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2699 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2700 if (val == AR_RTC_STATUS_ON)
2701 break;
2702 udelay(50);
2703 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2704 AR_RTC_FORCE_WAKE_EN);
2705 }
2706 if (i == 0) {
2707 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2708 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2709 return false;
2710 }
2711 }
2712
2713 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2714
2715 return true;
2716 }
2717
2718 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2719 {
2720 int status = true, setChip = true;
2721 static const char *modes[] = {
2722 "AWAKE",
2723 "FULL-SLEEP",
2724 "NETWORK SLEEP",
2725 "UNDEFINED"
2726 };
2727
2728 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2729 modes[ah->power_mode], modes[mode],
2730 setChip ? "set chip " : "");
2731
2732 switch (mode) {
2733 case ATH9K_PM_AWAKE:
2734 status = ath9k_hw_set_power_awake(ah, setChip);
2735 break;
2736 case ATH9K_PM_FULL_SLEEP:
2737 ath9k_set_power_sleep(ah, setChip);
2738 ah->chip_fullsleep = true;
2739 break;
2740 case ATH9K_PM_NETWORK_SLEEP:
2741 ath9k_set_power_network_sleep(ah, setChip);
2742 break;
2743 default:
2744 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2745 "Unknown power mode %u\n", mode);
2746 return false;
2747 }
2748 ah->power_mode = mode;
2749
2750 return status;
2751 }
2752
2753 /*
2754 * Helper for ASPM support.
2755 *
2756 * Disable PLL when in L0s as well as receiver clock when in L1.
2757 * This power saving option must be enabled through the SerDes.
2758 *
2759 * Programming the SerDes must go through the same 288 bit serial shift
2760 * register as the other analog registers. Hence the 9 writes.
2761 */
2762 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2763 {
2764 u8 i;
2765
2766 if (ah->is_pciexpress != true)
2767 return;
2768
2769 /* Do not touch SerDes registers */
2770 if (ah->config.pcie_powersave_enable == 2)
2771 return;
2772
2773 /* Nothing to do on restore for 11N */
2774 if (restore)
2775 return;
2776
2777 if (AR_SREV_9280_20_OR_LATER(ah)) {
2778 /*
2779 * AR9280 2.0 or later chips use SerDes values from the
2780 * initvals.h initialized depending on chipset during
2781 * ath9k_hw_do_attach()
2782 */
2783 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2784 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2785 INI_RA(&ah->iniPcieSerdes, i, 1));
2786 }
2787 } else if (AR_SREV_9280(ah) &&
2788 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2789 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2790 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2791
2792 /* RX shut off when elecidle is asserted */
2793 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2794 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2795 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2796
2797 /* Shut off CLKREQ active in L1 */
2798 if (ah->config.pcie_clock_req)
2799 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2800 else
2801 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2802
2803 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2804 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2805 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2806
2807 /* Load the new settings */
2808 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2809
2810 } else {
2811 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2812 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2813
2814 /* RX shut off when elecidle is asserted */
2815 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2816 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2817 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2818
2819 /*
2820 * Ignore ah->ah_config.pcie_clock_req setting for
2821 * pre-AR9280 11n
2822 */
2823 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2824
2825 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2826 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2827 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2828
2829 /* Load the new settings */
2830 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2831 }
2832
2833 udelay(1000);
2834
2835 /* set bit 19 to allow forcing of pcie core into L1 state */
2836 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2837
2838 /* Several PCIe massages to ensure proper behaviour */
2839 if (ah->config.pcie_waen) {
2840 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2841 } else {
2842 if (AR_SREV_9285(ah))
2843 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2844 /*
2845 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2846 * otherwise card may disappear.
2847 */
2848 else if (AR_SREV_9280(ah))
2849 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2850 else
2851 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2852 }
2853 }
2854
2855 /**********************/
2856 /* Interrupt Handling */
2857 /**********************/
2858
2859 bool ath9k_hw_intrpend(struct ath_hw *ah)
2860 {
2861 u32 host_isr;
2862
2863 if (AR_SREV_9100(ah))
2864 return true;
2865
2866 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2867 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2868 return true;
2869
2870 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2871 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2872 && (host_isr != AR_INTR_SPURIOUS))
2873 return true;
2874
2875 return false;
2876 }
2877
2878 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2879 {
2880 u32 isr = 0;
2881 u32 mask2 = 0;
2882 struct ath9k_hw_capabilities *pCap = &ah->caps;
2883 u32 sync_cause = 0;
2884 bool fatal_int = false;
2885
2886 if (!AR_SREV_9100(ah)) {
2887 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2888 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2889 == AR_RTC_STATUS_ON) {
2890 isr = REG_READ(ah, AR_ISR);
2891 }
2892 }
2893
2894 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2895 AR_INTR_SYNC_DEFAULT;
2896
2897 *masked = 0;
2898
2899 if (!isr && !sync_cause)
2900 return false;
2901 } else {
2902 *masked = 0;
2903 isr = REG_READ(ah, AR_ISR);
2904 }
2905
2906 if (isr) {
2907 if (isr & AR_ISR_BCNMISC) {
2908 u32 isr2;
2909 isr2 = REG_READ(ah, AR_ISR_S2);
2910 if (isr2 & AR_ISR_S2_TIM)
2911 mask2 |= ATH9K_INT_TIM;
2912 if (isr2 & AR_ISR_S2_DTIM)
2913 mask2 |= ATH9K_INT_DTIM;
2914 if (isr2 & AR_ISR_S2_DTIMSYNC)
2915 mask2 |= ATH9K_INT_DTIMSYNC;
2916 if (isr2 & (AR_ISR_S2_CABEND))
2917 mask2 |= ATH9K_INT_CABEND;
2918 if (isr2 & AR_ISR_S2_GTT)
2919 mask2 |= ATH9K_INT_GTT;
2920 if (isr2 & AR_ISR_S2_CST)
2921 mask2 |= ATH9K_INT_CST;
2922 if (isr2 & AR_ISR_S2_TSFOOR)
2923 mask2 |= ATH9K_INT_TSFOOR;
2924 }
2925
2926 isr = REG_READ(ah, AR_ISR_RAC);
2927 if (isr == 0xffffffff) {
2928 *masked = 0;
2929 return false;
2930 }
2931
2932 *masked = isr & ATH9K_INT_COMMON;
2933
2934 if (ah->intr_mitigation) {
2935 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2936 *masked |= ATH9K_INT_RX;
2937 }
2938
2939 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2940 *masked |= ATH9K_INT_RX;
2941 if (isr &
2942 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2943 AR_ISR_TXEOL)) {
2944 u32 s0_s, s1_s;
2945
2946 *masked |= ATH9K_INT_TX;
2947
2948 s0_s = REG_READ(ah, AR_ISR_S0_S);
2949 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2950 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2951
2952 s1_s = REG_READ(ah, AR_ISR_S1_S);
2953 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2954 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2955 }
2956
2957 if (isr & AR_ISR_RXORN) {
2958 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2959 "receive FIFO overrun interrupt\n");
2960 }
2961
2962 if (!AR_SREV_9100(ah)) {
2963 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2964 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2965 if (isr5 & AR_ISR_S5_TIM_TIMER)
2966 *masked |= ATH9K_INT_TIM_TIMER;
2967 }
2968 }
2969
2970 *masked |= mask2;
2971 }
2972
2973 if (AR_SREV_9100(ah))
2974 return true;
2975
2976 if (sync_cause) {
2977 fatal_int =
2978 (sync_cause &
2979 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2980 ? true : false;
2981
2982 if (fatal_int) {
2983 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2984 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2985 "received PCI FATAL interrupt\n");
2986 }
2987 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2988 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2989 "received PCI PERR interrupt\n");
2990 }
2991 }
2992 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2993 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2994 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2995 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2996 REG_WRITE(ah, AR_RC, 0);
2997 *masked |= ATH9K_INT_FATAL;
2998 }
2999 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3000 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3001 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3002 }
3003
3004 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3005 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3006 }
3007
3008 return true;
3009 }
3010
3011 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3012 {
3013 return ah->mask_reg;
3014 }
3015
3016 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3017 {
3018 u32 omask = ah->mask_reg;
3019 u32 mask, mask2;
3020 struct ath9k_hw_capabilities *pCap = &ah->caps;
3021
3022 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3023
3024 if (omask & ATH9K_INT_GLOBAL) {
3025 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3026 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3027 (void) REG_READ(ah, AR_IER);
3028 if (!AR_SREV_9100(ah)) {
3029 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3030 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3031
3032 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3033 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3034 }
3035 }
3036
3037 mask = ints & ATH9K_INT_COMMON;
3038 mask2 = 0;
3039
3040 if (ints & ATH9K_INT_TX) {
3041 if (ah->txok_interrupt_mask)
3042 mask |= AR_IMR_TXOK;
3043 if (ah->txdesc_interrupt_mask)
3044 mask |= AR_IMR_TXDESC;
3045 if (ah->txerr_interrupt_mask)
3046 mask |= AR_IMR_TXERR;
3047 if (ah->txeol_interrupt_mask)
3048 mask |= AR_IMR_TXEOL;
3049 }
3050 if (ints & ATH9K_INT_RX) {
3051 mask |= AR_IMR_RXERR;
3052 if (ah->intr_mitigation)
3053 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3054 else
3055 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3056 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3057 mask |= AR_IMR_GENTMR;
3058 }
3059
3060 if (ints & (ATH9K_INT_BMISC)) {
3061 mask |= AR_IMR_BCNMISC;
3062 if (ints & ATH9K_INT_TIM)
3063 mask2 |= AR_IMR_S2_TIM;
3064 if (ints & ATH9K_INT_DTIM)
3065 mask2 |= AR_IMR_S2_DTIM;
3066 if (ints & ATH9K_INT_DTIMSYNC)
3067 mask2 |= AR_IMR_S2_DTIMSYNC;
3068 if (ints & ATH9K_INT_CABEND)
3069 mask2 |= AR_IMR_S2_CABEND;
3070 if (ints & ATH9K_INT_TSFOOR)
3071 mask2 |= AR_IMR_S2_TSFOOR;
3072 }
3073
3074 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3075 mask |= AR_IMR_BCNMISC;
3076 if (ints & ATH9K_INT_GTT)
3077 mask2 |= AR_IMR_S2_GTT;
3078 if (ints & ATH9K_INT_CST)
3079 mask2 |= AR_IMR_S2_CST;
3080 }
3081
3082 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3083 REG_WRITE(ah, AR_IMR, mask);
3084 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3085 AR_IMR_S2_DTIM |
3086 AR_IMR_S2_DTIMSYNC |
3087 AR_IMR_S2_CABEND |
3088 AR_IMR_S2_CABTO |
3089 AR_IMR_S2_TSFOOR |
3090 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3091 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3092 ah->mask_reg = ints;
3093
3094 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3095 if (ints & ATH9K_INT_TIM_TIMER)
3096 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3097 else
3098 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3099 }
3100
3101 if (ints & ATH9K_INT_GLOBAL) {
3102 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3103 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3104 if (!AR_SREV_9100(ah)) {
3105 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3106 AR_INTR_MAC_IRQ);
3107 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3108
3109
3110 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3111 AR_INTR_SYNC_DEFAULT);
3112 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3113 AR_INTR_SYNC_DEFAULT);
3114 }
3115 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3116 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3117 }
3118
3119 return omask;
3120 }
3121
3122 /*******************/
3123 /* Beacon Handling */
3124 /*******************/
3125
3126 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3127 {
3128 int flags = 0;
3129
3130 ah->beacon_interval = beacon_period;
3131
3132 switch (ah->opmode) {
3133 case NL80211_IFTYPE_STATION:
3134 case NL80211_IFTYPE_MONITOR:
3135 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3136 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3137 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3138 flags |= AR_TBTT_TIMER_EN;
3139 break;
3140 case NL80211_IFTYPE_ADHOC:
3141 REG_SET_BIT(ah, AR_TXCFG,
3142 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3143 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3144 TU_TO_USEC(next_beacon +
3145 (ah->atim_window ? ah->
3146 atim_window : 1)));
3147 flags |= AR_NDP_TIMER_EN;
3148 case NL80211_IFTYPE_AP:
3149 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3150 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3151 TU_TO_USEC(next_beacon -
3152 ah->config.
3153 dma_beacon_response_time));
3154 REG_WRITE(ah, AR_NEXT_SWBA,
3155 TU_TO_USEC(next_beacon -
3156 ah->config.
3157 sw_beacon_response_time));
3158 flags |=
3159 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3160 break;
3161 default:
3162 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3163 "%s: unsupported opmode: %d\n",
3164 __func__, ah->opmode);
3165 return;
3166 break;
3167 }
3168
3169 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3170 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3171 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3172 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3173
3174 beacon_period &= ~ATH9K_BEACON_ENA;
3175 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3176 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3177 ath9k_hw_reset_tsf(ah);
3178 }
3179
3180 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3181 }
3182
3183 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3184 const struct ath9k_beacon_state *bs)
3185 {
3186 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3187 struct ath9k_hw_capabilities *pCap = &ah->caps;
3188
3189 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3190
3191 REG_WRITE(ah, AR_BEACON_PERIOD,
3192 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3193 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3194 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3195
3196 REG_RMW_FIELD(ah, AR_RSSI_THR,
3197 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3198
3199 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3200
3201 if (bs->bs_sleepduration > beaconintval)
3202 beaconintval = bs->bs_sleepduration;
3203
3204 dtimperiod = bs->bs_dtimperiod;
3205 if (bs->bs_sleepduration > dtimperiod)
3206 dtimperiod = bs->bs_sleepduration;
3207
3208 if (beaconintval == dtimperiod)
3209 nextTbtt = bs->bs_nextdtim;
3210 else
3211 nextTbtt = bs->bs_nexttbtt;
3212
3213 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3214 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3215 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3216 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3217
3218 REG_WRITE(ah, AR_NEXT_DTIM,
3219 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3220 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3221
3222 REG_WRITE(ah, AR_SLEEP1,
3223 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3224 | AR_SLEEP1_ASSUME_DTIM);
3225
3226 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3227 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3228 else
3229 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3230
3231 REG_WRITE(ah, AR_SLEEP2,
3232 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3233
3234 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3235 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3236
3237 REG_SET_BIT(ah, AR_TIMER_MODE,
3238 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3239 AR_DTIM_TIMER_EN);
3240
3241 /* TSF Out of Range Threshold */
3242 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3243 }
3244
3245 /*******************/
3246 /* HW Capabilities */
3247 /*******************/
3248
3249 bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3250 {
3251 struct ath9k_hw_capabilities *pCap = &ah->caps;
3252 u16 capField = 0, eeval;
3253
3254 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3255 ah->regulatory.current_rd = eeval;
3256
3257 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3258 if (AR_SREV_9285_10_OR_LATER(ah))
3259 eeval |= AR9285_RDEXT_DEFAULT;
3260 ah->regulatory.current_rd_ext = eeval;
3261
3262 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3263
3264 if (ah->opmode != NL80211_IFTYPE_AP &&
3265 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3266 if (ah->regulatory.current_rd == 0x64 ||
3267 ah->regulatory.current_rd == 0x65)
3268 ah->regulatory.current_rd += 5;
3269 else if (ah->regulatory.current_rd == 0x41)
3270 ah->regulatory.current_rd = 0x43;
3271 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3272 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3273 }
3274
3275 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3276 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3277
3278 if (eeval & AR5416_OPFLAGS_11A) {
3279 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3280 if (ah->config.ht_enable) {
3281 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3282 set_bit(ATH9K_MODE_11NA_HT20,
3283 pCap->wireless_modes);
3284 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3285 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3286 pCap->wireless_modes);
3287 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3288 pCap->wireless_modes);
3289 }
3290 }
3291 }
3292
3293 if (eeval & AR5416_OPFLAGS_11G) {
3294 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3295 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3296 if (ah->config.ht_enable) {
3297 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3298 set_bit(ATH9K_MODE_11NG_HT20,
3299 pCap->wireless_modes);
3300 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3301 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3302 pCap->wireless_modes);
3303 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3304 pCap->wireless_modes);
3305 }
3306 }
3307 }
3308
3309 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3310 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3311 !(eeval & AR5416_OPFLAGS_11A))
3312 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3313 else
3314 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3315
3316 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3317 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3318
3319 pCap->low_2ghz_chan = 2312;
3320 pCap->high_2ghz_chan = 2732;
3321
3322 pCap->low_5ghz_chan = 4920;
3323 pCap->high_5ghz_chan = 6100;
3324
3325 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3326 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3327 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3328
3329 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3330 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3331 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3332
3333 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3334
3335 if (ah->config.ht_enable)
3336 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3337 else
3338 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3339
3340 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3341 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3342 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3343 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3344
3345 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3346 pCap->total_queues =
3347 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3348 else
3349 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3350
3351 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3352 pCap->keycache_size =
3353 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3354 else
3355 pCap->keycache_size = AR_KEYTABLE_SIZE;
3356
3357 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3358 pCap->num_mr_retries = 4;
3359 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3360
3361 if (AR_SREV_9285_10_OR_LATER(ah))
3362 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3363 else if (AR_SREV_9280_10_OR_LATER(ah))
3364 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3365 else
3366 pCap->num_gpio_pins = AR_NUM_GPIO;
3367
3368 if (AR_SREV_9280_10_OR_LATER(ah)) {
3369 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3370 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3371 } else {
3372 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3373 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3374 }
3375
3376 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3377 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3378 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3379 } else {
3380 pCap->rts_aggr_limit = (8 * 1024);
3381 }
3382
3383 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3384
3385 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3386 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3387 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3388 ah->rfkill_gpio =
3389 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3390 ah->rfkill_polarity =
3391 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3392
3393 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3394 }
3395 #endif
3396
3397 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3398 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3399 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3400 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3401 (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3402 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3403 else
3404 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3405
3406 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3407 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3408 else
3409 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3410
3411 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3412 pCap->reg_cap =
3413 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3414 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3415 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3416 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3417 } else {
3418 pCap->reg_cap =
3419 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3420 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3421 }
3422
3423 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3424
3425 pCap->num_antcfg_5ghz =
3426 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3427 pCap->num_antcfg_2ghz =
3428 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3429
3430 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3431 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3432 ah->btactive_gpio = 6;
3433 ah->wlanactive_gpio = 5;
3434 }
3435
3436 return true;
3437 }
3438
3439 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3440 u32 capability, u32 *result)
3441 {
3442 switch (type) {
3443 case ATH9K_CAP_CIPHER:
3444 switch (capability) {
3445 case ATH9K_CIPHER_AES_CCM:
3446 case ATH9K_CIPHER_AES_OCB:
3447 case ATH9K_CIPHER_TKIP:
3448 case ATH9K_CIPHER_WEP:
3449 case ATH9K_CIPHER_MIC:
3450 case ATH9K_CIPHER_CLR:
3451 return true;
3452 default:
3453 return false;
3454 }
3455 case ATH9K_CAP_TKIP_MIC:
3456 switch (capability) {
3457 case 0:
3458 return true;
3459 case 1:
3460 return (ah->sta_id1_defaults &
3461 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3462 false;
3463 }
3464 case ATH9K_CAP_TKIP_SPLIT:
3465 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3466 false : true;
3467 case ATH9K_CAP_DIVERSITY:
3468 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3469 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3470 true : false;
3471 case ATH9K_CAP_MCAST_KEYSRCH:
3472 switch (capability) {
3473 case 0:
3474 return true;
3475 case 1:
3476 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3477 return false;
3478 } else {
3479 return (ah->sta_id1_defaults &
3480 AR_STA_ID1_MCAST_KSRCH) ? true :
3481 false;
3482 }
3483 }
3484 return false;
3485 case ATH9K_CAP_TXPOW:
3486 switch (capability) {
3487 case 0:
3488 return 0;
3489 case 1:
3490 *result = ah->regulatory.power_limit;
3491 return 0;
3492 case 2:
3493 *result = ah->regulatory.max_power_level;
3494 return 0;
3495 case 3:
3496 *result = ah->regulatory.tp_scale;
3497 return 0;
3498 }
3499 return false;
3500 case ATH9K_CAP_DS:
3501 return (AR_SREV_9280_20_OR_LATER(ah) &&
3502 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3503 ? false : true;
3504 default:
3505 return false;
3506 }
3507 }
3508
3509 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3510 u32 capability, u32 setting, int *status)
3511 {
3512 u32 v;
3513
3514 switch (type) {
3515 case ATH9K_CAP_TKIP_MIC:
3516 if (setting)
3517 ah->sta_id1_defaults |=
3518 AR_STA_ID1_CRPT_MIC_ENABLE;
3519 else
3520 ah->sta_id1_defaults &=
3521 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3522 return true;
3523 case ATH9K_CAP_DIVERSITY:
3524 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3525 if (setting)
3526 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3527 else
3528 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3529 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3530 return true;
3531 case ATH9K_CAP_MCAST_KEYSRCH:
3532 if (setting)
3533 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3534 else
3535 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3536 return true;
3537 default:
3538 return false;
3539 }
3540 }
3541
3542 /****************************/
3543 /* GPIO / RFKILL / Antennae */
3544 /****************************/
3545
3546 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3547 u32 gpio, u32 type)
3548 {
3549 int addr;
3550 u32 gpio_shift, tmp;
3551
3552 if (gpio > 11)
3553 addr = AR_GPIO_OUTPUT_MUX3;
3554 else if (gpio > 5)
3555 addr = AR_GPIO_OUTPUT_MUX2;
3556 else
3557 addr = AR_GPIO_OUTPUT_MUX1;
3558
3559 gpio_shift = (gpio % 6) * 5;
3560
3561 if (AR_SREV_9280_20_OR_LATER(ah)
3562 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3563 REG_RMW(ah, addr, (type << gpio_shift),
3564 (0x1f << gpio_shift));
3565 } else {
3566 tmp = REG_READ(ah, addr);
3567 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3568 tmp &= ~(0x1f << gpio_shift);
3569 tmp |= (type << gpio_shift);
3570 REG_WRITE(ah, addr, tmp);
3571 }
3572 }
3573
3574 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3575 {
3576 u32 gpio_shift;
3577
3578 ASSERT(gpio < ah->caps.num_gpio_pins);
3579
3580 gpio_shift = gpio << 1;
3581
3582 REG_RMW(ah,
3583 AR_GPIO_OE_OUT,
3584 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3585 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3586 }
3587
3588 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3589 {
3590 #define MS_REG_READ(x, y) \
3591 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3592
3593 if (gpio >= ah->caps.num_gpio_pins)
3594 return 0xffffffff;
3595
3596 if (AR_SREV_9285_10_OR_LATER(ah))
3597 return MS_REG_READ(AR9285, gpio) != 0;
3598 else if (AR_SREV_9280_10_OR_LATER(ah))
3599 return MS_REG_READ(AR928X, gpio) != 0;
3600 else
3601 return MS_REG_READ(AR, gpio) != 0;
3602 }
3603
3604 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3605 u32 ah_signal_type)
3606 {
3607 u32 gpio_shift;
3608
3609 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3610
3611 gpio_shift = 2 * gpio;
3612
3613 REG_RMW(ah,
3614 AR_GPIO_OE_OUT,
3615 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3616 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3617 }
3618
3619 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3620 {
3621 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3622 AR_GPIO_BIT(gpio));
3623 }
3624
3625 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3626 void ath9k_enable_rfkill(struct ath_hw *ah)
3627 {
3628 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3629 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3630
3631 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3632 AR_GPIO_INPUT_MUX2_RFSILENT);
3633
3634 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3635 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3636 }
3637 #endif
3638
3639 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3640 {
3641 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3642 }
3643
3644 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3645 {
3646 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3647 }
3648
3649 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3650 enum ath9k_ant_setting settings,
3651 struct ath9k_channel *chan,
3652 u8 *tx_chainmask,
3653 u8 *rx_chainmask,
3654 u8 *antenna_cfgd)
3655 {
3656 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3657
3658 if (AR_SREV_9280(ah)) {
3659 if (!tx_chainmask_cfg) {
3660
3661 tx_chainmask_cfg = *tx_chainmask;
3662 rx_chainmask_cfg = *rx_chainmask;
3663 }
3664
3665 switch (settings) {
3666 case ATH9K_ANT_FIXED_A:
3667 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3668 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3669 *antenna_cfgd = true;
3670 break;
3671 case ATH9K_ANT_FIXED_B:
3672 if (ah->caps.tx_chainmask >
3673 ATH9K_ANTENNA1_CHAINMASK) {
3674 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3675 }
3676 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3677 *antenna_cfgd = true;
3678 break;
3679 case ATH9K_ANT_VARIABLE:
3680 *tx_chainmask = tx_chainmask_cfg;
3681 *rx_chainmask = rx_chainmask_cfg;
3682 *antenna_cfgd = true;
3683 break;
3684 default:
3685 break;
3686 }
3687 } else {
3688 ah->diversity_control = settings;
3689 }
3690
3691 return true;
3692 }
3693
3694 /*********************/
3695 /* General Operation */
3696 /*********************/
3697
3698 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3699 {
3700 u32 bits = REG_READ(ah, AR_RX_FILTER);
3701 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3702
3703 if (phybits & AR_PHY_ERR_RADAR)
3704 bits |= ATH9K_RX_FILTER_PHYRADAR;
3705 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3706 bits |= ATH9K_RX_FILTER_PHYERR;
3707
3708 return bits;
3709 }
3710
3711 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3712 {
3713 u32 phybits;
3714
3715 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3716 phybits = 0;
3717 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3718 phybits |= AR_PHY_ERR_RADAR;
3719 if (bits & ATH9K_RX_FILTER_PHYERR)
3720 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3721 REG_WRITE(ah, AR_PHY_ERR, phybits);
3722
3723 if (phybits)
3724 REG_WRITE(ah, AR_RXCFG,
3725 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3726 else
3727 REG_WRITE(ah, AR_RXCFG,
3728 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3729 }
3730
3731 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3732 {
3733 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3734 }
3735
3736 bool ath9k_hw_disable(struct ath_hw *ah)
3737 {
3738 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3739 return false;
3740
3741 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3742 }
3743
3744 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3745 {
3746 struct ath9k_channel *chan = ah->curchan;
3747 struct ieee80211_channel *channel = chan->chan;
3748
3749 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3750
3751 if (ah->eep_ops->set_txpower(ah, chan,
3752 ath9k_regd_get_ctl(ah, chan),
3753 channel->max_antenna_gain * 2,
3754 channel->max_power * 2,
3755 min((u32) MAX_RATE_POWER,
3756 (u32) ah->regulatory.power_limit)) != 0)
3757 return false;
3758
3759 return true;
3760 }
3761
3762 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3763 {
3764 memcpy(ah->macaddr, mac, ETH_ALEN);
3765 }
3766
3767 void ath9k_hw_setopmode(struct ath_hw *ah)
3768 {
3769 ath9k_hw_set_operating_mode(ah, ah->opmode);
3770 }
3771
3772 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3773 {
3774 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3775 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3776 }
3777
3778 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3779 {
3780 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3781 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3782 }
3783
3784 void ath9k_hw_write_associd(struct ath_softc *sc)
3785 {
3786 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3787 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3788 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3789 }
3790
3791 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3792 {
3793 u64 tsf;
3794
3795 tsf = REG_READ(ah, AR_TSF_U32);
3796 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3797
3798 return tsf;
3799 }
3800
3801 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3802 {
3803 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3804 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3805 }
3806
3807 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3808 {
3809 int count;
3810
3811 count = 0;
3812 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3813 count++;
3814 if (count > 10) {
3815 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3816 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3817 break;
3818 }
3819 udelay(10);
3820 }
3821 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3822 }
3823
3824 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3825 {
3826 if (setting)
3827 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3828 else
3829 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3830
3831 return true;
3832 }
3833
3834 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3835 {
3836 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3837 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3838 ah->slottime = (u32) -1;
3839 return false;
3840 } else {
3841 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3842 ah->slottime = us;
3843 return true;
3844 }
3845 }
3846
3847 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3848 {
3849 u32 macmode;
3850
3851 if (mode == ATH9K_HT_MACMODE_2040 &&
3852 !ah->config.cwm_ignore_extcca)
3853 macmode = AR_2040_JOINED_RX_CLEAR;
3854 else
3855 macmode = 0;
3856
3857 REG_WRITE(ah, AR_2040_MODE, macmode);
3858 }
3859
3860 /***************************/
3861 /* Bluetooth Coexistence */
3862 /***************************/
3863
3864 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3865 {
3866 /* connect bt_active to baseband */
3867 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3868 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3869 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3870
3871 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3872 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3873
3874 /* Set input mux for bt_active to gpio pin */
3875 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3876 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3877 ah->btactive_gpio);
3878
3879 /* Configure the desired gpio port for input */
3880 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3881
3882 /* Configure the desired GPIO port for TX_FRAME output */
3883 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3884 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3885 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree