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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
blob335119a5687abf1788ee836e80fb73b9e6fb3519
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/ipv6.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42
43 #include "ixgbe.h"
44 #include "ixgbe_common.h"
45
46 char ixgbe_driver_name[] = "ixgbe";
47 static const char ixgbe_driver_string[] =
48 "Intel(R) 10 Gigabit PCI Express Network Driver";
49
50 #define DRV_VERSION "2.0.8-k2"
51 const char ixgbe_driver_version[] = DRV_VERSION;
52 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
53
54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
55 [board_82598] = &ixgbe_82598_info,
56 [board_82599] = &ixgbe_82599_info,
57 };
58
59 /* ixgbe_pci_tbl - PCI Device ID Table
60 *
61 * Wildcard entries (PCI_ANY_ID) should come last
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67 static struct pci_device_id ixgbe_pci_tbl[] = {
68 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 board_82598 },
70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
71 board_82598 },
72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
73 board_82598 },
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 board_82598 },
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
77 board_82598 },
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 board_82598 },
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91 board_82599 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93 board_82599 },
94
95 /* required last entry */
96 {0, }
97 };
98 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
100 #ifdef CONFIG_IXGBE_DCA
101 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
102 void *p);
103 static struct notifier_block dca_notifier = {
104 .notifier_call = ixgbe_notify_dca,
105 .next = NULL,
106 .priority = 0
107 };
108 #endif
109
110 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112 MODULE_LICENSE("GPL");
113 MODULE_VERSION(DRV_VERSION);
114
115 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
117 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118 {
119 u32 ctrl_ext;
120
121 /* Let firmware take over control of h/w */
122 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
124 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
125 }
126
127 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128 {
129 u32 ctrl_ext;
130
131 /* Let firmware know the driver has taken over */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
134 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
135 }
136
137 /*
138 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139 * @adapter: pointer to adapter struct
140 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141 * @queue: queue to map the corresponding interrupt to
142 * @msix_vector: the vector to map to the corresponding queue
143 *
144 */
145 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146 u8 queue, u8 msix_vector)
147 {
148 u32 ivar, index;
149 struct ixgbe_hw *hw = &adapter->hw;
150 switch (hw->mac.type) {
151 case ixgbe_mac_82598EB:
152 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153 if (direction == -1)
154 direction = 0;
155 index = (((direction * 64) + queue) >> 2) & 0x1F;
156 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158 ivar |= (msix_vector << (8 * (queue & 0x3)));
159 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160 break;
161 case ixgbe_mac_82599EB:
162 if (direction == -1) {
163 /* other causes */
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 index = ((queue & 1) * 8);
166 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167 ivar &= ~(0xFF << index);
168 ivar |= (msix_vector << index);
169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170 break;
171 } else {
172 /* tx or rx causes */
173 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174 index = ((16 * (queue & 1)) + (8 * direction));
175 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176 ivar &= ~(0xFF << index);
177 ivar |= (msix_vector << index);
178 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179 break;
180 }
181 default:
182 break;
183 }
184 }
185
186 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
187 struct ixgbe_tx_buffer
188 *tx_buffer_info)
189 {
190 if (tx_buffer_info->dma) {
191 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
192 tx_buffer_info->length, PCI_DMA_TODEVICE);
193 tx_buffer_info->dma = 0;
194 }
195 if (tx_buffer_info->skb) {
196 dev_kfree_skb_any(tx_buffer_info->skb);
197 tx_buffer_info->skb = NULL;
198 }
199 /* tx_buffer_info must be completely set up in the transmit path */
200 }
201
202 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
203 struct ixgbe_ring *tx_ring,
204 unsigned int eop)
205 {
206 struct ixgbe_hw *hw = &adapter->hw;
207 u32 head, tail;
208
209 /* Detect a transmit hang in hardware, this serializes the
210 * check with the clearing of time_stamp and movement of eop */
211 head = IXGBE_READ_REG(hw, tx_ring->head);
212 tail = IXGBE_READ_REG(hw, tx_ring->tail);
213 adapter->detect_tx_hung = false;
214 if ((head != tail) &&
215 tx_ring->tx_buffer_info[eop].time_stamp &&
216 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
217 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
218 /* detected Tx unit hang */
219 union ixgbe_adv_tx_desc *tx_desc;
220 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
221 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
222 " Tx Queue <%d>\n"
223 " TDH, TDT <%x>, <%x>\n"
224 " next_to_use <%x>\n"
225 " next_to_clean <%x>\n"
226 "tx_buffer_info[next_to_clean]\n"
227 " time_stamp <%lx>\n"
228 " jiffies <%lx>\n",
229 tx_ring->queue_index,
230 head, tail,
231 tx_ring->next_to_use, eop,
232 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
233 return true;
234 }
235
236 return false;
237 }
238
239 #define IXGBE_MAX_TXD_PWR 14
240 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
241
242 /* Tx Descriptors needed, worst case */
243 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
244 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
245 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
246 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
247
248 static void ixgbe_tx_timeout(struct net_device *netdev);
249
250 /**
251 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
252 * @adapter: board private structure
253 * @tx_ring: tx ring to clean
254 *
255 * returns true if transmit work is done
256 **/
257 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
258 struct ixgbe_ring *tx_ring)
259 {
260 struct net_device *netdev = adapter->netdev;
261 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
262 struct ixgbe_tx_buffer *tx_buffer_info;
263 unsigned int i, eop, count = 0;
264 unsigned int total_bytes = 0, total_packets = 0;
265
266 i = tx_ring->next_to_clean;
267 eop = tx_ring->tx_buffer_info[i].next_to_watch;
268 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
269
270 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
271 (count < tx_ring->work_limit)) {
272 bool cleaned = false;
273 for ( ; !cleaned; count++) {
274 struct sk_buff *skb;
275 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
276 tx_buffer_info = &tx_ring->tx_buffer_info[i];
277 cleaned = (i == eop);
278 skb = tx_buffer_info->skb;
279
280 if (cleaned && skb) {
281 unsigned int segs, bytecount;
282
283 /* gso_segs is currently only valid for tcp */
284 segs = skb_shinfo(skb)->gso_segs ?: 1;
285 /* multiply data chunks by size of headers */
286 bytecount = ((segs - 1) * skb_headlen(skb)) +
287 skb->len;
288 total_packets += segs;
289 total_bytes += bytecount;
290 }
291
292 ixgbe_unmap_and_free_tx_resource(adapter,
293 tx_buffer_info);
294
295 tx_desc->wb.status = 0;
296
297 i++;
298 if (i == tx_ring->count)
299 i = 0;
300 }
301
302 eop = tx_ring->tx_buffer_info[i].next_to_watch;
303 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
304 }
305
306 tx_ring->next_to_clean = i;
307
308 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
309 if (unlikely(count && netif_carrier_ok(netdev) &&
310 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
311 /* Make sure that anybody stopping the queue after this
312 * sees the new next_to_clean.
313 */
314 smp_mb();
315 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
316 !test_bit(__IXGBE_DOWN, &adapter->state)) {
317 netif_wake_subqueue(netdev, tx_ring->queue_index);
318 ++adapter->restart_queue;
319 }
320 }
321
322 if (adapter->detect_tx_hung) {
323 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
324 /* schedule immediate reset if we believe we hung */
325 DPRINTK(PROBE, INFO,
326 "tx hang %d detected, resetting adapter\n",
327 adapter->tx_timeout_count + 1);
328 ixgbe_tx_timeout(adapter->netdev);
329 }
330 }
331
332 /* re-arm the interrupt */
333 if (count >= tx_ring->work_limit)
334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
335
336 tx_ring->total_bytes += total_bytes;
337 tx_ring->total_packets += total_packets;
338 tx_ring->stats.packets += total_packets;
339 tx_ring->stats.bytes += total_bytes;
340 adapter->net_stats.tx_bytes += total_bytes;
341 adapter->net_stats.tx_packets += total_packets;
342 return (count < tx_ring->work_limit);
343 }
344
345 #ifdef CONFIG_IXGBE_DCA
346 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
347 struct ixgbe_ring *rx_ring)
348 {
349 u32 rxctrl;
350 int cpu = get_cpu();
351 int q = rx_ring - adapter->rx_ring;
352
353 if (rx_ring->cpu != cpu) {
354 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
355 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
356 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
357 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
358 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
359 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
360 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
361 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
362 }
363 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
364 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
365 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
366 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
367 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
369 rx_ring->cpu = cpu;
370 }
371 put_cpu();
372 }
373
374 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
375 struct ixgbe_ring *tx_ring)
376 {
377 u32 txctrl;
378 int cpu = get_cpu();
379 int q = tx_ring - adapter->tx_ring;
380
381 if (tx_ring->cpu != cpu) {
382 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
383 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
384 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
385 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
386 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
387 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
388 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
389 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
390 }
391 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
393 tx_ring->cpu = cpu;
394 }
395 put_cpu();
396 }
397
398 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
399 {
400 int i;
401
402 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
403 return;
404
405 for (i = 0; i < adapter->num_tx_queues; i++) {
406 adapter->tx_ring[i].cpu = -1;
407 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
408 }
409 for (i = 0; i < adapter->num_rx_queues; i++) {
410 adapter->rx_ring[i].cpu = -1;
411 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
412 }
413 }
414
415 static int __ixgbe_notify_dca(struct device *dev, void *data)
416 {
417 struct net_device *netdev = dev_get_drvdata(dev);
418 struct ixgbe_adapter *adapter = netdev_priv(netdev);
419 unsigned long event = *(unsigned long *)data;
420
421 switch (event) {
422 case DCA_PROVIDER_ADD:
423 /* if we're already enabled, don't do it again */
424 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
425 break;
426 /* Always use CB2 mode, difference is masked
427 * in the CB driver. */
428 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
429 if (dca_add_requester(dev) == 0) {
430 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
431 ixgbe_setup_dca(adapter);
432 break;
433 }
434 /* Fall Through since DCA is disabled. */
435 case DCA_PROVIDER_REMOVE:
436 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
437 dca_remove_requester(dev);
438 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
439 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
440 }
441 break;
442 }
443
444 return 0;
445 }
446
447 #endif /* CONFIG_IXGBE_DCA */
448 /**
449 * ixgbe_receive_skb - Send a completed packet up the stack
450 * @adapter: board private structure
451 * @skb: packet to send up
452 * @status: hardware indication of status of receive
453 * @rx_ring: rx descriptor ring (for a specific queue) to setup
454 * @rx_desc: rx descriptor
455 **/
456 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
457 struct sk_buff *skb, u8 status,
458 union ixgbe_adv_rx_desc *rx_desc)
459 {
460 struct ixgbe_adapter *adapter = q_vector->adapter;
461 struct napi_struct *napi = &q_vector->napi;
462 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
463 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
464
465 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
466 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
467 if (adapter->vlgrp && is_vlan && (tag != 0))
468 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
469 else
470 napi_gro_receive(napi, skb);
471 } else {
472 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
473 if (adapter->vlgrp && is_vlan && (tag != 0))
474 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
475 else
476 netif_receive_skb(skb);
477 } else {
478 if (adapter->vlgrp && is_vlan && (tag != 0))
479 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
480 else
481 netif_rx(skb);
482 }
483 }
484 }
485
486 /**
487 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
488 * @adapter: address of board private structure
489 * @status_err: hardware indication of status of receive
490 * @skb: skb currently being received and modified
491 **/
492 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
493 u32 status_err, struct sk_buff *skb)
494 {
495 skb->ip_summed = CHECKSUM_NONE;
496
497 /* Rx csum disabled */
498 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
499 return;
500
501 /* if IP and error */
502 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
503 (status_err & IXGBE_RXDADV_ERR_IPE)) {
504 adapter->hw_csum_rx_error++;
505 return;
506 }
507
508 if (!(status_err & IXGBE_RXD_STAT_L4CS))
509 return;
510
511 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
512 adapter->hw_csum_rx_error++;
513 return;
514 }
515
516 /* It must be a TCP or UDP packet with a valid checksum */
517 skb->ip_summed = CHECKSUM_UNNECESSARY;
518 adapter->hw_csum_rx_good++;
519 }
520
521 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
522 struct ixgbe_ring *rx_ring, u32 val)
523 {
524 /*
525 * Force memory writes to complete before letting h/w
526 * know there are new descriptors to fetch. (Only
527 * applicable for weak-ordered memory model archs,
528 * such as IA-64).
529 */
530 wmb();
531 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
532 }
533
534 /**
535 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
536 * @adapter: address of board private structure
537 **/
538 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
539 struct ixgbe_ring *rx_ring,
540 int cleaned_count)
541 {
542 struct pci_dev *pdev = adapter->pdev;
543 union ixgbe_adv_rx_desc *rx_desc;
544 struct ixgbe_rx_buffer *bi;
545 unsigned int i;
546 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
547
548 i = rx_ring->next_to_use;
549 bi = &rx_ring->rx_buffer_info[i];
550
551 while (cleaned_count--) {
552 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
553
554 if (!bi->page_dma &&
555 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
556 if (!bi->page) {
557 bi->page = alloc_page(GFP_ATOMIC);
558 if (!bi->page) {
559 adapter->alloc_rx_page_failed++;
560 goto no_buffers;
561 }
562 bi->page_offset = 0;
563 } else {
564 /* use a half page if we're re-using */
565 bi->page_offset ^= (PAGE_SIZE / 2);
566 }
567
568 bi->page_dma = pci_map_page(pdev, bi->page,
569 bi->page_offset,
570 (PAGE_SIZE / 2),
571 PCI_DMA_FROMDEVICE);
572 }
573
574 if (!bi->skb) {
575 struct sk_buff *skb;
576 skb = netdev_alloc_skb(adapter->netdev, bufsz);
577
578 if (!skb) {
579 adapter->alloc_rx_buff_failed++;
580 goto no_buffers;
581 }
582
583 /*
584 * Make buffer alignment 2 beyond a 16 byte boundary
585 * this will result in a 16 byte aligned IP header after
586 * the 14 byte MAC header is removed
587 */
588 skb_reserve(skb, NET_IP_ALIGN);
589
590 bi->skb = skb;
591 bi->dma = pci_map_single(pdev, skb->data, bufsz,
592 PCI_DMA_FROMDEVICE);
593 }
594 /* Refresh the desc even if buffer_addrs didn't change because
595 * each write-back erases this info. */
596 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
597 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
598 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
599 } else {
600 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
601 }
602
603 i++;
604 if (i == rx_ring->count)
605 i = 0;
606 bi = &rx_ring->rx_buffer_info[i];
607 }
608
609 no_buffers:
610 if (rx_ring->next_to_use != i) {
611 rx_ring->next_to_use = i;
612 if (i-- == 0)
613 i = (rx_ring->count - 1);
614
615 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
616 }
617 }
618
619 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
620 {
621 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
622 }
623
624 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
625 {
626 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
627 }
628
629 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
630 struct ixgbe_ring *rx_ring,
631 int *work_done, int work_to_do)
632 {
633 struct ixgbe_adapter *adapter = q_vector->adapter;
634 struct pci_dev *pdev = adapter->pdev;
635 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
636 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
637 struct sk_buff *skb;
638 unsigned int i;
639 u32 len, staterr;
640 u16 hdr_info;
641 bool cleaned = false;
642 int cleaned_count = 0;
643 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
644
645 i = rx_ring->next_to_clean;
646 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
647 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
648 rx_buffer_info = &rx_ring->rx_buffer_info[i];
649
650 while (staterr & IXGBE_RXD_STAT_DD) {
651 u32 upper_len = 0;
652 if (*work_done >= work_to_do)
653 break;
654 (*work_done)++;
655
656 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
657 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
658 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
659 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
660 if (hdr_info & IXGBE_RXDADV_SPH)
661 adapter->rx_hdr_split++;
662 if (len > IXGBE_RX_HDR_SIZE)
663 len = IXGBE_RX_HDR_SIZE;
664 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
665 } else {
666 len = le16_to_cpu(rx_desc->wb.upper.length);
667 }
668
669 cleaned = true;
670 skb = rx_buffer_info->skb;
671 prefetch(skb->data - NET_IP_ALIGN);
672 rx_buffer_info->skb = NULL;
673
674 if (len && !skb_shinfo(skb)->nr_frags) {
675 pci_unmap_single(pdev, rx_buffer_info->dma,
676 rx_ring->rx_buf_len,
677 PCI_DMA_FROMDEVICE);
678 skb_put(skb, len);
679 }
680
681 if (upper_len) {
682 pci_unmap_page(pdev, rx_buffer_info->page_dma,
683 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
684 rx_buffer_info->page_dma = 0;
685 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
686 rx_buffer_info->page,
687 rx_buffer_info->page_offset,
688 upper_len);
689
690 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
691 (page_count(rx_buffer_info->page) != 1))
692 rx_buffer_info->page = NULL;
693 else
694 get_page(rx_buffer_info->page);
695
696 skb->len += upper_len;
697 skb->data_len += upper_len;
698 skb->truesize += upper_len;
699 }
700
701 i++;
702 if (i == rx_ring->count)
703 i = 0;
704 next_buffer = &rx_ring->rx_buffer_info[i];
705
706 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
707 prefetch(next_rxd);
708
709 cleaned_count++;
710 if (staterr & IXGBE_RXD_STAT_EOP) {
711 rx_ring->stats.packets++;
712 rx_ring->stats.bytes += skb->len;
713 } else {
714 rx_buffer_info->skb = next_buffer->skb;
715 rx_buffer_info->dma = next_buffer->dma;
716 next_buffer->skb = skb;
717 next_buffer->dma = 0;
718 adapter->non_eop_descs++;
719 goto next_desc;
720 }
721
722 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
723 dev_kfree_skb_irq(skb);
724 goto next_desc;
725 }
726
727 ixgbe_rx_checksum(adapter, staterr, skb);
728
729 /* probably a little skewed due to removing CRC */
730 total_rx_bytes += skb->len;
731 total_rx_packets++;
732
733 skb->protocol = eth_type_trans(skb, adapter->netdev);
734 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
735
736 next_desc:
737 rx_desc->wb.upper.status_error = 0;
738
739 /* return some buffers to hardware, one at a time is too slow */
740 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
741 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
742 cleaned_count = 0;
743 }
744
745 /* use prefetched values */
746 rx_desc = next_rxd;
747 rx_buffer_info = next_buffer;
748
749 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
750 }
751
752 rx_ring->next_to_clean = i;
753 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
754
755 if (cleaned_count)
756 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
757
758 rx_ring->total_packets += total_rx_packets;
759 rx_ring->total_bytes += total_rx_bytes;
760 adapter->net_stats.rx_bytes += total_rx_bytes;
761 adapter->net_stats.rx_packets += total_rx_packets;
762
763 return cleaned;
764 }
765
766 static int ixgbe_clean_rxonly(struct napi_struct *, int);
767 /**
768 * ixgbe_configure_msix - Configure MSI-X hardware
769 * @adapter: board private structure
770 *
771 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
772 * interrupts.
773 **/
774 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
775 {
776 struct ixgbe_q_vector *q_vector;
777 int i, j, q_vectors, v_idx, r_idx;
778 u32 mask;
779
780 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
781
782 /*
783 * Populate the IVAR table and set the ITR values to the
784 * corresponding register.
785 */
786 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
787 q_vector = &adapter->q_vector[v_idx];
788 /* XXX for_each_bit(...) */
789 r_idx = find_first_bit(q_vector->rxr_idx,
790 adapter->num_rx_queues);
791
792 for (i = 0; i < q_vector->rxr_count; i++) {
793 j = adapter->rx_ring[r_idx].reg_idx;
794 ixgbe_set_ivar(adapter, 0, j, v_idx);
795 r_idx = find_next_bit(q_vector->rxr_idx,
796 adapter->num_rx_queues,
797 r_idx + 1);
798 }
799 r_idx = find_first_bit(q_vector->txr_idx,
800 adapter->num_tx_queues);
801
802 for (i = 0; i < q_vector->txr_count; i++) {
803 j = adapter->tx_ring[r_idx].reg_idx;
804 ixgbe_set_ivar(adapter, 1, j, v_idx);
805 r_idx = find_next_bit(q_vector->txr_idx,
806 adapter->num_tx_queues,
807 r_idx + 1);
808 }
809
810 /* if this is a tx only vector halve the interrupt rate */
811 if (q_vector->txr_count && !q_vector->rxr_count)
812 q_vector->eitr = (adapter->eitr_param >> 1);
813 else if (q_vector->rxr_count)
814 /* rx only */
815 q_vector->eitr = adapter->eitr_param;
816
817 /*
818 * since this is initial set up don't need to call
819 * ixgbe_write_eitr helper
820 */
821 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
822 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
823 }
824
825 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
826 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
827 v_idx);
828 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
829 ixgbe_set_ivar(adapter, -1, 1, v_idx);
830 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
831
832 /* set up to autoclear timer, and the vectors */
833 mask = IXGBE_EIMS_ENABLE_MASK;
834 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
836 }
837
838 enum latency_range {
839 lowest_latency = 0,
840 low_latency = 1,
841 bulk_latency = 2,
842 latency_invalid = 255
843 };
844
845 /**
846 * ixgbe_update_itr - update the dynamic ITR value based on statistics
847 * @adapter: pointer to adapter
848 * @eitr: eitr setting (ints per sec) to give last timeslice
849 * @itr_setting: current throttle rate in ints/second
850 * @packets: the number of packets during this measurement interval
851 * @bytes: the number of bytes during this measurement interval
852 *
853 * Stores a new ITR value based on packets and byte
854 * counts during the last interrupt. The advantage of per interrupt
855 * computation is faster updates and more accurate ITR for the current
856 * traffic pattern. Constants in this function were computed
857 * based on theoretical maximum wire speed and thresholds were set based
858 * on testing data as well as attempting to minimize response time
859 * while increasing bulk throughput.
860 * this functionality is controlled by the InterruptThrottleRate module
861 * parameter (see ixgbe_param.c)
862 **/
863 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
864 u32 eitr, u8 itr_setting,
865 int packets, int bytes)
866 {
867 unsigned int retval = itr_setting;
868 u32 timepassed_us;
869 u64 bytes_perint;
870
871 if (packets == 0)
872 goto update_itr_done;
873
874
875 /* simple throttlerate management
876 * 0-20MB/s lowest (100000 ints/s)
877 * 20-100MB/s low (20000 ints/s)
878 * 100-1249MB/s bulk (8000 ints/s)
879 */
880 /* what was last interrupt timeslice? */
881 timepassed_us = 1000000/eitr;
882 bytes_perint = bytes / timepassed_us; /* bytes/usec */
883
884 switch (itr_setting) {
885 case lowest_latency:
886 if (bytes_perint > adapter->eitr_low)
887 retval = low_latency;
888 break;
889 case low_latency:
890 if (bytes_perint > adapter->eitr_high)
891 retval = bulk_latency;
892 else if (bytes_perint <= adapter->eitr_low)
893 retval = lowest_latency;
894 break;
895 case bulk_latency:
896 if (bytes_perint <= adapter->eitr_high)
897 retval = low_latency;
898 break;
899 }
900
901 update_itr_done:
902 return retval;
903 }
904
905 /**
906 * ixgbe_write_eitr - write EITR register in hardware specific way
907 * @adapter: pointer to adapter struct
908 * @v_idx: vector index into q_vector array
909 * @itr_reg: new value to be written in *register* format, not ints/s
910 *
911 * This function is made to be called by ethtool and by the driver
912 * when it needs to update EITR registers at runtime. Hardware
913 * specific quirks/differences are taken care of here.
914 */
915 void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
916 {
917 struct ixgbe_hw *hw = &adapter->hw;
918 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
919 /* must write high and low 16 bits to reset counter */
920 itr_reg |= (itr_reg << 16);
921 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
922 /*
923 * set the WDIS bit to not clear the timer bits and cause an
924 * immediate assertion of the interrupt
925 */
926 itr_reg |= IXGBE_EITR_CNT_WDIS;
927 }
928 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
929 }
930
931 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
932 {
933 struct ixgbe_adapter *adapter = q_vector->adapter;
934 u32 new_itr;
935 u8 current_itr, ret_itr;
936 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
937 sizeof(struct ixgbe_q_vector);
938 struct ixgbe_ring *rx_ring, *tx_ring;
939
940 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
941 for (i = 0; i < q_vector->txr_count; i++) {
942 tx_ring = &(adapter->tx_ring[r_idx]);
943 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
944 q_vector->tx_itr,
945 tx_ring->total_packets,
946 tx_ring->total_bytes);
947 /* if the result for this queue would decrease interrupt
948 * rate for this vector then use that result */
949 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
950 q_vector->tx_itr - 1 : ret_itr);
951 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
952 r_idx + 1);
953 }
954
955 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
956 for (i = 0; i < q_vector->rxr_count; i++) {
957 rx_ring = &(adapter->rx_ring[r_idx]);
958 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
959 q_vector->rx_itr,
960 rx_ring->total_packets,
961 rx_ring->total_bytes);
962 /* if the result for this queue would decrease interrupt
963 * rate for this vector then use that result */
964 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
965 q_vector->rx_itr - 1 : ret_itr);
966 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
967 r_idx + 1);
968 }
969
970 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
971
972 switch (current_itr) {
973 /* counts and packets in update_itr are dependent on these numbers */
974 case lowest_latency:
975 new_itr = 100000;
976 break;
977 case low_latency:
978 new_itr = 20000; /* aka hwitr = ~200 */
979 break;
980 case bulk_latency:
981 default:
982 new_itr = 8000;
983 break;
984 }
985
986 if (new_itr != q_vector->eitr) {
987 u32 itr_reg;
988
989 /* save the algorithm value here, not the smoothed one */
990 q_vector->eitr = new_itr;
991 /* do an exponential smoothing */
992 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
993 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
994 ixgbe_write_eitr(adapter, v_idx, itr_reg);
995 }
996
997 return;
998 }
999
1000 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1001 {
1002 struct ixgbe_hw *hw = &adapter->hw;
1003
1004 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1005 (eicr & IXGBE_EICR_GPI_SDP1)) {
1006 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1007 /* write to clear the interrupt */
1008 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1009 }
1010 }
1011
1012 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1013 {
1014 struct ixgbe_hw *hw = &adapter->hw;
1015
1016 if (eicr & IXGBE_EICR_GPI_SDP1) {
1017 /* Clear the interrupt */
1018 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1019 schedule_work(&adapter->multispeed_fiber_task);
1020 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1021 /* Clear the interrupt */
1022 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1023 schedule_work(&adapter->sfp_config_module_task);
1024 } else {
1025 /* Interrupt isn't for us... */
1026 return;
1027 }
1028 }
1029
1030 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1031 {
1032 struct ixgbe_hw *hw = &adapter->hw;
1033
1034 adapter->lsc_int++;
1035 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1036 adapter->link_check_timeout = jiffies;
1037 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1038 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1039 schedule_work(&adapter->watchdog_task);
1040 }
1041 }
1042
1043 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1044 {
1045 struct net_device *netdev = data;
1046 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1047 struct ixgbe_hw *hw = &adapter->hw;
1048 u32 eicr;
1049
1050 /*
1051 * Workaround for Silicon errata. Use clear-by-write instead
1052 * of clear-by-read. Reading with EICS will return the
1053 * interrupt causes without clearing, which later be done
1054 * with the write to EICR.
1055 */
1056 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1057 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1058
1059 if (eicr & IXGBE_EICR_LSC)
1060 ixgbe_check_lsc(adapter);
1061
1062 if (hw->mac.type == ixgbe_mac_82598EB)
1063 ixgbe_check_fan_failure(adapter, eicr);
1064
1065 if (hw->mac.type == ixgbe_mac_82599EB)
1066 ixgbe_check_sfp_event(adapter, eicr);
1067 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1068 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1069
1070 return IRQ_HANDLED;
1071 }
1072
1073 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1074 {
1075 struct ixgbe_q_vector *q_vector = data;
1076 struct ixgbe_adapter *adapter = q_vector->adapter;
1077 struct ixgbe_ring *tx_ring;
1078 int i, r_idx;
1079
1080 if (!q_vector->txr_count)
1081 return IRQ_HANDLED;
1082
1083 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1084 for (i = 0; i < q_vector->txr_count; i++) {
1085 tx_ring = &(adapter->tx_ring[r_idx]);
1086 #ifdef CONFIG_IXGBE_DCA
1087 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1088 ixgbe_update_tx_dca(adapter, tx_ring);
1089 #endif
1090 tx_ring->total_bytes = 0;
1091 tx_ring->total_packets = 0;
1092 ixgbe_clean_tx_irq(adapter, tx_ring);
1093 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1094 r_idx + 1);
1095 }
1096
1097 return IRQ_HANDLED;
1098 }
1099
1100 /**
1101 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1102 * @irq: unused
1103 * @data: pointer to our q_vector struct for this interrupt vector
1104 **/
1105 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1106 {
1107 struct ixgbe_q_vector *q_vector = data;
1108 struct ixgbe_adapter *adapter = q_vector->adapter;
1109 struct ixgbe_ring *rx_ring;
1110 int r_idx;
1111 int i;
1112
1113 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1114 for (i = 0; i < q_vector->rxr_count; i++) {
1115 rx_ring = &(adapter->rx_ring[r_idx]);
1116 rx_ring->total_bytes = 0;
1117 rx_ring->total_packets = 0;
1118 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1119 r_idx + 1);
1120 }
1121
1122 if (!q_vector->rxr_count)
1123 return IRQ_HANDLED;
1124
1125 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1126 rx_ring = &(adapter->rx_ring[r_idx]);
1127 /* disable interrupts on this vector only */
1128 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1129 napi_schedule(&q_vector->napi);
1130
1131 return IRQ_HANDLED;
1132 }
1133
1134 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1135 {
1136 ixgbe_msix_clean_rx(irq, data);
1137 ixgbe_msix_clean_tx(irq, data);
1138
1139 return IRQ_HANDLED;
1140 }
1141
1142 /**
1143 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1144 * @napi: napi struct with our devices info in it
1145 * @budget: amount of work driver is allowed to do this pass, in packets
1146 *
1147 * This function is optimized for cleaning one queue only on a single
1148 * q_vector!!!
1149 **/
1150 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1151 {
1152 struct ixgbe_q_vector *q_vector =
1153 container_of(napi, struct ixgbe_q_vector, napi);
1154 struct ixgbe_adapter *adapter = q_vector->adapter;
1155 struct ixgbe_ring *rx_ring = NULL;
1156 int work_done = 0;
1157 long r_idx;
1158
1159 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1160 rx_ring = &(adapter->rx_ring[r_idx]);
1161 #ifdef CONFIG_IXGBE_DCA
1162 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1163 ixgbe_update_rx_dca(adapter, rx_ring);
1164 #endif
1165
1166 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1167
1168 /* If all Rx work done, exit the polling mode */
1169 if (work_done < budget) {
1170 napi_complete(napi);
1171 if (adapter->itr_setting & 1)
1172 ixgbe_set_itr_msix(q_vector);
1173 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1174 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
1175 }
1176
1177 return work_done;
1178 }
1179
1180 /**
1181 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1182 * @napi: napi struct with our devices info in it
1183 * @budget: amount of work driver is allowed to do this pass, in packets
1184 *
1185 * This function will clean more than one rx queue associated with a
1186 * q_vector.
1187 **/
1188 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1189 {
1190 struct ixgbe_q_vector *q_vector =
1191 container_of(napi, struct ixgbe_q_vector, napi);
1192 struct ixgbe_adapter *adapter = q_vector->adapter;
1193 struct ixgbe_ring *rx_ring = NULL;
1194 int work_done = 0, i;
1195 long r_idx;
1196 u16 enable_mask = 0;
1197
1198 /* attempt to distribute budget to each queue fairly, but don't allow
1199 * the budget to go below 1 because we'll exit polling */
1200 budget /= (q_vector->rxr_count ?: 1);
1201 budget = max(budget, 1);
1202 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1203 for (i = 0; i < q_vector->rxr_count; i++) {
1204 rx_ring = &(adapter->rx_ring[r_idx]);
1205 #ifdef CONFIG_IXGBE_DCA
1206 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1207 ixgbe_update_rx_dca(adapter, rx_ring);
1208 #endif
1209 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1210 enable_mask |= rx_ring->v_idx;
1211 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1212 r_idx + 1);
1213 }
1214
1215 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1216 rx_ring = &(adapter->rx_ring[r_idx]);
1217 /* If all Rx work done, exit the polling mode */
1218 if (work_done < budget) {
1219 napi_complete(napi);
1220 if (adapter->itr_setting & 1)
1221 ixgbe_set_itr_msix(q_vector);
1222 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1223 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1224 return 0;
1225 }
1226
1227 return work_done;
1228 }
1229 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1230 int r_idx)
1231 {
1232 a->q_vector[v_idx].adapter = a;
1233 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1234 a->q_vector[v_idx].rxr_count++;
1235 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1236 }
1237
1238 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1239 int r_idx)
1240 {
1241 a->q_vector[v_idx].adapter = a;
1242 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1243 a->q_vector[v_idx].txr_count++;
1244 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1245 }
1246
1247 /**
1248 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1249 * @adapter: board private structure to initialize
1250 * @vectors: allotted vector count for descriptor rings
1251 *
1252 * This function maps descriptor rings to the queue-specific vectors
1253 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1254 * one vector per ring/queue, but on a constrained vector budget, we
1255 * group the rings as "efficiently" as possible. You would add new
1256 * mapping configurations in here.
1257 **/
1258 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1259 int vectors)
1260 {
1261 int v_start = 0;
1262 int rxr_idx = 0, txr_idx = 0;
1263 int rxr_remaining = adapter->num_rx_queues;
1264 int txr_remaining = adapter->num_tx_queues;
1265 int i, j;
1266 int rqpv, tqpv;
1267 int err = 0;
1268
1269 /* No mapping required if MSI-X is disabled. */
1270 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1271 goto out;
1272
1273 /*
1274 * The ideal configuration...
1275 * We have enough vectors to map one per queue.
1276 */
1277 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1278 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1279 map_vector_to_rxq(adapter, v_start, rxr_idx);
1280
1281 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1282 map_vector_to_txq(adapter, v_start, txr_idx);
1283
1284 goto out;
1285 }
1286
1287 /*
1288 * If we don't have enough vectors for a 1-to-1
1289 * mapping, we'll have to group them so there are
1290 * multiple queues per vector.
1291 */
1292 /* Re-adjusting *qpv takes care of the remainder. */
1293 for (i = v_start; i < vectors; i++) {
1294 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1295 for (j = 0; j < rqpv; j++) {
1296 map_vector_to_rxq(adapter, i, rxr_idx);
1297 rxr_idx++;
1298 rxr_remaining--;
1299 }
1300 }
1301 for (i = v_start; i < vectors; i++) {
1302 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1303 for (j = 0; j < tqpv; j++) {
1304 map_vector_to_txq(adapter, i, txr_idx);
1305 txr_idx++;
1306 txr_remaining--;
1307 }
1308 }
1309
1310 out:
1311 return err;
1312 }
1313
1314 /**
1315 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1316 * @adapter: board private structure
1317 *
1318 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1319 * interrupts from the kernel.
1320 **/
1321 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1322 {
1323 struct net_device *netdev = adapter->netdev;
1324 irqreturn_t (*handler)(int, void *);
1325 int i, vector, q_vectors, err;
1326 int ri=0, ti=0;
1327
1328 /* Decrement for Other and TCP Timer vectors */
1329 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1330
1331 /* Map the Tx/Rx rings to the vectors we were allotted. */
1332 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1333 if (err)
1334 goto out;
1335
1336 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1337 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1338 &ixgbe_msix_clean_many)
1339 for (vector = 0; vector < q_vectors; vector++) {
1340 handler = SET_HANDLER(&adapter->q_vector[vector]);
1341
1342 if(handler == &ixgbe_msix_clean_rx) {
1343 sprintf(adapter->name[vector], "%s-%s-%d",
1344 netdev->name, "rx", ri++);
1345 }
1346 else if(handler == &ixgbe_msix_clean_tx) {
1347 sprintf(adapter->name[vector], "%s-%s-%d",
1348 netdev->name, "tx", ti++);
1349 }
1350 else
1351 sprintf(adapter->name[vector], "%s-%s-%d",
1352 netdev->name, "TxRx", vector);
1353
1354 err = request_irq(adapter->msix_entries[vector].vector,
1355 handler, 0, adapter->name[vector],
1356 &(adapter->q_vector[vector]));
1357 if (err) {
1358 DPRINTK(PROBE, ERR,
1359 "request_irq failed for MSIX interrupt "
1360 "Error: %d\n", err);
1361 goto free_queue_irqs;
1362 }
1363 }
1364
1365 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1366 err = request_irq(adapter->msix_entries[vector].vector,
1367 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1368 if (err) {
1369 DPRINTK(PROBE, ERR,
1370 "request_irq for msix_lsc failed: %d\n", err);
1371 goto free_queue_irqs;
1372 }
1373
1374 return 0;
1375
1376 free_queue_irqs:
1377 for (i = vector - 1; i >= 0; i--)
1378 free_irq(adapter->msix_entries[--vector].vector,
1379 &(adapter->q_vector[i]));
1380 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1381 pci_disable_msix(adapter->pdev);
1382 kfree(adapter->msix_entries);
1383 adapter->msix_entries = NULL;
1384 out:
1385 return err;
1386 }
1387
1388 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1389 {
1390 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1391 u8 current_itr;
1392 u32 new_itr = q_vector->eitr;
1393 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1394 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1395
1396 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1397 q_vector->tx_itr,
1398 tx_ring->total_packets,
1399 tx_ring->total_bytes);
1400 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1401 q_vector->rx_itr,
1402 rx_ring->total_packets,
1403 rx_ring->total_bytes);
1404
1405 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1406
1407 switch (current_itr) {
1408 /* counts and packets in update_itr are dependent on these numbers */
1409 case lowest_latency:
1410 new_itr = 100000;
1411 break;
1412 case low_latency:
1413 new_itr = 20000; /* aka hwitr = ~200 */
1414 break;
1415 case bulk_latency:
1416 new_itr = 8000;
1417 break;
1418 default:
1419 break;
1420 }
1421
1422 if (new_itr != q_vector->eitr) {
1423 u32 itr_reg;
1424
1425 /* save the algorithm value here, not the smoothed one */
1426 q_vector->eitr = new_itr;
1427 /* do an exponential smoothing */
1428 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1429 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1430 ixgbe_write_eitr(adapter, 0, itr_reg);
1431 }
1432
1433 return;
1434 }
1435
1436 /**
1437 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1438 * @adapter: board private structure
1439 **/
1440 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1441 {
1442 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1443 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(2), ~0);
1446 }
1447 IXGBE_WRITE_FLUSH(&adapter->hw);
1448 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1449 int i;
1450 for (i = 0; i < adapter->num_msix_vectors; i++)
1451 synchronize_irq(adapter->msix_entries[i].vector);
1452 } else {
1453 synchronize_irq(adapter->pdev->irq);
1454 }
1455 }
1456
1457 /**
1458 * ixgbe_irq_enable - Enable default interrupt generation settings
1459 * @adapter: board private structure
1460 **/
1461 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1462 {
1463 u32 mask;
1464 mask = IXGBE_EIMS_ENABLE_MASK;
1465 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1466 mask |= IXGBE_EIMS_GPI_SDP1;
1467 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1468 mask |= IXGBE_EIMS_ECC;
1469 mask |= IXGBE_EIMS_GPI_SDP1;
1470 mask |= IXGBE_EIMS_GPI_SDP2;
1471 }
1472
1473 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1474 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1475 /* enable the rest of the queue vectors */
1476 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1),
1477 (IXGBE_EIMS_RTX_QUEUE << 16));
1478 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1479 ((IXGBE_EIMS_RTX_QUEUE << 16) |
1480 IXGBE_EIMS_RTX_QUEUE));
1481 }
1482 IXGBE_WRITE_FLUSH(&adapter->hw);
1483 }
1484
1485 /**
1486 * ixgbe_intr - legacy mode Interrupt Handler
1487 * @irq: interrupt number
1488 * @data: pointer to a network interface device structure
1489 **/
1490 static irqreturn_t ixgbe_intr(int irq, void *data)
1491 {
1492 struct net_device *netdev = data;
1493 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1494 struct ixgbe_hw *hw = &adapter->hw;
1495 u32 eicr;
1496
1497 /*
1498 * Workaround for silicon errata. Mask the interrupts
1499 * before the read of EICR.
1500 */
1501 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1502
1503 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1504 * therefore no explict interrupt disable is necessary */
1505 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1506 if (!eicr) {
1507 /* shared interrupt alert!
1508 * make sure interrupts are enabled because the read will
1509 * have disabled interrupts due to EIAM */
1510 ixgbe_irq_enable(adapter);
1511 return IRQ_NONE; /* Not our interrupt */
1512 }
1513
1514 if (eicr & IXGBE_EICR_LSC)
1515 ixgbe_check_lsc(adapter);
1516
1517 if (hw->mac.type == ixgbe_mac_82599EB)
1518 ixgbe_check_sfp_event(adapter, eicr);
1519
1520 ixgbe_check_fan_failure(adapter, eicr);
1521
1522 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
1523 adapter->tx_ring[0].total_packets = 0;
1524 adapter->tx_ring[0].total_bytes = 0;
1525 adapter->rx_ring[0].total_packets = 0;
1526 adapter->rx_ring[0].total_bytes = 0;
1527 /* would disable interrupts here but EIAM disabled it */
1528 __napi_schedule(&adapter->q_vector[0].napi);
1529 }
1530
1531 return IRQ_HANDLED;
1532 }
1533
1534 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1535 {
1536 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1537
1538 for (i = 0; i < q_vectors; i++) {
1539 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1540 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1541 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1542 q_vector->rxr_count = 0;
1543 q_vector->txr_count = 0;
1544 }
1545 }
1546
1547 /**
1548 * ixgbe_request_irq - initialize interrupts
1549 * @adapter: board private structure
1550 *
1551 * Attempts to configure interrupts using the best available
1552 * capabilities of the hardware and kernel.
1553 **/
1554 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1555 {
1556 struct net_device *netdev = adapter->netdev;
1557 int err;
1558
1559 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1560 err = ixgbe_request_msix_irqs(adapter);
1561 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1562 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1563 netdev->name, netdev);
1564 } else {
1565 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1566 netdev->name, netdev);
1567 }
1568
1569 if (err)
1570 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1571
1572 return err;
1573 }
1574
1575 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1576 {
1577 struct net_device *netdev = adapter->netdev;
1578
1579 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1580 int i, q_vectors;
1581
1582 q_vectors = adapter->num_msix_vectors;
1583
1584 i = q_vectors - 1;
1585 free_irq(adapter->msix_entries[i].vector, netdev);
1586
1587 i--;
1588 for (; i >= 0; i--) {
1589 free_irq(adapter->msix_entries[i].vector,
1590 &(adapter->q_vector[i]));
1591 }
1592
1593 ixgbe_reset_q_vectors(adapter);
1594 } else {
1595 free_irq(adapter->pdev->irq, netdev);
1596 }
1597 }
1598
1599 /**
1600 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1601 *
1602 **/
1603 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1604 {
1605 struct ixgbe_hw *hw = &adapter->hw;
1606
1607 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1608 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1609
1610 ixgbe_set_ivar(adapter, 0, 0, 0);
1611 ixgbe_set_ivar(adapter, 1, 0, 0);
1612
1613 map_vector_to_rxq(adapter, 0, 0);
1614 map_vector_to_txq(adapter, 0, 0);
1615
1616 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1617 }
1618
1619 /**
1620 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1621 * @adapter: board private structure
1622 *
1623 * Configure the Tx unit of the MAC after a reset.
1624 **/
1625 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1626 {
1627 u64 tdba;
1628 struct ixgbe_hw *hw = &adapter->hw;
1629 u32 i, j, tdlen, txctrl;
1630
1631 /* Setup the HW Tx Head and Tail descriptor pointers */
1632 for (i = 0; i < adapter->num_tx_queues; i++) {
1633 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1634 j = ring->reg_idx;
1635 tdba = ring->dma;
1636 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1637 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1638 (tdba & DMA_32BIT_MASK));
1639 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1640 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1641 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1642 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1643 adapter->tx_ring[i].head = IXGBE_TDH(j);
1644 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1645 /* Disable Tx Head Writeback RO bit, since this hoses
1646 * bookkeeping if things aren't delivered in order.
1647 */
1648 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1649 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1650 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1651 }
1652 if (hw->mac.type == ixgbe_mac_82599EB) {
1653 /* We enable 8 traffic classes, DCB only */
1654 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1655 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1656 IXGBE_MTQC_8TC_8TQ));
1657 }
1658 }
1659
1660 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1661
1662 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1663 {
1664 struct ixgbe_ring *rx_ring;
1665 u32 srrctl;
1666 int queue0 = 0;
1667 unsigned long mask;
1668
1669 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1670 queue0 = index;
1671 } else {
1672 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1673 queue0 = index & mask;
1674 index = index & mask;
1675 }
1676
1677 rx_ring = &adapter->rx_ring[queue0];
1678
1679 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1680
1681 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1682 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1683
1684 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1685 u16 bufsz = IXGBE_RXBUFFER_2048;
1686 /* grow the amount we can receive on large page machines */
1687 if (bufsz < (PAGE_SIZE / 2))
1688 bufsz = (PAGE_SIZE / 2);
1689 /* cap the bufsz at our largest descriptor size */
1690 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1691
1692 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1693 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1694 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1695 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1696 IXGBE_SRRCTL_BSIZEHDR_MASK);
1697 } else {
1698 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1699
1700 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1701 srrctl |= IXGBE_RXBUFFER_2048 >>
1702 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1703 else
1704 srrctl |= rx_ring->rx_buf_len >>
1705 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1706 }
1707
1708 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1709 }
1710
1711 /**
1712 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1713 * @adapter: board private structure
1714 *
1715 * Configure the Rx unit of the MAC after a reset.
1716 **/
1717 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1718 {
1719 u64 rdba;
1720 struct ixgbe_hw *hw = &adapter->hw;
1721 struct net_device *netdev = adapter->netdev;
1722 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1723 int i, j;
1724 u32 rdlen, rxctrl, rxcsum;
1725 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1726 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1727 0x6A3E67EA, 0x14364D17, 0x3BED200D};
1728 u32 fctrl, hlreg0;
1729 u32 reta = 0, mrqc = 0;
1730 u32 rdrxctl;
1731 int rx_buf_len;
1732
1733 /* Decide whether to use packet split mode or not */
1734 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1735
1736 /* Set the RX buffer length according to the mode */
1737 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1738 rx_buf_len = IXGBE_RX_HDR_SIZE;
1739 if (hw->mac.type == ixgbe_mac_82599EB) {
1740 /* PSRTYPE must be initialized in 82599 */
1741 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1742 IXGBE_PSRTYPE_UDPHDR |
1743 IXGBE_PSRTYPE_IPV4HDR |
1744 IXGBE_PSRTYPE_IPV6HDR;
1745 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1746 }
1747 } else {
1748 if (netdev->mtu <= ETH_DATA_LEN)
1749 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1750 else
1751 rx_buf_len = ALIGN(max_frame, 1024);
1752 }
1753
1754 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1755 fctrl |= IXGBE_FCTRL_BAM;
1756 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1757 fctrl |= IXGBE_FCTRL_PMCF;
1758 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1759
1760 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1761 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1762 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1763 else
1764 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1765 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1766
1767 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1768 /* disable receives while setting up the descriptors */
1769 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1770 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1771
1772 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1773 * the Base and Length of the Rx Descriptor Ring */
1774 for (i = 0; i < adapter->num_rx_queues; i++) {
1775 rdba = adapter->rx_ring[i].dma;
1776 j = adapter->rx_ring[i].reg_idx;
1777 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1778 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1779 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1780 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1781 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1782 adapter->rx_ring[i].head = IXGBE_RDH(j);
1783 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1784 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1785
1786 ixgbe_configure_srrctl(adapter, j);
1787 }
1788
1789 if (hw->mac.type == ixgbe_mac_82598EB) {
1790 /*
1791 * For VMDq support of different descriptor types or
1792 * buffer sizes through the use of multiple SRRCTL
1793 * registers, RDRXCTL.MVMEN must be set to 1
1794 *
1795 * also, the manual doesn't mention it clearly but DCA hints
1796 * will only use queue 0's tags unless this bit is set. Side
1797 * effects of setting this bit are only that SRRCTL must be
1798 * fully programmed [0..15]
1799 */
1800 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1801 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1802 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1803 }
1804
1805 /* Program MRQC for the distribution of queues */
1806 if (hw->mac.type == ixgbe_mac_82599EB) {
1807 int mask = adapter->flags & (
1808 IXGBE_FLAG_RSS_ENABLED
1809 | IXGBE_FLAG_DCB_ENABLED
1810 );
1811
1812 switch (mask) {
1813 case (IXGBE_FLAG_RSS_ENABLED):
1814 mrqc = IXGBE_MRQC_RSSEN;
1815 break;
1816 case (IXGBE_FLAG_DCB_ENABLED):
1817 mrqc = IXGBE_MRQC_RT8TCEN;
1818 break;
1819 default:
1820 break;
1821 }
1822 }
1823 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1824 /* Fill out redirection table */
1825 for (i = 0, j = 0; i < 128; i++, j++) {
1826 if (j == adapter->ring_feature[RING_F_RSS].indices)
1827 j = 0;
1828 /* reta = 4-byte sliding window of
1829 * 0x00..(indices-1)(indices-1)00..etc. */
1830 reta = (reta << 8) | (j * 0x11);
1831 if ((i & 3) == 3)
1832 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1833 }
1834
1835 /* Fill out hash function seeds */
1836 for (i = 0; i < 10; i++)
1837 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1838
1839 if (hw->mac.type == ixgbe_mac_82598EB)
1840 mrqc |= IXGBE_MRQC_RSSEN;
1841 /* Perform hash on these packet types */
1842 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1843 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1844 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1845 | IXGBE_MRQC_RSS_FIELD_IPV6
1846 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1847 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1848 }
1849 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1850
1851 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1852
1853 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1854 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1855 /* Disable indicating checksum in descriptor, enables
1856 * RSS hash */
1857 rxcsum |= IXGBE_RXCSUM_PCSD;
1858 }
1859 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1860 /* Enable IPv4 payload checksum for UDP fragments
1861 * if PCSD is not set */
1862 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1863 }
1864
1865 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1866
1867 if (hw->mac.type == ixgbe_mac_82599EB) {
1868 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1869 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1870 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1871 }
1872 }
1873
1874 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1875 {
1876 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1877 struct ixgbe_hw *hw = &adapter->hw;
1878
1879 /* add VID to filter table */
1880 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1881 }
1882
1883 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1884 {
1885 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1886 struct ixgbe_hw *hw = &adapter->hw;
1887
1888 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1889 ixgbe_irq_disable(adapter);
1890
1891 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1892
1893 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1894 ixgbe_irq_enable(adapter);
1895
1896 /* remove VID from filter table */
1897 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1898 }
1899
1900 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1901 struct vlan_group *grp)
1902 {
1903 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1904 u32 ctrl;
1905 int i, j;
1906
1907 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1908 ixgbe_irq_disable(adapter);
1909 adapter->vlgrp = grp;
1910
1911 /*
1912 * For a DCB driver, always enable VLAN tag stripping so we can
1913 * still receive traffic from a DCB-enabled host even if we're
1914 * not in DCB mode.
1915 */
1916 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1917 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1918 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1919 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1920 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1921 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1922 ctrl |= IXGBE_VLNCTRL_VFE;
1923 /* enable VLAN tag insert/strip */
1924 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1925 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1926 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1927 for (i = 0; i < adapter->num_rx_queues; i++) {
1928 j = adapter->rx_ring[i].reg_idx;
1929 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
1930 ctrl |= IXGBE_RXDCTL_VME;
1931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
1932 }
1933 }
1934 ixgbe_vlan_rx_add_vid(netdev, 0);
1935
1936 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1937 ixgbe_irq_enable(adapter);
1938 }
1939
1940 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1941 {
1942 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1943
1944 if (adapter->vlgrp) {
1945 u16 vid;
1946 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1947 if (!vlan_group_get_device(adapter->vlgrp, vid))
1948 continue;
1949 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1950 }
1951 }
1952 }
1953
1954 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1955 {
1956 struct dev_mc_list *mc_ptr;
1957 u8 *addr = *mc_addr_ptr;
1958 *vmdq = 0;
1959
1960 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1961 if (mc_ptr->next)
1962 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1963 else
1964 *mc_addr_ptr = NULL;
1965
1966 return addr;
1967 }
1968
1969 /**
1970 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1971 * @netdev: network interface device structure
1972 *
1973 * The set_rx_method entry point is called whenever the unicast/multicast
1974 * address list or the network interface flags are updated. This routine is
1975 * responsible for configuring the hardware for proper unicast, multicast and
1976 * promiscuous mode.
1977 **/
1978 static void ixgbe_set_rx_mode(struct net_device *netdev)
1979 {
1980 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1981 struct ixgbe_hw *hw = &adapter->hw;
1982 u32 fctrl, vlnctrl;
1983 u8 *addr_list = NULL;
1984 int addr_count = 0;
1985
1986 /* Check for Promiscuous and All Multicast modes */
1987
1988 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1989 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1990
1991 if (netdev->flags & IFF_PROMISC) {
1992 hw->addr_ctrl.user_set_promisc = 1;
1993 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1994 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1995 } else {
1996 if (netdev->flags & IFF_ALLMULTI) {
1997 fctrl |= IXGBE_FCTRL_MPE;
1998 fctrl &= ~IXGBE_FCTRL_UPE;
1999 } else {
2000 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2001 }
2002 vlnctrl |= IXGBE_VLNCTRL_VFE;
2003 hw->addr_ctrl.user_set_promisc = 0;
2004 }
2005
2006 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2007 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2008
2009 /* reprogram secondary unicast list */
2010 addr_count = netdev->uc_count;
2011 if (addr_count)
2012 addr_list = netdev->uc_list->dmi_addr;
2013 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2014 ixgbe_addr_list_itr);
2015
2016 /* reprogram multicast list */
2017 addr_count = netdev->mc_count;
2018 if (addr_count)
2019 addr_list = netdev->mc_list->dmi_addr;
2020 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2021 ixgbe_addr_list_itr);
2022 }
2023
2024 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2025 {
2026 int q_idx;
2027 struct ixgbe_q_vector *q_vector;
2028 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2029
2030 /* legacy and MSI only use one vector */
2031 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2032 q_vectors = 1;
2033
2034 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2035 struct napi_struct *napi;
2036 q_vector = &adapter->q_vector[q_idx];
2037 if (!q_vector->rxr_count)
2038 continue;
2039 napi = &q_vector->napi;
2040 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2041 (q_vector->rxr_count > 1))
2042 napi->poll = &ixgbe_clean_rxonly_many;
2043
2044 napi_enable(napi);
2045 }
2046 }
2047
2048 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2049 {
2050 int q_idx;
2051 struct ixgbe_q_vector *q_vector;
2052 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2053
2054 /* legacy and MSI only use one vector */
2055 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2056 q_vectors = 1;
2057
2058 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2059 q_vector = &adapter->q_vector[q_idx];
2060 if (!q_vector->rxr_count)
2061 continue;
2062 napi_disable(&q_vector->napi);
2063 }
2064 }
2065
2066 #ifdef CONFIG_IXGBE_DCB
2067 /*
2068 * ixgbe_configure_dcb - Configure DCB hardware
2069 * @adapter: ixgbe adapter struct
2070 *
2071 * This is called by the driver on open to configure the DCB hardware.
2072 * This is also called by the gennetlink interface when reconfiguring
2073 * the DCB state.
2074 */
2075 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2076 {
2077 struct ixgbe_hw *hw = &adapter->hw;
2078 u32 txdctl, vlnctrl;
2079 int i, j;
2080
2081 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2082 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2083 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2084
2085 /* reconfigure the hardware */
2086 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2087
2088 for (i = 0; i < adapter->num_tx_queues; i++) {
2089 j = adapter->tx_ring[i].reg_idx;
2090 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2091 /* PThresh workaround for Tx hang with DFP enabled. */
2092 txdctl |= 32;
2093 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2094 }
2095 /* Enable VLAN tag insert/strip */
2096 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2097 if (hw->mac.type == ixgbe_mac_82598EB) {
2098 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2099 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2100 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2101 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2102 vlnctrl |= IXGBE_VLNCTRL_VFE;
2103 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2104 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2105 for (i = 0; i < adapter->num_rx_queues; i++) {
2106 j = adapter->rx_ring[i].reg_idx;
2107 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2108 vlnctrl |= IXGBE_RXDCTL_VME;
2109 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2110 }
2111 }
2112 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2113 }
2114
2115 #endif
2116 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2117 {
2118 struct net_device *netdev = adapter->netdev;
2119 int i;
2120
2121 ixgbe_set_rx_mode(netdev);
2122
2123 ixgbe_restore_vlan(adapter);
2124 #ifdef CONFIG_IXGBE_DCB
2125 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2126 netif_set_gso_max_size(netdev, 32768);
2127 ixgbe_configure_dcb(adapter);
2128 } else {
2129 netif_set_gso_max_size(netdev, 65536);
2130 }
2131 #else
2132 netif_set_gso_max_size(netdev, 65536);
2133 #endif
2134
2135 ixgbe_configure_tx(adapter);
2136 ixgbe_configure_rx(adapter);
2137 for (i = 0; i < adapter->num_rx_queues; i++)
2138 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2139 (adapter->rx_ring[i].count - 1));
2140 }
2141
2142 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2143 {
2144 switch (hw->phy.type) {
2145 case ixgbe_phy_sfp_avago:
2146 case ixgbe_phy_sfp_ftl:
2147 case ixgbe_phy_sfp_intel:
2148 case ixgbe_phy_sfp_unknown:
2149 case ixgbe_phy_tw_tyco:
2150 case ixgbe_phy_tw_unknown:
2151 return true;
2152 default:
2153 return false;
2154 }
2155 }
2156
2157 /**
2158 * ixgbe_sfp_link_config - set up SFP+ link
2159 * @adapter: pointer to private adapter struct
2160 **/
2161 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2162 {
2163 struct ixgbe_hw *hw = &adapter->hw;
2164
2165 if (hw->phy.multispeed_fiber) {
2166 /*
2167 * In multispeed fiber setups, the device may not have
2168 * had a physical connection when the driver loaded.
2169 * If that's the case, the initial link configuration
2170 * couldn't get the MAC into 10G or 1G mode, so we'll
2171 * never have a link status change interrupt fire.
2172 * We need to try and force an autonegotiation
2173 * session, then bring up link.
2174 */
2175 hw->mac.ops.setup_sfp(hw);
2176 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2177 schedule_work(&adapter->multispeed_fiber_task);
2178 } else {
2179 /*
2180 * Direct Attach Cu and non-multispeed fiber modules
2181 * still need to be configured properly prior to
2182 * attempting link.
2183 */
2184 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2185 schedule_work(&adapter->sfp_config_module_task);
2186 }
2187 }
2188
2189 /**
2190 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2191 * @hw: pointer to private hardware struct
2192 *
2193 * Returns 0 on success, negative on failure
2194 **/
2195 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2196 {
2197 u32 autoneg;
2198 bool link_up = false;
2199 u32 ret = IXGBE_ERR_LINK_SETUP;
2200
2201 if (hw->mac.ops.check_link)
2202 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2203
2204 if (ret)
2205 goto link_cfg_out;
2206
2207 if (hw->mac.ops.get_link_capabilities)
2208 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2209 &hw->mac.autoneg);
2210 if (ret)
2211 goto link_cfg_out;
2212
2213 if (hw->mac.ops.setup_link_speed)
2214 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2215 link_cfg_out:
2216 return ret;
2217 }
2218
2219 #define IXGBE_MAX_RX_DESC_POLL 10
2220 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2221 int rxr)
2222 {
2223 int j = adapter->rx_ring[rxr].reg_idx;
2224 int k;
2225
2226 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2227 if (IXGBE_READ_REG(&adapter->hw,
2228 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2229 break;
2230 else
2231 msleep(1);
2232 }
2233 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2234 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2235 "not set within the polling period\n", rxr);
2236 }
2237 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2238 (adapter->rx_ring[rxr].count - 1));
2239 }
2240
2241 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2242 {
2243 struct net_device *netdev = adapter->netdev;
2244 struct ixgbe_hw *hw = &adapter->hw;
2245 int i, j = 0;
2246 int num_rx_rings = adapter->num_rx_queues;
2247 int err;
2248 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2249 u32 txdctl, rxdctl, mhadd;
2250 u32 dmatxctl;
2251 u32 gpie;
2252
2253 ixgbe_get_hw_control(adapter);
2254
2255 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2256 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2257 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2258 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2259 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2260 } else {
2261 /* MSI only */
2262 gpie = 0;
2263 }
2264 /* XXX: to interrupt immediately for EICS writes, enable this */
2265 /* gpie |= IXGBE_GPIE_EIMEN; */
2266 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2267 }
2268
2269 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2270 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2271 * specifically only auto mask tx and rx interrupts */
2272 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2273 }
2274
2275 /* Enable fan failure interrupt if media type is copper */
2276 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2277 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2278 gpie |= IXGBE_SDP1_GPIEN;
2279 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2280 }
2281
2282 if (hw->mac.type == ixgbe_mac_82599EB) {
2283 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2284 gpie |= IXGBE_SDP1_GPIEN;
2285 gpie |= IXGBE_SDP2_GPIEN;
2286 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2287 }
2288
2289 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2290 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2291 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2292 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2293
2294 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2295 }
2296
2297 for (i = 0; i < adapter->num_tx_queues; i++) {
2298 j = adapter->tx_ring[i].reg_idx;
2299 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2300 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2301 txdctl |= (8 << 16);
2302 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2303 }
2304
2305 if (hw->mac.type == ixgbe_mac_82599EB) {
2306 /* DMATXCTL.EN must be set after all Tx queue config is done */
2307 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2308 dmatxctl |= IXGBE_DMATXCTL_TE;
2309 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2310 }
2311 for (i = 0; i < adapter->num_tx_queues; i++) {
2312 j = adapter->tx_ring[i].reg_idx;
2313 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2314 txdctl |= IXGBE_TXDCTL_ENABLE;
2315 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2316 }
2317
2318 for (i = 0; i < num_rx_rings; i++) {
2319 j = adapter->rx_ring[i].reg_idx;
2320 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2321 /* enable PTHRESH=32 descriptors (half the internal cache)
2322 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2323 * this also removes a pesky rx_no_buffer_count increment */
2324 rxdctl |= 0x0020;
2325 rxdctl |= IXGBE_RXDCTL_ENABLE;
2326 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2327 if (hw->mac.type == ixgbe_mac_82599EB)
2328 ixgbe_rx_desc_queue_enable(adapter, i);
2329 }
2330 /* enable all receives */
2331 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2332 if (hw->mac.type == ixgbe_mac_82598EB)
2333 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2334 else
2335 rxdctl |= IXGBE_RXCTRL_RXEN;
2336 hw->mac.ops.enable_rx_dma(hw, rxdctl);
2337
2338 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2339 ixgbe_configure_msix(adapter);
2340 else
2341 ixgbe_configure_msi_and_legacy(adapter);
2342
2343 clear_bit(__IXGBE_DOWN, &adapter->state);
2344 ixgbe_napi_enable_all(adapter);
2345
2346 /* clear any pending interrupts, may auto mask */
2347 IXGBE_READ_REG(hw, IXGBE_EICR);
2348
2349 ixgbe_irq_enable(adapter);
2350
2351 /*
2352 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2353 * arrived before interrupts were enabled. We need to kick off
2354 * the SFP+ module setup first, then try to bring up link.
2355 * If we're not hot-pluggable SFP+, we just need to configure link
2356 * and bring it up.
2357 */
2358 err = hw->phy.ops.identify(hw);
2359 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2360 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2361 ixgbe_down(adapter);
2362 return err;
2363 }
2364
2365 if (ixgbe_is_sfp(hw)) {
2366 ixgbe_sfp_link_config(adapter);
2367 } else {
2368 err = ixgbe_non_sfp_link_config(hw);
2369 if (err)
2370 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2371 }
2372
2373 /* enable transmits */
2374 netif_tx_start_all_queues(netdev);
2375
2376 /* bring the link up in the watchdog, this could race with our first
2377 * link up interrupt but shouldn't be a problem */
2378 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2379 adapter->link_check_timeout = jiffies;
2380 mod_timer(&adapter->watchdog_timer, jiffies);
2381 return 0;
2382 }
2383
2384 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2385 {
2386 WARN_ON(in_interrupt());
2387 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2388 msleep(1);
2389 ixgbe_down(adapter);
2390 ixgbe_up(adapter);
2391 clear_bit(__IXGBE_RESETTING, &adapter->state);
2392 }
2393
2394 int ixgbe_up(struct ixgbe_adapter *adapter)
2395 {
2396 /* hardware has been reset, we need to reload some things */
2397 ixgbe_configure(adapter);
2398
2399 ixgbe_napi_add_all(adapter);
2400
2401 return ixgbe_up_complete(adapter);
2402 }
2403
2404 void ixgbe_reset(struct ixgbe_adapter *adapter)
2405 {
2406 struct ixgbe_hw *hw = &adapter->hw;
2407 if (hw->mac.ops.init_hw(hw))
2408 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2409
2410 /* reprogram the RAR[0] in case user changed it. */
2411 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2412
2413 }
2414
2415 /**
2416 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2417 * @adapter: board private structure
2418 * @rx_ring: ring to free buffers from
2419 **/
2420 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2421 struct ixgbe_ring *rx_ring)
2422 {
2423 struct pci_dev *pdev = adapter->pdev;
2424 unsigned long size;
2425 unsigned int i;
2426
2427 /* Free all the Rx ring sk_buffs */
2428
2429 for (i = 0; i < rx_ring->count; i++) {
2430 struct ixgbe_rx_buffer *rx_buffer_info;
2431
2432 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2433 if (rx_buffer_info->dma) {
2434 pci_unmap_single(pdev, rx_buffer_info->dma,
2435 rx_ring->rx_buf_len,
2436 PCI_DMA_FROMDEVICE);
2437 rx_buffer_info->dma = 0;
2438 }
2439 if (rx_buffer_info->skb) {
2440 dev_kfree_skb(rx_buffer_info->skb);
2441 rx_buffer_info->skb = NULL;
2442 }
2443 if (!rx_buffer_info->page)
2444 continue;
2445 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2446 PCI_DMA_FROMDEVICE);
2447 rx_buffer_info->page_dma = 0;
2448 put_page(rx_buffer_info->page);
2449 rx_buffer_info->page = NULL;
2450 rx_buffer_info->page_offset = 0;
2451 }
2452
2453 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2454 memset(rx_ring->rx_buffer_info, 0, size);
2455
2456 /* Zero out the descriptor ring */
2457 memset(rx_ring->desc, 0, rx_ring->size);
2458
2459 rx_ring->next_to_clean = 0;
2460 rx_ring->next_to_use = 0;
2461
2462 if (rx_ring->head)
2463 writel(0, adapter->hw.hw_addr + rx_ring->head);
2464 if (rx_ring->tail)
2465 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2466 }
2467
2468 /**
2469 * ixgbe_clean_tx_ring - Free Tx Buffers
2470 * @adapter: board private structure
2471 * @tx_ring: ring to be cleaned
2472 **/
2473 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2474 struct ixgbe_ring *tx_ring)
2475 {
2476 struct ixgbe_tx_buffer *tx_buffer_info;
2477 unsigned long size;
2478 unsigned int i;
2479
2480 /* Free all the Tx ring sk_buffs */
2481
2482 for (i = 0; i < tx_ring->count; i++) {
2483 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2484 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2485 }
2486
2487 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2488 memset(tx_ring->tx_buffer_info, 0, size);
2489
2490 /* Zero out the descriptor ring */
2491 memset(tx_ring->desc, 0, tx_ring->size);
2492
2493 tx_ring->next_to_use = 0;
2494 tx_ring->next_to_clean = 0;
2495
2496 if (tx_ring->head)
2497 writel(0, adapter->hw.hw_addr + tx_ring->head);
2498 if (tx_ring->tail)
2499 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2500 }
2501
2502 /**
2503 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2504 * @adapter: board private structure
2505 **/
2506 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2507 {
2508 int i;
2509
2510 for (i = 0; i < adapter->num_rx_queues; i++)
2511 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2512 }
2513
2514 /**
2515 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2516 * @adapter: board private structure
2517 **/
2518 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2519 {
2520 int i;
2521
2522 for (i = 0; i < adapter->num_tx_queues; i++)
2523 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2524 }
2525
2526 void ixgbe_down(struct ixgbe_adapter *adapter)
2527 {
2528 struct net_device *netdev = adapter->netdev;
2529 struct ixgbe_hw *hw = &adapter->hw;
2530 u32 rxctrl;
2531 u32 txdctl;
2532 int i, j;
2533
2534 /* signal that we are down to the interrupt handler */
2535 set_bit(__IXGBE_DOWN, &adapter->state);
2536
2537 /* disable receives */
2538 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2539 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2540
2541 netif_tx_disable(netdev);
2542
2543 IXGBE_WRITE_FLUSH(hw);
2544 msleep(10);
2545
2546 netif_tx_stop_all_queues(netdev);
2547
2548 ixgbe_irq_disable(adapter);
2549
2550 ixgbe_napi_disable_all(adapter);
2551
2552 del_timer_sync(&adapter->watchdog_timer);
2553 cancel_work_sync(&adapter->watchdog_task);
2554
2555 /* disable transmits in the hardware now that interrupts are off */
2556 for (i = 0; i < adapter->num_tx_queues; i++) {
2557 j = adapter->tx_ring[i].reg_idx;
2558 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2559 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2560 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2561 }
2562 /* Disable the Tx DMA engine on 82599 */
2563 if (hw->mac.type == ixgbe_mac_82599EB)
2564 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2565 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2566 ~IXGBE_DMATXCTL_TE));
2567
2568 netif_carrier_off(netdev);
2569
2570 #ifdef CONFIG_IXGBE_DCA
2571 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2572 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2573 dca_remove_requester(&adapter->pdev->dev);
2574 }
2575
2576 #endif
2577 if (!pci_channel_offline(adapter->pdev))
2578 ixgbe_reset(adapter);
2579 ixgbe_clean_all_tx_rings(adapter);
2580 ixgbe_clean_all_rx_rings(adapter);
2581
2582 #ifdef CONFIG_IXGBE_DCA
2583 /* since we reset the hardware DCA settings were cleared */
2584 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2585 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2586 /* always use CB2 mode, difference is masked
2587 * in the CB driver */
2588 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2589 ixgbe_setup_dca(adapter);
2590 }
2591 #endif
2592 }
2593
2594 /**
2595 * ixgbe_poll - NAPI Rx polling callback
2596 * @napi: structure for representing this polling device
2597 * @budget: how many packets driver is allowed to clean
2598 *
2599 * This function is used for legacy and MSI, NAPI mode
2600 **/
2601 static int ixgbe_poll(struct napi_struct *napi, int budget)
2602 {
2603 struct ixgbe_q_vector *q_vector =
2604 container_of(napi, struct ixgbe_q_vector, napi);
2605 struct ixgbe_adapter *adapter = q_vector->adapter;
2606 int tx_clean_complete, work_done = 0;
2607
2608 #ifdef CONFIG_IXGBE_DCA
2609 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2610 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2611 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2612 }
2613 #endif
2614
2615 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2616 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2617
2618 if (!tx_clean_complete)
2619 work_done = budget;
2620
2621 /* If budget not fully consumed, exit the polling mode */
2622 if (work_done < budget) {
2623 napi_complete(napi);
2624 if (adapter->itr_setting & 1)
2625 ixgbe_set_itr(adapter);
2626 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2627 ixgbe_irq_enable(adapter);
2628 }
2629 return work_done;
2630 }
2631
2632 /**
2633 * ixgbe_tx_timeout - Respond to a Tx Hang
2634 * @netdev: network interface device structure
2635 **/
2636 static void ixgbe_tx_timeout(struct net_device *netdev)
2637 {
2638 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2639
2640 /* Do the reset outside of interrupt context */
2641 schedule_work(&adapter->reset_task);
2642 }
2643
2644 static void ixgbe_reset_task(struct work_struct *work)
2645 {
2646 struct ixgbe_adapter *adapter;
2647 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2648
2649 /* If we're already down or resetting, just bail */
2650 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2651 test_bit(__IXGBE_RESETTING, &adapter->state))
2652 return;
2653
2654 adapter->tx_timeout_count++;
2655
2656 ixgbe_reinit_locked(adapter);
2657 }
2658
2659 #ifdef CONFIG_IXGBE_DCB
2660 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2661 {
2662 bool ret = false;
2663
2664 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2665 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2666 adapter->num_rx_queues =
2667 adapter->ring_feature[RING_F_DCB].indices;
2668 adapter->num_tx_queues =
2669 adapter->ring_feature[RING_F_DCB].indices;
2670 ret = true;
2671 } else {
2672 ret = false;
2673 }
2674
2675 return ret;
2676 }
2677 #endif
2678
2679 /**
2680 * ixgbe_set_rss_queues: Allocate queues for RSS
2681 * @adapter: board private structure to initialize
2682 *
2683 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2684 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2685 *
2686 **/
2687 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2688 {
2689 bool ret = false;
2690
2691 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2692 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2693 adapter->num_rx_queues =
2694 adapter->ring_feature[RING_F_RSS].indices;
2695 adapter->num_tx_queues =
2696 adapter->ring_feature[RING_F_RSS].indices;
2697 ret = true;
2698 } else {
2699 ret = false;
2700 }
2701
2702 return ret;
2703 }
2704
2705 /*
2706 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2707 * @adapter: board private structure to initialize
2708 *
2709 * This is the top level queue allocation routine. The order here is very
2710 * important, starting with the "most" number of features turned on at once,
2711 * and ending with the smallest set of features. This way large combinations
2712 * can be allocated if they're turned on, and smaller combinations are the
2713 * fallthrough conditions.
2714 *
2715 **/
2716 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2717 {
2718 /* Start with base case */
2719 adapter->num_rx_queues = 1;
2720 adapter->num_tx_queues = 1;
2721
2722 #ifdef CONFIG_IXGBE_DCB
2723 if (ixgbe_set_dcb_queues(adapter))
2724 return;
2725
2726 #endif
2727 if (ixgbe_set_rss_queues(adapter))
2728 return;
2729 }
2730
2731 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2732 int vectors)
2733 {
2734 int err, vector_threshold;
2735
2736 /* We'll want at least 3 (vector_threshold):
2737 * 1) TxQ[0] Cleanup
2738 * 2) RxQ[0] Cleanup
2739 * 3) Other (Link Status Change, etc.)
2740 * 4) TCP Timer (optional)
2741 */
2742 vector_threshold = MIN_MSIX_COUNT;
2743
2744 /* The more we get, the more we will assign to Tx/Rx Cleanup
2745 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2746 * Right now, we simply care about how many we'll get; we'll
2747 * set them up later while requesting irq's.
2748 */
2749 while (vectors >= vector_threshold) {
2750 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2751 vectors);
2752 if (!err) /* Success in acquiring all requested vectors. */
2753 break;
2754 else if (err < 0)
2755 vectors = 0; /* Nasty failure, quit now */
2756 else /* err == number of vectors we should try again with */
2757 vectors = err;
2758 }
2759
2760 if (vectors < vector_threshold) {
2761 /* Can't allocate enough MSI-X interrupts? Oh well.
2762 * This just means we'll go with either a single MSI
2763 * vector or fall back to legacy interrupts.
2764 */
2765 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2766 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2767 kfree(adapter->msix_entries);
2768 adapter->msix_entries = NULL;
2769 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2770 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2771 ixgbe_set_num_queues(adapter);
2772 } else {
2773 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2774 /*
2775 * Adjust for only the vectors we'll use, which is minimum
2776 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2777 * vectors we were allocated.
2778 */
2779 adapter->num_msix_vectors = min(vectors,
2780 adapter->max_msix_q_vectors + NON_Q_VECTORS);
2781 }
2782 }
2783
2784 /**
2785 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2786 * @adapter: board private structure to initialize
2787 *
2788 * Cache the descriptor ring offsets for RSS to the assigned rings.
2789 *
2790 **/
2791 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2792 {
2793 int i;
2794 bool ret = false;
2795
2796 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2797 for (i = 0; i < adapter->num_rx_queues; i++)
2798 adapter->rx_ring[i].reg_idx = i;
2799 for (i = 0; i < adapter->num_tx_queues; i++)
2800 adapter->tx_ring[i].reg_idx = i;
2801 ret = true;
2802 } else {
2803 ret = false;
2804 }
2805
2806 return ret;
2807 }
2808
2809 #ifdef CONFIG_IXGBE_DCB
2810 /**
2811 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2812 * @adapter: board private structure to initialize
2813 *
2814 * Cache the descriptor ring offsets for DCB to the assigned rings.
2815 *
2816 **/
2817 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2818 {
2819 int i;
2820 bool ret = false;
2821 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2822
2823 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2824 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2825 /* the number of queues is assumed to be symmetric */
2826 for (i = 0; i < dcb_i; i++) {
2827 adapter->rx_ring[i].reg_idx = i << 3;
2828 adapter->tx_ring[i].reg_idx = i << 2;
2829 }
2830 ret = true;
2831 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2832 for (i = 0; i < dcb_i; i++) {
2833 adapter->rx_ring[i].reg_idx = i << 4;
2834 adapter->tx_ring[i].reg_idx = i << 4;
2835 }
2836 ret = true;
2837 } else {
2838 ret = false;
2839 }
2840 } else {
2841 ret = false;
2842 }
2843
2844 return ret;
2845 }
2846 #endif
2847
2848 /**
2849 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2850 * @adapter: board private structure to initialize
2851 *
2852 * Once we know the feature-set enabled for the device, we'll cache
2853 * the register offset the descriptor ring is assigned to.
2854 *
2855 * Note, the order the various feature calls is important. It must start with
2856 * the "most" features enabled at the same time, then trickle down to the
2857 * least amount of features turned on at once.
2858 **/
2859 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2860 {
2861 /* start with default case */
2862 adapter->rx_ring[0].reg_idx = 0;
2863 adapter->tx_ring[0].reg_idx = 0;
2864
2865 #ifdef CONFIG_IXGBE_DCB
2866 if (ixgbe_cache_ring_dcb(adapter))
2867 return;
2868
2869 #endif
2870 if (ixgbe_cache_ring_rss(adapter))
2871 return;
2872 }
2873
2874 /**
2875 * ixgbe_alloc_queues - Allocate memory for all rings
2876 * @adapter: board private structure to initialize
2877 *
2878 * We allocate one ring per queue at run-time since we don't know the
2879 * number of queues at compile-time. The polling_netdev array is
2880 * intended for Multiqueue, but should work fine with a single queue.
2881 **/
2882 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2883 {
2884 int i;
2885
2886 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2887 sizeof(struct ixgbe_ring), GFP_KERNEL);
2888 if (!adapter->tx_ring)
2889 goto err_tx_ring_allocation;
2890
2891 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2892 sizeof(struct ixgbe_ring), GFP_KERNEL);
2893 if (!adapter->rx_ring)
2894 goto err_rx_ring_allocation;
2895
2896 for (i = 0; i < adapter->num_tx_queues; i++) {
2897 adapter->tx_ring[i].count = adapter->tx_ring_count;
2898 adapter->tx_ring[i].queue_index = i;
2899 }
2900
2901 for (i = 0; i < adapter->num_rx_queues; i++) {
2902 adapter->rx_ring[i].count = adapter->rx_ring_count;
2903 adapter->rx_ring[i].queue_index = i;
2904 }
2905
2906 ixgbe_cache_ring_register(adapter);
2907
2908 return 0;
2909
2910 err_rx_ring_allocation:
2911 kfree(adapter->tx_ring);
2912 err_tx_ring_allocation:
2913 return -ENOMEM;
2914 }
2915
2916 /**
2917 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2918 * @adapter: board private structure to initialize
2919 *
2920 * Attempt to configure the interrupts using the best available
2921 * capabilities of the hardware and the kernel.
2922 **/
2923 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
2924 {
2925 int err = 0;
2926 int vector, v_budget;
2927
2928 /*
2929 * It's easy to be greedy for MSI-X vectors, but it really
2930 * doesn't do us much good if we have a lot more vectors
2931 * than CPU's. So let's be conservative and only ask for
2932 * (roughly) twice the number of vectors as there are CPU's.
2933 */
2934 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2935 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2936
2937 /*
2938 * At the same time, hardware can only support a maximum of
2939 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2940 * we can easily reach upwards of 64 Rx descriptor queues and
2941 * 32 Tx queues. Thus, we cap it off in those rare cases where
2942 * the cpu count also exceeds our vector limit.
2943 */
2944 v_budget = min(v_budget, MAX_MSIX_COUNT);
2945
2946 /* A failure in MSI-X entry allocation isn't fatal, but it does
2947 * mean we disable MSI-X capabilities of the adapter. */
2948 adapter->msix_entries = kcalloc(v_budget,
2949 sizeof(struct msix_entry), GFP_KERNEL);
2950 if (!adapter->msix_entries) {
2951 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2952 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2953 ixgbe_set_num_queues(adapter);
2954 kfree(adapter->tx_ring);
2955 kfree(adapter->rx_ring);
2956 err = ixgbe_alloc_queues(adapter);
2957 if (err) {
2958 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2959 "for queues\n");
2960 goto out;
2961 }
2962
2963 goto try_msi;
2964 }
2965
2966 for (vector = 0; vector < v_budget; vector++)
2967 adapter->msix_entries[vector].entry = vector;
2968
2969 ixgbe_acquire_msix_vectors(adapter, v_budget);
2970
2971 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2972 goto out;
2973
2974 try_msi:
2975 err = pci_enable_msi(adapter->pdev);
2976 if (!err) {
2977 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2978 } else {
2979 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2980 "falling back to legacy. Error: %d\n", err);
2981 /* reset err */
2982 err = 0;
2983 }
2984
2985 out:
2986 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2987 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2988
2989 return err;
2990 }
2991
2992 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2993 {
2994 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2995 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2996 pci_disable_msix(adapter->pdev);
2997 kfree(adapter->msix_entries);
2998 adapter->msix_entries = NULL;
2999 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3000 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3001 pci_disable_msi(adapter->pdev);
3002 }
3003 return;
3004 }
3005
3006 /**
3007 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3008 * @adapter: board private structure to initialize
3009 *
3010 * We determine which interrupt scheme to use based on...
3011 * - Kernel support (MSI, MSI-X)
3012 * - which can be user-defined (via MODULE_PARAM)
3013 * - Hardware queue count (num_*_queues)
3014 * - defined by miscellaneous hardware support/features (RSS, etc.)
3015 **/
3016 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3017 {
3018 int err;
3019
3020 /* Number of supported queues */
3021 ixgbe_set_num_queues(adapter);
3022
3023 err = ixgbe_alloc_queues(adapter);
3024 if (err) {
3025 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3026 goto err_alloc_queues;
3027 }
3028
3029 err = ixgbe_set_interrupt_capability(adapter);
3030 if (err) {
3031 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3032 goto err_set_interrupt;
3033 }
3034
3035 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3036 "Tx Queue count = %u\n",
3037 (adapter->num_rx_queues > 1) ? "Enabled" :
3038 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3039
3040 set_bit(__IXGBE_DOWN, &adapter->state);
3041
3042 return 0;
3043
3044 err_set_interrupt:
3045 kfree(adapter->tx_ring);
3046 kfree(adapter->rx_ring);
3047 err_alloc_queues:
3048 return err;
3049 }
3050
3051 /**
3052 * ixgbe_sfp_timer - worker thread to find a missing module
3053 * @data: pointer to our adapter struct
3054 **/
3055 static void ixgbe_sfp_timer(unsigned long data)
3056 {
3057 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3058
3059 /*
3060 * Do the sfp_timer outside of interrupt context due to the
3061 * delays that sfp+ detection requires
3062 */
3063 schedule_work(&adapter->sfp_task);
3064 }
3065
3066 /**
3067 * ixgbe_sfp_task - worker thread to find a missing module
3068 * @work: pointer to work_struct containing our data
3069 **/
3070 static void ixgbe_sfp_task(struct work_struct *work)
3071 {
3072 struct ixgbe_adapter *adapter = container_of(work,
3073 struct ixgbe_adapter,
3074 sfp_task);
3075 struct ixgbe_hw *hw = &adapter->hw;
3076
3077 if ((hw->phy.type == ixgbe_phy_nl) &&
3078 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3079 s32 ret = hw->phy.ops.identify_sfp(hw);
3080 if (ret)
3081 goto reschedule;
3082 ret = hw->phy.ops.reset(hw);
3083 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3084 DPRINTK(PROBE, ERR, "failed to initialize because an "
3085 "unsupported SFP+ module type was detected.\n"
3086 "Reload the driver after installing a "
3087 "supported module.\n");
3088 unregister_netdev(adapter->netdev);
3089 } else {
3090 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3091 hw->phy.sfp_type);
3092 }
3093 /* don't need this routine any more */
3094 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3095 }
3096 return;
3097 reschedule:
3098 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3099 mod_timer(&adapter->sfp_timer,
3100 round_jiffies(jiffies + (2 * HZ)));
3101 }
3102
3103 /**
3104 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3105 * @adapter: board private structure to initialize
3106 *
3107 * ixgbe_sw_init initializes the Adapter private data structure.
3108 * Fields are initialized based on PCI device information and
3109 * OS network device settings (MTU size).
3110 **/
3111 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3112 {
3113 struct ixgbe_hw *hw = &adapter->hw;
3114 struct pci_dev *pdev = adapter->pdev;
3115 unsigned int rss;
3116 #ifdef CONFIG_IXGBE_DCB
3117 int j;
3118 struct tc_configuration *tc;
3119 #endif
3120
3121 /* PCI config space info */
3122
3123 hw->vendor_id = pdev->vendor;
3124 hw->device_id = pdev->device;
3125 hw->revision_id = pdev->revision;
3126 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3127 hw->subsystem_device_id = pdev->subsystem_device;
3128
3129 /* Set capability flags */
3130 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3131 adapter->ring_feature[RING_F_RSS].indices = rss;
3132 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3133 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3134 if (hw->mac.type == ixgbe_mac_82598EB)
3135 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3136 else if (hw->mac.type == ixgbe_mac_82599EB)
3137 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3138
3139 #ifdef CONFIG_IXGBE_DCB
3140 /* Configure DCB traffic classes */
3141 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3142 tc = &adapter->dcb_cfg.tc_config[j];
3143 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3144 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3145 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3146 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3147 tc->dcb_pfc = pfc_disabled;
3148 }
3149 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3150 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3151 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3152 adapter->dcb_cfg.round_robin_enable = false;
3153 adapter->dcb_set_bitmap = 0x00;
3154 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3155 adapter->ring_feature[RING_F_DCB].indices);
3156
3157 #endif
3158
3159 /* default flow control settings */
3160 hw->fc.requested_mode = ixgbe_fc_none;
3161 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3162 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3163 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3164 hw->fc.send_xon = true;
3165
3166 /* enable itr by default in dynamic mode */
3167 adapter->itr_setting = 1;
3168 adapter->eitr_param = 20000;
3169
3170 /* set defaults for eitr in MegaBytes */
3171 adapter->eitr_low = 10;
3172 adapter->eitr_high = 20;
3173
3174 /* set default ring sizes */
3175 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3176 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3177
3178 /* initialize eeprom parameters */
3179 if (ixgbe_init_eeprom_params_generic(hw)) {
3180 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3181 return -EIO;
3182 }
3183
3184 /* enable rx csum by default */
3185 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3186
3187 set_bit(__IXGBE_DOWN, &adapter->state);
3188
3189 return 0;
3190 }
3191
3192 /**
3193 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3194 * @adapter: board private structure
3195 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3196 *
3197 * Return 0 on success, negative on failure
3198 **/
3199 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3200 struct ixgbe_ring *tx_ring)
3201 {
3202 struct pci_dev *pdev = adapter->pdev;
3203 int size;
3204
3205 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3206 tx_ring->tx_buffer_info = vmalloc(size);
3207 if (!tx_ring->tx_buffer_info)
3208 goto err;
3209 memset(tx_ring->tx_buffer_info, 0, size);
3210
3211 /* round up to nearest 4K */
3212 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3213 tx_ring->size = ALIGN(tx_ring->size, 4096);
3214
3215 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3216 &tx_ring->dma);
3217 if (!tx_ring->desc)
3218 goto err;
3219
3220 tx_ring->next_to_use = 0;
3221 tx_ring->next_to_clean = 0;
3222 tx_ring->work_limit = tx_ring->count;
3223 return 0;
3224
3225 err:
3226 vfree(tx_ring->tx_buffer_info);
3227 tx_ring->tx_buffer_info = NULL;
3228 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3229 "descriptor ring\n");
3230 return -ENOMEM;
3231 }
3232
3233 /**
3234 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3235 * @adapter: board private structure
3236 *
3237 * If this function returns with an error, then it's possible one or
3238 * more of the rings is populated (while the rest are not). It is the
3239 * callers duty to clean those orphaned rings.
3240 *
3241 * Return 0 on success, negative on failure
3242 **/
3243 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3244 {
3245 int i, err = 0;
3246
3247 for (i = 0; i < adapter->num_tx_queues; i++) {
3248 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3249 if (!err)
3250 continue;
3251 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3252 break;
3253 }
3254
3255 return err;
3256 }
3257
3258 /**
3259 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3260 * @adapter: board private structure
3261 * @rx_ring: rx descriptor ring (for a specific queue) to setup
3262 *
3263 * Returns 0 on success, negative on failure
3264 **/
3265 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3266 struct ixgbe_ring *rx_ring)
3267 {
3268 struct pci_dev *pdev = adapter->pdev;
3269 int size;
3270
3271 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3272 rx_ring->rx_buffer_info = vmalloc(size);
3273 if (!rx_ring->rx_buffer_info) {
3274 DPRINTK(PROBE, ERR,
3275 "vmalloc allocation failed for the rx desc ring\n");
3276 goto alloc_failed;
3277 }
3278 memset(rx_ring->rx_buffer_info, 0, size);
3279
3280 /* Round up to nearest 4K */
3281 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3282 rx_ring->size = ALIGN(rx_ring->size, 4096);
3283
3284 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3285
3286 if (!rx_ring->desc) {
3287 DPRINTK(PROBE, ERR,
3288 "Memory allocation failed for the rx desc ring\n");
3289 vfree(rx_ring->rx_buffer_info);
3290 goto alloc_failed;
3291 }
3292
3293 rx_ring->next_to_clean = 0;
3294 rx_ring->next_to_use = 0;
3295
3296 return 0;
3297
3298 alloc_failed:
3299 return -ENOMEM;
3300 }
3301
3302 /**
3303 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3304 * @adapter: board private structure
3305 *
3306 * If this function returns with an error, then it's possible one or
3307 * more of the rings is populated (while the rest are not). It is the
3308 * callers duty to clean those orphaned rings.
3309 *
3310 * Return 0 on success, negative on failure
3311 **/
3312
3313 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3314 {
3315 int i, err = 0;
3316
3317 for (i = 0; i < adapter->num_rx_queues; i++) {
3318 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3319 if (!err)
3320 continue;
3321 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3322 break;
3323 }
3324
3325 return err;
3326 }
3327
3328 /**
3329 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3330 * @adapter: board private structure
3331 * @tx_ring: Tx descriptor ring for a specific queue
3332 *
3333 * Free all transmit software resources
3334 **/
3335 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3336 struct ixgbe_ring *tx_ring)
3337 {
3338 struct pci_dev *pdev = adapter->pdev;
3339
3340 ixgbe_clean_tx_ring(adapter, tx_ring);
3341
3342 vfree(tx_ring->tx_buffer_info);
3343 tx_ring->tx_buffer_info = NULL;
3344
3345 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3346
3347 tx_ring->desc = NULL;
3348 }
3349
3350 /**
3351 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3352 * @adapter: board private structure
3353 *
3354 * Free all transmit software resources
3355 **/
3356 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3357 {
3358 int i;
3359
3360 for (i = 0; i < adapter->num_tx_queues; i++)
3361 if (adapter->tx_ring[i].desc)
3362 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3363 }
3364
3365 /**
3366 * ixgbe_free_rx_resources - Free Rx Resources
3367 * @adapter: board private structure
3368 * @rx_ring: ring to clean the resources from
3369 *
3370 * Free all receive software resources
3371 **/
3372 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3373 struct ixgbe_ring *rx_ring)
3374 {
3375 struct pci_dev *pdev = adapter->pdev;
3376
3377 ixgbe_clean_rx_ring(adapter, rx_ring);
3378
3379 vfree(rx_ring->rx_buffer_info);
3380 rx_ring->rx_buffer_info = NULL;
3381
3382 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3383
3384 rx_ring->desc = NULL;
3385 }
3386
3387 /**
3388 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3389 * @adapter: board private structure
3390 *
3391 * Free all receive software resources
3392 **/
3393 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3394 {
3395 int i;
3396
3397 for (i = 0; i < adapter->num_rx_queues; i++)
3398 if (adapter->rx_ring[i].desc)
3399 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3400 }
3401
3402 /**
3403 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3404 * @netdev: network interface device structure
3405 * @new_mtu: new value for maximum frame size
3406 *
3407 * Returns 0 on success, negative on failure
3408 **/
3409 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3410 {
3411 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3412 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3413
3414 /* MTU < 68 is an error and causes problems on some kernels */
3415 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3416 return -EINVAL;
3417
3418 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3419 netdev->mtu, new_mtu);
3420 /* must set new MTU before calling down or up */
3421 netdev->mtu = new_mtu;
3422
3423 if (netif_running(netdev))
3424 ixgbe_reinit_locked(adapter);
3425
3426 return 0;
3427 }
3428
3429 /**
3430 * ixgbe_open - Called when a network interface is made active
3431 * @netdev: network interface device structure
3432 *
3433 * Returns 0 on success, negative value on failure
3434 *
3435 * The open entry point is called when a network interface is made
3436 * active by the system (IFF_UP). At this point all resources needed
3437 * for transmit and receive operations are allocated, the interrupt
3438 * handler is registered with the OS, the watchdog timer is started,
3439 * and the stack is notified that the interface is ready.
3440 **/
3441 static int ixgbe_open(struct net_device *netdev)
3442 {
3443 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3444 int err;
3445
3446 /* disallow open during test */
3447 if (test_bit(__IXGBE_TESTING, &adapter->state))
3448 return -EBUSY;
3449
3450 /* allocate transmit descriptors */
3451 err = ixgbe_setup_all_tx_resources(adapter);
3452 if (err)
3453 goto err_setup_tx;
3454
3455 /* allocate receive descriptors */
3456 err = ixgbe_setup_all_rx_resources(adapter);
3457 if (err)
3458 goto err_setup_rx;
3459
3460 ixgbe_configure(adapter);
3461
3462 ixgbe_napi_add_all(adapter);
3463
3464 err = ixgbe_request_irq(adapter);
3465 if (err)
3466 goto err_req_irq;
3467
3468 err = ixgbe_up_complete(adapter);
3469 if (err)
3470 goto err_up;
3471
3472 netif_tx_start_all_queues(netdev);
3473
3474 return 0;
3475
3476 err_up:
3477 ixgbe_release_hw_control(adapter);
3478 ixgbe_free_irq(adapter);
3479 err_req_irq:
3480 ixgbe_free_all_rx_resources(adapter);
3481 err_setup_rx:
3482 ixgbe_free_all_tx_resources(adapter);
3483 err_setup_tx:
3484 ixgbe_reset(adapter);
3485
3486 return err;
3487 }
3488
3489 /**
3490 * ixgbe_close - Disables a network interface
3491 * @netdev: network interface device structure
3492 *
3493 * Returns 0, this is not allowed to fail
3494 *
3495 * The close entry point is called when an interface is de-activated
3496 * by the OS. The hardware is still under the drivers control, but
3497 * needs to be disabled. A global MAC reset is issued to stop the
3498 * hardware, and all transmit and receive resources are freed.
3499 **/
3500 static int ixgbe_close(struct net_device *netdev)
3501 {
3502 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3503
3504 ixgbe_down(adapter);
3505 ixgbe_free_irq(adapter);
3506
3507 ixgbe_free_all_tx_resources(adapter);
3508 ixgbe_free_all_rx_resources(adapter);
3509
3510 ixgbe_release_hw_control(adapter);
3511
3512 return 0;
3513 }
3514
3515 /**
3516 * ixgbe_napi_add_all - prep napi structs for use
3517 * @adapter: private struct
3518 *
3519 * helper function to napi_add each possible q_vector->napi
3520 */
3521 void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3522 {
3523 int q_idx, q_vectors;
3524 struct net_device *netdev = adapter->netdev;
3525 int (*poll)(struct napi_struct *, int);
3526
3527 /* check if we already have our netdev->napi_list populated */
3528 if (&netdev->napi_list != netdev->napi_list.next)
3529 return;
3530
3531 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3532 poll = &ixgbe_clean_rxonly;
3533 /* Only enable as many vectors as we have rx queues. */
3534 q_vectors = adapter->num_rx_queues;
3535 } else {
3536 poll = &ixgbe_poll;
3537 /* only one q_vector for legacy modes */
3538 q_vectors = 1;
3539 }
3540
3541 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3542 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3543 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3544 }
3545 }
3546
3547 void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
3548 {
3549 int q_idx;
3550 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3551
3552 /* legacy and MSI only use one vector */
3553 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3554 q_vectors = 1;
3555
3556 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3557 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3558 if (!q_vector->rxr_count)
3559 continue;
3560 netif_napi_del(&q_vector->napi);
3561 }
3562 }
3563
3564 #ifdef CONFIG_PM
3565 static int ixgbe_resume(struct pci_dev *pdev)
3566 {
3567 struct net_device *netdev = pci_get_drvdata(pdev);
3568 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3569 u32 err;
3570
3571 pci_set_power_state(pdev, PCI_D0);
3572 pci_restore_state(pdev);
3573 err = pci_enable_device(pdev);
3574 if (err) {
3575 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3576 "suspend\n");
3577 return err;
3578 }
3579 pci_set_master(pdev);
3580
3581 pci_enable_wake(pdev, PCI_D3hot, 0);
3582 pci_enable_wake(pdev, PCI_D3cold, 0);
3583
3584 err = ixgbe_init_interrupt_scheme(adapter);
3585 if (err) {
3586 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3587 "device\n");
3588 return err;
3589 }
3590
3591 ixgbe_reset(adapter);
3592
3593 if (netif_running(netdev)) {
3594 err = ixgbe_open(adapter->netdev);
3595 if (err)
3596 return err;
3597 }
3598
3599 netif_device_attach(netdev);
3600
3601 return 0;
3602 }
3603
3604 #endif /* CONFIG_PM */
3605 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3606 {
3607 struct net_device *netdev = pci_get_drvdata(pdev);
3608 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3609 struct ixgbe_hw *hw = &adapter->hw;
3610 u32 ctrl, fctrl;
3611 u32 wufc = adapter->wol;
3612 #ifdef CONFIG_PM
3613 int retval = 0;
3614 #endif
3615
3616 netif_device_detach(netdev);
3617
3618 if (netif_running(netdev)) {
3619 ixgbe_down(adapter);
3620 ixgbe_free_irq(adapter);
3621 ixgbe_free_all_tx_resources(adapter);
3622 ixgbe_free_all_rx_resources(adapter);
3623 }
3624 ixgbe_reset_interrupt_capability(adapter);
3625 ixgbe_napi_del_all(adapter);
3626 INIT_LIST_HEAD(&netdev->napi_list);
3627 kfree(adapter->tx_ring);
3628 kfree(adapter->rx_ring);
3629
3630 #ifdef CONFIG_PM
3631 retval = pci_save_state(pdev);
3632 if (retval)
3633 return retval;
3634
3635 #endif
3636 if (wufc) {
3637 ixgbe_set_rx_mode(netdev);
3638
3639 /* turn on all-multi mode if wake on multicast is enabled */
3640 if (wufc & IXGBE_WUFC_MC) {
3641 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3642 fctrl |= IXGBE_FCTRL_MPE;
3643 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3644 }
3645
3646 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3647 ctrl |= IXGBE_CTRL_GIO_DIS;
3648 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3649
3650 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3651 } else {
3652 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3653 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3654 }
3655
3656 if (wufc && hw->mac.type == ixgbe_mac_82599EB) {
3657 pci_enable_wake(pdev, PCI_D3hot, 1);
3658 pci_enable_wake(pdev, PCI_D3cold, 1);
3659 } else {
3660 pci_enable_wake(pdev, PCI_D3hot, 0);
3661 pci_enable_wake(pdev, PCI_D3cold, 0);
3662 }
3663
3664 ixgbe_release_hw_control(adapter);
3665
3666 pci_disable_device(pdev);
3667
3668 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3669
3670 return 0;
3671 }
3672
3673 static void ixgbe_shutdown(struct pci_dev *pdev)
3674 {
3675 ixgbe_suspend(pdev, PMSG_SUSPEND);
3676 }
3677
3678 /**
3679 * ixgbe_update_stats - Update the board statistics counters.
3680 * @adapter: board private structure
3681 **/
3682 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3683 {
3684 struct ixgbe_hw *hw = &adapter->hw;
3685 u64 total_mpc = 0;
3686 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3687
3688 if (hw->mac.type == ixgbe_mac_82599EB) {
3689 for (i = 0; i < 16; i++)
3690 adapter->hw_rx_no_dma_resources +=
3691 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3692 }
3693
3694 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3695 for (i = 0; i < 8; i++) {
3696 /* for packet buffers not used, the register should read 0 */
3697 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3698 missed_rx += mpc;
3699 adapter->stats.mpc[i] += mpc;
3700 total_mpc += adapter->stats.mpc[i];
3701 if (hw->mac.type == ixgbe_mac_82598EB)
3702 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3703 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3704 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3705 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3706 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3707 if (hw->mac.type == ixgbe_mac_82599EB) {
3708 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3709 IXGBE_PXONRXCNT(i));
3710 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3711 IXGBE_PXOFFRXCNT(i));
3712 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3713 } else {
3714 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3715 IXGBE_PXONRXC(i));
3716 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3717 IXGBE_PXOFFRXC(i));
3718 }
3719 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3720 IXGBE_PXONTXC(i));
3721 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3722 IXGBE_PXOFFTXC(i));
3723 }
3724 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3725 /* work around hardware counting issue */
3726 adapter->stats.gprc -= missed_rx;
3727
3728 /* 82598 hardware only has a 32 bit counter in the high register */
3729 if (hw->mac.type == ixgbe_mac_82599EB) {
3730 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3731 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3732 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3733 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3734 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3735 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3736 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3737 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3738 } else {
3739 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3740 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3741 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3742 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3743 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3744 }
3745 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3746 adapter->stats.bprc += bprc;
3747 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3748 if (hw->mac.type == ixgbe_mac_82598EB)
3749 adapter->stats.mprc -= bprc;
3750 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3751 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3752 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3753 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3754 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3755 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3756 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3757 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3758 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3759 adapter->stats.lxontxc += lxon;
3760 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3761 adapter->stats.lxofftxc += lxoff;
3762 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3763 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3764 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3765 /*
3766 * 82598 errata - tx of flow control packets is included in tx counters
3767 */
3768 xon_off_tot = lxon + lxoff;
3769 adapter->stats.gptc -= xon_off_tot;
3770 adapter->stats.mptc -= xon_off_tot;
3771 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3772 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3773 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3774 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3775 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3776 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3777 adapter->stats.ptc64 -= xon_off_tot;
3778 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3779 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3780 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3781 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3782 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3783 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3784
3785 /* Fill out the OS statistics structure */
3786 adapter->net_stats.multicast = adapter->stats.mprc;
3787
3788 /* Rx Errors */
3789 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3790 adapter->stats.rlec;
3791 adapter->net_stats.rx_dropped = 0;
3792 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3793 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3794 adapter->net_stats.rx_missed_errors = total_mpc;
3795 }
3796
3797 /**
3798 * ixgbe_watchdog - Timer Call-back
3799 * @data: pointer to adapter cast into an unsigned long
3800 **/
3801 static void ixgbe_watchdog(unsigned long data)
3802 {
3803 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3804 struct ixgbe_hw *hw = &adapter->hw;
3805
3806 /* Do the watchdog outside of interrupt context due to the lovely
3807 * delays that some of the newer hardware requires */
3808 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3809 /* Cause software interrupt to ensure rx rings are cleaned */
3810 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3811 u32 eics =
3812 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3813 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3814 } else {
3815 /* For legacy and MSI interrupts don't set any bits that
3816 * are enabled for EIAM, because this operation would
3817 * set *both* EIMS and EICS for any bit in EIAM */
3818 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3819 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3820 }
3821 /* Reset the timer */
3822 mod_timer(&adapter->watchdog_timer,
3823 round_jiffies(jiffies + 2 * HZ));
3824 }
3825
3826 schedule_work(&adapter->watchdog_task);
3827 }
3828
3829 /**
3830 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
3831 * @work: pointer to work_struct containing our data
3832 **/
3833 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
3834 {
3835 struct ixgbe_adapter *adapter = container_of(work,
3836 struct ixgbe_adapter,
3837 multispeed_fiber_task);
3838 struct ixgbe_hw *hw = &adapter->hw;
3839 u32 autoneg;
3840
3841 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
3842 if (hw->mac.ops.get_link_capabilities)
3843 hw->mac.ops.get_link_capabilities(hw, &autoneg,
3844 &hw->mac.autoneg);
3845 if (hw->mac.ops.setup_link_speed)
3846 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3847 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3848 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
3849 }
3850
3851 /**
3852 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
3853 * @work: pointer to work_struct containing our data
3854 **/
3855 static void ixgbe_sfp_config_module_task(struct work_struct *work)
3856 {
3857 struct ixgbe_adapter *adapter = container_of(work,
3858 struct ixgbe_adapter,
3859 sfp_config_module_task);
3860 struct ixgbe_hw *hw = &adapter->hw;
3861 u32 err;
3862
3863 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
3864 err = hw->phy.ops.identify_sfp(hw);
3865 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3866 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
3867 ixgbe_down(adapter);
3868 return;
3869 }
3870 hw->mac.ops.setup_sfp(hw);
3871
3872 if (!adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)
3873 /* This will also work for DA Twinax connections */
3874 schedule_work(&adapter->multispeed_fiber_task);
3875 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
3876 }
3877
3878 /**
3879 * ixgbe_watchdog_task - worker thread to bring link up
3880 * @work: pointer to work_struct containing our data
3881 **/
3882 static void ixgbe_watchdog_task(struct work_struct *work)
3883 {
3884 struct ixgbe_adapter *adapter = container_of(work,
3885 struct ixgbe_adapter,
3886 watchdog_task);
3887 struct net_device *netdev = adapter->netdev;
3888 struct ixgbe_hw *hw = &adapter->hw;
3889 u32 link_speed = adapter->link_speed;
3890 bool link_up = adapter->link_up;
3891
3892 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3893
3894 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3895 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3896 if (link_up ||
3897 time_after(jiffies, (adapter->link_check_timeout +
3898 IXGBE_TRY_LINK_TIMEOUT))) {
3899 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3900 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3901 }
3902 adapter->link_up = link_up;
3903 adapter->link_speed = link_speed;
3904 }
3905
3906 if (link_up) {
3907 if (!netif_carrier_ok(netdev)) {
3908 bool flow_rx, flow_tx;
3909
3910 if (hw->mac.type == ixgbe_mac_82599EB) {
3911 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3912 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3913 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
3914 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
3915 } else {
3916 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3917 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3918 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
3919 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
3920 }
3921
3922 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3923 "Flow Control: %s\n",
3924 netdev->name,
3925 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3926 "10 Gbps" :
3927 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3928 "1 Gbps" : "unknown speed")),
3929 ((flow_rx && flow_tx) ? "RX/TX" :
3930 (flow_rx ? "RX" :
3931 (flow_tx ? "TX" : "None"))));
3932
3933 netif_carrier_on(netdev);
3934 } else {
3935 /* Force detection of hung controller */
3936 adapter->detect_tx_hung = true;
3937 }
3938 } else {
3939 adapter->link_up = false;
3940 adapter->link_speed = 0;
3941 if (netif_carrier_ok(netdev)) {
3942 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3943 netdev->name);
3944 netif_carrier_off(netdev);
3945 }
3946 }
3947
3948 ixgbe_update_stats(adapter);
3949 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
3950 }
3951
3952 static int ixgbe_tso(struct ixgbe_adapter *adapter,
3953 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3954 u32 tx_flags, u8 *hdr_len)
3955 {
3956 struct ixgbe_adv_tx_context_desc *context_desc;
3957 unsigned int i;
3958 int err;
3959 struct ixgbe_tx_buffer *tx_buffer_info;
3960 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3961 u32 mss_l4len_idx, l4len;
3962
3963 if (skb_is_gso(skb)) {
3964 if (skb_header_cloned(skb)) {
3965 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3966 if (err)
3967 return err;
3968 }
3969 l4len = tcp_hdrlen(skb);
3970 *hdr_len += l4len;
3971
3972 if (skb->protocol == htons(ETH_P_IP)) {
3973 struct iphdr *iph = ip_hdr(skb);
3974 iph->tot_len = 0;
3975 iph->check = 0;
3976 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3977 iph->daddr, 0,
3978 IPPROTO_TCP,
3979 0);
3980 adapter->hw_tso_ctxt++;
3981 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3982 ipv6_hdr(skb)->payload_len = 0;
3983 tcp_hdr(skb)->check =
3984 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3985 &ipv6_hdr(skb)->daddr,
3986 0, IPPROTO_TCP, 0);
3987 adapter->hw_tso6_ctxt++;
3988 }
3989
3990 i = tx_ring->next_to_use;
3991
3992 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3993 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3994
3995 /* VLAN MACLEN IPLEN */
3996 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3997 vlan_macip_lens |=
3998 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3999 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4000 IXGBE_ADVTXD_MACLEN_SHIFT);
4001 *hdr_len += skb_network_offset(skb);
4002 vlan_macip_lens |=
4003 (skb_transport_header(skb) - skb_network_header(skb));
4004 *hdr_len +=
4005 (skb_transport_header(skb) - skb_network_header(skb));
4006 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4007 context_desc->seqnum_seed = 0;
4008
4009 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4010 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4011 IXGBE_ADVTXD_DTYP_CTXT);
4012
4013 if (skb->protocol == htons(ETH_P_IP))
4014 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4015 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4016 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4017
4018 /* MSS L4LEN IDX */
4019 mss_l4len_idx =
4020 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4021 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4022 /* use index 1 for TSO */
4023 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4024 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4025
4026 tx_buffer_info->time_stamp = jiffies;
4027 tx_buffer_info->next_to_watch = i;
4028
4029 i++;
4030 if (i == tx_ring->count)
4031 i = 0;
4032 tx_ring->next_to_use = i;
4033
4034 return true;
4035 }
4036 return false;
4037 }
4038
4039 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4040 struct ixgbe_ring *tx_ring,
4041 struct sk_buff *skb, u32 tx_flags)
4042 {
4043 struct ixgbe_adv_tx_context_desc *context_desc;
4044 unsigned int i;
4045 struct ixgbe_tx_buffer *tx_buffer_info;
4046 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4047
4048 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4049 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4050 i = tx_ring->next_to_use;
4051 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4052 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4053
4054 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4055 vlan_macip_lens |=
4056 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4057 vlan_macip_lens |= (skb_network_offset(skb) <<
4058 IXGBE_ADVTXD_MACLEN_SHIFT);
4059 if (skb->ip_summed == CHECKSUM_PARTIAL)
4060 vlan_macip_lens |= (skb_transport_header(skb) -
4061 skb_network_header(skb));
4062
4063 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4064 context_desc->seqnum_seed = 0;
4065
4066 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4067 IXGBE_ADVTXD_DTYP_CTXT);
4068
4069 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4070 switch (skb->protocol) {
4071 case cpu_to_be16(ETH_P_IP):
4072 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4073 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4074 type_tucmd_mlhl |=
4075 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4076 break;
4077 case cpu_to_be16(ETH_P_IPV6):
4078 /* XXX what about other V6 headers?? */
4079 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4080 type_tucmd_mlhl |=
4081 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4082 break;
4083 default:
4084 if (unlikely(net_ratelimit())) {
4085 DPRINTK(PROBE, WARNING,
4086 "partial checksum but proto=%x!\n",
4087 skb->protocol);
4088 }
4089 break;
4090 }
4091 }
4092
4093 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4094 /* use index zero for tx checksum offload */
4095 context_desc->mss_l4len_idx = 0;
4096
4097 tx_buffer_info->time_stamp = jiffies;
4098 tx_buffer_info->next_to_watch = i;
4099
4100 adapter->hw_csum_tx_good++;
4101 i++;
4102 if (i == tx_ring->count)
4103 i = 0;
4104 tx_ring->next_to_use = i;
4105
4106 return true;
4107 }
4108
4109 return false;
4110 }
4111
4112 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4113 struct ixgbe_ring *tx_ring,
4114 struct sk_buff *skb, unsigned int first)
4115 {
4116 struct ixgbe_tx_buffer *tx_buffer_info;
4117 unsigned int len = skb->len;
4118 unsigned int offset = 0, size, count = 0, i;
4119 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4120 unsigned int f;
4121
4122 len -= skb->data_len;
4123
4124 i = tx_ring->next_to_use;
4125
4126 while (len) {
4127 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4128 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4129
4130 tx_buffer_info->length = size;
4131 tx_buffer_info->dma = pci_map_single(adapter->pdev,
4132 skb->data + offset,
4133 size, PCI_DMA_TODEVICE);
4134 tx_buffer_info->time_stamp = jiffies;
4135 tx_buffer_info->next_to_watch = i;
4136
4137 len -= size;
4138 offset += size;
4139 count++;
4140 i++;
4141 if (i == tx_ring->count)
4142 i = 0;
4143 }
4144
4145 for (f = 0; f < nr_frags; f++) {
4146 struct skb_frag_struct *frag;
4147
4148 frag = &skb_shinfo(skb)->frags[f];
4149 len = frag->size;
4150 offset = frag->page_offset;
4151
4152 while (len) {
4153 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4154 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4155
4156 tx_buffer_info->length = size;
4157 tx_buffer_info->dma = pci_map_page(adapter->pdev,
4158 frag->page,
4159 offset,
4160 size,
4161 PCI_DMA_TODEVICE);
4162 tx_buffer_info->time_stamp = jiffies;
4163 tx_buffer_info->next_to_watch = i;
4164
4165 len -= size;
4166 offset += size;
4167 count++;
4168 i++;
4169 if (i == tx_ring->count)
4170 i = 0;
4171 }
4172 }
4173 if (i == 0)
4174 i = tx_ring->count - 1;
4175 else
4176 i = i - 1;
4177 tx_ring->tx_buffer_info[i].skb = skb;
4178 tx_ring->tx_buffer_info[first].next_to_watch = i;
4179
4180 return count;
4181 }
4182
4183 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4184 struct ixgbe_ring *tx_ring,
4185 int tx_flags, int count, u32 paylen, u8 hdr_len)
4186 {
4187 union ixgbe_adv_tx_desc *tx_desc = NULL;
4188 struct ixgbe_tx_buffer *tx_buffer_info;
4189 u32 olinfo_status = 0, cmd_type_len = 0;
4190 unsigned int i;
4191 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4192
4193 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4194
4195 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4196
4197 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4198 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4199
4200 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4201 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4202
4203 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4204 IXGBE_ADVTXD_POPTS_SHIFT;
4205
4206 /* use index 1 context for tso */
4207 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4208 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4209 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4210 IXGBE_ADVTXD_POPTS_SHIFT;
4211
4212 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4213 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4214 IXGBE_ADVTXD_POPTS_SHIFT;
4215
4216 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4217
4218 i = tx_ring->next_to_use;
4219 while (count--) {
4220 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4221 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4222 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4223 tx_desc->read.cmd_type_len =
4224 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4225 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4226 i++;
4227 if (i == tx_ring->count)
4228 i = 0;
4229 }
4230
4231 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4232
4233 /*
4234 * Force memory writes to complete before letting h/w
4235 * know there are new descriptors to fetch. (Only
4236 * applicable for weak-ordered memory model archs,
4237 * such as IA-64).
4238 */
4239 wmb();
4240
4241 tx_ring->next_to_use = i;
4242 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4243 }
4244
4245 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
4246 struct ixgbe_ring *tx_ring, int size)
4247 {
4248 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4249
4250 netif_stop_subqueue(netdev, tx_ring->queue_index);
4251 /* Herbert's original patch had:
4252 * smp_mb__after_netif_stop_queue();
4253 * but since that doesn't exist yet, just open code it. */
4254 smp_mb();
4255
4256 /* We need to check again in a case another CPU has just
4257 * made room available. */
4258 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4259 return -EBUSY;
4260
4261 /* A reprieve! - use start_queue because it doesn't call schedule */
4262 netif_start_subqueue(netdev, tx_ring->queue_index);
4263 ++adapter->restart_queue;
4264 return 0;
4265 }
4266
4267 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
4268 struct ixgbe_ring *tx_ring, int size)
4269 {
4270 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4271 return 0;
4272 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4273 }
4274
4275 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4276 {
4277 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4278 struct ixgbe_ring *tx_ring;
4279 unsigned int first;
4280 unsigned int tx_flags = 0;
4281 u8 hdr_len = 0;
4282 int r_idx = 0, tso;
4283 int count = 0;
4284 unsigned int f;
4285
4286 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
4287 tx_ring = &adapter->tx_ring[r_idx];
4288
4289 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4290 tx_flags |= vlan_tx_tag_get(skb);
4291 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4292 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4293 tx_flags |= (skb->queue_mapping << 13);
4294 }
4295 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4296 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4297 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4298 tx_flags |= (skb->queue_mapping << 13);
4299 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4300 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4301 }
4302 /* three things can cause us to need a context descriptor */
4303 if (skb_is_gso(skb) ||
4304 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4305 (tx_flags & IXGBE_TX_FLAGS_VLAN))
4306 count++;
4307
4308 count += TXD_USE_COUNT(skb_headlen(skb));
4309 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4310 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4311
4312 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
4313 adapter->tx_busy++;
4314 return NETDEV_TX_BUSY;
4315 }
4316
4317 if (skb->protocol == htons(ETH_P_IP))
4318 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4319 first = tx_ring->next_to_use;
4320 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4321 if (tso < 0) {
4322 dev_kfree_skb_any(skb);
4323 return NETDEV_TX_OK;
4324 }
4325
4326 if (tso)
4327 tx_flags |= IXGBE_TX_FLAGS_TSO;
4328 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4329 (skb->ip_summed == CHECKSUM_PARTIAL))
4330 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4331
4332 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
4333 ixgbe_tx_map(adapter, tx_ring, skb, first),
4334 skb->len, hdr_len);
4335
4336 netdev->trans_start = jiffies;
4337
4338 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
4339
4340 return NETDEV_TX_OK;
4341 }
4342
4343 /**
4344 * ixgbe_get_stats - Get System Network Statistics
4345 * @netdev: network interface device structure
4346 *
4347 * Returns the address of the device statistics structure.
4348 * The statistics are actually updated from the timer callback.
4349 **/
4350 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4351 {
4352 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4353
4354 /* only return the current stats */
4355 return &adapter->net_stats;
4356 }
4357
4358 /**
4359 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4360 * @netdev: network interface device structure
4361 * @p: pointer to an address structure
4362 *
4363 * Returns 0 on success, negative on failure
4364 **/
4365 static int ixgbe_set_mac(struct net_device *netdev, void *p)
4366 {
4367 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4368 struct ixgbe_hw *hw = &adapter->hw;
4369 struct sockaddr *addr = p;
4370
4371 if (!is_valid_ether_addr(addr->sa_data))
4372 return -EADDRNOTAVAIL;
4373
4374 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4375 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4376
4377 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4378
4379 return 0;
4380 }
4381
4382 #ifdef CONFIG_NET_POLL_CONTROLLER
4383 /*
4384 * Polling 'interrupt' - used by things like netconsole to send skbs
4385 * without having to re-enable interrupts. It's not called while
4386 * the interrupt routine is executing.
4387 */
4388 static void ixgbe_netpoll(struct net_device *netdev)
4389 {
4390 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4391
4392 disable_irq(adapter->pdev->irq);
4393 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4394 ixgbe_intr(adapter->pdev->irq, netdev);
4395 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4396 enable_irq(adapter->pdev->irq);
4397 }
4398 #endif
4399
4400 static const struct net_device_ops ixgbe_netdev_ops = {
4401 .ndo_open = ixgbe_open,
4402 .ndo_stop = ixgbe_close,
4403 .ndo_start_xmit = ixgbe_xmit_frame,
4404 .ndo_get_stats = ixgbe_get_stats,
4405 .ndo_set_rx_mode = ixgbe_set_rx_mode,
4406 .ndo_set_multicast_list = ixgbe_set_rx_mode,
4407 .ndo_validate_addr = eth_validate_addr,
4408 .ndo_set_mac_address = ixgbe_set_mac,
4409 .ndo_change_mtu = ixgbe_change_mtu,
4410 .ndo_tx_timeout = ixgbe_tx_timeout,
4411 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
4412 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
4413 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
4414 #ifdef CONFIG_NET_POLL_CONTROLLER
4415 .ndo_poll_controller = ixgbe_netpoll,
4416 #endif
4417 };
4418
4419 /**
4420 * ixgbe_probe - Device Initialization Routine
4421 * @pdev: PCI device information struct
4422 * @ent: entry in ixgbe_pci_tbl
4423 *
4424 * Returns 0 on success, negative on failure
4425 *
4426 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4427 * The OS initialization, configuring of the adapter private structure,
4428 * and a hardware reset occur.
4429 **/
4430 static int __devinit ixgbe_probe(struct pci_dev *pdev,
4431 const struct pci_device_id *ent)
4432 {
4433 struct net_device *netdev;
4434 struct ixgbe_adapter *adapter = NULL;
4435 struct ixgbe_hw *hw;
4436 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
4437 static int cards_found;
4438 int i, err, pci_using_dac;
4439 u16 pm_value = 0;
4440 u32 part_num, eec;
4441
4442 err = pci_enable_device(pdev);
4443 if (err)
4444 return err;
4445
4446 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
4447 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
4448 pci_using_dac = 1;
4449 } else {
4450 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4451 if (err) {
4452 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4453 if (err) {
4454 dev_err(&pdev->dev, "No usable DMA "
4455 "configuration, aborting\n");
4456 goto err_dma;
4457 }
4458 }
4459 pci_using_dac = 0;
4460 }
4461
4462 err = pci_request_regions(pdev, ixgbe_driver_name);
4463 if (err) {
4464 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4465 goto err_pci_reg;
4466 }
4467
4468 err = pci_enable_pcie_error_reporting(pdev);
4469 if (err) {
4470 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4471 "0x%x\n", err);
4472 /* non-fatal, continue */
4473 }
4474
4475 pci_set_master(pdev);
4476 pci_save_state(pdev);
4477
4478 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
4479 if (!netdev) {
4480 err = -ENOMEM;
4481 goto err_alloc_etherdev;
4482 }
4483
4484 SET_NETDEV_DEV(netdev, &pdev->dev);
4485
4486 pci_set_drvdata(pdev, netdev);
4487 adapter = netdev_priv(netdev);
4488
4489 adapter->netdev = netdev;
4490 adapter->pdev = pdev;
4491 hw = &adapter->hw;
4492 hw->back = adapter;
4493 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4494
4495 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4496 pci_resource_len(pdev, 0));
4497 if (!hw->hw_addr) {
4498 err = -EIO;
4499 goto err_ioremap;
4500 }
4501
4502 for (i = 1; i <= 5; i++) {
4503 if (pci_resource_len(pdev, i) == 0)
4504 continue;
4505 }
4506
4507 netdev->netdev_ops = &ixgbe_netdev_ops;
4508 ixgbe_set_ethtool_ops(netdev);
4509 netdev->watchdog_timeo = 5 * HZ;
4510 strcpy(netdev->name, pci_name(pdev));
4511
4512 adapter->bd_number = cards_found;
4513
4514 /* Setup hw api */
4515 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4516 hw->mac.type = ii->mac;
4517
4518 /* EEPROM */
4519 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4520 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4521 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4522 if (!(eec & (1 << 8)))
4523 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4524
4525 /* PHY */
4526 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4527 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4528
4529 /* set up this timer and work struct before calling get_invariants
4530 * which might start the timer
4531 */
4532 init_timer(&adapter->sfp_timer);
4533 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4534 adapter->sfp_timer.data = (unsigned long) adapter;
4535
4536 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4537
4538 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4539 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4540
4541 /* a new SFP+ module arrival, called from GPI SDP2 context */
4542 INIT_WORK(&adapter->sfp_config_module_task,
4543 ixgbe_sfp_config_module_task);
4544
4545 err = ii->get_invariants(hw);
4546 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4547 /* start a kernel thread to watch for a module to arrive */
4548 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4549 mod_timer(&adapter->sfp_timer,
4550 round_jiffies(jiffies + (2 * HZ)));
4551 err = 0;
4552 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4553 DPRINTK(PROBE, ERR, "failed to load because an "
4554 "unsupported SFP+ module type was detected.\n");
4555 goto err_hw_init;
4556 } else if (err) {
4557 goto err_hw_init;
4558 }
4559
4560 /* setup the private structure */
4561 err = ixgbe_sw_init(adapter);
4562 if (err)
4563 goto err_sw_init;
4564
4565 /* reset_hw fills in the perm_addr as well */
4566 err = hw->mac.ops.reset_hw(hw);
4567 if (err) {
4568 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4569 goto err_sw_init;
4570 }
4571
4572 netdev->features = NETIF_F_SG |
4573 NETIF_F_IP_CSUM |
4574 NETIF_F_HW_VLAN_TX |
4575 NETIF_F_HW_VLAN_RX |
4576 NETIF_F_HW_VLAN_FILTER;
4577
4578 netdev->features |= NETIF_F_IPV6_CSUM;
4579 netdev->features |= NETIF_F_TSO;
4580 netdev->features |= NETIF_F_TSO6;
4581 netdev->features |= NETIF_F_GRO;
4582
4583 netdev->vlan_features |= NETIF_F_TSO;
4584 netdev->vlan_features |= NETIF_F_TSO6;
4585 netdev->vlan_features |= NETIF_F_IP_CSUM;
4586 netdev->vlan_features |= NETIF_F_SG;
4587
4588 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4589 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4590
4591 #ifdef CONFIG_IXGBE_DCB
4592 netdev->dcbnl_ops = &dcbnl_ops;
4593 #endif
4594
4595 if (pci_using_dac)
4596 netdev->features |= NETIF_F_HIGHDMA;
4597
4598 /* make sure the EEPROM is good */
4599 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
4600 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4601 err = -EIO;
4602 goto err_eeprom;
4603 }
4604
4605 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4606 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4607
4608 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4609 dev_err(&pdev->dev, "invalid MAC address\n");
4610 err = -EIO;
4611 goto err_eeprom;
4612 }
4613
4614 init_timer(&adapter->watchdog_timer);
4615 adapter->watchdog_timer.function = &ixgbe_watchdog;
4616 adapter->watchdog_timer.data = (unsigned long)adapter;
4617
4618 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
4619 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
4620
4621 err = ixgbe_init_interrupt_scheme(adapter);
4622 if (err)
4623 goto err_sw_init;
4624
4625 switch (pdev->device) {
4626 case IXGBE_DEV_ID_82599_KX4:
4627 #define IXGBE_PCIE_PMCSR 0x44
4628 adapter->wol = IXGBE_WUFC_MAG;
4629 pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value);
4630 pci_write_config_word(pdev, IXGBE_PCIE_PMCSR,
4631 (pm_value | (1 << 8)));
4632 break;
4633 default:
4634 adapter->wol = 0;
4635 break;
4636 }
4637 device_init_wakeup(&adapter->pdev->dev, true);
4638 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4639
4640 /* print bus type/speed/width info */
4641 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
4642 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4643 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4644 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4645 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4646 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
4647 "Unknown"),
4648 netdev->dev_addr);
4649 ixgbe_read_pba_num_generic(hw, &part_num);
4650 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4651 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4652 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4653 (part_num >> 8), (part_num & 0xff));
4654 else
4655 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4656 hw->mac.type, hw->phy.type,
4657 (part_num >> 8), (part_num & 0xff));
4658
4659 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
4660 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
4661 "this card is not sufficient for optimal "
4662 "performance.\n");
4663 dev_warn(&pdev->dev, "For optimal performance a x8 "
4664 "PCI-Express slot is required.\n");
4665 }
4666
4667 /* save off EEPROM version number */
4668 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4669
4670 /* reset the hardware with the new settings */
4671 hw->mac.ops.start_hw(hw);
4672
4673 netif_carrier_off(netdev);
4674
4675 strcpy(netdev->name, "eth%d");
4676 err = register_netdev(netdev);
4677 if (err)
4678 goto err_register;
4679
4680 #ifdef CONFIG_IXGBE_DCA
4681 if (dca_add_requester(&pdev->dev) == 0) {
4682 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4683 /* always use CB2 mode, difference is masked
4684 * in the CB driver */
4685 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4686 ixgbe_setup_dca(adapter);
4687 }
4688 #endif
4689
4690 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4691 cards_found++;
4692 return 0;
4693
4694 err_register:
4695 ixgbe_release_hw_control(adapter);
4696 err_hw_init:
4697 err_sw_init:
4698 ixgbe_reset_interrupt_capability(adapter);
4699 err_eeprom:
4700 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4701 del_timer_sync(&adapter->sfp_timer);
4702 cancel_work_sync(&adapter->sfp_task);
4703 cancel_work_sync(&adapter->multispeed_fiber_task);
4704 cancel_work_sync(&adapter->sfp_config_module_task);
4705 iounmap(hw->hw_addr);
4706 err_ioremap:
4707 free_netdev(netdev);
4708 err_alloc_etherdev:
4709 pci_release_regions(pdev);
4710 err_pci_reg:
4711 err_dma:
4712 pci_disable_device(pdev);
4713 return err;
4714 }
4715
4716 /**
4717 * ixgbe_remove - Device Removal Routine
4718 * @pdev: PCI device information struct
4719 *
4720 * ixgbe_remove is called by the PCI subsystem to alert the driver
4721 * that it should release a PCI device. The could be caused by a
4722 * Hot-Plug event, or because the driver is going to be removed from
4723 * memory.
4724 **/
4725 static void __devexit ixgbe_remove(struct pci_dev *pdev)
4726 {
4727 struct net_device *netdev = pci_get_drvdata(pdev);
4728 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4729 int err;
4730
4731 set_bit(__IXGBE_DOWN, &adapter->state);
4732 /* clear the module not found bit to make sure the worker won't
4733 * reschedule
4734 */
4735 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4736 del_timer_sync(&adapter->watchdog_timer);
4737
4738 del_timer_sync(&adapter->sfp_timer);
4739 cancel_work_sync(&adapter->watchdog_task);
4740 cancel_work_sync(&adapter->sfp_task);
4741 cancel_work_sync(&adapter->multispeed_fiber_task);
4742 cancel_work_sync(&adapter->sfp_config_module_task);
4743 flush_scheduled_work();
4744
4745 #ifdef CONFIG_IXGBE_DCA
4746 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4747 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4748 dca_remove_requester(&pdev->dev);
4749 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4750 }
4751
4752 #endif
4753 if (netdev->reg_state == NETREG_REGISTERED)
4754 unregister_netdev(netdev);
4755
4756 ixgbe_reset_interrupt_capability(adapter);
4757
4758 ixgbe_release_hw_control(adapter);
4759
4760 iounmap(adapter->hw.hw_addr);
4761 pci_release_regions(pdev);
4762
4763 DPRINTK(PROBE, INFO, "complete\n");
4764 kfree(adapter->tx_ring);
4765 kfree(adapter->rx_ring);
4766
4767 free_netdev(netdev);
4768
4769 err = pci_disable_pcie_error_reporting(pdev);
4770 if (err)
4771 dev_err(&pdev->dev,
4772 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4773
4774 pci_disable_device(pdev);
4775 }
4776
4777 /**
4778 * ixgbe_io_error_detected - called when PCI error is detected
4779 * @pdev: Pointer to PCI device
4780 * @state: The current pci connection state
4781 *
4782 * This function is called after a PCI bus error affecting
4783 * this device has been detected.
4784 */
4785 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
4786 pci_channel_state_t state)
4787 {
4788 struct net_device *netdev = pci_get_drvdata(pdev);
4789 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4790
4791 netif_device_detach(netdev);
4792
4793 if (netif_running(netdev))
4794 ixgbe_down(adapter);
4795 pci_disable_device(pdev);
4796
4797 /* Request a slot reset. */
4798 return PCI_ERS_RESULT_NEED_RESET;
4799 }
4800
4801 /**
4802 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4803 * @pdev: Pointer to PCI device
4804 *
4805 * Restart the card from scratch, as if from a cold-boot.
4806 */
4807 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4808 {
4809 struct net_device *netdev = pci_get_drvdata(pdev);
4810 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4811 pci_ers_result_t result;
4812 int err;
4813
4814 if (pci_enable_device(pdev)) {
4815 DPRINTK(PROBE, ERR,
4816 "Cannot re-enable PCI device after reset.\n");
4817 result = PCI_ERS_RESULT_DISCONNECT;
4818 } else {
4819 pci_set_master(pdev);
4820 pci_restore_state(pdev);
4821
4822 pci_enable_wake(pdev, PCI_D3hot, 0);
4823 pci_enable_wake(pdev, PCI_D3cold, 0);
4824
4825 ixgbe_reset(adapter);
4826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4827 result = PCI_ERS_RESULT_RECOVERED;
4828 }
4829
4830 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4831 if (err) {
4832 dev_err(&pdev->dev,
4833 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4834 /* non-fatal, continue */
4835 }
4836
4837 return result;
4838 }
4839
4840 /**
4841 * ixgbe_io_resume - called when traffic can start flowing again.
4842 * @pdev: Pointer to PCI device
4843 *
4844 * This callback is called when the error recovery driver tells us that
4845 * its OK to resume normal operation.
4846 */
4847 static void ixgbe_io_resume(struct pci_dev *pdev)
4848 {
4849 struct net_device *netdev = pci_get_drvdata(pdev);
4850 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4851
4852 if (netif_running(netdev)) {
4853 if (ixgbe_up(adapter)) {
4854 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4855 return;
4856 }
4857 }
4858
4859 netif_device_attach(netdev);
4860 }
4861
4862 static struct pci_error_handlers ixgbe_err_handler = {
4863 .error_detected = ixgbe_io_error_detected,
4864 .slot_reset = ixgbe_io_slot_reset,
4865 .resume = ixgbe_io_resume,
4866 };
4867
4868 static struct pci_driver ixgbe_driver = {
4869 .name = ixgbe_driver_name,
4870 .id_table = ixgbe_pci_tbl,
4871 .probe = ixgbe_probe,
4872 .remove = __devexit_p(ixgbe_remove),
4873 #ifdef CONFIG_PM
4874 .suspend = ixgbe_suspend,
4875 .resume = ixgbe_resume,
4876 #endif
4877 .shutdown = ixgbe_shutdown,
4878 .err_handler = &ixgbe_err_handler
4879 };
4880
4881 /**
4882 * ixgbe_init_module - Driver Registration Routine
4883 *
4884 * ixgbe_init_module is the first routine called when the driver is
4885 * loaded. All it does is register with the PCI subsystem.
4886 **/
4887 static int __init ixgbe_init_module(void)
4888 {
4889 int ret;
4890 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4891 ixgbe_driver_string, ixgbe_driver_version);
4892
4893 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4894
4895 #ifdef CONFIG_IXGBE_DCA
4896 dca_register_notify(&dca_notifier);
4897 #endif
4898
4899 ret = pci_register_driver(&ixgbe_driver);
4900 return ret;
4901 }
4902
4903 module_init(ixgbe_init_module);
4904
4905 /**
4906 * ixgbe_exit_module - Driver Exit Cleanup Routine
4907 *
4908 * ixgbe_exit_module is called just before the driver is removed
4909 * from memory.
4910 **/
4911 static void __exit ixgbe_exit_module(void)
4912 {
4913 #ifdef CONFIG_IXGBE_DCA
4914 dca_unregister_notify(&dca_notifier);
4915 #endif
4916 pci_unregister_driver(&ixgbe_driver);
4917 }
4918
4919 #ifdef CONFIG_IXGBE_DCA
4920 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
4921 void *p)
4922 {
4923 int ret_val;
4924
4925 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
4926 __ixgbe_notify_dca);
4927
4928 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4929 }
4930 #endif /* CONFIG_IXGBE_DCA */
4931
4932 module_exit(ixgbe_exit_module);
4933
4934 /* ixgbe_main.c */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree