2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
37 #include "rt2x00pci.h"
41 * Allow hardware encryption to be disabled.
43 static int modparam_nohwcrypt
= 0;
44 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
45 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
58 #define WAIT_FOR_BBP(__dev, __reg) \
59 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
60 #define WAIT_FOR_RF(__dev, __reg) \
61 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
62 #define WAIT_FOR_MCU(__dev, __reg) \
63 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
64 H2M_MAILBOX_CSR_OWNER, (__reg))
66 static void rt61pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
67 const unsigned int word
, const u8 value
)
71 mutex_lock(&rt2x00dev
->csr_mutex
);
74 * Wait until the BBP becomes available, afterwards we
75 * can safely write the new data into the register.
77 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
79 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
80 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
81 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
82 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
84 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
87 mutex_unlock(&rt2x00dev
->csr_mutex
);
90 static void rt61pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
91 const unsigned int word
, u8
*value
)
95 mutex_lock(&rt2x00dev
->csr_mutex
);
98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
105 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
107 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
108 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
109 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
111 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
113 WAIT_FOR_BBP(rt2x00dev
, ®
);
116 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
118 mutex_unlock(&rt2x00dev
->csr_mutex
);
121 static void rt61pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
122 const unsigned int word
, const u32 value
)
126 mutex_lock(&rt2x00dev
->csr_mutex
);
129 * Wait until the RF becomes available, afterwards we
130 * can safely write the new data into the register.
132 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
134 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
135 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
, 21);
136 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
137 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
139 rt2x00pci_register_write(rt2x00dev
, PHY_CSR4
, reg
);
140 rt2x00_rf_write(rt2x00dev
, word
, value
);
143 mutex_unlock(&rt2x00dev
->csr_mutex
);
146 static void rt61pci_mcu_request(struct rt2x00_dev
*rt2x00dev
,
147 const u8 command
, const u8 token
,
148 const u8 arg0
, const u8 arg1
)
152 mutex_lock(&rt2x00dev
->csr_mutex
);
155 * Wait until the MCU becomes available, afterwards we
156 * can safely write the new data into the register.
158 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
159 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
160 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
161 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
162 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
163 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
165 rt2x00pci_register_read(rt2x00dev
, HOST_CMD_CSR
, ®
);
166 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
167 rt2x00_set_field32(®
, HOST_CMD_CSR_INTERRUPT_MCU
, 1);
168 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, reg
);
171 mutex_unlock(&rt2x00dev
->csr_mutex
);
175 static void rt61pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
177 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
180 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
182 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
183 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
184 eeprom
->reg_data_clock
=
185 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
186 eeprom
->reg_chip_select
=
187 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
190 static void rt61pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
192 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
195 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
196 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
197 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
198 !!eeprom
->reg_data_clock
);
199 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
200 !!eeprom
->reg_chip_select
);
202 rt2x00pci_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
205 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
206 static const struct rt2x00debug rt61pci_rt2x00debug
= {
207 .owner
= THIS_MODULE
,
209 .read
= rt2x00pci_register_read
,
210 .write
= rt2x00pci_register_write
,
211 .flags
= RT2X00DEBUGFS_OFFSET
,
212 .word_base
= CSR_REG_BASE
,
213 .word_size
= sizeof(u32
),
214 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
217 .read
= rt2x00_eeprom_read
,
218 .write
= rt2x00_eeprom_write
,
219 .word_base
= EEPROM_BASE
,
220 .word_size
= sizeof(u16
),
221 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
224 .read
= rt61pci_bbp_read
,
225 .write
= rt61pci_bbp_write
,
226 .word_base
= BBP_BASE
,
227 .word_size
= sizeof(u8
),
228 .word_count
= BBP_SIZE
/ sizeof(u8
),
231 .read
= rt2x00_rf_read
,
232 .write
= rt61pci_rf_write
,
233 .word_base
= RF_BASE
,
234 .word_size
= sizeof(u32
),
235 .word_count
= RF_SIZE
/ sizeof(u32
),
238 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
240 #ifdef CONFIG_RT2X00_LIB_RFKILL
241 static int rt61pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
245 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
246 return rt2x00_get_field32(reg
, MAC_CSR13_BIT5
);
249 #define rt61pci_rfkill_poll NULL
250 #endif /* CONFIG_RT2X00_LIB_RFKILL */
252 #ifdef CONFIG_RT2X00_LIB_LEDS
253 static void rt61pci_brightness_set(struct led_classdev
*led_cdev
,
254 enum led_brightness brightness
)
256 struct rt2x00_led
*led
=
257 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
258 unsigned int enabled
= brightness
!= LED_OFF
;
259 unsigned int a_mode
=
260 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
261 unsigned int bg_mode
=
262 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
264 if (led
->type
== LED_TYPE_RADIO
) {
265 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
266 MCU_LEDCS_RADIO_STATUS
, enabled
);
268 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
269 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
270 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
271 } else if (led
->type
== LED_TYPE_ASSOC
) {
272 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
273 MCU_LEDCS_LINK_BG_STATUS
, bg_mode
);
274 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
275 MCU_LEDCS_LINK_A_STATUS
, a_mode
);
277 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
278 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
279 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
280 } else if (led
->type
== LED_TYPE_QUALITY
) {
282 * The brightness is divided into 6 levels (0 - 5),
283 * this means we need to convert the brightness
284 * argument into the matching level within that range.
286 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
287 brightness
/ (LED_FULL
/ 6), 0);
291 static int rt61pci_blink_set(struct led_classdev
*led_cdev
,
292 unsigned long *delay_on
,
293 unsigned long *delay_off
)
295 struct rt2x00_led
*led
=
296 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
299 rt2x00pci_register_read(led
->rt2x00dev
, MAC_CSR14
, ®
);
300 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, *delay_on
);
301 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, *delay_off
);
302 rt2x00pci_register_write(led
->rt2x00dev
, MAC_CSR14
, reg
);
307 static void rt61pci_init_led(struct rt2x00_dev
*rt2x00dev
,
308 struct rt2x00_led
*led
,
311 led
->rt2x00dev
= rt2x00dev
;
313 led
->led_dev
.brightness_set
= rt61pci_brightness_set
;
314 led
->led_dev
.blink_set
= rt61pci_blink_set
;
315 led
->flags
= LED_INITIALIZED
;
317 #endif /* CONFIG_RT2X00_LIB_LEDS */
320 * Configuration handlers.
322 static int rt61pci_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
323 struct rt2x00lib_crypto
*crypto
,
324 struct ieee80211_key_conf
*key
)
326 struct hw_key_entry key_entry
;
327 struct rt2x00_field32 field
;
331 if (crypto
->cmd
== SET_KEY
) {
333 * rt2x00lib can't determine the correct free
334 * key_idx for shared keys. We have 1 register
335 * with key valid bits. The goal is simple, read
336 * the register, if that is full we have no slots
338 * Note that each BSS is allowed to have up to 4
339 * shared keys, so put a mask over the allowed
342 mask
= (0xf << crypto
->bssidx
);
344 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
347 if (reg
&& reg
== mask
)
350 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
353 * Upload key to hardware
355 memcpy(key_entry
.key
, crypto
->key
,
356 sizeof(key_entry
.key
));
357 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
358 sizeof(key_entry
.tx_mic
));
359 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
360 sizeof(key_entry
.rx_mic
));
362 reg
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
363 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
364 &key_entry
, sizeof(key_entry
));
367 * The cipher types are stored over 2 registers.
368 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
369 * bssidx 1 and 2 keys are stored in SEC_CSR5.
370 * Using the correct defines correctly will cause overhead,
371 * so just calculate the correct offset.
373 if (key
->hw_key_idx
< 8) {
374 field
.bit_offset
= (3 * key
->hw_key_idx
);
375 field
.bit_mask
= 0x7 << field
.bit_offset
;
377 rt2x00pci_register_read(rt2x00dev
, SEC_CSR1
, ®
);
378 rt2x00_set_field32(®
, field
, crypto
->cipher
);
379 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, reg
);
381 field
.bit_offset
= (3 * (key
->hw_key_idx
- 8));
382 field
.bit_mask
= 0x7 << field
.bit_offset
;
384 rt2x00pci_register_read(rt2x00dev
, SEC_CSR5
, ®
);
385 rt2x00_set_field32(®
, field
, crypto
->cipher
);
386 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, reg
);
390 * The driver does not support the IV/EIV generation
391 * in hardware. However it doesn't support the IV/EIV
392 * inside the ieee80211 frame either, but requires it
393 * to be provided seperately for the descriptor.
394 * rt2x00lib will cut the IV/EIV data out of all frames
395 * given to us by mac80211, but we must tell mac80211
396 * to generate the IV/EIV data.
398 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
402 * SEC_CSR0 contains only single-bit fields to indicate
403 * a particular key is valid. Because using the FIELD32()
404 * defines directly will cause a lot of overhead we use
405 * a calculation to determine the correct bit directly.
407 mask
= 1 << key
->hw_key_idx
;
409 rt2x00pci_register_read(rt2x00dev
, SEC_CSR0
, ®
);
410 if (crypto
->cmd
== SET_KEY
)
412 else if (crypto
->cmd
== DISABLE_KEY
)
414 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, reg
);
419 static int rt61pci_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
420 struct rt2x00lib_crypto
*crypto
,
421 struct ieee80211_key_conf
*key
)
423 struct hw_pairwise_ta_entry addr_entry
;
424 struct hw_key_entry key_entry
;
428 if (crypto
->cmd
== SET_KEY
) {
430 * rt2x00lib can't determine the correct free
431 * key_idx for pairwise keys. We have 2 registers
432 * with key valid bits. The goal is simple, read
433 * the first register, if that is full move to
435 * When both registers are full, we drop the key,
436 * otherwise we use the first invalid entry.
438 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
439 if (reg
&& reg
== ~0) {
440 key
->hw_key_idx
= 32;
441 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
442 if (reg
&& reg
== ~0)
446 key
->hw_key_idx
+= reg
? ffz(reg
) : 0;
449 * Upload key to hardware
451 memcpy(key_entry
.key
, crypto
->key
,
452 sizeof(key_entry
.key
));
453 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
454 sizeof(key_entry
.tx_mic
));
455 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
456 sizeof(key_entry
.rx_mic
));
458 memset(&addr_entry
, 0, sizeof(addr_entry
));
459 memcpy(&addr_entry
, crypto
->address
, ETH_ALEN
);
460 addr_entry
.cipher
= crypto
->cipher
;
462 reg
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
463 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
464 &key_entry
, sizeof(key_entry
));
466 reg
= PAIRWISE_TA_ENTRY(key
->hw_key_idx
);
467 rt2x00pci_register_multiwrite(rt2x00dev
, reg
,
468 &addr_entry
, sizeof(addr_entry
));
471 * Enable pairwise lookup table for given BSS idx,
472 * without this received frames will not be decrypted
475 rt2x00pci_register_read(rt2x00dev
, SEC_CSR4
, ®
);
476 reg
|= (1 << crypto
->bssidx
);
477 rt2x00pci_register_write(rt2x00dev
, SEC_CSR4
, reg
);
480 * The driver does not support the IV/EIV generation
481 * in hardware. However it doesn't support the IV/EIV
482 * inside the ieee80211 frame either, but requires it
483 * to be provided seperately for the descriptor.
484 * rt2x00lib will cut the IV/EIV data out of all frames
485 * given to us by mac80211, but we must tell mac80211
486 * to generate the IV/EIV data.
488 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
492 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
493 * a particular key is valid. Because using the FIELD32()
494 * defines directly will cause a lot of overhead we use
495 * a calculation to determine the correct bit directly.
497 if (key
->hw_key_idx
< 32) {
498 mask
= 1 << key
->hw_key_idx
;
500 rt2x00pci_register_read(rt2x00dev
, SEC_CSR2
, ®
);
501 if (crypto
->cmd
== SET_KEY
)
503 else if (crypto
->cmd
== DISABLE_KEY
)
505 rt2x00pci_register_write(rt2x00dev
, SEC_CSR2
, reg
);
507 mask
= 1 << (key
->hw_key_idx
- 32);
509 rt2x00pci_register_read(rt2x00dev
, SEC_CSR3
, ®
);
510 if (crypto
->cmd
== SET_KEY
)
512 else if (crypto
->cmd
== DISABLE_KEY
)
514 rt2x00pci_register_write(rt2x00dev
, SEC_CSR3
, reg
);
520 static void rt61pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
521 const unsigned int filter_flags
)
526 * Start configuration steps.
527 * Note that the version error will always be dropped
528 * and broadcast frames will always be accepted since
529 * there is no filter for it at this time.
531 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
532 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
,
533 !(filter_flags
& FIF_FCSFAIL
));
534 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
,
535 !(filter_flags
& FIF_PLCPFAIL
));
536 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
,
537 !(filter_flags
& FIF_CONTROL
));
538 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
,
539 !(filter_flags
& FIF_PROMISC_IN_BSS
));
540 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
,
541 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
542 !rt2x00dev
->intf_ap_count
);
543 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
544 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
,
545 !(filter_flags
& FIF_ALLMULTI
));
546 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BROADCAST
, 0);
547 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
,
548 !(filter_flags
& FIF_CONTROL
));
549 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
552 static void rt61pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
553 struct rt2x00_intf
*intf
,
554 struct rt2x00intf_conf
*conf
,
555 const unsigned int flags
)
557 unsigned int beacon_base
;
560 if (flags
& CONFIG_UPDATE_TYPE
) {
562 * Clear current synchronisation setup.
563 * For the Beacon base registers we only need to clear
564 * the first byte since that byte contains the VALID and OWNER
565 * bits which (when set to 0) will invalidate the entire beacon.
567 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
568 rt2x00pci_register_write(rt2x00dev
, beacon_base
, 0);
571 * Enable synchronisation.
573 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
574 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
575 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, conf
->sync
);
576 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
577 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
580 if (flags
& CONFIG_UPDATE_MAC
) {
581 reg
= le32_to_cpu(conf
->mac
[1]);
582 rt2x00_set_field32(®
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
583 conf
->mac
[1] = cpu_to_le32(reg
);
585 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR2
,
586 conf
->mac
, sizeof(conf
->mac
));
589 if (flags
& CONFIG_UPDATE_BSSID
) {
590 reg
= le32_to_cpu(conf
->bssid
[1]);
591 rt2x00_set_field32(®
, MAC_CSR5_BSS_ID_MASK
, 3);
592 conf
->bssid
[1] = cpu_to_le32(reg
);
594 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR4
,
595 conf
->bssid
, sizeof(conf
->bssid
));
599 static void rt61pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
600 struct rt2x00lib_erp
*erp
)
604 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
605 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, erp
->ack_timeout
);
606 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
608 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
609 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
,
610 !!erp
->short_preamble
);
611 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
613 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR5
, erp
->basic_rates
);
615 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
616 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
, erp
->slot_time
);
617 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
619 rt2x00pci_register_read(rt2x00dev
, MAC_CSR8
, ®
);
620 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, erp
->sifs
);
621 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
622 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, erp
->eifs
);
623 rt2x00pci_register_write(rt2x00dev
, MAC_CSR8
, reg
);
626 static void rt61pci_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
627 struct antenna_setup
*ant
)
633 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
634 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
635 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
637 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
,
638 rt2x00_rf(&rt2x00dev
->chip
, RF5325
));
641 * Configure the RX antenna.
644 case ANTENNA_HW_DIVERSITY
:
645 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
646 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
647 (rt2x00dev
->curr_band
!= IEEE80211_BAND_5GHZ
));
650 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
651 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
652 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
653 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
655 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
659 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
660 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
661 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
662 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
664 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
668 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
669 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
670 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
673 static void rt61pci_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
674 struct antenna_setup
*ant
)
680 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
681 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
682 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
684 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
,
685 rt2x00_rf(&rt2x00dev
->chip
, RF2529
));
686 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
687 !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
));
690 * Configure the RX antenna.
693 case ANTENNA_HW_DIVERSITY
:
694 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
697 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
698 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
702 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
703 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
707 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
708 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
709 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
712 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev
*rt2x00dev
,
713 const int p1
, const int p2
)
717 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
719 rt2x00_set_field32(®
, MAC_CSR13_BIT4
, p1
);
720 rt2x00_set_field32(®
, MAC_CSR13_BIT12
, 0);
722 rt2x00_set_field32(®
, MAC_CSR13_BIT3
, !p2
);
723 rt2x00_set_field32(®
, MAC_CSR13_BIT11
, 0);
725 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, reg
);
728 static void rt61pci_config_antenna_2529(struct rt2x00_dev
*rt2x00dev
,
729 struct antenna_setup
*ant
)
735 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
736 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
737 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
740 * Configure the RX antenna.
744 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
745 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
746 rt61pci_config_antenna_2529_rx(rt2x00dev
, 0, 0);
748 case ANTENNA_HW_DIVERSITY
:
750 * FIXME: Antenna selection for the rf 2529 is very confusing
751 * in the legacy driver. Just default to antenna B until the
752 * legacy code can be properly translated into rt2x00 code.
756 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
757 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
758 rt61pci_config_antenna_2529_rx(rt2x00dev
, 1, 1);
762 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
763 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
764 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
770 * value[0] -> non-LNA
776 static const struct antenna_sel antenna_sel_a
[] = {
777 { 96, { 0x58, 0x78 } },
778 { 104, { 0x38, 0x48 } },
779 { 75, { 0xfe, 0x80 } },
780 { 86, { 0xfe, 0x80 } },
781 { 88, { 0xfe, 0x80 } },
782 { 35, { 0x60, 0x60 } },
783 { 97, { 0x58, 0x58 } },
784 { 98, { 0x58, 0x58 } },
787 static const struct antenna_sel antenna_sel_bg
[] = {
788 { 96, { 0x48, 0x68 } },
789 { 104, { 0x2c, 0x3c } },
790 { 75, { 0xfe, 0x80 } },
791 { 86, { 0xfe, 0x80 } },
792 { 88, { 0xfe, 0x80 } },
793 { 35, { 0x50, 0x50 } },
794 { 97, { 0x48, 0x48 } },
795 { 98, { 0x48, 0x48 } },
798 static void rt61pci_config_ant(struct rt2x00_dev
*rt2x00dev
,
799 struct antenna_setup
*ant
)
801 const struct antenna_sel
*sel
;
807 * We should never come here because rt2x00lib is supposed
808 * to catch this and send us the correct antenna explicitely.
810 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
811 ant
->tx
== ANTENNA_SW_DIVERSITY
);
813 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
815 lna
= test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
817 sel
= antenna_sel_bg
;
818 lna
= test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
821 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
822 rt61pci_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
824 rt2x00pci_register_read(rt2x00dev
, PHY_CSR0
, ®
);
826 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
,
827 rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
828 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
,
829 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
831 rt2x00pci_register_write(rt2x00dev
, PHY_CSR0
, reg
);
833 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
834 rt2x00_rf(&rt2x00dev
->chip
, RF5325
))
835 rt61pci_config_antenna_5x(rt2x00dev
, ant
);
836 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
837 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
838 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2529
)) {
839 if (test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
))
840 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
842 rt61pci_config_antenna_2529(rt2x00dev
, ant
);
846 static void rt61pci_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
847 struct rt2x00lib_conf
*libconf
)
852 if (libconf
->conf
->channel
->band
== IEEE80211_BAND_2GHZ
) {
853 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
856 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
857 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
859 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
862 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
863 lna_gain
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
866 rt2x00dev
->lna_gain
= lna_gain
;
869 static void rt61pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
870 struct rf_channel
*rf
, const int txpower
)
876 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
877 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
879 smart
= !(rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
880 rt2x00_rf(&rt2x00dev
->chip
, RF2527
));
882 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
883 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
884 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
887 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
888 r94
+= txpower
- MAX_TXPOWER
;
889 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
891 rt61pci_bbp_write(rt2x00dev
, 94, r94
);
893 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
894 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
895 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
896 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
900 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
901 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
902 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
903 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
907 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
908 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
909 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
910 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
915 static void rt61pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
918 struct rf_channel rf
;
920 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
921 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
922 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
923 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
925 rt61pci_config_channel(rt2x00dev
, &rf
, txpower
);
928 static void rt61pci_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
929 struct rt2x00lib_conf
*libconf
)
933 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
934 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
,
935 libconf
->conf
->long_frame_max_tx_count
);
936 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
,
937 libconf
->conf
->short_frame_max_tx_count
);
938 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
941 static void rt61pci_config_duration(struct rt2x00_dev
*rt2x00dev
,
942 struct rt2x00lib_conf
*libconf
)
946 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
947 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
948 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
950 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
951 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
952 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
954 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
955 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
,
956 libconf
->conf
->beacon_int
* 16);
957 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
960 static void rt61pci_config_ps(struct rt2x00_dev
*rt2x00dev
,
961 struct rt2x00lib_conf
*libconf
)
963 enum dev_state state
=
964 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
965 STATE_SLEEP
: STATE_AWAKE
;
968 if (state
== STATE_SLEEP
) {
969 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
970 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
,
971 libconf
->conf
->beacon_int
- 10);
972 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
,
973 libconf
->conf
->listen_interval
- 1);
974 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 5);
976 /* We must first disable autowake before it can be enabled */
977 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
978 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
980 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 1);
981 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
983 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000005);
984 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x0000001c);
985 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000060);
987 rt61pci_mcu_request(rt2x00dev
, MCU_SLEEP
, 0xff, 0, 0);
989 rt2x00pci_register_read(rt2x00dev
, MAC_CSR11
, ®
);
990 rt2x00_set_field32(®
, MAC_CSR11_DELAY_AFTER_TBCN
, 0);
991 rt2x00_set_field32(®
, MAC_CSR11_TBCN_BEFORE_WAKEUP
, 0);
992 rt2x00_set_field32(®
, MAC_CSR11_AUTOWAKE
, 0);
993 rt2x00_set_field32(®
, MAC_CSR11_WAKEUP_LATENCY
, 0);
994 rt2x00pci_register_write(rt2x00dev
, MAC_CSR11
, reg
);
996 rt2x00pci_register_write(rt2x00dev
, SOFT_RESET_CSR
, 0x00000007);
997 rt2x00pci_register_write(rt2x00dev
, IO_CNTL_CSR
, 0x00000018);
998 rt2x00pci_register_write(rt2x00dev
, PCI_USEC_CSR
, 0x00000020);
1000 rt61pci_mcu_request(rt2x00dev
, MCU_WAKEUP
, 0xff, 0, 0);
1004 static void rt61pci_config(struct rt2x00_dev
*rt2x00dev
,
1005 struct rt2x00lib_conf
*libconf
,
1006 const unsigned int flags
)
1008 /* Always recalculate LNA gain before changing configuration */
1009 rt61pci_config_lna_gain(rt2x00dev
, libconf
);
1011 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
1012 rt61pci_config_channel(rt2x00dev
, &libconf
->rf
,
1013 libconf
->conf
->power_level
);
1014 if ((flags
& IEEE80211_CONF_CHANGE_POWER
) &&
1015 !(flags
& IEEE80211_CONF_CHANGE_CHANNEL
))
1016 rt61pci_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
1017 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
1018 rt61pci_config_retry_limit(rt2x00dev
, libconf
);
1019 if (flags
& IEEE80211_CONF_CHANGE_BEACON_INTERVAL
)
1020 rt61pci_config_duration(rt2x00dev
, libconf
);
1021 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1022 rt61pci_config_ps(rt2x00dev
, libconf
);
1028 static void rt61pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
1029 struct link_qual
*qual
)
1034 * Update FCS error count from register.
1036 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1037 qual
->rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
1040 * Update False CCA count from register.
1042 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1043 qual
->false_cca
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
1046 static inline void rt61pci_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1047 struct link_qual
*qual
, u8 vgc_level
)
1049 if (qual
->vgc_level
!= vgc_level
) {
1050 rt61pci_bbp_write(rt2x00dev
, 17, vgc_level
);
1051 qual
->vgc_level
= vgc_level
;
1052 qual
->vgc_level_reg
= vgc_level
;
1056 static void rt61pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
,
1057 struct link_qual
*qual
)
1059 rt61pci_set_vgc(rt2x00dev
, qual
, 0x20);
1062 static void rt61pci_link_tuner(struct rt2x00_dev
*rt2x00dev
,
1063 struct link_qual
*qual
, const u32 count
)
1069 * Determine r17 bounds.
1071 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1074 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
1081 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
1088 * If we are not associated, we should go straight to the
1089 * dynamic CCA tuning.
1091 if (!rt2x00dev
->intf_associated
)
1092 goto dynamic_cca_tune
;
1095 * Special big-R17 for very short distance
1097 if (qual
->rssi
>= -35) {
1098 rt61pci_set_vgc(rt2x00dev
, qual
, 0x60);
1103 * Special big-R17 for short distance
1105 if (qual
->rssi
>= -58) {
1106 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1111 * Special big-R17 for middle-short distance
1113 if (qual
->rssi
>= -66) {
1114 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x10);
1119 * Special mid-R17 for middle distance
1121 if (qual
->rssi
>= -74) {
1122 rt61pci_set_vgc(rt2x00dev
, qual
, low_bound
+ 0x08);
1127 * Special case: Change up_bound based on the rssi.
1128 * Lower up_bound when rssi is weaker then -74 dBm.
1130 up_bound
-= 2 * (-74 - qual
->rssi
);
1131 if (low_bound
> up_bound
)
1132 up_bound
= low_bound
;
1134 if (qual
->vgc_level
> up_bound
) {
1135 rt61pci_set_vgc(rt2x00dev
, qual
, up_bound
);
1142 * r17 does not yet exceed upper limit, continue and base
1143 * the r17 tuning on the false CCA count.
1145 if ((qual
->false_cca
> 512) && (qual
->vgc_level
< up_bound
))
1146 rt61pci_set_vgc(rt2x00dev
, qual
, ++qual
->vgc_level
);
1147 else if ((qual
->false_cca
< 100) && (qual
->vgc_level
> low_bound
))
1148 rt61pci_set_vgc(rt2x00dev
, qual
, --qual
->vgc_level
);
1152 * Firmware functions
1154 static char *rt61pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
1158 switch (rt2x00dev
->chip
.rt
) {
1160 fw_name
= FIRMWARE_RT2561
;
1163 fw_name
= FIRMWARE_RT2561s
;
1166 fw_name
= FIRMWARE_RT2661
;
1176 static int rt61pci_check_firmware(struct rt2x00_dev
*rt2x00dev
,
1177 const u8
*data
, const size_t len
)
1183 * Only support 8kb firmware files.
1186 return FW_BAD_LENGTH
;
1189 * The last 2 bytes in the firmware array are the crc checksum itself,
1190 * this means that we should never pass those 2 bytes to the crc
1193 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
1196 * Use the crc itu-t algorithm.
1198 crc
= crc_itu_t(0, data
, len
- 2);
1199 crc
= crc_itu_t_byte(crc
, 0);
1200 crc
= crc_itu_t_byte(crc
, 0);
1202 return (fw_crc
== crc
) ? FW_OK
: FW_BAD_CRC
;
1205 static int rt61pci_load_firmware(struct rt2x00_dev
*rt2x00dev
,
1206 const u8
*data
, const size_t len
)
1212 * Wait for stable hardware.
1214 for (i
= 0; i
< 100; i
++) {
1215 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1222 ERROR(rt2x00dev
, "Unstable hardware.\n");
1227 * Prepare MCU and mailbox for firmware loading.
1230 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1231 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1232 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1233 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1234 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, 0);
1237 * Write firmware to device.
1240 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
1241 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 1);
1242 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1244 rt2x00pci_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
1247 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 0);
1248 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1250 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 0);
1251 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
1253 for (i
= 0; i
< 100; i
++) {
1254 rt2x00pci_register_read(rt2x00dev
, MCU_CNTL_CSR
, ®
);
1255 if (rt2x00_get_field32(reg
, MCU_CNTL_CSR_READY
))
1261 ERROR(rt2x00dev
, "MCU Control register not ready.\n");
1266 * Hardware needs another millisecond before it is ready.
1271 * Reset MAC and BBP registers.
1274 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1275 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1276 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1278 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1279 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1280 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1281 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1283 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1284 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1285 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1291 * Initialization functions.
1293 static bool rt61pci_get_entry_state(struct queue_entry
*entry
)
1295 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1298 if (entry
->queue
->qid
== QID_RX
) {
1299 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1301 return rt2x00_get_field32(word
, RXD_W0_OWNER_NIC
);
1303 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1305 return (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1306 rt2x00_get_field32(word
, TXD_W0_VALID
));
1310 static void rt61pci_clear_entry(struct queue_entry
*entry
)
1312 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1313 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1316 if (entry
->queue
->qid
== QID_RX
) {
1317 rt2x00_desc_read(entry_priv
->desc
, 5, &word
);
1318 rt2x00_set_field32(&word
, RXD_W5_BUFFER_PHYSICAL_ADDRESS
,
1320 rt2x00_desc_write(entry_priv
->desc
, 5, word
);
1322 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1323 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
1324 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1326 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1327 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
1328 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
1329 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1333 static int rt61pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
1335 struct queue_entry_priv_pci
*entry_priv
;
1339 * Initialize registers.
1341 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR0
, ®
);
1342 rt2x00_set_field32(®
, TX_RING_CSR0_AC0_RING_SIZE
,
1343 rt2x00dev
->tx
[0].limit
);
1344 rt2x00_set_field32(®
, TX_RING_CSR0_AC1_RING_SIZE
,
1345 rt2x00dev
->tx
[1].limit
);
1346 rt2x00_set_field32(®
, TX_RING_CSR0_AC2_RING_SIZE
,
1347 rt2x00dev
->tx
[2].limit
);
1348 rt2x00_set_field32(®
, TX_RING_CSR0_AC3_RING_SIZE
,
1349 rt2x00dev
->tx
[3].limit
);
1350 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR0
, reg
);
1352 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR1
, ®
);
1353 rt2x00_set_field32(®
, TX_RING_CSR1_TXD_SIZE
,
1354 rt2x00dev
->tx
[0].desc_size
/ 4);
1355 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR1
, reg
);
1357 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
1358 rt2x00pci_register_read(rt2x00dev
, AC0_BASE_CSR
, ®
);
1359 rt2x00_set_field32(®
, AC0_BASE_CSR_RING_REGISTER
,
1360 entry_priv
->desc_dma
);
1361 rt2x00pci_register_write(rt2x00dev
, AC0_BASE_CSR
, reg
);
1363 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
1364 rt2x00pci_register_read(rt2x00dev
, AC1_BASE_CSR
, ®
);
1365 rt2x00_set_field32(®
, AC1_BASE_CSR_RING_REGISTER
,
1366 entry_priv
->desc_dma
);
1367 rt2x00pci_register_write(rt2x00dev
, AC1_BASE_CSR
, reg
);
1369 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
1370 rt2x00pci_register_read(rt2x00dev
, AC2_BASE_CSR
, ®
);
1371 rt2x00_set_field32(®
, AC2_BASE_CSR_RING_REGISTER
,
1372 entry_priv
->desc_dma
);
1373 rt2x00pci_register_write(rt2x00dev
, AC2_BASE_CSR
, reg
);
1375 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
1376 rt2x00pci_register_read(rt2x00dev
, AC3_BASE_CSR
, ®
);
1377 rt2x00_set_field32(®
, AC3_BASE_CSR_RING_REGISTER
,
1378 entry_priv
->desc_dma
);
1379 rt2x00pci_register_write(rt2x00dev
, AC3_BASE_CSR
, reg
);
1381 rt2x00pci_register_read(rt2x00dev
, RX_RING_CSR
, ®
);
1382 rt2x00_set_field32(®
, RX_RING_CSR_RING_SIZE
, rt2x00dev
->rx
->limit
);
1383 rt2x00_set_field32(®
, RX_RING_CSR_RXD_SIZE
,
1384 rt2x00dev
->rx
->desc_size
/ 4);
1385 rt2x00_set_field32(®
, RX_RING_CSR_RXD_WRITEBACK_SIZE
, 4);
1386 rt2x00pci_register_write(rt2x00dev
, RX_RING_CSR
, reg
);
1388 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
1389 rt2x00pci_register_read(rt2x00dev
, RX_BASE_CSR
, ®
);
1390 rt2x00_set_field32(®
, RX_BASE_CSR_RING_REGISTER
,
1391 entry_priv
->desc_dma
);
1392 rt2x00pci_register_write(rt2x00dev
, RX_BASE_CSR
, reg
);
1394 rt2x00pci_register_read(rt2x00dev
, TX_DMA_DST_CSR
, ®
);
1395 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC0
, 2);
1396 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC1
, 2);
1397 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC2
, 2);
1398 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC3
, 2);
1399 rt2x00pci_register_write(rt2x00dev
, TX_DMA_DST_CSR
, reg
);
1401 rt2x00pci_register_read(rt2x00dev
, LOAD_TX_RING_CSR
, ®
);
1402 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC0
, 1);
1403 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC1
, 1);
1404 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC2
, 1);
1405 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC3
, 1);
1406 rt2x00pci_register_write(rt2x00dev
, LOAD_TX_RING_CSR
, reg
);
1408 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1409 rt2x00_set_field32(®
, RX_CNTL_CSR_LOAD_RXD
, 1);
1410 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1415 static int rt61pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
1419 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1420 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
1421 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1422 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
1423 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1425 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
1426 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
1427 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
1428 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
1429 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
1430 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
1431 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
1432 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
1433 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
1434 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
1437 * CCK TXD BBP registers
1439 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
1440 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
1441 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
1442 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
1443 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
1444 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
1445 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
1446 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
1447 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
1448 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
1451 * OFDM TXD BBP registers
1453 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
1454 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
1455 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
1456 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
1457 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
1458 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
1459 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
1460 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
1462 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
1463 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
1464 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
1465 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
1466 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
1467 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
1469 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
1470 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
1471 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
1472 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
1473 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1474 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1476 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1477 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
, 0);
1478 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1479 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 0);
1480 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1481 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1482 rt2x00_set_field32(®
, TXRX_CSR9_TIMESTAMP_COMPENSATE
, 0);
1483 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1485 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1487 rt2x00pci_register_write(rt2x00dev
, MAC_CSR6
, 0x00000fff);
1489 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1490 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1491 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1493 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x0000071c);
1495 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1498 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, 0x0000e000);
1501 * Invalidate all Shared Keys (SEC_CSR0),
1502 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1504 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1505 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1506 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1508 rt2x00pci_register_write(rt2x00dev
, PHY_CSR1
, 0x000023b0);
1509 rt2x00pci_register_write(rt2x00dev
, PHY_CSR5
, 0x060a100c);
1510 rt2x00pci_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1511 rt2x00pci_register_write(rt2x00dev
, PHY_CSR7
, 0x00000a08);
1513 rt2x00pci_register_write(rt2x00dev
, PCI_CFG_CSR
, 0x28ca4404);
1515 rt2x00pci_register_write(rt2x00dev
, TEST_MODE_CSR
, 0x00000200);
1517 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1521 * For the Beacon base registers we only need to clear
1522 * the first byte since that byte contains the VALID and OWNER
1523 * bits which (when set to 0) will invalidate the entire beacon.
1525 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1526 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1527 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1528 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1531 * We must clear the error counters.
1532 * These registers are cleared on read,
1533 * so we may pass a useless variable to store the value.
1535 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1536 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1537 rt2x00pci_register_read(rt2x00dev
, STA_CSR2
, ®
);
1540 * Reset MAC and BBP registers.
1542 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1543 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1544 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1545 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1547 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1548 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1549 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1550 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1552 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1553 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1554 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1559 static int rt61pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1564 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1565 rt61pci_bbp_read(rt2x00dev
, 0, &value
);
1566 if ((value
!= 0xff) && (value
!= 0x00))
1568 udelay(REGISTER_BUSY_DELAY
);
1571 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1575 static int rt61pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1582 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev
)))
1585 rt61pci_bbp_write(rt2x00dev
, 3, 0x00);
1586 rt61pci_bbp_write(rt2x00dev
, 15, 0x30);
1587 rt61pci_bbp_write(rt2x00dev
, 21, 0xc8);
1588 rt61pci_bbp_write(rt2x00dev
, 22, 0x38);
1589 rt61pci_bbp_write(rt2x00dev
, 23, 0x06);
1590 rt61pci_bbp_write(rt2x00dev
, 24, 0xfe);
1591 rt61pci_bbp_write(rt2x00dev
, 25, 0x0a);
1592 rt61pci_bbp_write(rt2x00dev
, 26, 0x0d);
1593 rt61pci_bbp_write(rt2x00dev
, 34, 0x12);
1594 rt61pci_bbp_write(rt2x00dev
, 37, 0x07);
1595 rt61pci_bbp_write(rt2x00dev
, 39, 0xf8);
1596 rt61pci_bbp_write(rt2x00dev
, 41, 0x60);
1597 rt61pci_bbp_write(rt2x00dev
, 53, 0x10);
1598 rt61pci_bbp_write(rt2x00dev
, 54, 0x18);
1599 rt61pci_bbp_write(rt2x00dev
, 60, 0x10);
1600 rt61pci_bbp_write(rt2x00dev
, 61, 0x04);
1601 rt61pci_bbp_write(rt2x00dev
, 62, 0x04);
1602 rt61pci_bbp_write(rt2x00dev
, 75, 0xfe);
1603 rt61pci_bbp_write(rt2x00dev
, 86, 0xfe);
1604 rt61pci_bbp_write(rt2x00dev
, 88, 0xfe);
1605 rt61pci_bbp_write(rt2x00dev
, 90, 0x0f);
1606 rt61pci_bbp_write(rt2x00dev
, 99, 0x00);
1607 rt61pci_bbp_write(rt2x00dev
, 102, 0x16);
1608 rt61pci_bbp_write(rt2x00dev
, 107, 0x04);
1610 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1611 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1613 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1614 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1615 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1616 rt61pci_bbp_write(rt2x00dev
, reg_id
, value
);
1624 * Device state switch handlers.
1626 static void rt61pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1627 enum dev_state state
)
1631 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1632 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
,
1633 (state
== STATE_RADIO_RX_OFF
) ||
1634 (state
== STATE_RADIO_RX_OFF_LINK
));
1635 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1638 static void rt61pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1639 enum dev_state state
)
1641 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
1645 * When interrupts are being enabled, the interrupt registers
1646 * should clear the register to assure a clean state.
1648 if (state
== STATE_RADIO_IRQ_ON
) {
1649 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
1650 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
1652 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®
);
1653 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg
);
1657 * Only toggle the interrupts bits we are going to use.
1658 * Non-checked interrupt bits are disabled by default.
1660 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
1661 rt2x00_set_field32(®
, INT_MASK_CSR_TXDONE
, mask
);
1662 rt2x00_set_field32(®
, INT_MASK_CSR_RXDONE
, mask
);
1663 rt2x00_set_field32(®
, INT_MASK_CSR_ENABLE_MITIGATION
, mask
);
1664 rt2x00_set_field32(®
, INT_MASK_CSR_MITIGATION_PERIOD
, 0xff);
1665 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
1667 rt2x00pci_register_read(rt2x00dev
, MCU_INT_MASK_CSR
, ®
);
1668 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_0
, mask
);
1669 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_1
, mask
);
1670 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_2
, mask
);
1671 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_3
, mask
);
1672 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_4
, mask
);
1673 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_5
, mask
);
1674 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_6
, mask
);
1675 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_7
, mask
);
1676 rt2x00pci_register_write(rt2x00dev
, MCU_INT_MASK_CSR
, reg
);
1679 static int rt61pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1684 * Initialize all registers.
1686 if (unlikely(rt61pci_init_queues(rt2x00dev
) ||
1687 rt61pci_init_registers(rt2x00dev
) ||
1688 rt61pci_init_bbp(rt2x00dev
)))
1694 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1695 rt2x00_set_field32(®
, RX_CNTL_CSR_ENABLE_RX_DMA
, 1);
1696 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1701 static void rt61pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1706 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1709 static int rt61pci_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1715 put_to_sleep
= (state
!= STATE_AWAKE
);
1717 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1718 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1719 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1720 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1723 * Device is not guaranteed to be in the requested state yet.
1724 * We must wait until the register indicates that the
1725 * device has entered the correct state.
1727 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1728 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1729 state
= rt2x00_get_field32(reg
, MAC_CSR12_BBP_CURRENT_STATE
);
1730 if (state
== !put_to_sleep
)
1738 static int rt61pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1739 enum dev_state state
)
1744 case STATE_RADIO_ON
:
1745 retval
= rt61pci_enable_radio(rt2x00dev
);
1747 case STATE_RADIO_OFF
:
1748 rt61pci_disable_radio(rt2x00dev
);
1750 case STATE_RADIO_RX_ON
:
1751 case STATE_RADIO_RX_ON_LINK
:
1752 case STATE_RADIO_RX_OFF
:
1753 case STATE_RADIO_RX_OFF_LINK
:
1754 rt61pci_toggle_rx(rt2x00dev
, state
);
1756 case STATE_RADIO_IRQ_ON
:
1757 case STATE_RADIO_IRQ_OFF
:
1758 rt61pci_toggle_irq(rt2x00dev
, state
);
1760 case STATE_DEEP_SLEEP
:
1764 retval
= rt61pci_set_state(rt2x00dev
, state
);
1771 if (unlikely(retval
))
1772 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1779 * TX descriptor initialization
1781 static void rt61pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1782 struct sk_buff
*skb
,
1783 struct txentry_desc
*txdesc
)
1785 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1786 __le32
*txd
= skbdesc
->desc
;
1790 * Start writing the descriptor words.
1792 rt2x00_desc_read(txd
, 1, &word
);
1793 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, txdesc
->queue
);
1794 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, txdesc
->aifs
);
1795 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, txdesc
->cw_min
);
1796 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, txdesc
->cw_max
);
1797 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, txdesc
->iv_offset
);
1798 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
,
1799 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
1800 rt2x00_set_field32(&word
, TXD_W1_BUFFER_COUNT
, 1);
1801 rt2x00_desc_write(txd
, 1, word
);
1803 rt2x00_desc_read(txd
, 2, &word
);
1804 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, txdesc
->signal
);
1805 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, txdesc
->service
);
1806 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1807 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1808 rt2x00_desc_write(txd
, 2, word
);
1810 if (test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
)) {
1811 _rt2x00_desc_write(txd
, 3, skbdesc
->iv
[0]);
1812 _rt2x00_desc_write(txd
, 4, skbdesc
->iv
[1]);
1815 rt2x00_desc_read(txd
, 5, &word
);
1816 rt2x00_set_field32(&word
, TXD_W5_PID_TYPE
, skbdesc
->entry
->queue
->qid
);
1817 rt2x00_set_field32(&word
, TXD_W5_PID_SUBTYPE
,
1818 skbdesc
->entry
->entry_idx
);
1819 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1820 TXPOWER_TO_DEV(rt2x00dev
->tx_power
));
1821 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1822 rt2x00_desc_write(txd
, 5, word
);
1824 rt2x00_desc_read(txd
, 6, &word
);
1825 rt2x00_set_field32(&word
, TXD_W6_BUFFER_PHYSICAL_ADDRESS
,
1827 rt2x00_desc_write(txd
, 6, word
);
1829 if (skbdesc
->desc_len
> TXINFO_SIZE
) {
1830 rt2x00_desc_read(txd
, 11, &word
);
1831 rt2x00_set_field32(&word
, TXD_W11_BUFFER_LENGTH0
, skb
->len
);
1832 rt2x00_desc_write(txd
, 11, word
);
1835 rt2x00_desc_read(txd
, 0, &word
);
1836 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1837 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1838 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1839 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1840 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1841 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1842 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1843 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1844 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1845 (txdesc
->rate_mode
== RATE_MODE_OFDM
));
1846 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1847 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1848 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1849 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
,
1850 test_bit(ENTRY_TXD_ENCRYPT_MMIC
, &txdesc
->flags
));
1851 rt2x00_set_field32(&word
, TXD_W0_KEY_TABLE
,
1852 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE
, &txdesc
->flags
));
1853 rt2x00_set_field32(&word
, TXD_W0_KEY_INDEX
, txdesc
->key_idx
);
1854 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, skb
->len
);
1855 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1856 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1857 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, txdesc
->cipher
);
1858 rt2x00_desc_write(txd
, 0, word
);
1862 * TX data initialization
1864 static void rt61pci_write_beacon(struct queue_entry
*entry
)
1866 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1867 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1868 unsigned int beacon_base
;
1872 * Disable beaconing while we are reloading the beacon data,
1873 * otherwise we might be sending out invalid data.
1875 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1876 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1877 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1878 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1879 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1882 * Write entire beacon with descriptor to register.
1884 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
1885 rt2x00pci_register_multiwrite(rt2x00dev
,
1887 skbdesc
->desc
, skbdesc
->desc_len
);
1888 rt2x00pci_register_multiwrite(rt2x00dev
,
1889 beacon_base
+ skbdesc
->desc_len
,
1890 entry
->skb
->data
, entry
->skb
->len
);
1893 * Clean up beacon skb.
1895 dev_kfree_skb_any(entry
->skb
);
1899 static void rt61pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1900 const enum data_queue_qid queue
)
1904 if (queue
== QID_BEACON
) {
1906 * For Wi-Fi faily generated beacons between participating
1907 * stations. Set TBTT phase adaptive adjustment step to 8us.
1909 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
1911 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1912 if (!rt2x00_get_field32(reg
, TXRX_CSR9_BEACON_GEN
)) {
1913 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
1914 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
1915 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1916 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1921 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1922 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC0
, (queue
== QID_AC_BE
));
1923 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC1
, (queue
== QID_AC_BK
));
1924 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC2
, (queue
== QID_AC_VI
));
1925 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC3
, (queue
== QID_AC_VO
));
1926 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1929 static void rt61pci_kill_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1930 const enum data_queue_qid qid
)
1934 if (qid
== QID_BEACON
) {
1935 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, 0);
1939 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1940 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC0
, (qid
== QID_AC_BE
));
1941 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC1
, (qid
== QID_AC_BK
));
1942 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC2
, (qid
== QID_AC_VI
));
1943 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC3
, (qid
== QID_AC_VO
));
1944 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1948 * RX control handlers
1950 static int rt61pci_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
1952 u8 offset
= rt2x00dev
->lna_gain
;
1955 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
1970 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1971 if (lna
== 3 || lna
== 2)
1975 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
1978 static void rt61pci_fill_rxdone(struct queue_entry
*entry
,
1979 struct rxdone_entry_desc
*rxdesc
)
1981 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1982 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1986 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
1987 rt2x00_desc_read(entry_priv
->desc
, 1, &word1
);
1989 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1990 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1992 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
)) {
1994 rt2x00_get_field32(word0
, RXD_W0_CIPHER_ALG
);
1995 rxdesc
->cipher_status
=
1996 rt2x00_get_field32(word0
, RXD_W0_CIPHER_ERROR
);
1999 if (rxdesc
->cipher
!= CIPHER_NONE
) {
2000 _rt2x00_desc_read(entry_priv
->desc
, 2, &rxdesc
->iv
[0]);
2001 _rt2x00_desc_read(entry_priv
->desc
, 3, &rxdesc
->iv
[1]);
2002 rxdesc
->dev_flags
|= RXDONE_CRYPTO_IV
;
2004 _rt2x00_desc_read(entry_priv
->desc
, 4, &rxdesc
->icv
);
2005 rxdesc
->dev_flags
|= RXDONE_CRYPTO_ICV
;
2008 * Hardware has stripped IV/EIV data from 802.11 frame during
2009 * decryption. It has provided the data seperately but rt2x00lib
2010 * should decide if it should be reinserted.
2012 rxdesc
->flags
|= RX_FLAG_IV_STRIPPED
;
2015 * FIXME: Legacy driver indicates that the frame does
2016 * contain the Michael Mic. Unfortunately, in rt2x00
2017 * the MIC seems to be missing completely...
2019 rxdesc
->flags
|= RX_FLAG_MMIC_STRIPPED
;
2021 if (rxdesc
->cipher_status
== RX_CRYPTO_SUCCESS
)
2022 rxdesc
->flags
|= RX_FLAG_DECRYPTED
;
2023 else if (rxdesc
->cipher_status
== RX_CRYPTO_FAIL_MIC
)
2024 rxdesc
->flags
|= RX_FLAG_MMIC_ERROR
;
2028 * Obtain the status about this packet.
2029 * When frame was received with an OFDM bitrate,
2030 * the signal is the PLCP value. If it was received with
2031 * a CCK bitrate the signal is the rate in 100kbit/s.
2033 rxdesc
->signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
2034 rxdesc
->rssi
= rt61pci_agc_to_rssi(rt2x00dev
, word1
);
2035 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
2037 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
2038 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
2040 rxdesc
->dev_flags
|= RXDONE_SIGNAL_BITRATE
;
2041 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
2042 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
2046 * Interrupt functions.
2048 static void rt61pci_txdone(struct rt2x00_dev
*rt2x00dev
)
2050 struct data_queue
*queue
;
2051 struct queue_entry
*entry
;
2052 struct queue_entry
*entry_done
;
2053 struct queue_entry_priv_pci
*entry_priv
;
2054 struct txdone_entry_desc txdesc
;
2062 * During each loop we will compare the freshly read
2063 * STA_CSR4 register value with the value read from
2064 * the previous loop. If the 2 values are equal then
2065 * we should stop processing because the chance it
2066 * quite big that the device has been unplugged and
2067 * we risk going into an endless loop.
2072 rt2x00pci_register_read(rt2x00dev
, STA_CSR4
, ®
);
2073 if (!rt2x00_get_field32(reg
, STA_CSR4_VALID
))
2081 * Skip this entry when it contains an invalid
2082 * queue identication number.
2084 type
= rt2x00_get_field32(reg
, STA_CSR4_PID_TYPE
);
2085 queue
= rt2x00queue_get_queue(rt2x00dev
, type
);
2086 if (unlikely(!queue
))
2090 * Skip this entry when it contains an invalid
2093 index
= rt2x00_get_field32(reg
, STA_CSR4_PID_SUBTYPE
);
2094 if (unlikely(index
>= queue
->limit
))
2097 entry
= &queue
->entries
[index
];
2098 entry_priv
= entry
->priv_data
;
2099 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
2101 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
2102 !rt2x00_get_field32(word
, TXD_W0_VALID
))
2105 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2106 while (entry
!= entry_done
) {
2108 * Just report any entries we missed as failed.
2111 "TX status report missed for entry %d\n",
2112 entry_done
->entry_idx
);
2115 __set_bit(TXDONE_UNKNOWN
, &txdesc
.flags
);
2118 rt2x00lib_txdone(entry_done
, &txdesc
);
2119 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
2123 * Obtain the status about this packet.
2126 switch (rt2x00_get_field32(reg
, STA_CSR4_TX_RESULT
)) {
2127 case 0: /* Success, maybe with retry */
2128 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
2130 case 6: /* Failure, excessive retries */
2131 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
2132 /* Don't break, this is a failed frame! */
2133 default: /* Failure */
2134 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
2136 txdesc
.retry
= rt2x00_get_field32(reg
, STA_CSR4_RETRY_COUNT
);
2138 rt2x00lib_txdone(entry
, &txdesc
);
2142 static irqreturn_t
rt61pci_interrupt(int irq
, void *dev_instance
)
2144 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
2149 * Get the interrupt sources & saved to local variable.
2150 * Write register value back to clear pending interrupts.
2152 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®_mcu
);
2153 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg_mcu
);
2155 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
2156 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
2158 if (!reg
&& !reg_mcu
)
2161 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
2165 * Handle interrupts, walk through all bits
2166 * and run the tasks, the bits are checked in order of
2171 * 1 - Rx ring done interrupt.
2173 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RXDONE
))
2174 rt2x00pci_rxdone(rt2x00dev
);
2177 * 2 - Tx ring done interrupt.
2179 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TXDONE
))
2180 rt61pci_txdone(rt2x00dev
);
2183 * 3 - Handle MCU command done.
2186 rt2x00pci_register_write(rt2x00dev
,
2187 M2H_CMD_DONE_CSR
, 0xffffffff);
2193 * Device probe functions.
2195 static int rt61pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2197 struct eeprom_93cx6 eeprom
;
2203 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
2205 eeprom
.data
= rt2x00dev
;
2206 eeprom
.register_read
= rt61pci_eepromregister_read
;
2207 eeprom
.register_write
= rt61pci_eepromregister_write
;
2208 eeprom
.width
= rt2x00_get_field32(reg
, E2PROM_CSR_TYPE_93C46
) ?
2209 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
2210 eeprom
.reg_data_in
= 0;
2211 eeprom
.reg_data_out
= 0;
2212 eeprom
.reg_data_clock
= 0;
2213 eeprom
.reg_chip_select
= 0;
2215 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
2216 EEPROM_SIZE
/ sizeof(u16
));
2219 * Start validation of the data that has been read.
2221 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2222 if (!is_valid_ether_addr(mac
)) {
2223 random_ether_addr(mac
);
2224 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2227 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2228 if (word
== 0xffff) {
2229 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
2230 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
2232 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
2234 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
2235 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
2236 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
2237 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5225
);
2238 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2239 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2242 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2243 if (word
== 0xffff) {
2244 rt2x00_set_field16(&word
, EEPROM_NIC_ENABLE_DIVERSITY
, 0);
2245 rt2x00_set_field16(&word
, EEPROM_NIC_TX_DIVERSITY
, 0);
2246 rt2x00_set_field16(&word
, EEPROM_NIC_RX_FIXED
, 0);
2247 rt2x00_set_field16(&word
, EEPROM_NIC_TX_FIXED
, 0);
2248 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2249 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2250 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2251 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2252 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2255 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
2256 if (word
== 0xffff) {
2257 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
2259 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
2260 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
2263 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2264 if (word
== 0xffff) {
2265 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2266 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
2267 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2268 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2271 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
2272 if (word
== 0xffff) {
2273 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2274 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2275 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2276 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
2278 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
2279 if (value
< -10 || value
> 10)
2280 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
2281 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
2282 if (value
< -10 || value
> 10)
2283 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
2284 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
2287 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
2288 if (word
== 0xffff) {
2289 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2290 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2291 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2292 EEPROM(rt2x00dev
, "RSSI OFFSET A: 0x%04x\n", word
);
2294 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
2295 if (value
< -10 || value
> 10)
2296 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
2297 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
2298 if (value
< -10 || value
> 10)
2299 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
2300 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2306 static int rt61pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2313 * Read EEPROM word for configuration.
2315 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2318 * Identify RF chipset.
2320 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2321 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2322 rt2x00_set_chip_rf(rt2x00dev
, value
, reg
);
2324 if (!rt2x00_rf(&rt2x00dev
->chip
, RF5225
) &&
2325 !rt2x00_rf(&rt2x00dev
->chip
, RF5325
) &&
2326 !rt2x00_rf(&rt2x00dev
->chip
, RF2527
) &&
2327 !rt2x00_rf(&rt2x00dev
->chip
, RF2529
)) {
2328 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2333 * Determine number of antenna's.
2335 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_NUM
) == 2)
2336 __set_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
);
2339 * Identify default antenna configuration.
2341 rt2x00dev
->default_ant
.tx
=
2342 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
2343 rt2x00dev
->default_ant
.rx
=
2344 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
2347 * Read the Frame type.
2349 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
2350 __set_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
);
2353 * Detect if this device has an hardware controlled radio.
2355 #ifdef CONFIG_RT2X00_LIB_RFKILL
2356 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
2357 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2358 #endif /* CONFIG_RT2X00_LIB_RFKILL */
2361 * Read frequency offset and RF programming sequence.
2363 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2364 if (rt2x00_get_field16(eeprom
, EEPROM_FREQ_SEQ
))
2365 __set_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
);
2367 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2370 * Read external LNA informations.
2372 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2374 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2375 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2376 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2377 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2380 * When working with a RF2529 chip without double antenna
2381 * the antenna settings should be gathered from the NIC
2384 if (rt2x00_rf(&rt2x00dev
->chip
, RF2529
) &&
2385 !test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
)) {
2386 rt2x00dev
->default_ant
.rx
=
2387 ANTENNA_A
+ rt2x00_get_field16(eeprom
, EEPROM_NIC_RX_FIXED
);
2388 rt2x00dev
->default_ant
.tx
=
2389 ANTENNA_B
- rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_FIXED
);
2391 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_DIVERSITY
))
2392 rt2x00dev
->default_ant
.tx
= ANTENNA_SW_DIVERSITY
;
2393 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_ENABLE_DIVERSITY
))
2394 rt2x00dev
->default_ant
.rx
= ANTENNA_SW_DIVERSITY
;
2398 * Store led settings, for correct led behaviour.
2399 * If the eeprom value is invalid,
2400 * switch to default led mode.
2402 #ifdef CONFIG_RT2X00_LIB_LEDS
2403 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
2404 value
= rt2x00_get_field16(eeprom
, EEPROM_LED_LED_MODE
);
2406 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2407 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2408 if (value
== LED_MODE_SIGNAL_STRENGTH
)
2409 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
2412 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_LED_MODE
, value
);
2413 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
2414 rt2x00_get_field16(eeprom
,
2415 EEPROM_LED_POLARITY_GPIO_0
));
2416 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
2417 rt2x00_get_field16(eeprom
,
2418 EEPROM_LED_POLARITY_GPIO_1
));
2419 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
2420 rt2x00_get_field16(eeprom
,
2421 EEPROM_LED_POLARITY_GPIO_2
));
2422 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
2423 rt2x00_get_field16(eeprom
,
2424 EEPROM_LED_POLARITY_GPIO_3
));
2425 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
2426 rt2x00_get_field16(eeprom
,
2427 EEPROM_LED_POLARITY_GPIO_4
));
2428 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_ACT
,
2429 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
2430 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_BG
,
2431 rt2x00_get_field16(eeprom
,
2432 EEPROM_LED_POLARITY_RDY_G
));
2433 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_A
,
2434 rt2x00_get_field16(eeprom
,
2435 EEPROM_LED_POLARITY_RDY_A
));
2436 #endif /* CONFIG_RT2X00_LIB_LEDS */
2442 * RF value list for RF5225 & RF5325
2443 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2445 static const struct rf_channel rf_vals_noseq
[] = {
2446 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2447 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2448 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2449 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2450 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2451 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2452 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2453 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2454 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2455 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2456 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2457 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2458 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2459 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2461 /* 802.11 UNI / HyperLan 2 */
2462 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2463 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2464 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2465 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2466 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2467 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2468 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2469 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2471 /* 802.11 HyperLan 2 */
2472 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2473 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2474 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2475 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2476 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2477 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2478 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2479 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2480 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2481 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2484 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2485 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2486 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2487 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2488 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2489 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2491 /* MMAC(Japan)J52 ch 34,38,42,46 */
2492 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2493 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2494 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2495 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2499 * RF value list for RF5225 & RF5325
2500 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2502 static const struct rf_channel rf_vals_seq
[] = {
2503 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2504 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2505 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2506 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2507 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2508 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2509 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2510 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2511 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2512 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2513 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2514 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2515 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2516 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2518 /* 802.11 UNI / HyperLan 2 */
2519 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2520 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2521 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2522 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2523 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2524 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2525 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2526 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2528 /* 802.11 HyperLan 2 */
2529 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2530 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2531 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2532 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2533 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2534 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2535 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2536 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2537 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2538 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2541 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2542 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2543 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2544 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2545 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2546 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2548 /* MMAC(Japan)J52 ch 34,38,42,46 */
2549 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2550 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2551 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2552 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2555 static int rt61pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2557 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2558 struct channel_info
*info
;
2563 * Initialize all hw fields.
2565 rt2x00dev
->hw
->flags
=
2566 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2567 IEEE80211_HW_SIGNAL_DBM
|
2568 IEEE80211_HW_SUPPORTS_PS
|
2569 IEEE80211_HW_PS_NULLFUNC_STACK
;
2570 rt2x00dev
->hw
->extra_tx_headroom
= 0;
2572 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2573 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2574 rt2x00_eeprom_addr(rt2x00dev
,
2575 EEPROM_MAC_ADDR_0
));
2578 * Initialize hw_mode information.
2580 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2581 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2583 if (!test_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
)) {
2584 spec
->num_channels
= 14;
2585 spec
->channels
= rf_vals_noseq
;
2587 spec
->num_channels
= 14;
2588 spec
->channels
= rf_vals_seq
;
2591 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
2592 rt2x00_rf(&rt2x00dev
->chip
, RF5325
)) {
2593 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2594 spec
->num_channels
= ARRAY_SIZE(rf_vals_seq
);
2598 * Create channel information array
2600 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
2604 spec
->channels_info
= info
;
2606 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
2607 for (i
= 0; i
< 14; i
++)
2608 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2610 if (spec
->num_channels
> 14) {
2611 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
2612 for (i
= 14; i
< spec
->num_channels
; i
++)
2613 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
2619 static int rt61pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
2624 * Allocate eeprom data.
2626 retval
= rt61pci_validate_eeprom(rt2x00dev
);
2630 retval
= rt61pci_init_eeprom(rt2x00dev
);
2635 * Initialize hw specifications.
2637 retval
= rt61pci_probe_hw_mode(rt2x00dev
);
2642 * This device requires firmware and DMA mapped skbs.
2644 __set_bit(DRIVER_REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
2645 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
2646 if (!modparam_nohwcrypt
)
2647 __set_bit(CONFIG_SUPPORT_HW_CRYPTO
, &rt2x00dev
->flags
);
2650 * Set the rssi offset.
2652 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
2658 * IEEE80211 stack callback functions.
2660 static int rt61pci_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2661 const struct ieee80211_tx_queue_params
*params
)
2663 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2664 struct data_queue
*queue
;
2665 struct rt2x00_field32 field
;
2671 * First pass the configuration through rt2x00lib, that will
2672 * update the queue settings and validate the input. After that
2673 * we are free to update the registers based on the value
2674 * in the queue parameter.
2676 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2681 * We only need to perform additional register initialization
2687 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2689 /* Update WMM TXOP register */
2690 offset
= AC_TXOP_CSR0
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2691 field
.bit_offset
= (queue_idx
& 1) * 16;
2692 field
.bit_mask
= 0xffff << field
.bit_offset
;
2694 rt2x00pci_register_read(rt2x00dev
, offset
, ®
);
2695 rt2x00_set_field32(®
, field
, queue
->txop
);
2696 rt2x00pci_register_write(rt2x00dev
, offset
, reg
);
2698 /* Update WMM registers */
2699 field
.bit_offset
= queue_idx
* 4;
2700 field
.bit_mask
= 0xf << field
.bit_offset
;
2702 rt2x00pci_register_read(rt2x00dev
, AIFSN_CSR
, ®
);
2703 rt2x00_set_field32(®
, field
, queue
->aifs
);
2704 rt2x00pci_register_write(rt2x00dev
, AIFSN_CSR
, reg
);
2706 rt2x00pci_register_read(rt2x00dev
, CWMIN_CSR
, ®
);
2707 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2708 rt2x00pci_register_write(rt2x00dev
, CWMIN_CSR
, reg
);
2710 rt2x00pci_register_read(rt2x00dev
, CWMAX_CSR
, ®
);
2711 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2712 rt2x00pci_register_write(rt2x00dev
, CWMAX_CSR
, reg
);
2717 static u64
rt61pci_get_tsf(struct ieee80211_hw
*hw
)
2719 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2723 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
2724 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
2725 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
2726 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
2731 static const struct ieee80211_ops rt61pci_mac80211_ops
= {
2733 .start
= rt2x00mac_start
,
2734 .stop
= rt2x00mac_stop
,
2735 .add_interface
= rt2x00mac_add_interface
,
2736 .remove_interface
= rt2x00mac_remove_interface
,
2737 .config
= rt2x00mac_config
,
2738 .configure_filter
= rt2x00mac_configure_filter
,
2739 .set_key
= rt2x00mac_set_key
,
2740 .get_stats
= rt2x00mac_get_stats
,
2741 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2742 .conf_tx
= rt61pci_conf_tx
,
2743 .get_tx_stats
= rt2x00mac_get_tx_stats
,
2744 .get_tsf
= rt61pci_get_tsf
,
2747 static const struct rt2x00lib_ops rt61pci_rt2x00_ops
= {
2748 .irq_handler
= rt61pci_interrupt
,
2749 .probe_hw
= rt61pci_probe_hw
,
2750 .get_firmware_name
= rt61pci_get_firmware_name
,
2751 .check_firmware
= rt61pci_check_firmware
,
2752 .load_firmware
= rt61pci_load_firmware
,
2753 .initialize
= rt2x00pci_initialize
,
2754 .uninitialize
= rt2x00pci_uninitialize
,
2755 .get_entry_state
= rt61pci_get_entry_state
,
2756 .clear_entry
= rt61pci_clear_entry
,
2757 .set_device_state
= rt61pci_set_device_state
,
2758 .rfkill_poll
= rt61pci_rfkill_poll
,
2759 .link_stats
= rt61pci_link_stats
,
2760 .reset_tuner
= rt61pci_reset_tuner
,
2761 .link_tuner
= rt61pci_link_tuner
,
2762 .write_tx_desc
= rt61pci_write_tx_desc
,
2763 .write_tx_data
= rt2x00pci_write_tx_data
,
2764 .write_beacon
= rt61pci_write_beacon
,
2765 .kick_tx_queue
= rt61pci_kick_tx_queue
,
2766 .kill_tx_queue
= rt61pci_kill_tx_queue
,
2767 .fill_rxdone
= rt61pci_fill_rxdone
,
2768 .config_shared_key
= rt61pci_config_shared_key
,
2769 .config_pairwise_key
= rt61pci_config_pairwise_key
,
2770 .config_filter
= rt61pci_config_filter
,
2771 .config_intf
= rt61pci_config_intf
,
2772 .config_erp
= rt61pci_config_erp
,
2773 .config_ant
= rt61pci_config_ant
,
2774 .config
= rt61pci_config
,
2777 static const struct data_queue_desc rt61pci_queue_rx
= {
2778 .entry_num
= RX_ENTRIES
,
2779 .data_size
= DATA_FRAME_SIZE
,
2780 .desc_size
= RXD_DESC_SIZE
,
2781 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2784 static const struct data_queue_desc rt61pci_queue_tx
= {
2785 .entry_num
= TX_ENTRIES
,
2786 .data_size
= DATA_FRAME_SIZE
,
2787 .desc_size
= TXD_DESC_SIZE
,
2788 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2791 static const struct data_queue_desc rt61pci_queue_bcn
= {
2792 .entry_num
= 4 * BEACON_ENTRIES
,
2793 .data_size
= 0, /* No DMA required for beacons */
2794 .desc_size
= TXINFO_SIZE
,
2795 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2798 static const struct rt2x00_ops rt61pci_ops
= {
2799 .name
= KBUILD_MODNAME
,
2802 .eeprom_size
= EEPROM_SIZE
,
2804 .tx_queues
= NUM_TX_QUEUES
,
2805 .rx
= &rt61pci_queue_rx
,
2806 .tx
= &rt61pci_queue_tx
,
2807 .bcn
= &rt61pci_queue_bcn
,
2808 .lib
= &rt61pci_rt2x00_ops
,
2809 .hw
= &rt61pci_mac80211_ops
,
2810 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2811 .debugfs
= &rt61pci_rt2x00debug
,
2812 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2816 * RT61pci module information.
2818 static struct pci_device_id rt61pci_device_table
[] = {
2820 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops
) },
2822 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops
) },
2824 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops
) },
2828 MODULE_AUTHOR(DRV_PROJECT
);
2829 MODULE_VERSION(DRV_VERSION
);
2830 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2831 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2832 "PCI & PCMCIA chipset based cards");
2833 MODULE_DEVICE_TABLE(pci
, rt61pci_device_table
);
2834 MODULE_FIRMWARE(FIRMWARE_RT2561
);
2835 MODULE_FIRMWARE(FIRMWARE_RT2561s
);
2836 MODULE_FIRMWARE(FIRMWARE_RT2661
);
2837 MODULE_LICENSE("GPL");
2839 static struct pci_driver rt61pci_driver
= {
2840 .name
= KBUILD_MODNAME
,
2841 .id_table
= rt61pci_device_table
,
2842 .probe
= rt2x00pci_probe
,
2843 .remove
= __devexit_p(rt2x00pci_remove
),
2844 .suspend
= rt2x00pci_suspend
,
2845 .resume
= rt2x00pci_resume
,
2848 static int __init
rt61pci_init(void)
2850 return pci_register_driver(&rt61pci_driver
);
2853 static void __exit
rt61pci_exit(void)
2855 pci_unregister_driver(&rt61pci_driver
);
2858 module_init(rt61pci_init
);
2859 module_exit(rt61pci_exit
);