drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179 void
 180 radeon_link_encoder_connector(struct drm_device *dev)
 181 {
 182         struct drm_connector *connector;
 183         struct radeon_connector *radeon_connector;
 184         struct drm_encoder *encoder;
 185         struct radeon_encoder *radeon_encoder;
 186
 187         /* walk the list and link encoders to connectors */
 188         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 189                 radeon_connector = to_radeon_connector(connector);
 190                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 191                         radeon_encoder = to_radeon_encoder(encoder);
 192                         if (radeon_encoder->devices & radeon_connector->devices)
 193                                 drm_mode_connector_attach_encoder(connector, encoder);
 194                 }
 195         }
 196 }
 197
 198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 199 {
 200         struct drm_device *dev = encoder->dev;
 201         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 202         struct drm_connector *connector;
 203
 204         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 205                 if (connector->encoder == encoder) {
 206                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 207                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 208                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 209                                   radeon_encoder->active_device, radeon_encoder->devices,
 210                                   radeon_connector->devices, encoder->encoder_type);
 211                 }
 212         }
 213 }
 214
 215 static struct drm_connector *
 216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 217 {
 218         struct drm_device *dev = encoder->dev;
 219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 220         struct drm_connector *connector;
 221         struct radeon_connector *radeon_connector;
 222
 223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 224                 radeon_connector = to_radeon_connector(connector);
 225                 if (radeon_encoder->active_device & radeon_connector->devices)
 226                         return connector;
 227         }
 228         return NULL;
 229 }
 230
 231 static struct radeon_connector_atom_dig *
 232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
 233 {
 234         struct drm_device *dev = encoder->dev;
 235         struct radeon_device *rdev = dev->dev_private;
 236         struct drm_connector *connector;
 237         struct radeon_connector *radeon_connector;
 238         struct radeon_connector_atom_dig *dig_connector;
 239
 240         if (!rdev->is_atom_bios)
 241                 return NULL;
 242
 243         connector = radeon_get_connector_for_encoder(encoder);
 244         if (!connector)
 245                 return NULL;
 246
 247         radeon_connector = to_radeon_connector(connector);
 248
 249         if (!radeon_connector->con_priv)
 250                 return NULL;
 251
 252         dig_connector = radeon_connector->con_priv;
 253
 254         return dig_connector;
 255 }
 256
 257 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 258                                    struct drm_display_mode *mode,
 259                                    struct drm_display_mode *adjusted_mode)
 260 {
 261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 262         struct drm_device *dev = encoder->dev;
 263         struct radeon_device *rdev = dev->dev_private;
 264
 265         /* adjust pm to upcoming mode change */
 266         radeon_pm_compute_clocks(rdev);
 267
 268         /* set the active encoder to connector routing */
 269         radeon_encoder_set_active_device(encoder);
 270         drm_mode_set_crtcinfo(adjusted_mode, 0);
 271
 272         /* hw bug */
 273         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 274             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 275                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 276
 277         /* get the native mode for LVDS */
 278         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 279                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 280                 int mode_id = adjusted_mode->base.id;
 281                 *adjusted_mode = *native_mode;
 282                 if (!ASIC_IS_AVIVO(rdev)) {
 283                         adjusted_mode->hdisplay = mode->hdisplay;
 284                         adjusted_mode->vdisplay = mode->vdisplay;
 285                         adjusted_mode->crtc_hdisplay = mode->hdisplay;
 286                         adjusted_mode->crtc_vdisplay = mode->vdisplay;
 287                 }
 288                 adjusted_mode->base.id = mode_id;
 289         }
 290
 291         /* get the native mode for TV */
 292         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 293                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 294                 if (tv_dac) {
 295                         if (tv_dac->tv_std == TV_STD_NTSC ||
 296                             tv_dac->tv_std == TV_STD_NTSC_J ||
 297                             tv_dac->tv_std == TV_STD_PAL_M)
 298                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 299                         else
 300                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 301                 }
 302         }
 303
 304         if (ASIC_IS_DCE3(rdev) &&
 305             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
 306                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 307                 radeon_dp_set_link_config(connector, mode);
 308         }
 309
 310         return true;
 311 }
 312
 313 static void
 314 atombios_dac_setup(struct drm_encoder *encoder, int action)
 315 {
 316         struct drm_device *dev = encoder->dev;
 317         struct radeon_device *rdev = dev->dev_private;
 318         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 319         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 320         int index = 0, num = 0;
 321         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 322         enum radeon_tv_std tv_std = TV_STD_NTSC;
 323
 324         if (dac_info->tv_std)
 325                 tv_std = dac_info->tv_std;
 326
 327         memset(&args, 0, sizeof(args));
 328
 329         switch (radeon_encoder->encoder_id) {
 330         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 331         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 332                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 333                 num = 1;
 334                 break;
 335         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 336         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 337                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 338                 num = 2;
 339                 break;
 340         }
 341
 342         args.ucAction = action;
 343
 344         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 345                 args.ucDacStandard = ATOM_DAC1_PS2;
 346         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 347                 args.ucDacStandard = ATOM_DAC1_CV;
 348         else {
 349                 switch (tv_std) {
 350                 case TV_STD_PAL:
 351                 case TV_STD_PAL_M:
 352                 case TV_STD_SCART_PAL:
 353                 case TV_STD_SECAM:
 354                 case TV_STD_PAL_CN:
 355                         args.ucDacStandard = ATOM_DAC1_PAL;
 356                         break;
 357                 case TV_STD_NTSC:
 358                 case TV_STD_NTSC_J:
 359                 case TV_STD_PAL_60:
 360                 default:
 361                         args.ucDacStandard = ATOM_DAC1_NTSC;
 362                         break;
 363                 }
 364         }
 365         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 366
 367         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 368
 369 }
 370
 371 static void
 372 atombios_tv_setup(struct drm_encoder *encoder, int action)
 373 {
 374         struct drm_device *dev = encoder->dev;
 375         struct radeon_device *rdev = dev->dev_private;
 376         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 377         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 378         int index = 0;
 379         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 380         enum radeon_tv_std tv_std = TV_STD_NTSC;
 381
 382         if (dac_info->tv_std)
 383                 tv_std = dac_info->tv_std;
 384
 385         memset(&args, 0, sizeof(args));
 386
 387         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 388
 389         args.sTVEncoder.ucAction = action;
 390
 391         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 392                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 393         else {
 394                 switch (tv_std) {
 395                 case TV_STD_NTSC:
 396                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 397                         break;
 398                 case TV_STD_PAL:
 399                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 400                         break;
 401                 case TV_STD_PAL_M:
 402                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 403                         break;
 404                 case TV_STD_PAL_60:
 405                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 406                         break;
 407                 case TV_STD_NTSC_J:
 408                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 409                         break;
 410                 case TV_STD_SCART_PAL:
 411                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 412                         break;
 413                 case TV_STD_SECAM:
 414                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 415                         break;
 416                 case TV_STD_PAL_CN:
 417                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 418                         break;
 419                 default:
 420                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 421                         break;
 422                 }
 423         }
 424
 425         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 426
 427         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 428
 429 }
 430
 431 void
 432 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 433 {
 434         struct drm_device *dev = encoder->dev;
 435         struct radeon_device *rdev = dev->dev_private;
 436         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 437         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 438         int index = 0;
 439
 440         memset(&args, 0, sizeof(args));
 441
 442         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 443
 444         args.sXTmdsEncoder.ucEnable = action;
 445
 446         if (radeon_encoder->pixel_clock > 165000)
 447                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 448
 449         /*if (pScrn->rgbBits == 8)*/
 450         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 451
 452         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 453
 454 }
 455
 456 static void
 457 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 458 {
 459         struct drm_device *dev = encoder->dev;
 460         struct radeon_device *rdev = dev->dev_private;
 461         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 462         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 463         int index = 0;
 464
 465         memset(&args, 0, sizeof(args));
 466
 467         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 468
 469         args.sDVOEncoder.ucAction = action;
 470         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 471
 472         if (radeon_encoder->pixel_clock > 165000)
 473                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 474
 475         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 476
 477 }
 478
 479 union lvds_encoder_control {
 480         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 481         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 482 };
 483
 484 void
 485 atombios_digital_setup(struct drm_encoder *encoder, int action)
 486 {
 487         struct drm_device *dev = encoder->dev;
 488         struct radeon_device *rdev = dev->dev_private;
 489         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 490         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 491         struct radeon_connector_atom_dig *dig_connector =
 492                 radeon_get_atom_connector_priv_from_encoder(encoder);
 493         union lvds_encoder_control args;
 494         int index = 0;
 495         int hdmi_detected = 0;
 496         uint8_t frev, crev;
 497
 498         if (!dig || !dig_connector)
 499                 return;
 500
 501         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 502                 hdmi_detected = 1;
 503
 504         memset(&args, 0, sizeof(args));
 505
 506         switch (radeon_encoder->encoder_id) {
 507         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 508                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 509                 break;
 510         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 511         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 512                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 513                 break;
 514         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 515                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 516                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 517                 else
 518                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 519                 break;
 520         }
 521
 522         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 523
 524         switch (frev) {
 525         case 1:
 526         case 2:
 527                 switch (crev) {
 528                 case 1:
 529                         args.v1.ucMisc = 0;
 530                         args.v1.ucAction = action;
 531                         if (hdmi_detected)
 532                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 533                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 534                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 535                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 536                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 537                                 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 538                                         args.v1.ucMisc |= (1 << 1);
 539                         } else {
 540                                 if (dig_connector->linkb)
 541                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 542                                 if (radeon_encoder->pixel_clock > 165000)
 543                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 544                                 /*if (pScrn->rgbBits == 8) */
 545                                 args.v1.ucMisc |= (1 << 1);
 546                         }
 547                         break;
 548                 case 2:
 549                 case 3:
 550                         args.v2.ucMisc = 0;
 551                         args.v2.ucAction = action;
 552                         if (crev == 3) {
 553                                 if (dig->coherent_mode)
 554                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 555                         }
 556                         if (hdmi_detected)
 557                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 558                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 559                         args.v2.ucTruncate = 0;
 560                         args.v2.ucSpatial = 0;
 561                         args.v2.ucTemporal = 0;
 562                         args.v2.ucFRC = 0;
 563                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 564                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 565                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 566                                 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
 567                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 568                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 569                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 570                                 }
 571                                 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
 572                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 573                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 574                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 575                                         if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 576                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 577                                 }
 578                         } else {
 579                                 if (dig_connector->linkb)
 580                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 581                                 if (radeon_encoder->pixel_clock > 165000)
 582                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 583                         }
 584                         break;
 585                 default:
 586                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 587                         break;
 588                 }
 589                 break;
 590         default:
 591                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 592                 break;
 593         }
 594
 595         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 596 }
 597
 598 int
 599 atombios_get_encoder_mode(struct drm_encoder *encoder)
 600 {
 601         struct drm_connector *connector;
 602         struct radeon_connector *radeon_connector;
 603         struct radeon_connector_atom_dig *dig_connector;
 604
 605         connector = radeon_get_connector_for_encoder(encoder);
 606         if (!connector)
 607                 return 0;
 608
 609         radeon_connector = to_radeon_connector(connector);
 610
 611         switch (connector->connector_type) {
 612         case DRM_MODE_CONNECTOR_DVII:
 613         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 614                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 615                         return ATOM_ENCODER_MODE_HDMI;
 616                 else if (radeon_connector->use_digital)
 617                         return ATOM_ENCODER_MODE_DVI;
 618                 else
 619                         return ATOM_ENCODER_MODE_CRT;
 620                 break;
 621         case DRM_MODE_CONNECTOR_DVID:
 622         case DRM_MODE_CONNECTOR_HDMIA:
 623         default:
 624                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 625                         return ATOM_ENCODER_MODE_HDMI;
 626                 else
 627                         return ATOM_ENCODER_MODE_DVI;
 628                 break;
 629         case DRM_MODE_CONNECTOR_LVDS:
 630                 return ATOM_ENCODER_MODE_LVDS;
 631                 break;
 632         case DRM_MODE_CONNECTOR_DisplayPort:
 633         case DRM_MODE_CONNECTOR_eDP:
 634                 dig_connector = radeon_connector->con_priv;
 635                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 636                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 637                         return ATOM_ENCODER_MODE_DP;
 638                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
 639                         return ATOM_ENCODER_MODE_HDMI;
 640                 else
 641                         return ATOM_ENCODER_MODE_DVI;
 642                 break;
 643         case DRM_MODE_CONNECTOR_DVIA:
 644         case DRM_MODE_CONNECTOR_VGA:
 645                 return ATOM_ENCODER_MODE_CRT;
 646                 break;
 647         case DRM_MODE_CONNECTOR_Composite:
 648         case DRM_MODE_CONNECTOR_SVIDEO:
 649         case DRM_MODE_CONNECTOR_9PinDIN:
 650                 /* fix me */
 651                 return ATOM_ENCODER_MODE_TV;
 652                 /*return ATOM_ENCODER_MODE_CV;*/
 653                 break;
 654         }
 655 }
 656
 657 /*
 658  * DIG Encoder/Transmitter Setup
 659  *
 660  * DCE 3.0/3.1
 661  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 662  * Supports up to 3 digital outputs
 663  * - 2 DIG encoder blocks.
 664  * DIG1 can drive UNIPHY link A or link B
 665  * DIG2 can drive UNIPHY link B or LVTMA
 666  *
 667  * DCE 3.2
 668  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 669  * Supports up to 5 digital outputs
 670  * - 2 DIG encoder blocks.
 671  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 672  *
 673  * DCE 4.0
 674  * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
 675  * Supports up to 6 digital outputs
 676  * - 6 DIG encoder blocks.
 677  * - DIG to PHY mapping is hardcoded
 678  * DIG1 drives UNIPHY0 link A, A+B
 679  * DIG2 drives UNIPHY0 link B
 680  * DIG3 drives UNIPHY1 link A, A+B
 681  * DIG4 drives UNIPHY1 link B
 682  * DIG5 drives UNIPHY2 link A, A+B
 683  * DIG6 drives UNIPHY2 link B
 684  *
 685  * Routing
 686  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 687  * Examples:
 688  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 689  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 690  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 691  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 692  */
 693
 694 union dig_encoder_control {
 695         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 696         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 697         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 698 };
 699
 700 void
 701 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 702 {
 703         struct drm_device *dev = encoder->dev;
 704         struct radeon_device *rdev = dev->dev_private;
 705         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 706         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 707         struct radeon_connector_atom_dig *dig_connector =
 708                 radeon_get_atom_connector_priv_from_encoder(encoder);
 709         union dig_encoder_control args;
 710         int index = 0, num = 0;
 711         uint8_t frev, crev;
 712
 713         if (!dig || !dig_connector)
 714                 return;
 715
 716         memset(&args, 0, sizeof(args));
 717
 718         if (ASIC_IS_DCE4(rdev))
 719                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 720         else {
 721                 if (dig->dig_encoder)
 722                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 723                 else
 724                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 725         }
 726         num = dig->dig_encoder + 1;
 727
 728         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 729
 730         args.v1.ucAction = action;
 731         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 732         args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 733
 734         if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 735                 if (dig_connector->dp_clock == 270000)
 736                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 737                 args.v1.ucLaneNum = dig_connector->dp_lane_count;
 738         } else if (radeon_encoder->pixel_clock > 165000)
 739                 args.v1.ucLaneNum = 8;
 740         else
 741                 args.v1.ucLaneNum = 4;
 742
 743         if (ASIC_IS_DCE4(rdev)) {
 744                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 745                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 746         } else {
 747                 switch (radeon_encoder->encoder_id) {
 748                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 749                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 750                         break;
 751                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 752                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 753                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 754                         break;
 755                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 756                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 757                         break;
 758                 }
 759                 if (dig_connector->linkb)
 760                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 761                 else
 762                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 763         }
 764
 765         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 766
 767 }
 768
 769 union dig_transmitter_control {
 770         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 771         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 772         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 773 };
 774
 775 void
 776 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 777 {
 778         struct drm_device *dev = encoder->dev;
 779         struct radeon_device *rdev = dev->dev_private;
 780         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 781         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 782         struct radeon_connector_atom_dig *dig_connector =
 783                 radeon_get_atom_connector_priv_from_encoder(encoder);
 784         struct drm_connector *connector;
 785         struct radeon_connector *radeon_connector;
 786         union dig_transmitter_control args;
 787         int index = 0, num = 0;
 788         uint8_t frev, crev;
 789         bool is_dp = false;
 790         int pll_id = 0;
 791
 792         if (!dig || !dig_connector)
 793                 return;
 794
 795         connector = radeon_get_connector_for_encoder(encoder);
 796         radeon_connector = to_radeon_connector(connector);
 797
 798         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 799                 is_dp = true;
 800
 801         memset(&args, 0, sizeof(args));
 802
 803         if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
 804                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 805         else {
 806                 switch (radeon_encoder->encoder_id) {
 807                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 808                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 809                         break;
 810                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 811                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 812                         break;
 813                 }
 814         }
 815
 816         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 817
 818         args.v1.ucAction = action;
 819         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 820                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 821         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 822                 args.v1.asMode.ucLaneSel = lane_num;
 823                 args.v1.asMode.ucLaneSet = lane_set;
 824         } else {
 825                 if (is_dp)
 826                         args.v1.usPixelClock =
 827                                 cpu_to_le16(dig_connector->dp_clock / 10);
 828                 else if (radeon_encoder->pixel_clock > 165000)
 829                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 830                 else
 831                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 832         }
 833         if (ASIC_IS_DCE4(rdev)) {
 834                 if (is_dp)
 835                         args.v3.ucLaneNum = dig_connector->dp_lane_count;
 836                 else if (radeon_encoder->pixel_clock > 165000)
 837                         args.v3.ucLaneNum = 8;
 838                 else
 839                         args.v3.ucLaneNum = 4;
 840
 841                 if (dig_connector->linkb) {
 842                         args.v3.acConfig.ucLinkSel = 1;
 843                         args.v3.acConfig.ucEncoderSel = 1;
 844                 }
 845
 846                 /* Select the PLL for the PHY
 847                  * DP PHY should be clocked from external src if there is
 848                  * one.
 849                  */
 850                 if (encoder->crtc) {
 851                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 852                         pll_id = radeon_crtc->pll_id;
 853                 }
 854                 if (is_dp && rdev->clock.dp_extclk)
 855                         args.v3.acConfig.ucRefClkSource = 2; /* external src */
 856                 else
 857                         args.v3.acConfig.ucRefClkSource = pll_id;
 858
 859                 switch (radeon_encoder->encoder_id) {
 860                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 861                         args.v3.acConfig.ucTransmitterSel = 0;
 862                         num = 0;
 863                         break;
 864                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 865                         args.v3.acConfig.ucTransmitterSel = 1;
 866                         num = 1;
 867                         break;
 868                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 869                         args.v3.acConfig.ucTransmitterSel = 2;
 870                         num = 2;
 871                         break;
 872                 }
 873
 874                 if (is_dp)
 875                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 876                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 877                         if (dig->coherent_mode)
 878                                 args.v3.acConfig.fCoherentMode = 1;
 879                 }
 880         } else if (ASIC_IS_DCE32(rdev)) {
 881                 if (dig->dig_encoder == 1)
 882                         args.v2.acConfig.ucEncoderSel = 1;
 883                 if (dig_connector->linkb)
 884                         args.v2.acConfig.ucLinkSel = 1;
 885
 886                 switch (radeon_encoder->encoder_id) {
 887                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 888                         args.v2.acConfig.ucTransmitterSel = 0;
 889                         num = 0;
 890                         break;
 891                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 892                         args.v2.acConfig.ucTransmitterSel = 1;
 893                         num = 1;
 894                         break;
 895                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 896                         args.v2.acConfig.ucTransmitterSel = 2;
 897                         num = 2;
 898                         break;
 899                 }
 900
 901                 if (is_dp)
 902                         args.v2.acConfig.fCoherentMode = 1;
 903                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 904                         if (dig->coherent_mode)
 905                                 args.v2.acConfig.fCoherentMode = 1;
 906                 }
 907         } else {
 908                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 909
 910                 if (dig->dig_encoder)
 911                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 912                 else
 913                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 914
 915                 switch (radeon_encoder->encoder_id) {
 916                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 917                         if (rdev->flags & RADEON_IS_IGP) {
 918                                 if (radeon_encoder->pixel_clock > 165000) {
 919                                         if (dig_connector->igp_lane_info & 0x3)
 920                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 921                                         else if (dig_connector->igp_lane_info & 0xc)
 922                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 923                                 } else {
 924                                         if (dig_connector->igp_lane_info & 0x1)
 925                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 926                                         else if (dig_connector->igp_lane_info & 0x2)
 927                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 928                                         else if (dig_connector->igp_lane_info & 0x4)
 929                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 930                                         else if (dig_connector->igp_lane_info & 0x8)
 931                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 932                                 }
 933                         }
 934                         break;
 935                 }
 936
 937                 if (radeon_encoder->pixel_clock > 165000)
 938                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 939
 940                 if (dig_connector->linkb)
 941                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 942                 else
 943                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 944
 945                 if (is_dp)
 946                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 947                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 948                         if (dig->coherent_mode)
 949                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 950                 }
 951         }
 952
 953         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 954 }
 955
 956 static void
 957 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 958 {
 959         struct drm_device *dev = encoder->dev;
 960         struct radeon_device *rdev = dev->dev_private;
 961         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 962         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 963         ENABLE_YUV_PS_ALLOCATION args;
 964         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 965         uint32_t temp, reg;
 966
 967         memset(&args, 0, sizeof(args));
 968
 969         if (rdev->family >= CHIP_R600)
 970                 reg = R600_BIOS_3_SCRATCH;
 971         else
 972                 reg = RADEON_BIOS_3_SCRATCH;
 973
 974         /* XXX: fix up scratch reg handling */
 975         temp = RREG32(reg);
 976         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 977                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 978                              (radeon_crtc->crtc_id << 18)));
 979         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 980                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 981         else
 982                 WREG32(reg, 0);
 983
 984         if (enable)
 985                 args.ucEnable = ATOM_ENABLE;
 986         args.ucCRTC = radeon_crtc->crtc_id;
 987
 988         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 989
 990         WREG32(reg, temp);
 991 }
 992
 993 static void
 994 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 995 {
 996         struct drm_device *dev = encoder->dev;
 997         struct radeon_device *rdev = dev->dev_private;
 998         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 999         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1000         int index = 0;
1001         bool is_dig = false;
1002
1003         memset(&args, 0, sizeof(args));
1004
1005         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1006                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1007                   radeon_encoder->active_device);
1008         switch (radeon_encoder->encoder_id) {
1009         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1010         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1011                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1012                 break;
1013         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1014         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1015         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1016         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1017                 is_dig = true;
1018                 break;
1019         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1020         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1021         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1022                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1023                 break;
1024         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1025                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1026                 break;
1027         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1028                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1029                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1030                 else
1031                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1032                 break;
1033         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1034         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1035                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1036                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1037                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1038                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1039                 else
1040                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1041                 break;
1042         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1043         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1044                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1045                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1046                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1047                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1048                 else
1049                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1050                 break;
1051         }
1052
1053         if (is_dig) {
1054                 switch (mode) {
1055                 case DRM_MODE_DPMS_ON:
1056                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1057                         {
1058                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1059                                 dp_link_train(encoder, connector);
1060                         }
1061                         break;
1062                 case DRM_MODE_DPMS_STANDBY:
1063                 case DRM_MODE_DPMS_SUSPEND:
1064                 case DRM_MODE_DPMS_OFF:
1065                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1066                         break;
1067                 }
1068         } else {
1069                 switch (mode) {
1070                 case DRM_MODE_DPMS_ON:
1071                         args.ucAction = ATOM_ENABLE;
1072                         break;
1073                 case DRM_MODE_DPMS_STANDBY:
1074                 case DRM_MODE_DPMS_SUSPEND:
1075                 case DRM_MODE_DPMS_OFF:
1076                         args.ucAction = ATOM_DISABLE;
1077                         break;
1078                 }
1079                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1080         }
1081         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1082
1083         /* adjust pm to dpms change */
1084         radeon_pm_compute_clocks(rdev);
1085 }
1086
1087 union crtc_source_param {
1088         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1089         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1090 };
1091
1092 static void
1093 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1094 {
1095         struct drm_device *dev = encoder->dev;
1096         struct radeon_device *rdev = dev->dev_private;
1097         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1098         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1099         union crtc_source_param args;
1100         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1101         uint8_t frev, crev;
1102         struct radeon_encoder_atom_dig *dig;
1103
1104         memset(&args, 0, sizeof(args));
1105
1106         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1107
1108         switch (frev) {
1109         case 1:
1110                 switch (crev) {
1111                 case 1:
1112                 default:
1113                         if (ASIC_IS_AVIVO(rdev))
1114                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1115                         else {
1116                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1117                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1118                                 } else {
1119                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1120                                 }
1121                         }
1122                         switch (radeon_encoder->encoder_id) {
1123                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1124                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1125                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1126                                 break;
1127                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1128                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1129                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1130                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1131                                 else
1132                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1133                                 break;
1134                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1135                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1136                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1137                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1138                                 break;
1139                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1140                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1141                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1142                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1143                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1144                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1145                                 else
1146                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1147                                 break;
1148                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1149                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1150                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1151                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1152                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1153                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1154                                 else
1155                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1156                                 break;
1157                         }
1158                         break;
1159                 case 2:
1160                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1161                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1162                         switch (radeon_encoder->encoder_id) {
1163                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1164                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1165                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1166                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1167                                 dig = radeon_encoder->enc_priv;
1168                                 switch (dig->dig_encoder) {
1169                                 case 0:
1170                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1171                                         break;
1172                                 case 1:
1173                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1174                                         break;
1175                                 case 2:
1176                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1177                                         break;
1178                                 case 3:
1179                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1180                                         break;
1181                                 case 4:
1182                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1183                                         break;
1184                                 case 5:
1185                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1186                                         break;
1187                                 }
1188                                 break;
1189                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1190                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1191                                 break;
1192                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1193                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1194                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1195                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1196                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1197                                 else
1198                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1199                                 break;
1200                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1201                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1202                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1203                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1204                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1205                                 else
1206                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1207                                 break;
1208                         }
1209                         break;
1210                 }
1211                 break;
1212         default:
1213                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1214                 break;
1215         }
1216
1217         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1218
1219         /* update scratch regs with new routing */
1220         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1221 }
1222
1223 static void
1224 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1225                               struct drm_display_mode *mode)
1226 {
1227         struct drm_device *dev = encoder->dev;
1228         struct radeon_device *rdev = dev->dev_private;
1229         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1230         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1231
1232         /* Funky macbooks */
1233         if ((dev->pdev->device == 0x71C5) &&
1234             (dev->pdev->subsystem_vendor == 0x106b) &&
1235             (dev->pdev->subsystem_device == 0x0080)) {
1236                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1237                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1238
1239                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1240                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1241
1242                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1243                 }
1244         }
1245
1246         /* set scaler clears this on some chips */
1247         /* XXX check DCE4 */
1248         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1249                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1250                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1251                                AVIVO_D1MODE_INTERLEAVE_EN);
1252         }
1253 }
1254
1255 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1256 {
1257         struct drm_device *dev = encoder->dev;
1258         struct radeon_device *rdev = dev->dev_private;
1259         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1260         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1261         struct drm_encoder *test_encoder;
1262         struct radeon_encoder_atom_dig *dig;
1263         uint32_t dig_enc_in_use = 0;
1264
1265         if (ASIC_IS_DCE4(rdev)) {
1266                 struct radeon_connector_atom_dig *dig_connector =
1267                         radeon_get_atom_connector_priv_from_encoder(encoder);
1268
1269                 switch (radeon_encoder->encoder_id) {
1270                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1271                         if (dig_connector->linkb)
1272                                 return 1;
1273                         else
1274                                 return 0;
1275                         break;
1276                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1277                         if (dig_connector->linkb)
1278                                 return 3;
1279                         else
1280                                 return 2;
1281                         break;
1282                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1283                         if (dig_connector->linkb)
1284                                 return 5;
1285                         else
1286                                 return 4;
1287                         break;
1288                 }
1289         }
1290
1291         /* on DCE32 and encoder can driver any block so just crtc id */
1292         if (ASIC_IS_DCE32(rdev)) {
1293                 return radeon_crtc->crtc_id;
1294         }
1295
1296         /* on DCE3 - LVTMA can only be driven by DIGB */
1297         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1298                 struct radeon_encoder *radeon_test_encoder;
1299
1300                 if (encoder == test_encoder)
1301                         continue;
1302
1303                 if (!radeon_encoder_is_digital(test_encoder))
1304                         continue;
1305
1306                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1307                 dig = radeon_test_encoder->enc_priv;
1308
1309                 if (dig->dig_encoder >= 0)
1310                         dig_enc_in_use |= (1 << dig->dig_encoder);
1311         }
1312
1313         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1314                 if (dig_enc_in_use & 0x2)
1315                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1316                 return 1;
1317         }
1318         if (!(dig_enc_in_use & 1))
1319                 return 0;
1320         return 1;
1321 }
1322
1323 static void
1324 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1325                              struct drm_display_mode *mode,
1326                              struct drm_display_mode *adjusted_mode)
1327 {
1328         struct drm_device *dev = encoder->dev;
1329         struct radeon_device *rdev = dev->dev_private;
1330         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1331
1332         radeon_encoder->pixel_clock = adjusted_mode->clock;
1333
1334         if (ASIC_IS_AVIVO(rdev)) {
1335                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1336                         atombios_yuv_setup(encoder, true);
1337                 else
1338                         atombios_yuv_setup(encoder, false);
1339         }
1340
1341         switch (radeon_encoder->encoder_id) {
1342         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1343         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1344         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1345         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1346                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1347                 break;
1348         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1349         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1350         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1351         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1352                 if (ASIC_IS_DCE4(rdev)) {
1353                         /* disable the transmitter */
1354                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1355                         /* setup and enable the encoder */
1356                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1357
1358                         /* init and enable the transmitter */
1359                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1360                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1361                 } else {
1362                         /* disable the encoder and transmitter */
1363                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1364                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1365
1366                         /* setup and enable the encoder and transmitter */
1367                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1368                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1369                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1370                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1371                 }
1372                 break;
1373         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1374                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1375                 break;
1376         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1377         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1378                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1379                 break;
1380         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1381         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1382         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1383         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1384                 atombios_dac_setup(encoder, ATOM_ENABLE);
1385                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1386                         atombios_tv_setup(encoder, ATOM_ENABLE);
1387                 break;
1388         }
1389         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1390
1391         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1392                 r600_hdmi_enable(encoder);
1393                 r600_hdmi_setmode(encoder, adjusted_mode);
1394         }
1395 }
1396
1397 static bool
1398 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1399 {
1400         struct drm_device *dev = encoder->dev;
1401         struct radeon_device *rdev = dev->dev_private;
1402         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1403         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1404
1405         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1406                                        ATOM_DEVICE_CV_SUPPORT |
1407                                        ATOM_DEVICE_CRT_SUPPORT)) {
1408                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1409                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1410                 uint8_t frev, crev;
1411
1412                 memset(&args, 0, sizeof(args));
1413
1414                 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1415
1416                 args.sDacload.ucMisc = 0;
1417
1418                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1419                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1420                         args.sDacload.ucDacType = ATOM_DAC_A;
1421                 else
1422                         args.sDacload.ucDacType = ATOM_DAC_B;
1423
1424                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1425                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1426                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1427                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1428                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1429                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1430                         if (crev >= 3)
1431                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1432                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1433                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1434                         if (crev >= 3)
1435                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1436                 }
1437
1438                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1439
1440                 return true;
1441         } else
1442                 return false;
1443 }
1444
1445 static enum drm_connector_status
1446 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1447 {
1448         struct drm_device *dev = encoder->dev;
1449         struct radeon_device *rdev = dev->dev_private;
1450         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1451         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1452         uint32_t bios_0_scratch;
1453
1454         if (!atombios_dac_load_detect(encoder, connector)) {
1455                 DRM_DEBUG("detect returned false \n");
1456                 return connector_status_unknown;
1457         }
1458
1459         if (rdev->family >= CHIP_R600)
1460                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1461         else
1462                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1463
1464         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1465         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1466                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1467                         return connector_status_connected;
1468         }
1469         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1470                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1471                         return connector_status_connected;
1472         }
1473         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1474                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1475                         return connector_status_connected;
1476         }
1477         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1478                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1479                         return connector_status_connected; /* CTV */
1480                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1481                         return connector_status_connected; /* STV */
1482         }
1483         return connector_status_disconnected;
1484 }
1485
1486 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1487 {
1488         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1489
1490         if (radeon_encoder->active_device &
1491             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1492                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1493                 if (dig)
1494                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1495         }
1496
1497         radeon_atom_output_lock(encoder, true);
1498         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1499
1500         /* this is needed for the pll/ss setup to work correctly in some cases */
1501         atombios_set_encoder_crtc_source(encoder);
1502 }
1503
1504 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1505 {
1506         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1507         radeon_atom_output_lock(encoder, false);
1508 }
1509
1510 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1511 {
1512         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1513         struct radeon_encoder_atom_dig *dig;
1514         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1515
1516         if (radeon_encoder_is_digital(encoder)) {
1517                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1518                         r600_hdmi_disable(encoder);
1519                 dig = radeon_encoder->enc_priv;
1520                 dig->dig_encoder = -1;
1521         }
1522         radeon_encoder->active_device = 0;
1523 }
1524
1525 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1526         .dpms = radeon_atom_encoder_dpms,
1527         .mode_fixup = radeon_atom_mode_fixup,
1528         .prepare = radeon_atom_encoder_prepare,
1529         .mode_set = radeon_atom_encoder_mode_set,
1530         .commit = radeon_atom_encoder_commit,
1531         .disable = radeon_atom_encoder_disable,
1532         /* no detect for TMDS/LVDS yet */
1533 };
1534
1535 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1536         .dpms = radeon_atom_encoder_dpms,
1537         .mode_fixup = radeon_atom_mode_fixup,
1538         .prepare = radeon_atom_encoder_prepare,
1539         .mode_set = radeon_atom_encoder_mode_set,
1540         .commit = radeon_atom_encoder_commit,
1541         .detect = radeon_atom_dac_detect,
1542 };
1543
1544 void radeon_enc_destroy(struct drm_encoder *encoder)
1545 {
1546         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1547         kfree(radeon_encoder->enc_priv);
1548         drm_encoder_cleanup(encoder);
1549         kfree(radeon_encoder);
1550 }
1551
1552 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1553         .destroy = radeon_enc_destroy,
1554 };
1555
1556 struct radeon_encoder_atom_dac *
1557 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1558 {
1559         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1560
1561         if (!dac)
1562                 return NULL;
1563
1564         dac->tv_std = TV_STD_NTSC;
1565         return dac;
1566 }
1567
1568 struct radeon_encoder_atom_dig *
1569 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1570 {
1571         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1572
1573         if (!dig)
1574                 return NULL;
1575
1576         /* coherent mode by default */
1577         dig->coherent_mode = true;
1578         dig->dig_encoder = -1;
1579
1580         return dig;
1581 }
1582
1583 void
1584 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1585 {
1586         struct radeon_device *rdev = dev->dev_private;
1587         struct drm_encoder *encoder;
1588         struct radeon_encoder *radeon_encoder;
1589
1590         /* see if we already added it */
1591         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1592                 radeon_encoder = to_radeon_encoder(encoder);
1593                 if (radeon_encoder->encoder_id == encoder_id) {
1594                         radeon_encoder->devices |= supported_device;
1595                         return;
1596                 }
1597
1598         }
1599
1600         /* add a new one */
1601         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1602         if (!radeon_encoder)
1603                 return;
1604
1605         encoder = &radeon_encoder->base;
1606         switch (rdev->num_crtc) {
1607         case 1:
1608                 encoder->possible_crtcs = 0x1;
1609                 break;
1610         case 2:
1611         default:
1612                 encoder->possible_crtcs = 0x3;
1613                 break;
1614         case 6:
1615                 encoder->possible_crtcs = 0x3f;
1616                 break;
1617         }
1618
1619         radeon_encoder->enc_priv = NULL;
1620
1621         radeon_encoder->encoder_id = encoder_id;
1622         radeon_encoder->devices = supported_device;
1623         radeon_encoder->rmx_type = RMX_OFF;
1624
1625         switch (radeon_encoder->encoder_id) {
1626         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1627         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1628         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1629         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1630                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1631                         radeon_encoder->rmx_type = RMX_FULL;
1632                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1633                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1634                 } else {
1635                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1636                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1637                 }
1638                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1639                 break;
1640         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1641                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1642                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1643                 break;
1644         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1645         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1646         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1647                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1648                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1649                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1650                 break;
1651         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1652         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1653         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1654         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1655         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1656         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1657         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1658                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1659                         radeon_encoder->rmx_type = RMX_FULL;
1660                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1661                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1662                 } else {
1663                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1664                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1665                 }
1666                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1667                 break;
1668         }
1669 }