arch/arm/mach-vexpress/platsmp.c

   1 /*
   2  *  linux/arch/arm/mach-vexpress/platsmp.c
   3  *
   4  *  Copyright (C) 2002 ARM Ltd.
   5  *  All Rights Reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/errno.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/smp.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/cacheflush.h>
  20 #include <asm/smp_scu.h>
  21 #include <asm/unified.h>
  22
  23 #include <mach/ct-ca9x4.h>
  24 #include <mach/motherboard.h>
  25 #define V2M_PA_CS7 0x10000000
  26
  27 #include "core.h"
  28
  29 extern void vexpress_secondary_startup(void);
  30
  31 /*
  32  * control for which core is the next to come out of the secondary
  33  * boot "holding pen"
  34  */
  35 volatile int __cpuinitdata pen_release = -1;
  36
  37 static void __iomem *scu_base_addr(void)
  38 {
  39         return MMIO_P2V(A9_MPCORE_SCU);
  40 }
  41
  42 static DEFINE_SPINLOCK(boot_lock);
  43
  44 void __cpuinit platform_secondary_init(unsigned int cpu)
  45 {
  46         /*
  47          * if any interrupts are already enabled for the primary
  48          * core (e.g. timer irq), then they will not have been enabled
  49          * for us: do so
  50          */
  51         gic_cpu_init(0, gic_cpu_base_addr);
  52
  53         /*
  54          * let the primary processor know we're out of the
  55          * pen, then head off into the C entry point
  56          */
  57         pen_release = -1;
  58         smp_wmb();
  59
  60         /*
  61          * Synchronise with the boot thread.
  62          */
  63         spin_lock(&boot_lock);
  64         spin_unlock(&boot_lock);
  65 }
  66
  67 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  68 {
  69         unsigned long timeout;
  70
  71         /*
  72          * Set synchronisation state between this boot processor
  73          * and the secondary one
  74          */
  75         spin_lock(&boot_lock);
  76
  77         /*
  78          * This is really belt and braces; we hold unintended secondary
  79          * CPUs in the holding pen until we're ready for them.  However,
  80          * since we haven't sent them a soft interrupt, they shouldn't
  81          * be there.
  82          */
  83         pen_release = cpu;
  84         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  85         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
  86
  87         /*
  88          * Send the secondary CPU a soft interrupt, thereby causing
  89          * the boot monitor to read the system wide flags register,
  90          * and branch to the address found there.
  91          */
  92         smp_cross_call(cpumask_of(cpu), 1);
  93
  94         timeout = jiffies + (1 * HZ);
  95         while (time_before(jiffies, timeout)) {
  96                 smp_rmb();
  97                 if (pen_release == -1)
  98                         break;
  99
 100                 udelay(10);
 101         }
 102
 103         /*
 104          * now the secondary core is starting up let it run its
 105          * calibrations, then wait for it to finish
 106          */
 107         spin_unlock(&boot_lock);
 108
 109         return pen_release != -1 ? -ENOSYS : 0;
 110 }
 111
 112 /*
 113  * Initialise the CPU possible map early - this describes the CPUs
 114  * which may be present or become present in the system.
 115  */
 116 void __init smp_init_cpus(void)
 117 {
 118         void __iomem *scu_base = scu_base_addr();
 119         unsigned int i, ncores;
 120
 121         ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 122
 123         /* sanity check */
 124         if (ncores > NR_CPUS) {
 125                 printk(KERN_WARNING
 126                        "vexpress: no. of cores (%d) greater than configured "
 127                        "maximum of %d - clipping\n",
 128                        ncores, NR_CPUS);
 129                 ncores = NR_CPUS;
 130         }
 131
 132         for (i = 0; i < ncores; i++)
 133                 set_cpu_possible(i, true);
 134 }
 135
 136 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 137 {
 138         int i;
 139
 140         /*
 141          * Initialise the present map, which describes the set of CPUs
 142          * actually populated at the present time.
 143          */
 144         for (i = 0; i < max_cpus; i++)
 145                 set_cpu_present(i, true);
 146
 147         scu_enable(scu_base_addr());
 148
 149         /*
 150          * Write the address of secondary startup into the
 151          * system-wide flags register. The boot monitor waits
 152          * until it receives a soft interrupt, and then the
 153          * secondary CPU branches to this address.
 154          */
 155         writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
 156         writel(BSYM(virt_to_phys(vexpress_secondary_startup)),
 157                 MMIO_P2V(V2M_SYS_FLAGSSET));
 158 }