arch/arm/mach-ux500/platsmp.c

   1 /*
   2  * Copyright (C) 2002 ARM Ltd.
   3  * Copyright (C) 2008 STMicroelctronics.
   4  * Copyright (C) 2009 ST-Ericsson.
   5  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
   6  *
   7  * This file is based on arm realview platform
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/errno.h>
  15 #include <linux/delay.h>
  16 #include <linux/device.h>
  17 #include <linux/smp.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/cacheflush.h>
  21 #include <asm/smp_scu.h>
  22 #include <mach/hardware.h>
  23
  24 /*
  25  * control for which core is the next to come out of the secondary
  26  * boot "holding pen"
  27  */
  28 volatile int __cpuinitdata pen_release = -1;
  29
  30 static DEFINE_SPINLOCK(boot_lock);
  31
  32 void __cpuinit platform_secondary_init(unsigned int cpu)
  33 {
  34         /*
  35          * if any interrupts are already enabled for the primary
  36          * core (e.g. timer irq), then they will not have been enabled
  37          * for us: do so
  38          */
  39         gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
  40
  41         /*
  42          * let the primary processor know we're out of the
  43          * pen, then head off into the C entry point
  44          */
  45         pen_release = -1;
  46
  47         /*
  48          * Synchronise with the boot thread.
  49          */
  50         spin_lock(&boot_lock);
  51         spin_unlock(&boot_lock);
  52 }
  53
  54 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  55 {
  56         unsigned long timeout;
  57
  58         /*
  59          * set synchronisation state between this boot processor
  60          * and the secondary one
  61          */
  62         spin_lock(&boot_lock);
  63
  64         /*
  65          * The secondary processor is waiting to be released from
  66          * the holding pen - release it, then wait for it to flag
  67          * that it has been released by resetting pen_release.
  68          */
  69         pen_release = cpu;
  70         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  71         outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1);
  72
  73         smp_cross_call(cpumask_of(cpu), 1);
  74
  75         timeout = jiffies + (1 * HZ);
  76         while (time_before(jiffies, timeout)) {
  77                 if (pen_release == -1)
  78                         break;
  79         }
  80
  81         /*
  82          * now the secondary core is starting up let it run its
  83          * calibrations, then wait for it to finish
  84          */
  85         spin_unlock(&boot_lock);
  86
  87         return pen_release != -1 ? -ENOSYS : 0;
  88 }
  89
  90 static void __init wakeup_secondary(void)
  91 {
  92         /* nobody is to be released from the pen yet */
  93         pen_release = -1;
  94
  95         /*
  96          * write the address of secondary startup into the backup ram register
  97          * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
  98          * backup ram register at offset 0x1FF0, which is what boot rom code
  99          * is waiting for. This would wake up the secondary core from WFE
 100          */
 101 #define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4
 102         __raw_writel(virt_to_phys(u8500_secondary_startup),
 103                 __io_address(UX500_BACKUPRAM0_BASE) +
 104                 U8500_CPU1_JUMPADDR_OFFSET);
 105
 106 #define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
 107         __raw_writel(0xA1FEED01,
 108                 __io_address(UX500_BACKUPRAM0_BASE) +
 109                 U8500_CPU1_WAKEMAGIC_OFFSET);
 110
 111         /* make sure write buffer is drained */
 112         mb();
 113 }
 114
 115 /*
 116  * Initialise the CPU possible map early - this describes the CPUs
 117  * which may be present or become present in the system.
 118  */
 119 void __init smp_init_cpus(void)
 120 {
 121         unsigned int i, ncores;
 122
 123         ncores = scu_get_core_count(__io_address(UX500_SCU_BASE));
 124
 125         /* sanity check */
 126         if (ncores > NR_CPUS) {
 127                 printk(KERN_WARNING
 128                        "U8500: no. of cores (%d) greater than configured "
 129                        "maximum of %d - clipping\n",
 130                        ncores, NR_CPUS);
 131                 ncores = NR_CPUS;
 132         }
 133
 134         for (i = 0; i < ncores; i++)
 135                 set_cpu_possible(i, true);
 136 }
 137
 138 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 139 {
 140         int i;
 141
 142         /*
 143          * Initialise the present map, which describes the set of CPUs
 144          * actually populated at the present time.
 145          */
 146         for (i = 0; i < max_cpus; i++)
 147                 set_cpu_present(i, true);
 148
 149         scu_enable(__io_address(UX500_SCU_BASE));
 150         wakeup_secondary();
 151 }