2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define assert(expr) \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
51 #expr,__FILE__,__func__,__LINE__); \
53 #define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
56 #define assert(expr) do {} while (0)
57 #define dprintk(fmt, args...) do {} while (0)
58 #endif /* RTL8169_DEBUG */
60 #define R8169_MSG_DEFAULT \
61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
63 #define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68 static const int multicast_filter_limit
= 32;
70 /* MAC address length */
71 #define MAC_ADDR_LEN 6
73 #define MAX_READ_REQUEST_SHIFT 12
74 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
75 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
78 #define R8169_REGS_SIZE 256
79 #define R8169_NAPI_WEIGHT 64
80 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
83 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
86 #define RTL8169_TX_TIMEOUT (6*HZ)
87 #define RTL8169_PHY_TIMEOUT (10*HZ)
89 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
91 #define RTL_EEPROM_SIG_ADDR 0x0000
93 /* write/read MMIO register */
94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg) readb (ioaddr + (reg))
98 #define RTL_R16(reg) readw (ioaddr + (reg))
99 #define RTL_R32(reg) readl (ioaddr + (reg))
102 RTL_GIGA_MAC_VER_01
= 0,
136 RTL_GIGA_MAC_NONE
= 0xff,
139 enum rtl_tx_desc_version
{
144 #define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
147 static const struct {
149 enum rtl_tx_desc_version txd_version
;
151 } rtl_chip_infos
[] = {
153 [RTL_GIGA_MAC_VER_01
] =
154 _R("RTL8169", RTL_TD_0
, NULL
),
155 [RTL_GIGA_MAC_VER_02
] =
156 _R("RTL8169s", RTL_TD_0
, NULL
),
157 [RTL_GIGA_MAC_VER_03
] =
158 _R("RTL8110s", RTL_TD_0
, NULL
),
159 [RTL_GIGA_MAC_VER_04
] =
160 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
),
161 [RTL_GIGA_MAC_VER_05
] =
162 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
163 [RTL_GIGA_MAC_VER_06
] =
164 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
166 [RTL_GIGA_MAC_VER_07
] =
167 _R("RTL8102e", RTL_TD_1
, NULL
),
168 [RTL_GIGA_MAC_VER_08
] =
169 _R("RTL8102e", RTL_TD_1
, NULL
),
170 [RTL_GIGA_MAC_VER_09
] =
171 _R("RTL8102e", RTL_TD_1
, NULL
),
172 [RTL_GIGA_MAC_VER_10
] =
173 _R("RTL8101e", RTL_TD_0
, NULL
),
174 [RTL_GIGA_MAC_VER_11
] =
175 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
176 [RTL_GIGA_MAC_VER_12
] =
177 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
178 [RTL_GIGA_MAC_VER_13
] =
179 _R("RTL8101e", RTL_TD_0
, NULL
),
180 [RTL_GIGA_MAC_VER_14
] =
181 _R("RTL8100e", RTL_TD_0
, NULL
),
182 [RTL_GIGA_MAC_VER_15
] =
183 _R("RTL8100e", RTL_TD_0
, NULL
),
184 [RTL_GIGA_MAC_VER_16
] =
185 _R("RTL8101e", RTL_TD_0
, NULL
),
186 [RTL_GIGA_MAC_VER_17
] =
187 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
188 [RTL_GIGA_MAC_VER_18
] =
189 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
190 [RTL_GIGA_MAC_VER_19
] =
191 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
192 [RTL_GIGA_MAC_VER_20
] =
193 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
194 [RTL_GIGA_MAC_VER_21
] =
195 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
196 [RTL_GIGA_MAC_VER_22
] =
197 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
198 [RTL_GIGA_MAC_VER_23
] =
199 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
200 [RTL_GIGA_MAC_VER_24
] =
201 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
202 [RTL_GIGA_MAC_VER_25
] =
203 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
),
204 [RTL_GIGA_MAC_VER_26
] =
205 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
),
206 [RTL_GIGA_MAC_VER_27
] =
207 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
208 [RTL_GIGA_MAC_VER_28
] =
209 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
210 [RTL_GIGA_MAC_VER_29
] =
211 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
212 [RTL_GIGA_MAC_VER_30
] =
213 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
214 [RTL_GIGA_MAC_VER_31
] =
215 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
216 [RTL_GIGA_MAC_VER_32
] =
217 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
),
218 [RTL_GIGA_MAC_VER_33
] =
219 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
),
220 [RTL_GIGA_MAC_VER_34
] =
221 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
)
231 static void rtl_hw_start_8169(struct net_device
*);
232 static void rtl_hw_start_8168(struct net_device
*);
233 static void rtl_hw_start_8101(struct net_device
*);
235 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
242 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
243 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
244 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
245 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
246 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
248 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
252 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
254 static int rx_buf_sz
= 16383;
261 MAC0
= 0, /* Ethernet hardware address. */
263 MAR0
= 8, /* Multicast filter. */
264 CounterAddrLow
= 0x10,
265 CounterAddrHigh
= 0x14,
266 TxDescStartAddrLow
= 0x20,
267 TxDescStartAddrHigh
= 0x24,
268 TxHDescStartAddrLow
= 0x28,
269 TxHDescStartAddrHigh
= 0x2c,
278 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
279 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
282 #define RX128_INT_EN (1 << 15) /* 8111c and later */
283 #define RX_MULTI_EN (1 << 14) /* 8111c only */
284 #define RXCFG_FIFO_SHIFT 13
285 /* No threshold before first PCI xfer */
286 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
287 #define RXCFG_DMA_SHIFT 8
288 /* Unlimited maximum PCI burst. */
289 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
305 RxDescAddrLow
= 0xe4,
306 RxDescAddrHigh
= 0xe8,
307 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
309 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
311 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
313 #define TxPacketMax (8064 >> 7)
316 FuncEventMask
= 0xf4,
317 FuncPresetState
= 0xf8,
318 FuncForceEvent
= 0xfc,
321 enum rtl8110_registers
{
327 enum rtl8168_8101_registers
{
330 #define CSIAR_FLAG 0x80000000
331 #define CSIAR_WRITE_CMD 0x80000000
332 #define CSIAR_BYTE_ENABLE 0x0f
333 #define CSIAR_BYTE_ENABLE_SHIFT 12
334 #define CSIAR_ADDR_MASK 0x0fff
337 #define EPHYAR_FLAG 0x80000000
338 #define EPHYAR_WRITE_CMD 0x80000000
339 #define EPHYAR_REG_MASK 0x1f
340 #define EPHYAR_REG_SHIFT 16
341 #define EPHYAR_DATA_MASK 0xffff
343 #define PFM_EN (1 << 6)
345 #define FIX_NAK_1 (1 << 4)
346 #define FIX_NAK_2 (1 << 3)
349 #define NOW_IS_OOB (1 << 7)
350 #define EN_NDP (1 << 3)
351 #define EN_OOB_RESET (1 << 2)
353 #define EFUSEAR_FLAG 0x80000000
354 #define EFUSEAR_WRITE_CMD 0x80000000
355 #define EFUSEAR_READ_CMD 0x00000000
356 #define EFUSEAR_REG_MASK 0x03ff
357 #define EFUSEAR_REG_SHIFT 8
358 #define EFUSEAR_DATA_MASK 0xff
361 enum rtl8168_registers
{
366 #define ERIAR_FLAG 0x80000000
367 #define ERIAR_WRITE_CMD 0x80000000
368 #define ERIAR_READ_CMD 0x00000000
369 #define ERIAR_ADDR_BYTE_ALIGN 4
370 #define ERIAR_TYPE_SHIFT 16
371 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
372 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
373 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
374 #define ERIAR_MASK_SHIFT 12
375 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
377 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
378 EPHY_RXER_NUM
= 0x7c,
379 OCPDR
= 0xb0, /* OCP GPHY access */
380 #define OCPDR_WRITE_CMD 0x80000000
381 #define OCPDR_READ_CMD 0x00000000
382 #define OCPDR_REG_MASK 0x7f
383 #define OCPDR_GPHY_REG_SHIFT 16
384 #define OCPDR_DATA_MASK 0xffff
386 #define OCPAR_FLAG 0x80000000
387 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
388 #define OCPAR_GPHY_READ_CMD 0x0000f060
389 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC
= 0xf0, /* 8168e only. */
391 #define TXPLA_RST (1 << 29)
392 #define PWM_EN (1 << 22)
395 enum rtl_register_content
{
396 /* InterruptStatusBits */
400 TxDescUnavail
= 0x0080,
424 /* TXPoll register p.5 */
425 HPQ
= 0x80, /* Poll cmd on the high prio queue */
426 NPQ
= 0x40, /* Poll cmd on the low prio queue */
427 FSWInt
= 0x01, /* Forced software interrupt */
431 Cfg9346_Unlock
= 0xc0,
436 AcceptBroadcast
= 0x08,
437 AcceptMulticast
= 0x04,
439 AcceptAllPhys
= 0x01,
440 #define RX_CONFIG_ACCEPT_MASK 0x3f
443 TxInterFrameGapShift
= 24,
444 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
446 /* Config1 register p.24 */
449 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
450 Speed_down
= (1 << 4),
454 PMEnable
= (1 << 0), /* Power Management Enable */
456 /* Config2 register p. 25 */
457 PCI_Clock_66MHz
= 0x01,
458 PCI_Clock_33MHz
= 0x00,
460 /* Config3 register p.25 */
461 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
462 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
463 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
465 /* Config5 register p.27 */
466 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
467 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
468 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
470 LanWake
= (1 << 1), /* LanWake enable/disable */
471 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
474 TBIReset
= 0x80000000,
475 TBILoopback
= 0x40000000,
476 TBINwEnable
= 0x20000000,
477 TBINwRestart
= 0x10000000,
478 TBILinkOk
= 0x02000000,
479 TBINwComplete
= 0x01000000,
482 EnableBist
= (1 << 15), // 8168 8101
483 Mac_dbgo_oe
= (1 << 14), // 8168 8101
484 Normal_mode
= (1 << 13), // unused
485 Force_half_dup
= (1 << 12), // 8168 8101
486 Force_rxflow_en
= (1 << 11), // 8168 8101
487 Force_txflow_en
= (1 << 10), // 8168 8101
488 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
489 ASF
= (1 << 8), // 8168 8101
490 PktCntrDisable
= (1 << 7), // 8168 8101
491 Mac_dbgo_sel
= 0x001c, // 8168
496 INTT_0
= 0x0000, // 8168
497 INTT_1
= 0x0001, // 8168
498 INTT_2
= 0x0002, // 8168
499 INTT_3
= 0x0003, // 8168
501 /* rtl8169_PHYstatus */
512 TBILinkOK
= 0x02000000,
514 /* DumpCounterCommand */
519 /* First doubleword. */
520 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
521 RingEnd
= (1 << 30), /* End of descriptor ring */
522 FirstFrag
= (1 << 29), /* First segment of a packet */
523 LastFrag
= (1 << 28), /* Final segment of a packet */
527 enum rtl_tx_desc_bit
{
528 /* First doubleword. */
529 TD_LSO
= (1 << 27), /* Large Send Offload */
530 #define TD_MSS_MAX 0x07ffu /* MSS value */
532 /* Second doubleword. */
533 TxVlanTag
= (1 << 17), /* Add VLAN tag */
536 /* 8169, 8168b and 810x except 8102e. */
537 enum rtl_tx_desc_bit_0
{
538 /* First doubleword. */
539 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
540 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
541 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
542 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
545 /* 8102e, 8168c and beyond. */
546 enum rtl_tx_desc_bit_1
{
547 /* Second doubleword. */
548 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
549 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
550 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
551 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
554 static const struct rtl_tx_desc_info
{
561 } tx_desc_info
[] = {
564 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
565 .tcp
= TD0_IP_CS
| TD0_TCP_CS
567 .mss_shift
= TD0_MSS_SHIFT
,
572 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
573 .tcp
= TD1_IP_CS
| TD1_TCP_CS
575 .mss_shift
= TD1_MSS_SHIFT
,
580 enum rtl_rx_desc_bit
{
582 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
583 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
585 #define RxProtoUDP (PID1)
586 #define RxProtoTCP (PID0)
587 #define RxProtoIP (PID1 | PID0)
588 #define RxProtoMask RxProtoIP
590 IPFail
= (1 << 16), /* IP checksum failed */
591 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
592 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
593 RxVlanTag
= (1 << 16), /* VLAN tag available */
596 #define RsvdMask 0x3fffc000
613 u8 __pad
[sizeof(void *) - sizeof(u32
)];
617 RTL_FEATURE_WOL
= (1 << 0),
618 RTL_FEATURE_MSI
= (1 << 1),
619 RTL_FEATURE_GMII
= (1 << 2),
622 struct rtl8169_counters
{
629 __le32 tx_one_collision
;
630 __le32 tx_multi_collision
;
638 struct rtl8169_private
{
639 void __iomem
*mmio_addr
; /* memory map physical address */
640 struct pci_dev
*pci_dev
;
641 struct net_device
*dev
;
642 struct napi_struct napi
;
647 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
648 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
651 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
652 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
653 dma_addr_t TxPhyAddr
;
654 dma_addr_t RxPhyAddr
;
655 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
656 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
657 struct timer_list timer
;
664 void (*write
)(void __iomem
*, int, int);
665 int (*read
)(void __iomem
*, int);
668 struct pll_power_ops
{
669 void (*down
)(struct rtl8169_private
*);
670 void (*up
)(struct rtl8169_private
*);
673 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
674 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
675 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
676 void (*hw_start
)(struct net_device
*);
677 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
678 unsigned int (*link_ok
)(void __iomem
*);
679 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
680 struct delayed_work task
;
683 struct mii_if_info mii
;
684 struct rtl8169_counters counters
;
689 const struct firmware
*fw
;
691 #define RTL_VER_SIZE 32
693 char version
[RTL_VER_SIZE
];
695 struct rtl_fw_phy_action
{
700 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
703 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
704 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
705 module_param(use_dac
, int, 0);
706 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
707 module_param_named(debug
, debug
.msg_enable
, int, 0);
708 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
709 MODULE_LICENSE("GPL");
710 MODULE_VERSION(RTL8169_VERSION
);
711 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
712 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
713 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
714 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
715 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
716 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
718 static int rtl8169_open(struct net_device
*dev
);
719 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
720 struct net_device
*dev
);
721 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
722 static int rtl8169_init_ring(struct net_device
*dev
);
723 static void rtl_hw_start(struct net_device
*dev
);
724 static int rtl8169_close(struct net_device
*dev
);
725 static void rtl_set_rx_mode(struct net_device
*dev
);
726 static void rtl8169_tx_timeout(struct net_device
*dev
);
727 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
728 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
729 void __iomem
*, u32 budget
);
730 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
731 static void rtl8169_down(struct net_device
*dev
);
732 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
733 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
735 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
737 void __iomem
*ioaddr
= tp
->mmio_addr
;
740 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
741 for (i
= 0; i
< 20; i
++) {
743 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
746 return RTL_R32(OCPDR
);
749 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
751 void __iomem
*ioaddr
= tp
->mmio_addr
;
754 RTL_W32(OCPDR
, data
);
755 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
756 for (i
= 0; i
< 20; i
++) {
758 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
763 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
765 void __iomem
*ioaddr
= tp
->mmio_addr
;
769 RTL_W32(ERIAR
, 0x800010e8);
771 for (i
= 0; i
< 5; i
++) {
773 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
777 ocp_write(tp
, 0x1, 0x30, 0x00000001);
780 #define OOB_CMD_RESET 0x00
781 #define OOB_CMD_DRIVER_START 0x05
782 #define OOB_CMD_DRIVER_STOP 0x06
784 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
786 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
789 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
794 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
796 reg
= rtl8168_get_ocp_reg(tp
);
798 for (i
= 0; i
< 10; i
++) {
800 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
805 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
810 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
812 reg
= rtl8168_get_ocp_reg(tp
);
814 for (i
= 0; i
< 10; i
++) {
816 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
821 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
823 u16 reg
= rtl8168_get_ocp_reg(tp
);
825 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
828 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
832 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
834 for (i
= 20; i
> 0; i
--) {
836 * Check if the RTL8169 has completed writing to the specified
839 if (!(RTL_R32(PHYAR
) & 0x80000000))
844 * According to hardware specs a 20us delay is required after write
845 * complete indication, but before sending next command.
850 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
854 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
856 for (i
= 20; i
> 0; i
--) {
858 * Check if the RTL8169 has completed retrieving data from
859 * the specified MII register.
861 if (RTL_R32(PHYAR
) & 0x80000000) {
862 value
= RTL_R32(PHYAR
) & 0xffff;
868 * According to hardware specs a 20us delay is required after read
869 * complete indication, but before sending next command.
876 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
880 RTL_W32(OCPDR
, data
|
881 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
882 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
883 RTL_W32(EPHY_RXER_NUM
, 0);
885 for (i
= 0; i
< 100; i
++) {
887 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
892 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
894 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
895 (value
& OCPDR_DATA_MASK
));
898 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
902 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
905 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
906 RTL_W32(EPHY_RXER_NUM
, 0);
908 for (i
= 0; i
< 100; i
++) {
910 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
914 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
917 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
919 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
921 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
924 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
926 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
929 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
931 r8168dp_2_mdio_start(ioaddr
);
933 r8169_mdio_write(ioaddr
, reg_addr
, value
);
935 r8168dp_2_mdio_stop(ioaddr
);
938 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
942 r8168dp_2_mdio_start(ioaddr
);
944 value
= r8169_mdio_read(ioaddr
, reg_addr
);
946 r8168dp_2_mdio_stop(ioaddr
);
951 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
953 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
956 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
958 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
961 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
963 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
966 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
970 val
= rtl_readphy(tp
, reg_addr
);
971 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
974 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
977 struct rtl8169_private
*tp
= netdev_priv(dev
);
979 rtl_writephy(tp
, location
, val
);
982 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
984 struct rtl8169_private
*tp
= netdev_priv(dev
);
986 return rtl_readphy(tp
, location
);
989 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
993 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
994 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
996 for (i
= 0; i
< 100; i
++) {
997 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
1003 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
1008 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1010 for (i
= 0; i
< 100; i
++) {
1011 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
1012 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
1021 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
1025 RTL_W32(CSIDR
, value
);
1026 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
1027 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1029 for (i
= 0; i
< 100; i
++) {
1030 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
1036 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
1041 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
1042 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1044 for (i
= 0; i
< 100; i
++) {
1045 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
1046 value
= RTL_R32(CSIDR
);
1056 void rtl_eri_write(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 val
, int type
)
1060 BUG_ON((addr
& 3) || (mask
== 0));
1061 RTL_W32(ERIDR
, val
);
1062 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1064 for (i
= 0; i
< 100; i
++) {
1065 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
1071 static u32
rtl_eri_read(void __iomem
*ioaddr
, int addr
, int type
)
1076 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1078 for (i
= 0; i
< 100; i
++) {
1079 if (RTL_R32(ERIAR
) & ERIAR_FLAG
) {
1080 value
= RTL_R32(ERIDR
);
1090 rtl_w1w0_eri(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 p
, u32 m
, int type
)
1094 val
= rtl_eri_read(ioaddr
, addr
, type
);
1095 rtl_eri_write(ioaddr
, addr
, mask
, (val
& ~m
) | p
, type
);
1104 static void rtl_write_exgmac_batch(void __iomem
*ioaddr
,
1105 const struct exgmac_reg
*r
, int len
)
1108 rtl_eri_write(ioaddr
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1113 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1118 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1120 for (i
= 0; i
< 300; i
++) {
1121 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1122 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1131 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
1133 RTL_W16(IntrMask
, 0x0000);
1135 RTL_W16(IntrStatus
, 0xffff);
1138 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1140 void __iomem
*ioaddr
= tp
->mmio_addr
;
1142 return RTL_R32(TBICSR
) & TBIReset
;
1145 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1147 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1150 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1152 return RTL_R32(TBICSR
) & TBILinkOk
;
1155 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1157 return RTL_R8(PHYstatus
) & LinkStatus
;
1160 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1162 void __iomem
*ioaddr
= tp
->mmio_addr
;
1164 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1167 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1171 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1172 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1175 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1177 void __iomem
*ioaddr
= tp
->mmio_addr
;
1178 struct net_device
*dev
= tp
->dev
;
1180 if (!netif_running(dev
))
1183 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
1184 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1185 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1186 0x00000011, ERIAR_EXGMAC
);
1187 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1188 0x00000005, ERIAR_EXGMAC
);
1189 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1190 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1191 0x0000001f, ERIAR_EXGMAC
);
1192 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1193 0x00000005, ERIAR_EXGMAC
);
1195 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1196 0x0000001f, ERIAR_EXGMAC
);
1197 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1198 0x0000003f, ERIAR_EXGMAC
);
1200 /* Reset packet filter */
1201 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1203 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1208 static void __rtl8169_check_link_status(struct net_device
*dev
,
1209 struct rtl8169_private
*tp
,
1210 void __iomem
*ioaddr
, bool pm
)
1212 unsigned long flags
;
1214 spin_lock_irqsave(&tp
->lock
, flags
);
1215 if (tp
->link_ok(ioaddr
)) {
1216 rtl_link_chg_patch(tp
);
1217 /* This is to cancel a scheduled suspend if there's one. */
1219 pm_request_resume(&tp
->pci_dev
->dev
);
1220 netif_carrier_on(dev
);
1221 if (net_ratelimit())
1222 netif_info(tp
, ifup
, dev
, "link up\n");
1224 netif_carrier_off(dev
);
1225 netif_info(tp
, ifdown
, dev
, "link down\n");
1227 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
1229 spin_unlock_irqrestore(&tp
->lock
, flags
);
1232 static void rtl8169_check_link_status(struct net_device
*dev
,
1233 struct rtl8169_private
*tp
,
1234 void __iomem
*ioaddr
)
1236 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1239 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1241 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1243 void __iomem
*ioaddr
= tp
->mmio_addr
;
1247 options
= RTL_R8(Config1
);
1248 if (!(options
& PMEnable
))
1251 options
= RTL_R8(Config3
);
1252 if (options
& LinkUp
)
1253 wolopts
|= WAKE_PHY
;
1254 if (options
& MagicPacket
)
1255 wolopts
|= WAKE_MAGIC
;
1257 options
= RTL_R8(Config5
);
1259 wolopts
|= WAKE_UCAST
;
1261 wolopts
|= WAKE_BCAST
;
1263 wolopts
|= WAKE_MCAST
;
1268 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1270 struct rtl8169_private
*tp
= netdev_priv(dev
);
1272 spin_lock_irq(&tp
->lock
);
1274 wol
->supported
= WAKE_ANY
;
1275 wol
->wolopts
= __rtl8169_get_wol(tp
);
1277 spin_unlock_irq(&tp
->lock
);
1280 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1282 void __iomem
*ioaddr
= tp
->mmio_addr
;
1284 static const struct {
1289 { WAKE_ANY
, Config1
, PMEnable
},
1290 { WAKE_PHY
, Config3
, LinkUp
},
1291 { WAKE_MAGIC
, Config3
, MagicPacket
},
1292 { WAKE_UCAST
, Config5
, UWF
},
1293 { WAKE_BCAST
, Config5
, BWF
},
1294 { WAKE_MCAST
, Config5
, MWF
},
1295 { WAKE_ANY
, Config5
, LanWake
}
1298 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1300 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1301 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1302 if (wolopts
& cfg
[i
].opt
)
1303 options
|= cfg
[i
].mask
;
1304 RTL_W8(cfg
[i
].reg
, options
);
1307 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1310 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1312 struct rtl8169_private
*tp
= netdev_priv(dev
);
1314 spin_lock_irq(&tp
->lock
);
1317 tp
->features
|= RTL_FEATURE_WOL
;
1319 tp
->features
&= ~RTL_FEATURE_WOL
;
1320 __rtl8169_set_wol(tp
, wol
->wolopts
);
1321 spin_unlock_irq(&tp
->lock
);
1323 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1328 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1330 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1333 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1334 struct ethtool_drvinfo
*info
)
1336 struct rtl8169_private
*tp
= netdev_priv(dev
);
1337 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1339 strcpy(info
->driver
, MODULENAME
);
1340 strcpy(info
->version
, RTL8169_VERSION
);
1341 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
1342 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1343 strcpy(info
->fw_version
, IS_ERR_OR_NULL(rtl_fw
) ? "N/A" :
1347 static int rtl8169_get_regs_len(struct net_device
*dev
)
1349 return R8169_REGS_SIZE
;
1352 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1353 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1355 struct rtl8169_private
*tp
= netdev_priv(dev
);
1356 void __iomem
*ioaddr
= tp
->mmio_addr
;
1360 reg
= RTL_R32(TBICSR
);
1361 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1362 (duplex
== DUPLEX_FULL
)) {
1363 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1364 } else if (autoneg
== AUTONEG_ENABLE
)
1365 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1367 netif_warn(tp
, link
, dev
,
1368 "incorrect speed setting refused in TBI mode\n");
1375 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1376 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1378 struct rtl8169_private
*tp
= netdev_priv(dev
);
1379 int giga_ctrl
, bmcr
;
1382 rtl_writephy(tp
, 0x1f, 0x0000);
1384 if (autoneg
== AUTONEG_ENABLE
) {
1387 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1388 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1389 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1391 if (adv
& ADVERTISED_10baseT_Half
)
1392 auto_nego
|= ADVERTISE_10HALF
;
1393 if (adv
& ADVERTISED_10baseT_Full
)
1394 auto_nego
|= ADVERTISE_10FULL
;
1395 if (adv
& ADVERTISED_100baseT_Half
)
1396 auto_nego
|= ADVERTISE_100HALF
;
1397 if (adv
& ADVERTISED_100baseT_Full
)
1398 auto_nego
|= ADVERTISE_100FULL
;
1400 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1402 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1403 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1405 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1406 if (tp
->mii
.supports_gmii
) {
1407 if (adv
& ADVERTISED_1000baseT_Half
)
1408 giga_ctrl
|= ADVERTISE_1000HALF
;
1409 if (adv
& ADVERTISED_1000baseT_Full
)
1410 giga_ctrl
|= ADVERTISE_1000FULL
;
1411 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1412 ADVERTISED_1000baseT_Full
)) {
1413 netif_info(tp
, link
, dev
,
1414 "PHY does not support 1000Mbps\n");
1418 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1420 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1421 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1425 if (speed
== SPEED_10
)
1427 else if (speed
== SPEED_100
)
1428 bmcr
= BMCR_SPEED100
;
1432 if (duplex
== DUPLEX_FULL
)
1433 bmcr
|= BMCR_FULLDPLX
;
1436 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1438 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1439 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1440 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1441 rtl_writephy(tp
, 0x17, 0x2138);
1442 rtl_writephy(tp
, 0x0e, 0x0260);
1444 rtl_writephy(tp
, 0x17, 0x2108);
1445 rtl_writephy(tp
, 0x0e, 0x0000);
1454 static int rtl8169_set_speed(struct net_device
*dev
,
1455 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1457 struct rtl8169_private
*tp
= netdev_priv(dev
);
1460 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1464 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1465 (advertising
& ADVERTISED_1000baseT_Full
)) {
1466 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1472 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1474 struct rtl8169_private
*tp
= netdev_priv(dev
);
1475 unsigned long flags
;
1478 del_timer_sync(&tp
->timer
);
1480 spin_lock_irqsave(&tp
->lock
, flags
);
1481 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1482 cmd
->duplex
, cmd
->advertising
);
1483 spin_unlock_irqrestore(&tp
->lock
, flags
);
1488 static u32
rtl8169_fix_features(struct net_device
*dev
, u32 features
)
1490 if (dev
->mtu
> TD_MSS_MAX
)
1491 features
&= ~NETIF_F_ALL_TSO
;
1496 static int rtl8169_set_features(struct net_device
*dev
, u32 features
)
1498 struct rtl8169_private
*tp
= netdev_priv(dev
);
1499 void __iomem
*ioaddr
= tp
->mmio_addr
;
1500 unsigned long flags
;
1502 spin_lock_irqsave(&tp
->lock
, flags
);
1504 if (features
& NETIF_F_RXCSUM
)
1505 tp
->cp_cmd
|= RxChkSum
;
1507 tp
->cp_cmd
&= ~RxChkSum
;
1509 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1510 tp
->cp_cmd
|= RxVlan
;
1512 tp
->cp_cmd
&= ~RxVlan
;
1514 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1517 spin_unlock_irqrestore(&tp
->lock
, flags
);
1522 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1523 struct sk_buff
*skb
)
1525 return (vlan_tx_tag_present(skb
)) ?
1526 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1529 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1531 u32 opts2
= le32_to_cpu(desc
->opts2
);
1533 if (opts2
& RxVlanTag
)
1534 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1539 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1541 struct rtl8169_private
*tp
= netdev_priv(dev
);
1542 void __iomem
*ioaddr
= tp
->mmio_addr
;
1546 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1547 cmd
->port
= PORT_FIBRE
;
1548 cmd
->transceiver
= XCVR_INTERNAL
;
1550 status
= RTL_R32(TBICSR
);
1551 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1552 cmd
->autoneg
= !!(status
& TBINwEnable
);
1554 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1555 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1560 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1562 struct rtl8169_private
*tp
= netdev_priv(dev
);
1564 return mii_ethtool_gset(&tp
->mii
, cmd
);
1567 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1569 struct rtl8169_private
*tp
= netdev_priv(dev
);
1570 unsigned long flags
;
1573 spin_lock_irqsave(&tp
->lock
, flags
);
1575 rc
= tp
->get_settings(dev
, cmd
);
1577 spin_unlock_irqrestore(&tp
->lock
, flags
);
1581 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1584 struct rtl8169_private
*tp
= netdev_priv(dev
);
1585 unsigned long flags
;
1587 if (regs
->len
> R8169_REGS_SIZE
)
1588 regs
->len
= R8169_REGS_SIZE
;
1590 spin_lock_irqsave(&tp
->lock
, flags
);
1591 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1592 spin_unlock_irqrestore(&tp
->lock
, flags
);
1595 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1597 struct rtl8169_private
*tp
= netdev_priv(dev
);
1599 return tp
->msg_enable
;
1602 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1604 struct rtl8169_private
*tp
= netdev_priv(dev
);
1606 tp
->msg_enable
= value
;
1609 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1616 "tx_single_collisions",
1617 "tx_multi_collisions",
1625 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1629 return ARRAY_SIZE(rtl8169_gstrings
);
1635 static void rtl8169_update_counters(struct net_device
*dev
)
1637 struct rtl8169_private
*tp
= netdev_priv(dev
);
1638 void __iomem
*ioaddr
= tp
->mmio_addr
;
1639 struct device
*d
= &tp
->pci_dev
->dev
;
1640 struct rtl8169_counters
*counters
;
1646 * Some chips are unable to dump tally counters when the receiver
1649 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1652 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1656 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1657 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1658 RTL_W32(CounterAddrLow
, cmd
);
1659 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1662 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1663 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1669 RTL_W32(CounterAddrLow
, 0);
1670 RTL_W32(CounterAddrHigh
, 0);
1672 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1675 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1676 struct ethtool_stats
*stats
, u64
*data
)
1678 struct rtl8169_private
*tp
= netdev_priv(dev
);
1682 rtl8169_update_counters(dev
);
1684 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1685 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1686 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1687 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1688 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1689 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1690 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1691 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1692 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1693 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1694 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1695 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1696 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1699 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1703 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1708 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1709 .get_drvinfo
= rtl8169_get_drvinfo
,
1710 .get_regs_len
= rtl8169_get_regs_len
,
1711 .get_link
= ethtool_op_get_link
,
1712 .get_settings
= rtl8169_get_settings
,
1713 .set_settings
= rtl8169_set_settings
,
1714 .get_msglevel
= rtl8169_get_msglevel
,
1715 .set_msglevel
= rtl8169_set_msglevel
,
1716 .get_regs
= rtl8169_get_regs
,
1717 .get_wol
= rtl8169_get_wol
,
1718 .set_wol
= rtl8169_set_wol
,
1719 .get_strings
= rtl8169_get_strings
,
1720 .get_sset_count
= rtl8169_get_sset_count
,
1721 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1724 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1725 struct net_device
*dev
, u8 default_version
)
1727 void __iomem
*ioaddr
= tp
->mmio_addr
;
1729 * The driver currently handles the 8168Bf and the 8168Be identically
1730 * but they can be identified more specifically through the test below
1733 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1735 * Same thing for the 8101Eb and the 8101Ec:
1737 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1739 static const struct rtl_mac_info
{
1745 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
1746 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1747 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1748 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1751 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1752 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1753 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1755 /* 8168DP family. */
1756 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1757 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1758 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1761 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1762 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1763 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1764 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1765 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1766 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1767 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1768 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1769 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1772 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1773 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1774 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1775 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1778 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1779 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1780 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1781 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1782 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1783 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1784 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1785 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1786 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1787 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1788 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1789 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1790 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1791 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1792 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1793 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1794 /* FIXME: where did these entries come from ? -- FR */
1795 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1796 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1799 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1800 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1801 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1802 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1803 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1804 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1807 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1809 const struct rtl_mac_info
*p
= mac_info
;
1812 reg
= RTL_R32(TxConfig
);
1813 while ((reg
& p
->mask
) != p
->val
)
1815 tp
->mac_version
= p
->mac_version
;
1817 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
1818 netif_notice(tp
, probe
, dev
,
1819 "unknown MAC, using family default\n");
1820 tp
->mac_version
= default_version
;
1824 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1826 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1834 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1835 const struct phy_reg
*regs
, int len
)
1838 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1843 #define PHY_READ 0x00000000
1844 #define PHY_DATA_OR 0x10000000
1845 #define PHY_DATA_AND 0x20000000
1846 #define PHY_BJMPN 0x30000000
1847 #define PHY_READ_EFUSE 0x40000000
1848 #define PHY_READ_MAC_BYTE 0x50000000
1849 #define PHY_WRITE_MAC_BYTE 0x60000000
1850 #define PHY_CLEAR_READCOUNT 0x70000000
1851 #define PHY_WRITE 0x80000000
1852 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1853 #define PHY_COMP_EQ_SKIPN 0xa0000000
1854 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1855 #define PHY_WRITE_PREVIOUS 0xc0000000
1856 #define PHY_SKIPN 0xd0000000
1857 #define PHY_DELAY_MS 0xe0000000
1858 #define PHY_WRITE_ERI_WORD 0xf0000000
1862 char version
[RTL_VER_SIZE
];
1868 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1870 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1872 const struct firmware
*fw
= rtl_fw
->fw
;
1873 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
1874 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
1875 char *version
= rtl_fw
->version
;
1878 if (fw
->size
< FW_OPCODE_SIZE
)
1881 if (!fw_info
->magic
) {
1882 size_t i
, size
, start
;
1885 if (fw
->size
< sizeof(*fw_info
))
1888 for (i
= 0; i
< fw
->size
; i
++)
1889 checksum
+= fw
->data
[i
];
1893 start
= le32_to_cpu(fw_info
->fw_start
);
1894 if (start
> fw
->size
)
1897 size
= le32_to_cpu(fw_info
->fw_len
);
1898 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
1901 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
1903 pa
->code
= (__le32
*)(fw
->data
+ start
);
1906 if (fw
->size
% FW_OPCODE_SIZE
)
1909 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
1911 pa
->code
= (__le32
*)fw
->data
;
1912 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
1914 version
[RTL_VER_SIZE
- 1] = 0;
1921 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
1922 struct rtl_fw_phy_action
*pa
)
1927 for (index
= 0; index
< pa
->size
; index
++) {
1928 u32 action
= le32_to_cpu(pa
->code
[index
]);
1929 u32 regno
= (action
& 0x0fff0000) >> 16;
1931 switch(action
& 0xf0000000) {
1935 case PHY_READ_EFUSE
:
1936 case PHY_CLEAR_READCOUNT
:
1938 case PHY_WRITE_PREVIOUS
:
1943 if (regno
> index
) {
1944 netif_err(tp
, ifup
, tp
->dev
,
1945 "Out of range of firmware\n");
1949 case PHY_READCOUNT_EQ_SKIP
:
1950 if (index
+ 2 >= pa
->size
) {
1951 netif_err(tp
, ifup
, tp
->dev
,
1952 "Out of range of firmware\n");
1956 case PHY_COMP_EQ_SKIPN
:
1957 case PHY_COMP_NEQ_SKIPN
:
1959 if (index
+ 1 + regno
>= pa
->size
) {
1960 netif_err(tp
, ifup
, tp
->dev
,
1961 "Out of range of firmware\n");
1966 case PHY_READ_MAC_BYTE
:
1967 case PHY_WRITE_MAC_BYTE
:
1968 case PHY_WRITE_ERI_WORD
:
1970 netif_err(tp
, ifup
, tp
->dev
,
1971 "Invalid action 0x%08x\n", action
);
1980 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1982 struct net_device
*dev
= tp
->dev
;
1985 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
1986 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
1990 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
1996 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1998 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2002 predata
= count
= 0;
2004 for (index
= 0; index
< pa
->size
; ) {
2005 u32 action
= le32_to_cpu(pa
->code
[index
]);
2006 u32 data
= action
& 0x0000ffff;
2007 u32 regno
= (action
& 0x0fff0000) >> 16;
2012 switch(action
& 0xf0000000) {
2014 predata
= rtl_readphy(tp
, regno
);
2029 case PHY_READ_EFUSE
:
2030 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
2033 case PHY_CLEAR_READCOUNT
:
2038 rtl_writephy(tp
, regno
, data
);
2041 case PHY_READCOUNT_EQ_SKIP
:
2042 index
+= (count
== data
) ? 2 : 1;
2044 case PHY_COMP_EQ_SKIPN
:
2045 if (predata
== data
)
2049 case PHY_COMP_NEQ_SKIPN
:
2050 if (predata
!= data
)
2054 case PHY_WRITE_PREVIOUS
:
2055 rtl_writephy(tp
, regno
, predata
);
2066 case PHY_READ_MAC_BYTE
:
2067 case PHY_WRITE_MAC_BYTE
:
2068 case PHY_WRITE_ERI_WORD
:
2075 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2077 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2078 release_firmware(tp
->rtl_fw
->fw
);
2081 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2084 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2086 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2088 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2089 if (!IS_ERR_OR_NULL(rtl_fw
))
2090 rtl_phy_write_fw(tp
, rtl_fw
);
2093 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2095 if (rtl_readphy(tp
, reg
) != val
)
2096 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2098 rtl_apply_firmware(tp
);
2101 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2103 static const struct phy_reg phy_reg_init
[] = {
2165 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2168 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2170 static const struct phy_reg phy_reg_init
[] = {
2176 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2179 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2181 struct pci_dev
*pdev
= tp
->pci_dev
;
2183 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2184 (pdev
->subsystem_device
!= 0xe000))
2187 rtl_writephy(tp
, 0x1f, 0x0001);
2188 rtl_writephy(tp
, 0x10, 0xf01b);
2189 rtl_writephy(tp
, 0x1f, 0x0000);
2192 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2194 static const struct phy_reg phy_reg_init
[] = {
2234 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2236 rtl8169scd_hw_phy_config_quirk(tp
);
2239 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2241 static const struct phy_reg phy_reg_init
[] = {
2289 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2292 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2294 static const struct phy_reg phy_reg_init
[] = {
2299 rtl_writephy(tp
, 0x1f, 0x0001);
2300 rtl_patchphy(tp
, 0x16, 1 << 0);
2302 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2305 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2307 static const struct phy_reg phy_reg_init
[] = {
2313 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2316 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2318 static const struct phy_reg phy_reg_init
[] = {
2326 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2329 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2331 static const struct phy_reg phy_reg_init
[] = {
2337 rtl_writephy(tp
, 0x1f, 0x0000);
2338 rtl_patchphy(tp
, 0x14, 1 << 5);
2339 rtl_patchphy(tp
, 0x0d, 1 << 5);
2341 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2344 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2346 static const struct phy_reg phy_reg_init
[] = {
2366 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2368 rtl_patchphy(tp
, 0x14, 1 << 5);
2369 rtl_patchphy(tp
, 0x0d, 1 << 5);
2370 rtl_writephy(tp
, 0x1f, 0x0000);
2373 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2375 static const struct phy_reg phy_reg_init
[] = {
2393 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2395 rtl_patchphy(tp
, 0x16, 1 << 0);
2396 rtl_patchphy(tp
, 0x14, 1 << 5);
2397 rtl_patchphy(tp
, 0x0d, 1 << 5);
2398 rtl_writephy(tp
, 0x1f, 0x0000);
2401 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2403 static const struct phy_reg phy_reg_init
[] = {
2415 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2417 rtl_patchphy(tp
, 0x16, 1 << 0);
2418 rtl_patchphy(tp
, 0x14, 1 << 5);
2419 rtl_patchphy(tp
, 0x0d, 1 << 5);
2420 rtl_writephy(tp
, 0x1f, 0x0000);
2423 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2425 rtl8168c_3_hw_phy_config(tp
);
2428 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2430 static const struct phy_reg phy_reg_init_0
[] = {
2431 /* Channel Estimation */
2452 * Enhance line driver power
2461 * Can not link to 1Gbps with bad cable
2462 * Decrease SNR threshold form 21.07dB to 19.04dB
2470 void __iomem
*ioaddr
= tp
->mmio_addr
;
2472 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2476 * Fine Tune Switching regulator parameter
2478 rtl_writephy(tp
, 0x1f, 0x0002);
2479 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2480 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2482 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2483 static const struct phy_reg phy_reg_init
[] = {
2493 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2495 val
= rtl_readphy(tp
, 0x0d);
2497 if ((val
& 0x00ff) != 0x006c) {
2498 static const u32 set
[] = {
2499 0x0065, 0x0066, 0x0067, 0x0068,
2500 0x0069, 0x006a, 0x006b, 0x006c
2504 rtl_writephy(tp
, 0x1f, 0x0002);
2507 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2508 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2511 static const struct phy_reg phy_reg_init
[] = {
2519 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2522 /* RSET couple improve */
2523 rtl_writephy(tp
, 0x1f, 0x0002);
2524 rtl_patchphy(tp
, 0x0d, 0x0300);
2525 rtl_patchphy(tp
, 0x0f, 0x0010);
2527 /* Fine tune PLL performance */
2528 rtl_writephy(tp
, 0x1f, 0x0002);
2529 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2530 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2532 rtl_writephy(tp
, 0x1f, 0x0005);
2533 rtl_writephy(tp
, 0x05, 0x001b);
2535 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2537 rtl_writephy(tp
, 0x1f, 0x0000);
2540 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2542 static const struct phy_reg phy_reg_init_0
[] = {
2543 /* Channel Estimation */
2564 * Enhance line driver power
2573 * Can not link to 1Gbps with bad cable
2574 * Decrease SNR threshold form 21.07dB to 19.04dB
2582 void __iomem
*ioaddr
= tp
->mmio_addr
;
2584 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2586 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2587 static const struct phy_reg phy_reg_init
[] = {
2598 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2600 val
= rtl_readphy(tp
, 0x0d);
2601 if ((val
& 0x00ff) != 0x006c) {
2602 static const u32 set
[] = {
2603 0x0065, 0x0066, 0x0067, 0x0068,
2604 0x0069, 0x006a, 0x006b, 0x006c
2608 rtl_writephy(tp
, 0x1f, 0x0002);
2611 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2612 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2615 static const struct phy_reg phy_reg_init
[] = {
2623 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2626 /* Fine tune PLL performance */
2627 rtl_writephy(tp
, 0x1f, 0x0002);
2628 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2629 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2631 /* Switching regulator Slew rate */
2632 rtl_writephy(tp
, 0x1f, 0x0002);
2633 rtl_patchphy(tp
, 0x0f, 0x0017);
2635 rtl_writephy(tp
, 0x1f, 0x0005);
2636 rtl_writephy(tp
, 0x05, 0x001b);
2638 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2640 rtl_writephy(tp
, 0x1f, 0x0000);
2643 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2645 static const struct phy_reg phy_reg_init
[] = {
2701 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2704 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2706 static const struct phy_reg phy_reg_init
[] = {
2716 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2717 rtl_patchphy(tp
, 0x0d, 1 << 5);
2720 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
2722 static const struct phy_reg phy_reg_init
[] = {
2723 /* Enable Delay cap */
2729 /* Channel estimation fine tune */
2738 /* Update PFM & 10M TX idle timer */
2750 rtl_apply_firmware(tp
);
2752 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2754 /* DCO enable for 10M IDLE Power */
2755 rtl_writephy(tp
, 0x1f, 0x0007);
2756 rtl_writephy(tp
, 0x1e, 0x0023);
2757 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2758 rtl_writephy(tp
, 0x1f, 0x0000);
2760 /* For impedance matching */
2761 rtl_writephy(tp
, 0x1f, 0x0002);
2762 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2763 rtl_writephy(tp
, 0x1f, 0x0000);
2765 /* PHY auto speed down */
2766 rtl_writephy(tp
, 0x1f, 0x0007);
2767 rtl_writephy(tp
, 0x1e, 0x002d);
2768 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2769 rtl_writephy(tp
, 0x1f, 0x0000);
2770 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2772 rtl_writephy(tp
, 0x1f, 0x0005);
2773 rtl_writephy(tp
, 0x05, 0x8b86);
2774 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2775 rtl_writephy(tp
, 0x1f, 0x0000);
2777 rtl_writephy(tp
, 0x1f, 0x0005);
2778 rtl_writephy(tp
, 0x05, 0x8b85);
2779 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2780 rtl_writephy(tp
, 0x1f, 0x0007);
2781 rtl_writephy(tp
, 0x1e, 0x0020);
2782 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2783 rtl_writephy(tp
, 0x1f, 0x0006);
2784 rtl_writephy(tp
, 0x00, 0x5a00);
2785 rtl_writephy(tp
, 0x1f, 0x0000);
2786 rtl_writephy(tp
, 0x0d, 0x0007);
2787 rtl_writephy(tp
, 0x0e, 0x003c);
2788 rtl_writephy(tp
, 0x0d, 0x4007);
2789 rtl_writephy(tp
, 0x0e, 0x0000);
2790 rtl_writephy(tp
, 0x0d, 0x0000);
2793 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
2795 static const struct phy_reg phy_reg_init
[] = {
2796 /* Enable Delay cap */
2805 /* Channel estimation fine tune */
2822 rtl_apply_firmware(tp
);
2824 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2826 /* For 4-corner performance improve */
2827 rtl_writephy(tp
, 0x1f, 0x0005);
2828 rtl_writephy(tp
, 0x05, 0x8b80);
2829 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2830 rtl_writephy(tp
, 0x1f, 0x0000);
2832 /* PHY auto speed down */
2833 rtl_writephy(tp
, 0x1f, 0x0004);
2834 rtl_writephy(tp
, 0x1f, 0x0007);
2835 rtl_writephy(tp
, 0x1e, 0x002d);
2836 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
2837 rtl_writephy(tp
, 0x1f, 0x0002);
2838 rtl_writephy(tp
, 0x1f, 0x0000);
2839 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2841 /* improve 10M EEE waveform */
2842 rtl_writephy(tp
, 0x1f, 0x0005);
2843 rtl_writephy(tp
, 0x05, 0x8b86);
2844 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2845 rtl_writephy(tp
, 0x1f, 0x0000);
2847 /* Improve 2-pair detection performance */
2848 rtl_writephy(tp
, 0x1f, 0x0005);
2849 rtl_writephy(tp
, 0x05, 0x8b85);
2850 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
2851 rtl_writephy(tp
, 0x1f, 0x0000);
2854 rtl_w1w0_eri(tp
->mmio_addr
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003,
2856 rtl_writephy(tp
, 0x1f, 0x0005);
2857 rtl_writephy(tp
, 0x05, 0x8b85);
2858 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2859 rtl_writephy(tp
, 0x1f, 0x0004);
2860 rtl_writephy(tp
, 0x1f, 0x0007);
2861 rtl_writephy(tp
, 0x1e, 0x0020);
2862 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x0100);
2863 rtl_writephy(tp
, 0x1f, 0x0002);
2864 rtl_writephy(tp
, 0x1f, 0x0000);
2865 rtl_writephy(tp
, 0x0d, 0x0007);
2866 rtl_writephy(tp
, 0x0e, 0x003c);
2867 rtl_writephy(tp
, 0x0d, 0x4007);
2868 rtl_writephy(tp
, 0x0e, 0x0000);
2869 rtl_writephy(tp
, 0x0d, 0x0000);
2872 rtl_writephy(tp
, 0x1f, 0x0003);
2873 rtl_w1w0_phy(tp
, 0x19, 0x0000, 0x0001);
2874 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0400);
2875 rtl_writephy(tp
, 0x1f, 0x0000);
2878 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
2880 static const struct phy_reg phy_reg_init
[] = {
2887 rtl_writephy(tp
, 0x1f, 0x0000);
2888 rtl_patchphy(tp
, 0x11, 1 << 12);
2889 rtl_patchphy(tp
, 0x19, 1 << 13);
2890 rtl_patchphy(tp
, 0x10, 1 << 15);
2892 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2895 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
2897 static const struct phy_reg phy_reg_init
[] = {
2911 /* Disable ALDPS before ram code */
2912 rtl_writephy(tp
, 0x1f, 0x0000);
2913 rtl_writephy(tp
, 0x18, 0x0310);
2916 rtl_apply_firmware(tp
);
2918 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2921 static void rtl_hw_phy_config(struct net_device
*dev
)
2923 struct rtl8169_private
*tp
= netdev_priv(dev
);
2925 rtl8169_print_mac_version(tp
);
2927 switch (tp
->mac_version
) {
2928 case RTL_GIGA_MAC_VER_01
:
2930 case RTL_GIGA_MAC_VER_02
:
2931 case RTL_GIGA_MAC_VER_03
:
2932 rtl8169s_hw_phy_config(tp
);
2934 case RTL_GIGA_MAC_VER_04
:
2935 rtl8169sb_hw_phy_config(tp
);
2937 case RTL_GIGA_MAC_VER_05
:
2938 rtl8169scd_hw_phy_config(tp
);
2940 case RTL_GIGA_MAC_VER_06
:
2941 rtl8169sce_hw_phy_config(tp
);
2943 case RTL_GIGA_MAC_VER_07
:
2944 case RTL_GIGA_MAC_VER_08
:
2945 case RTL_GIGA_MAC_VER_09
:
2946 rtl8102e_hw_phy_config(tp
);
2948 case RTL_GIGA_MAC_VER_11
:
2949 rtl8168bb_hw_phy_config(tp
);
2951 case RTL_GIGA_MAC_VER_12
:
2952 rtl8168bef_hw_phy_config(tp
);
2954 case RTL_GIGA_MAC_VER_17
:
2955 rtl8168bef_hw_phy_config(tp
);
2957 case RTL_GIGA_MAC_VER_18
:
2958 rtl8168cp_1_hw_phy_config(tp
);
2960 case RTL_GIGA_MAC_VER_19
:
2961 rtl8168c_1_hw_phy_config(tp
);
2963 case RTL_GIGA_MAC_VER_20
:
2964 rtl8168c_2_hw_phy_config(tp
);
2966 case RTL_GIGA_MAC_VER_21
:
2967 rtl8168c_3_hw_phy_config(tp
);
2969 case RTL_GIGA_MAC_VER_22
:
2970 rtl8168c_4_hw_phy_config(tp
);
2972 case RTL_GIGA_MAC_VER_23
:
2973 case RTL_GIGA_MAC_VER_24
:
2974 rtl8168cp_2_hw_phy_config(tp
);
2976 case RTL_GIGA_MAC_VER_25
:
2977 rtl8168d_1_hw_phy_config(tp
);
2979 case RTL_GIGA_MAC_VER_26
:
2980 rtl8168d_2_hw_phy_config(tp
);
2982 case RTL_GIGA_MAC_VER_27
:
2983 rtl8168d_3_hw_phy_config(tp
);
2985 case RTL_GIGA_MAC_VER_28
:
2986 rtl8168d_4_hw_phy_config(tp
);
2988 case RTL_GIGA_MAC_VER_29
:
2989 case RTL_GIGA_MAC_VER_30
:
2990 rtl8105e_hw_phy_config(tp
);
2992 case RTL_GIGA_MAC_VER_31
:
2995 case RTL_GIGA_MAC_VER_32
:
2996 case RTL_GIGA_MAC_VER_33
:
2997 rtl8168e_1_hw_phy_config(tp
);
2999 case RTL_GIGA_MAC_VER_34
:
3000 rtl8168e_2_hw_phy_config(tp
);
3008 static void rtl8169_phy_timer(unsigned long __opaque
)
3010 struct net_device
*dev
= (struct net_device
*)__opaque
;
3011 struct rtl8169_private
*tp
= netdev_priv(dev
);
3012 struct timer_list
*timer
= &tp
->timer
;
3013 void __iomem
*ioaddr
= tp
->mmio_addr
;
3014 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
3016 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
3018 spin_lock_irq(&tp
->lock
);
3020 if (tp
->phy_reset_pending(tp
)) {
3022 * A busy loop could burn quite a few cycles on nowadays CPU.
3023 * Let's delay the execution of the timer for a few ticks.
3029 if (tp
->link_ok(ioaddr
))
3032 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
3034 tp
->phy_reset_enable(tp
);
3037 mod_timer(timer
, jiffies
+ timeout
);
3039 spin_unlock_irq(&tp
->lock
);
3042 #ifdef CONFIG_NET_POLL_CONTROLLER
3044 * Polling 'interrupt' - used by things like netconsole to send skbs
3045 * without having to re-enable interrupts. It's not called while
3046 * the interrupt routine is executing.
3048 static void rtl8169_netpoll(struct net_device
*dev
)
3050 struct rtl8169_private
*tp
= netdev_priv(dev
);
3051 struct pci_dev
*pdev
= tp
->pci_dev
;
3053 disable_irq(pdev
->irq
);
3054 rtl8169_interrupt(pdev
->irq
, dev
);
3055 enable_irq(pdev
->irq
);
3059 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
3060 void __iomem
*ioaddr
)
3063 pci_release_regions(pdev
);
3064 pci_clear_mwi(pdev
);
3065 pci_disable_device(pdev
);
3069 static void rtl8169_phy_reset(struct net_device
*dev
,
3070 struct rtl8169_private
*tp
)
3074 tp
->phy_reset_enable(tp
);
3075 for (i
= 0; i
< 100; i
++) {
3076 if (!tp
->phy_reset_pending(tp
))
3080 netif_err(tp
, link
, dev
, "PHY reset failed\n");
3083 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
3085 void __iomem
*ioaddr
= tp
->mmio_addr
;
3087 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
3088 (RTL_R8(PHYstatus
) & TBI_Enable
);
3091 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
3093 void __iomem
*ioaddr
= tp
->mmio_addr
;
3095 rtl_hw_phy_config(dev
);
3097 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
3098 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3102 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
3104 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3105 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
3107 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
3108 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3110 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3111 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
3114 rtl8169_phy_reset(dev
, tp
);
3116 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
3117 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3118 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
3119 (tp
->mii
.supports_gmii
?
3120 ADVERTISED_1000baseT_Half
|
3121 ADVERTISED_1000baseT_Full
: 0));
3123 if (rtl_tbi_enabled(tp
))
3124 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
3127 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
3129 void __iomem
*ioaddr
= tp
->mmio_addr
;
3133 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
3134 high
= addr
[4] | (addr
[5] << 8);
3136 spin_lock_irq(&tp
->lock
);
3138 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3140 RTL_W32(MAC4
, high
);
3146 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
3147 const struct exgmac_reg e
[] = {
3148 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= low
},
3149 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= high
},
3150 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= low
<< 16 },
3151 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= high
<< 16 |
3155 rtl_write_exgmac_batch(ioaddr
, e
, ARRAY_SIZE(e
));
3158 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3160 spin_unlock_irq(&tp
->lock
);
3163 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
3165 struct rtl8169_private
*tp
= netdev_priv(dev
);
3166 struct sockaddr
*addr
= p
;
3168 if (!is_valid_ether_addr(addr
->sa_data
))
3169 return -EADDRNOTAVAIL
;
3171 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
3173 rtl_rar_set(tp
, dev
->dev_addr
);
3178 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3180 struct rtl8169_private
*tp
= netdev_priv(dev
);
3181 struct mii_ioctl_data
*data
= if_mii(ifr
);
3183 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
3186 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
3187 struct mii_ioctl_data
*data
, int cmd
)
3191 data
->phy_id
= 32; /* Internal PHY */
3195 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
3199 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
3205 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
3210 static const struct rtl_cfg_info
{
3211 void (*hw_start
)(struct net_device
*);
3212 unsigned int region
;
3218 } rtl_cfg_infos
[] = {
3220 .hw_start
= rtl_hw_start_8169
,
3223 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3224 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3225 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3226 .features
= RTL_FEATURE_GMII
,
3227 .default_ver
= RTL_GIGA_MAC_VER_01
,
3230 .hw_start
= rtl_hw_start_8168
,
3233 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3234 TxErr
| TxOK
| RxOK
| RxErr
,
3235 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
3236 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
3237 .default_ver
= RTL_GIGA_MAC_VER_11
,
3240 .hw_start
= rtl_hw_start_8101
,
3243 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
3244 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3245 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3246 .features
= RTL_FEATURE_MSI
,
3247 .default_ver
= RTL_GIGA_MAC_VER_13
,
3251 /* Cfg9346_Unlock assumed. */
3252 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
3253 const struct rtl_cfg_info
*cfg
)
3258 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
3259 if (cfg
->features
& RTL_FEATURE_MSI
) {
3260 if (pci_enable_msi(pdev
)) {
3261 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
3264 msi
= RTL_FEATURE_MSI
;
3267 RTL_W8(Config2
, cfg2
);
3271 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
3273 if (tp
->features
& RTL_FEATURE_MSI
) {
3274 pci_disable_msi(pdev
);
3275 tp
->features
&= ~RTL_FEATURE_MSI
;
3279 static const struct net_device_ops rtl8169_netdev_ops
= {
3280 .ndo_open
= rtl8169_open
,
3281 .ndo_stop
= rtl8169_close
,
3282 .ndo_get_stats
= rtl8169_get_stats
,
3283 .ndo_start_xmit
= rtl8169_start_xmit
,
3284 .ndo_tx_timeout
= rtl8169_tx_timeout
,
3285 .ndo_validate_addr
= eth_validate_addr
,
3286 .ndo_change_mtu
= rtl8169_change_mtu
,
3287 .ndo_fix_features
= rtl8169_fix_features
,
3288 .ndo_set_features
= rtl8169_set_features
,
3289 .ndo_set_mac_address
= rtl_set_mac_address
,
3290 .ndo_do_ioctl
= rtl8169_ioctl
,
3291 .ndo_set_multicast_list
= rtl_set_rx_mode
,
3292 #ifdef CONFIG_NET_POLL_CONTROLLER
3293 .ndo_poll_controller
= rtl8169_netpoll
,
3298 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3300 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3302 switch (tp
->mac_version
) {
3303 case RTL_GIGA_MAC_VER_27
:
3304 ops
->write
= r8168dp_1_mdio_write
;
3305 ops
->read
= r8168dp_1_mdio_read
;
3307 case RTL_GIGA_MAC_VER_28
:
3308 case RTL_GIGA_MAC_VER_31
:
3309 ops
->write
= r8168dp_2_mdio_write
;
3310 ops
->read
= r8168dp_2_mdio_read
;
3313 ops
->write
= r8169_mdio_write
;
3314 ops
->read
= r8169_mdio_read
;
3319 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3321 rtl_writephy(tp
, 0x1f, 0x0000);
3322 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3325 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3327 rtl_writephy(tp
, 0x1f, 0x0000);
3328 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3331 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3333 void __iomem
*ioaddr
= tp
->mmio_addr
;
3335 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3336 rtl_writephy(tp
, 0x1f, 0x0000);
3337 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3339 if (tp
->mac_version
== RTL_GIGA_MAC_VER_29
||
3340 tp
->mac_version
== RTL_GIGA_MAC_VER_30
)
3341 RTL_W32(RxConfig
, RTL_R32(RxConfig
) | AcceptBroadcast
|
3342 AcceptMulticast
| AcceptMyPhys
);
3346 r810x_phy_power_down(tp
);
3349 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3351 r810x_phy_power_up(tp
);
3354 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3356 rtl_writephy(tp
, 0x1f, 0x0000);
3357 switch (tp
->mac_version
) {
3358 case RTL_GIGA_MAC_VER_11
:
3359 case RTL_GIGA_MAC_VER_12
:
3360 case RTL_GIGA_MAC_VER_17
:
3361 case RTL_GIGA_MAC_VER_18
:
3362 case RTL_GIGA_MAC_VER_19
:
3363 case RTL_GIGA_MAC_VER_20
:
3364 case RTL_GIGA_MAC_VER_21
:
3365 case RTL_GIGA_MAC_VER_22
:
3366 case RTL_GIGA_MAC_VER_23
:
3367 case RTL_GIGA_MAC_VER_24
:
3368 case RTL_GIGA_MAC_VER_25
:
3369 case RTL_GIGA_MAC_VER_26
:
3370 case RTL_GIGA_MAC_VER_27
:
3371 case RTL_GIGA_MAC_VER_28
:
3372 case RTL_GIGA_MAC_VER_31
:
3373 rtl_writephy(tp
, 0x0e, 0x0000);
3378 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3381 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3383 rtl_writephy(tp
, 0x1f, 0x0000);
3384 switch (tp
->mac_version
) {
3385 case RTL_GIGA_MAC_VER_32
:
3386 case RTL_GIGA_MAC_VER_33
:
3387 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3390 case RTL_GIGA_MAC_VER_11
:
3391 case RTL_GIGA_MAC_VER_12
:
3392 case RTL_GIGA_MAC_VER_17
:
3393 case RTL_GIGA_MAC_VER_18
:
3394 case RTL_GIGA_MAC_VER_19
:
3395 case RTL_GIGA_MAC_VER_20
:
3396 case RTL_GIGA_MAC_VER_21
:
3397 case RTL_GIGA_MAC_VER_22
:
3398 case RTL_GIGA_MAC_VER_23
:
3399 case RTL_GIGA_MAC_VER_24
:
3400 case RTL_GIGA_MAC_VER_25
:
3401 case RTL_GIGA_MAC_VER_26
:
3402 case RTL_GIGA_MAC_VER_27
:
3403 case RTL_GIGA_MAC_VER_28
:
3404 case RTL_GIGA_MAC_VER_31
:
3405 rtl_writephy(tp
, 0x0e, 0x0200);
3407 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3412 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3414 void __iomem
*ioaddr
= tp
->mmio_addr
;
3416 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3417 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3418 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3419 r8168dp_check_dash(tp
)) {
3423 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
3424 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
3425 (RTL_R16(CPlusCmd
) & ASF
)) {
3429 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3430 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3431 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3433 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3434 rtl_writephy(tp
, 0x1f, 0x0000);
3435 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3437 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3438 tp
->mac_version
== RTL_GIGA_MAC_VER_33
||
3439 tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
3440 RTL_W32(RxConfig
, RTL_R32(RxConfig
) | AcceptBroadcast
|
3441 AcceptMulticast
| AcceptMyPhys
);
3445 r8168_phy_power_down(tp
);
3447 switch (tp
->mac_version
) {
3448 case RTL_GIGA_MAC_VER_25
:
3449 case RTL_GIGA_MAC_VER_26
:
3450 case RTL_GIGA_MAC_VER_27
:
3451 case RTL_GIGA_MAC_VER_28
:
3452 case RTL_GIGA_MAC_VER_31
:
3453 case RTL_GIGA_MAC_VER_32
:
3454 case RTL_GIGA_MAC_VER_33
:
3455 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3460 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3462 void __iomem
*ioaddr
= tp
->mmio_addr
;
3464 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3465 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3466 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3467 r8168dp_check_dash(tp
)) {
3471 switch (tp
->mac_version
) {
3472 case RTL_GIGA_MAC_VER_25
:
3473 case RTL_GIGA_MAC_VER_26
:
3474 case RTL_GIGA_MAC_VER_27
:
3475 case RTL_GIGA_MAC_VER_28
:
3476 case RTL_GIGA_MAC_VER_31
:
3477 case RTL_GIGA_MAC_VER_32
:
3478 case RTL_GIGA_MAC_VER_33
:
3479 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3483 r8168_phy_power_up(tp
);
3486 static void rtl_pll_power_op(struct rtl8169_private
*tp
,
3487 void (*op
)(struct rtl8169_private
*))
3493 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3495 rtl_pll_power_op(tp
, tp
->pll_power_ops
.down
);
3498 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3500 rtl_pll_power_op(tp
, tp
->pll_power_ops
.up
);
3503 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3505 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3507 switch (tp
->mac_version
) {
3508 case RTL_GIGA_MAC_VER_07
:
3509 case RTL_GIGA_MAC_VER_08
:
3510 case RTL_GIGA_MAC_VER_09
:
3511 case RTL_GIGA_MAC_VER_10
:
3512 case RTL_GIGA_MAC_VER_16
:
3513 case RTL_GIGA_MAC_VER_29
:
3514 case RTL_GIGA_MAC_VER_30
:
3515 ops
->down
= r810x_pll_power_down
;
3516 ops
->up
= r810x_pll_power_up
;
3519 case RTL_GIGA_MAC_VER_11
:
3520 case RTL_GIGA_MAC_VER_12
:
3521 case RTL_GIGA_MAC_VER_17
:
3522 case RTL_GIGA_MAC_VER_18
:
3523 case RTL_GIGA_MAC_VER_19
:
3524 case RTL_GIGA_MAC_VER_20
:
3525 case RTL_GIGA_MAC_VER_21
:
3526 case RTL_GIGA_MAC_VER_22
:
3527 case RTL_GIGA_MAC_VER_23
:
3528 case RTL_GIGA_MAC_VER_24
:
3529 case RTL_GIGA_MAC_VER_25
:
3530 case RTL_GIGA_MAC_VER_26
:
3531 case RTL_GIGA_MAC_VER_27
:
3532 case RTL_GIGA_MAC_VER_28
:
3533 case RTL_GIGA_MAC_VER_31
:
3534 case RTL_GIGA_MAC_VER_32
:
3535 case RTL_GIGA_MAC_VER_33
:
3536 case RTL_GIGA_MAC_VER_34
:
3537 ops
->down
= r8168_pll_power_down
;
3538 ops
->up
= r8168_pll_power_up
;
3548 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
3550 void __iomem
*ioaddr
= tp
->mmio_addr
;
3552 switch (tp
->mac_version
) {
3553 case RTL_GIGA_MAC_VER_01
:
3554 case RTL_GIGA_MAC_VER_02
:
3555 case RTL_GIGA_MAC_VER_03
:
3556 case RTL_GIGA_MAC_VER_04
:
3557 case RTL_GIGA_MAC_VER_05
:
3558 case RTL_GIGA_MAC_VER_06
:
3559 case RTL_GIGA_MAC_VER_10
:
3560 case RTL_GIGA_MAC_VER_11
:
3561 case RTL_GIGA_MAC_VER_12
:
3562 case RTL_GIGA_MAC_VER_13
:
3563 case RTL_GIGA_MAC_VER_14
:
3564 case RTL_GIGA_MAC_VER_15
:
3565 case RTL_GIGA_MAC_VER_16
:
3566 case RTL_GIGA_MAC_VER_17
:
3567 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
3569 case RTL_GIGA_MAC_VER_18
:
3570 case RTL_GIGA_MAC_VER_19
:
3571 case RTL_GIGA_MAC_VER_20
:
3572 case RTL_GIGA_MAC_VER_21
:
3573 case RTL_GIGA_MAC_VER_22
:
3574 case RTL_GIGA_MAC_VER_23
:
3575 case RTL_GIGA_MAC_VER_24
:
3576 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
3579 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
3584 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3586 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3589 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3591 void __iomem
*ioaddr
= tp
->mmio_addr
;
3594 /* Soft reset the chip. */
3595 RTL_W8(ChipCmd
, CmdReset
);
3597 /* Check that the chip has finished the reset. */
3598 for (i
= 0; i
< 100; i
++) {
3599 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3604 rtl8169_init_ring_indexes(tp
);
3607 static int __devinit
3608 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3610 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3611 const unsigned int region
= cfg
->region
;
3612 struct rtl8169_private
*tp
;
3613 struct mii_if_info
*mii
;
3614 struct net_device
*dev
;
3615 void __iomem
*ioaddr
;
3619 if (netif_msg_drv(&debug
)) {
3620 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3621 MODULENAME
, RTL8169_VERSION
);
3624 dev
= alloc_etherdev(sizeof (*tp
));
3626 if (netif_msg_drv(&debug
))
3627 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3632 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3633 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3634 tp
= netdev_priv(dev
);
3637 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3641 mii
->mdio_read
= rtl_mdio_read
;
3642 mii
->mdio_write
= rtl_mdio_write
;
3643 mii
->phy_id_mask
= 0x1f;
3644 mii
->reg_num_mask
= 0x1f;
3645 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3647 /* disable ASPM completely as that cause random device stop working
3648 * problems as well as full system hangs for some PCIe devices users */
3649 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3650 PCIE_LINK_STATE_CLKPM
);
3652 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3653 rc
= pci_enable_device(pdev
);
3655 netif_err(tp
, probe
, dev
, "enable failure\n");
3656 goto err_out_free_dev_1
;
3659 if (pci_set_mwi(pdev
) < 0)
3660 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3662 /* make sure PCI base addr 1 is MMIO */
3663 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3664 netif_err(tp
, probe
, dev
,
3665 "region #%d not an MMIO resource, aborting\n",
3671 /* check for weird/broken PCI region reporting */
3672 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3673 netif_err(tp
, probe
, dev
,
3674 "Invalid PCI region size(s), aborting\n");
3679 rc
= pci_request_regions(pdev
, MODULENAME
);
3681 netif_err(tp
, probe
, dev
, "could not request regions\n");
3685 tp
->cp_cmd
= RxChkSum
;
3687 if ((sizeof(dma_addr_t
) > 4) &&
3688 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3689 tp
->cp_cmd
|= PCIDAC
;
3690 dev
->features
|= NETIF_F_HIGHDMA
;
3692 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3694 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3695 goto err_out_free_res_3
;
3699 /* ioremap MMIO region */
3700 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3702 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3704 goto err_out_free_res_3
;
3706 tp
->mmio_addr
= ioaddr
;
3708 if (!pci_is_pcie(pdev
))
3709 netif_info(tp
, probe
, dev
, "not PCI Express\n");
3711 /* Identify chip attached to board */
3712 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
3716 RTL_W16(IntrMask
, 0x0000);
3720 RTL_W16(IntrStatus
, 0xffff);
3722 pci_set_master(pdev
);
3725 * Pretend we are using VLANs; This bypasses a nasty bug where
3726 * Interrupts stop flowing on high load on 8110SCd controllers.
3728 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3729 tp
->cp_cmd
|= RxVlan
;
3731 rtl_init_mdio_ops(tp
);
3732 rtl_init_pll_power_ops(tp
);
3734 rtl8169_print_mac_version(tp
);
3736 chipset
= tp
->mac_version
;
3737 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
3739 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3740 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3741 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3742 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3743 tp
->features
|= RTL_FEATURE_WOL
;
3744 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3745 tp
->features
|= RTL_FEATURE_WOL
;
3746 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3747 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3749 if (rtl_tbi_enabled(tp
)) {
3750 tp
->set_speed
= rtl8169_set_speed_tbi
;
3751 tp
->get_settings
= rtl8169_gset_tbi
;
3752 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3753 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3754 tp
->link_ok
= rtl8169_tbi_link_ok
;
3755 tp
->do_ioctl
= rtl_tbi_ioctl
;
3757 tp
->set_speed
= rtl8169_set_speed_xmii
;
3758 tp
->get_settings
= rtl8169_gset_xmii
;
3759 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3760 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3761 tp
->link_ok
= rtl8169_xmii_link_ok
;
3762 tp
->do_ioctl
= rtl_xmii_ioctl
;
3765 spin_lock_init(&tp
->lock
);
3767 /* Get MAC address */
3768 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3769 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3770 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3772 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3773 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3774 dev
->irq
= pdev
->irq
;
3775 dev
->base_addr
= (unsigned long) ioaddr
;
3777 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3779 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3780 * properly for all devices */
3781 dev
->features
|= NETIF_F_RXCSUM
|
3782 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3784 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3785 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3786 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3789 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3790 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3791 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
3793 tp
->intr_mask
= 0xffff;
3794 tp
->hw_start
= cfg
->hw_start
;
3795 tp
->intr_event
= cfg
->intr_event
;
3796 tp
->napi_event
= cfg
->napi_event
;
3798 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
3799 ~(RxBOVF
| RxFOVF
) : ~0;
3801 init_timer(&tp
->timer
);
3802 tp
->timer
.data
= (unsigned long) dev
;
3803 tp
->timer
.function
= rtl8169_phy_timer
;
3805 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
3807 rc
= register_netdev(dev
);
3811 pci_set_drvdata(pdev
, dev
);
3813 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3814 rtl_chip_infos
[chipset
].name
, dev
->base_addr
, dev
->dev_addr
,
3815 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3817 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3818 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3819 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3820 rtl8168_driver_start(tp
);
3823 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3825 if (pci_dev_run_wake(pdev
))
3826 pm_runtime_put_noidle(&pdev
->dev
);
3828 netif_carrier_off(dev
);
3834 rtl_disable_msi(pdev
, tp
);
3837 pci_release_regions(pdev
);
3839 pci_clear_mwi(pdev
);
3840 pci_disable_device(pdev
);
3846 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3848 struct net_device
*dev
= pci_get_drvdata(pdev
);
3849 struct rtl8169_private
*tp
= netdev_priv(dev
);
3851 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3852 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3853 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3854 rtl8168_driver_stop(tp
);
3857 cancel_delayed_work_sync(&tp
->task
);
3859 unregister_netdev(dev
);
3861 rtl_release_firmware(tp
);
3863 if (pci_dev_run_wake(pdev
))
3864 pm_runtime_get_noresume(&pdev
->dev
);
3866 /* restore original MAC address */
3867 rtl_rar_set(tp
, dev
->perm_addr
);
3869 rtl_disable_msi(pdev
, tp
);
3870 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3871 pci_set_drvdata(pdev
, NULL
);
3874 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
3876 struct rtl_fw
*rtl_fw
;
3880 name
= rtl_lookup_firmware_name(tp
);
3882 goto out_no_firmware
;
3884 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
3888 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
3892 rc
= rtl_check_firmware(tp
, rtl_fw
);
3894 goto err_release_firmware
;
3896 tp
->rtl_fw
= rtl_fw
;
3900 err_release_firmware
:
3901 release_firmware(rtl_fw
->fw
);
3905 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
3912 static void rtl_request_firmware(struct rtl8169_private
*tp
)
3914 if (IS_ERR(tp
->rtl_fw
))
3915 rtl_request_uncached_firmware(tp
);
3918 static int rtl8169_open(struct net_device
*dev
)
3920 struct rtl8169_private
*tp
= netdev_priv(dev
);
3921 void __iomem
*ioaddr
= tp
->mmio_addr
;
3922 struct pci_dev
*pdev
= tp
->pci_dev
;
3923 int retval
= -ENOMEM
;
3925 pm_runtime_get_sync(&pdev
->dev
);
3928 * Rx and Tx desscriptors needs 256 bytes alignment.
3929 * dma_alloc_coherent provides more.
3931 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
3932 &tp
->TxPhyAddr
, GFP_KERNEL
);
3933 if (!tp
->TxDescArray
)
3934 goto err_pm_runtime_put
;
3936 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
3937 &tp
->RxPhyAddr
, GFP_KERNEL
);
3938 if (!tp
->RxDescArray
)
3941 retval
= rtl8169_init_ring(dev
);
3945 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3949 rtl_request_firmware(tp
);
3951 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3952 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3955 goto err_release_fw_2
;
3957 napi_enable(&tp
->napi
);
3959 rtl8169_init_phy(dev
, tp
);
3961 rtl8169_set_features(dev
, dev
->features
);
3963 rtl_pll_power_up(tp
);
3967 tp
->saved_wolopts
= 0;
3968 pm_runtime_put_noidle(&pdev
->dev
);
3970 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3975 rtl_release_firmware(tp
);
3976 rtl8169_rx_clear(tp
);
3978 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3980 tp
->RxDescArray
= NULL
;
3982 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3984 tp
->TxDescArray
= NULL
;
3986 pm_runtime_put_noidle(&pdev
->dev
);
3990 static void rtl_rx_close(struct rtl8169_private
*tp
)
3992 void __iomem
*ioaddr
= tp
->mmio_addr
;
3994 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
3997 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
3999 void __iomem
*ioaddr
= tp
->mmio_addr
;
4001 /* Disable interrupts */
4002 rtl8169_irq_mask_and_ack(ioaddr
);
4006 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4007 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4008 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4009 while (RTL_R8(TxPoll
) & NPQ
)
4011 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
4012 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4013 while (!(RTL_R32(TxConfig
) & TXCFG_EMPTY
))
4016 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4023 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
4025 void __iomem
*ioaddr
= tp
->mmio_addr
;
4027 /* Set DMA burst size and Interframe Gap Time */
4028 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4029 (InterFrameGap
<< TxInterFrameGapShift
));
4032 static void rtl_hw_start(struct net_device
*dev
)
4034 struct rtl8169_private
*tp
= netdev_priv(dev
);
4038 netif_start_queue(dev
);
4041 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
4042 void __iomem
*ioaddr
)
4045 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4046 * register to be written before TxDescAddrLow to work.
4047 * Switching from MMIO to I/O access fixes the issue as well.
4049 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4050 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4051 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4052 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4055 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
4059 cmd
= RTL_R16(CPlusCmd
);
4060 RTL_W16(CPlusCmd
, cmd
);
4064 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
4066 /* Low hurts. Let's disable the filtering. */
4067 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
4070 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
4072 static const struct rtl_cfg2_info
{
4077 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
4078 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
4079 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
4080 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
4082 const struct rtl_cfg2_info
*p
= cfg2_info
;
4086 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
4087 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
4088 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
4089 RTL_W32(0x7c, p
->val
);
4095 static void rtl_hw_start_8169(struct net_device
*dev
)
4097 struct rtl8169_private
*tp
= netdev_priv(dev
);
4098 void __iomem
*ioaddr
= tp
->mmio_addr
;
4099 struct pci_dev
*pdev
= tp
->pci_dev
;
4101 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
4102 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
4103 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
4106 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4107 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4108 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4109 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4110 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4111 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4115 RTL_W8(EarlyTxThres
, NoEarlyTx
);
4117 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4119 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4120 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4121 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4122 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4123 rtl_set_rx_tx_config_registers(tp
);
4125 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
4127 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4128 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
4129 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4130 "Bit-3 and bit-14 MUST be 1\n");
4131 tp
->cp_cmd
|= (1 << 14);
4134 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4136 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
4139 * Undocumented corner. Supposedly:
4140 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4142 RTL_W16(IntrMitigate
, 0x0000);
4144 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4146 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
4147 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
4148 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
4149 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
4150 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4151 rtl_set_rx_tx_config_registers(tp
);
4154 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4156 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4159 RTL_W32(RxMissed
, 0);
4161 rtl_set_rx_mode(dev
);
4163 /* no early-rx interrupts */
4164 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4166 /* Enable all known interrupts by setting the interrupt mask. */
4167 RTL_W16(IntrMask
, tp
->intr_event
);
4170 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
4172 int cap
= pci_pcie_cap(pdev
);
4177 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
4178 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
4179 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
4183 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
4187 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
4188 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
4191 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
4193 rtl_csi_access_enable(ioaddr
, 0x17000000);
4196 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
4198 rtl_csi_access_enable(ioaddr
, 0x27000000);
4202 unsigned int offset
;
4207 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
4212 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
4213 rtl_ephy_write(ioaddr
, e
->offset
, w
);
4218 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
4220 int cap
= pci_pcie_cap(pdev
);
4225 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4226 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
4227 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4231 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
4233 int cap
= pci_pcie_cap(pdev
);
4238 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4239 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
4240 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4244 #define R8168_CPCMD_QUIRK_MASK (\
4255 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4257 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4259 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4261 rtl_tx_performance_tweak(pdev
,
4262 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4265 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4267 rtl_hw_start_8168bb(ioaddr
, pdev
);
4269 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4271 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4274 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4276 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
4278 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4280 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4282 rtl_disable_clock_request(pdev
);
4284 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4287 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4289 static const struct ephy_info e_info_8168cp
[] = {
4290 { 0x01, 0, 0x0001 },
4291 { 0x02, 0x0800, 0x1000 },
4292 { 0x03, 0, 0x0042 },
4293 { 0x06, 0x0080, 0x0000 },
4297 rtl_csi_access_enable_2(ioaddr
);
4299 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
4301 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4304 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4306 rtl_csi_access_enable_2(ioaddr
);
4308 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4310 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4312 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4315 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4317 rtl_csi_access_enable_2(ioaddr
);
4319 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4322 RTL_W8(DBG_REG
, 0x20);
4324 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4326 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4328 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4331 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4333 static const struct ephy_info e_info_8168c_1
[] = {
4334 { 0x02, 0x0800, 0x1000 },
4335 { 0x03, 0, 0x0002 },
4336 { 0x06, 0x0080, 0x0000 }
4339 rtl_csi_access_enable_2(ioaddr
);
4341 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4343 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
4345 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4348 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4350 static const struct ephy_info e_info_8168c_2
[] = {
4351 { 0x01, 0, 0x0001 },
4352 { 0x03, 0x0400, 0x0220 }
4355 rtl_csi_access_enable_2(ioaddr
);
4357 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
4359 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4362 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4364 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4367 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4369 rtl_csi_access_enable_2(ioaddr
);
4371 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4374 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4376 rtl_csi_access_enable_2(ioaddr
);
4378 rtl_disable_clock_request(pdev
);
4380 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4382 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4384 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4387 static void rtl_hw_start_8168dp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4389 rtl_csi_access_enable_1(ioaddr
);
4391 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4393 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4395 rtl_disable_clock_request(pdev
);
4398 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4400 static const struct ephy_info e_info_8168d_4
[] = {
4402 { 0x19, 0x20, 0x50 },
4407 rtl_csi_access_enable_1(ioaddr
);
4409 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4411 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4413 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4414 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4417 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4418 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4421 rtl_enable_clock_request(pdev
);
4424 static void rtl_hw_start_8168e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4426 static const struct ephy_info e_info_8168e_1
[] = {
4427 { 0x00, 0x0200, 0x0100 },
4428 { 0x00, 0x0000, 0x0004 },
4429 { 0x06, 0x0002, 0x0001 },
4430 { 0x06, 0x0000, 0x0030 },
4431 { 0x07, 0x0000, 0x2000 },
4432 { 0x00, 0x0000, 0x0020 },
4433 { 0x03, 0x5800, 0x2000 },
4434 { 0x03, 0x0000, 0x0001 },
4435 { 0x01, 0x0800, 0x1000 },
4436 { 0x07, 0x0000, 0x4000 },
4437 { 0x1e, 0x0000, 0x2000 },
4438 { 0x19, 0xffff, 0xfe6c },
4439 { 0x0a, 0x0000, 0x0040 }
4442 rtl_csi_access_enable_2(ioaddr
);
4444 rtl_ephy_init(ioaddr
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
4446 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4448 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4450 rtl_disable_clock_request(pdev
);
4452 /* Reset tx FIFO pointer */
4453 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
4454 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
4456 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4459 static void rtl_hw_start_8168e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4461 static const struct ephy_info e_info_8168e_2
[] = {
4462 { 0x09, 0x0000, 0x0080 },
4463 { 0x19, 0x0000, 0x0224 }
4466 rtl_csi_access_enable_1(ioaddr
);
4468 rtl_ephy_init(ioaddr
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
4470 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4472 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4473 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4474 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4475 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4476 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4477 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
4478 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4479 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4482 RTL_W8(MaxTxPacketSize
, 0x27);
4484 rtl_disable_clock_request(pdev
);
4486 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4487 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4489 /* Adjust EEE LED frequency */
4490 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4492 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4493 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4494 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4497 static void rtl_hw_start_8168(struct net_device
*dev
)
4499 struct rtl8169_private
*tp
= netdev_priv(dev
);
4500 void __iomem
*ioaddr
= tp
->mmio_addr
;
4501 struct pci_dev
*pdev
= tp
->pci_dev
;
4503 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4505 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4507 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4509 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4511 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4513 RTL_W16(IntrMitigate
, 0x5151);
4515 /* Work around for RxFIFO overflow. */
4516 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
4517 tp
->mac_version
== RTL_GIGA_MAC_VER_22
) {
4518 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
4519 tp
->intr_event
&= ~RxOverflow
;
4522 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4524 rtl_set_rx_mode(dev
);
4526 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4527 (InterFrameGap
<< TxInterFrameGapShift
));
4531 switch (tp
->mac_version
) {
4532 case RTL_GIGA_MAC_VER_11
:
4533 rtl_hw_start_8168bb(ioaddr
, pdev
);
4536 case RTL_GIGA_MAC_VER_12
:
4537 case RTL_GIGA_MAC_VER_17
:
4538 rtl_hw_start_8168bef(ioaddr
, pdev
);
4541 case RTL_GIGA_MAC_VER_18
:
4542 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
4545 case RTL_GIGA_MAC_VER_19
:
4546 rtl_hw_start_8168c_1(ioaddr
, pdev
);
4549 case RTL_GIGA_MAC_VER_20
:
4550 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4553 case RTL_GIGA_MAC_VER_21
:
4554 rtl_hw_start_8168c_3(ioaddr
, pdev
);
4557 case RTL_GIGA_MAC_VER_22
:
4558 rtl_hw_start_8168c_4(ioaddr
, pdev
);
4561 case RTL_GIGA_MAC_VER_23
:
4562 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
4565 case RTL_GIGA_MAC_VER_24
:
4566 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
4569 case RTL_GIGA_MAC_VER_25
:
4570 case RTL_GIGA_MAC_VER_26
:
4571 case RTL_GIGA_MAC_VER_27
:
4572 rtl_hw_start_8168d(ioaddr
, pdev
);
4575 case RTL_GIGA_MAC_VER_28
:
4576 rtl_hw_start_8168d_4(ioaddr
, pdev
);
4579 case RTL_GIGA_MAC_VER_31
:
4580 rtl_hw_start_8168dp(ioaddr
, pdev
);
4583 case RTL_GIGA_MAC_VER_32
:
4584 case RTL_GIGA_MAC_VER_33
:
4585 rtl_hw_start_8168e_1(ioaddr
, pdev
);
4587 case RTL_GIGA_MAC_VER_34
:
4588 rtl_hw_start_8168e_2(ioaddr
, pdev
);
4592 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
4593 dev
->name
, tp
->mac_version
);
4597 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4599 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4601 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4603 RTL_W16(IntrMask
, tp
->intr_event
);
4606 #define R810X_CPCMD_QUIRK_MASK (\
4617 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4619 static const struct ephy_info e_info_8102e_1
[] = {
4620 { 0x01, 0, 0x6e65 },
4621 { 0x02, 0, 0x091f },
4622 { 0x03, 0, 0xc2f9 },
4623 { 0x06, 0, 0xafb5 },
4624 { 0x07, 0, 0x0e00 },
4625 { 0x19, 0, 0xec80 },
4626 { 0x01, 0, 0x2e65 },
4631 rtl_csi_access_enable_2(ioaddr
);
4633 RTL_W8(DBG_REG
, FIX_NAK_1
);
4635 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4638 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
4639 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4641 cfg1
= RTL_R8(Config1
);
4642 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
4643 RTL_W8(Config1
, cfg1
& ~LEDS0
);
4645 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
4648 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4650 rtl_csi_access_enable_2(ioaddr
);
4652 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4654 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
4655 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4658 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4660 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4662 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
4665 static void rtl_hw_start_8105e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4667 static const struct ephy_info e_info_8105e_1
[] = {
4668 { 0x07, 0, 0x4000 },
4669 { 0x19, 0, 0x0200 },
4670 { 0x19, 0, 0x0020 },
4671 { 0x1e, 0, 0x2000 },
4672 { 0x03, 0, 0x0001 },
4673 { 0x19, 0, 0x0100 },
4674 { 0x19, 0, 0x0004 },
4678 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4679 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
4681 /* Disable Early Tally Counter */
4682 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
4684 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
4685 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4687 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
4690 static void rtl_hw_start_8105e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4692 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4693 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
4696 static void rtl_hw_start_8101(struct net_device
*dev
)
4698 struct rtl8169_private
*tp
= netdev_priv(dev
);
4699 void __iomem
*ioaddr
= tp
->mmio_addr
;
4700 struct pci_dev
*pdev
= tp
->pci_dev
;
4702 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
4703 tp
->mac_version
== RTL_GIGA_MAC_VER_16
) {
4704 int cap
= pci_pcie_cap(pdev
);
4707 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
4708 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4712 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4714 switch (tp
->mac_version
) {
4715 case RTL_GIGA_MAC_VER_07
:
4716 rtl_hw_start_8102e_1(ioaddr
, pdev
);
4719 case RTL_GIGA_MAC_VER_08
:
4720 rtl_hw_start_8102e_3(ioaddr
, pdev
);
4723 case RTL_GIGA_MAC_VER_09
:
4724 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4727 case RTL_GIGA_MAC_VER_29
:
4728 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4730 case RTL_GIGA_MAC_VER_30
:
4731 rtl_hw_start_8105e_2(ioaddr
, pdev
);
4735 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4737 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4739 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4741 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
4742 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4744 RTL_W16(IntrMitigate
, 0x0000);
4746 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4748 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4749 rtl_set_rx_tx_config_registers(tp
);
4753 rtl_set_rx_mode(dev
);
4755 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
4757 RTL_W16(IntrMask
, tp
->intr_event
);
4760 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
4762 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
4766 netdev_update_features(dev
);
4771 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
4773 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
4774 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
4777 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
4778 void **data_buff
, struct RxDesc
*desc
)
4780 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
4785 rtl8169_make_unusable_by_asic(desc
);
4788 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
4790 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
4792 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
4795 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
4798 desc
->addr
= cpu_to_le64(mapping
);
4800 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4803 static inline void *rtl8169_align(void *data
)
4805 return (void *)ALIGN((long)data
, 16);
4808 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
4809 struct RxDesc
*desc
)
4813 struct device
*d
= &tp
->pci_dev
->dev
;
4814 struct net_device
*dev
= tp
->dev
;
4815 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
4817 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
4821 if (rtl8169_align(data
) != data
) {
4823 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
4828 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
4830 if (unlikely(dma_mapping_error(d
, mapping
))) {
4831 if (net_ratelimit())
4832 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
4836 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4844 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4848 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4849 if (tp
->Rx_databuff
[i
]) {
4850 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
4851 tp
->RxDescArray
+ i
);
4856 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4858 desc
->opts1
|= cpu_to_le32(RingEnd
);
4861 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
4865 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4868 if (tp
->Rx_databuff
[i
])
4871 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
4873 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
4876 tp
->Rx_databuff
[i
] = data
;
4879 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4883 rtl8169_rx_clear(tp
);
4887 static int rtl8169_init_ring(struct net_device
*dev
)
4889 struct rtl8169_private
*tp
= netdev_priv(dev
);
4891 rtl8169_init_ring_indexes(tp
);
4893 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4894 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
4896 return rtl8169_rx_fill(tp
);
4899 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
4900 struct TxDesc
*desc
)
4902 unsigned int len
= tx_skb
->len
;
4904 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
4912 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
4917 for (i
= 0; i
< n
; i
++) {
4918 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
4919 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4920 unsigned int len
= tx_skb
->len
;
4923 struct sk_buff
*skb
= tx_skb
->skb
;
4925 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4926 tp
->TxDescArray
+ entry
);
4928 tp
->dev
->stats
.tx_dropped
++;
4936 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4938 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
4939 tp
->cur_tx
= tp
->dirty_tx
= 0;
4942 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4944 struct rtl8169_private
*tp
= netdev_priv(dev
);
4946 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4947 schedule_delayed_work(&tp
->task
, 4);
4950 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4952 struct rtl8169_private
*tp
= netdev_priv(dev
);
4953 void __iomem
*ioaddr
= tp
->mmio_addr
;
4955 synchronize_irq(dev
->irq
);
4957 /* Wait for any pending NAPI task to complete */
4958 napi_disable(&tp
->napi
);
4960 rtl8169_irq_mask_and_ack(ioaddr
);
4962 tp
->intr_mask
= 0xffff;
4963 RTL_W16(IntrMask
, tp
->intr_event
);
4964 napi_enable(&tp
->napi
);
4967 static void rtl8169_reinit_task(struct work_struct
*work
)
4969 struct rtl8169_private
*tp
=
4970 container_of(work
, struct rtl8169_private
, task
.work
);
4971 struct net_device
*dev
= tp
->dev
;
4976 if (!netif_running(dev
))
4979 rtl8169_wait_for_quiescence(dev
);
4982 ret
= rtl8169_open(dev
);
4983 if (unlikely(ret
< 0)) {
4984 if (net_ratelimit())
4985 netif_err(tp
, drv
, dev
,
4986 "reinit failure (status = %d). Rescheduling\n",
4988 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4995 static void rtl8169_reset_task(struct work_struct
*work
)
4997 struct rtl8169_private
*tp
=
4998 container_of(work
, struct rtl8169_private
, task
.work
);
4999 struct net_device
*dev
= tp
->dev
;
5004 if (!netif_running(dev
))
5007 rtl8169_wait_for_quiescence(dev
);
5009 for (i
= 0; i
< NUM_RX_DESC
; i
++)
5010 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
5012 rtl8169_tx_clear(tp
);
5014 rtl8169_hw_reset(tp
);
5016 netif_wake_queue(dev
);
5017 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
5023 static void rtl8169_tx_timeout(struct net_device
*dev
)
5025 struct rtl8169_private
*tp
= netdev_priv(dev
);
5027 rtl8169_hw_reset(tp
);
5029 /* Let's wait a bit while any (async) irq lands on */
5030 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5033 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
5036 struct skb_shared_info
*info
= skb_shinfo(skb
);
5037 unsigned int cur_frag
, entry
;
5038 struct TxDesc
* uninitialized_var(txd
);
5039 struct device
*d
= &tp
->pci_dev
->dev
;
5042 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
5043 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
5048 entry
= (entry
+ 1) % NUM_TX_DESC
;
5050 txd
= tp
->TxDescArray
+ entry
;
5052 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
5053 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5054 if (unlikely(dma_mapping_error(d
, mapping
))) {
5055 if (net_ratelimit())
5056 netif_err(tp
, drv
, tp
->dev
,
5057 "Failed to map TX fragments DMA!\n");
5061 /* Anti gcc 2.95.3 bugware (sic) */
5062 status
= opts
[0] | len
|
5063 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5065 txd
->opts1
= cpu_to_le32(status
);
5066 txd
->opts2
= cpu_to_le32(opts
[1]);
5067 txd
->addr
= cpu_to_le64(mapping
);
5069 tp
->tx_skb
[entry
].len
= len
;
5073 tp
->tx_skb
[entry
].skb
= skb
;
5074 txd
->opts1
|= cpu_to_le32(LastFrag
);
5080 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5084 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
5085 struct sk_buff
*skb
, u32
*opts
)
5087 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
5088 u32 mss
= skb_shinfo(skb
)->gso_size
;
5089 int offset
= info
->opts_offset
;
5093 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
5094 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5095 const struct iphdr
*ip
= ip_hdr(skb
);
5097 if (ip
->protocol
== IPPROTO_TCP
)
5098 opts
[offset
] |= info
->checksum
.tcp
;
5099 else if (ip
->protocol
== IPPROTO_UDP
)
5100 opts
[offset
] |= info
->checksum
.udp
;
5106 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5107 struct net_device
*dev
)
5109 struct rtl8169_private
*tp
= netdev_priv(dev
);
5110 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
5111 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
5112 void __iomem
*ioaddr
= tp
->mmio_addr
;
5113 struct device
*d
= &tp
->pci_dev
->dev
;
5119 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
5120 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
5124 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
5127 len
= skb_headlen(skb
);
5128 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
5129 if (unlikely(dma_mapping_error(d
, mapping
))) {
5130 if (net_ratelimit())
5131 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
5135 tp
->tx_skb
[entry
].len
= len
;
5136 txd
->addr
= cpu_to_le64(mapping
);
5138 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
5141 rtl8169_tso_csum(tp
, skb
, opts
);
5143 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
5147 opts
[0] |= FirstFrag
;
5149 opts
[0] |= FirstFrag
| LastFrag
;
5150 tp
->tx_skb
[entry
].skb
= skb
;
5153 txd
->opts2
= cpu_to_le32(opts
[1]);
5157 /* Anti gcc 2.95.3 bugware (sic) */
5158 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5159 txd
->opts1
= cpu_to_le32(status
);
5161 tp
->cur_tx
+= frags
+ 1;
5165 RTL_W8(TxPoll
, NPQ
);
5167 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
5168 netif_stop_queue(dev
);
5170 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
5171 netif_wake_queue(dev
);
5174 return NETDEV_TX_OK
;
5177 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
5180 dev
->stats
.tx_dropped
++;
5181 return NETDEV_TX_OK
;
5184 netif_stop_queue(dev
);
5185 dev
->stats
.tx_dropped
++;
5186 return NETDEV_TX_BUSY
;
5189 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
5191 struct rtl8169_private
*tp
= netdev_priv(dev
);
5192 struct pci_dev
*pdev
= tp
->pci_dev
;
5193 u16 pci_status
, pci_cmd
;
5195 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
5196 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
5198 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5199 pci_cmd
, pci_status
);
5202 * The recovery sequence below admits a very elaborated explanation:
5203 * - it seems to work;
5204 * - I did not see what else could be done;
5205 * - it makes iop3xx happy.
5207 * Feel free to adjust to your needs.
5209 if (pdev
->broken_parity_status
)
5210 pci_cmd
&= ~PCI_COMMAND_PARITY
;
5212 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
5214 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
5216 pci_write_config_word(pdev
, PCI_STATUS
,
5217 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
5218 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
5219 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
5221 /* The infamous DAC f*ckup only happens at boot time */
5222 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
5223 void __iomem
*ioaddr
= tp
->mmio_addr
;
5225 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
5226 tp
->cp_cmd
&= ~PCIDAC
;
5227 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5228 dev
->features
&= ~NETIF_F_HIGHDMA
;
5231 rtl8169_hw_reset(tp
);
5233 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
5236 static void rtl8169_tx_interrupt(struct net_device
*dev
,
5237 struct rtl8169_private
*tp
,
5238 void __iomem
*ioaddr
)
5240 unsigned int dirty_tx
, tx_left
;
5242 dirty_tx
= tp
->dirty_tx
;
5244 tx_left
= tp
->cur_tx
- dirty_tx
;
5246 while (tx_left
> 0) {
5247 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
5248 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5252 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
5253 if (status
& DescOwn
)
5256 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5257 tp
->TxDescArray
+ entry
);
5258 if (status
& LastFrag
) {
5259 dev
->stats
.tx_packets
++;
5260 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
5261 dev_kfree_skb(tx_skb
->skb
);
5268 if (tp
->dirty_tx
!= dirty_tx
) {
5269 tp
->dirty_tx
= dirty_tx
;
5271 if (netif_queue_stopped(dev
) &&
5272 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
5273 netif_wake_queue(dev
);
5276 * 8168 hack: TxPoll requests are lost when the Tx packets are
5277 * too close. Let's kick an extra TxPoll request when a burst
5278 * of start_xmit activity is detected (if it is not detected,
5279 * it is slow enough). -- FR
5282 if (tp
->cur_tx
!= dirty_tx
)
5283 RTL_W8(TxPoll
, NPQ
);
5287 static inline int rtl8169_fragmented_frame(u32 status
)
5289 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
5292 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
5294 u32 status
= opts1
& RxProtoMask
;
5296 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
5297 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
5298 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5300 skb_checksum_none_assert(skb
);
5303 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
5304 struct rtl8169_private
*tp
,
5308 struct sk_buff
*skb
;
5309 struct device
*d
= &tp
->pci_dev
->dev
;
5311 data
= rtl8169_align(data
);
5312 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5314 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
5316 memcpy(skb
->data
, data
, pkt_size
);
5317 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5322 static int rtl8169_rx_interrupt(struct net_device
*dev
,
5323 struct rtl8169_private
*tp
,
5324 void __iomem
*ioaddr
, u32 budget
)
5326 unsigned int cur_rx
, rx_left
;
5329 cur_rx
= tp
->cur_rx
;
5330 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
5331 rx_left
= min(rx_left
, budget
);
5333 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
5334 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
5335 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
5339 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
5341 if (status
& DescOwn
)
5343 if (unlikely(status
& RxRES
)) {
5344 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
5346 dev
->stats
.rx_errors
++;
5347 if (status
& (RxRWT
| RxRUNT
))
5348 dev
->stats
.rx_length_errors
++;
5350 dev
->stats
.rx_crc_errors
++;
5351 if (status
& RxFOVF
) {
5352 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5353 dev
->stats
.rx_fifo_errors
++;
5355 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5357 struct sk_buff
*skb
;
5358 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
5359 int pkt_size
= (status
& 0x00001FFF) - 4;
5362 * The driver does not support incoming fragmented
5363 * frames. They are seen as a symptom of over-mtu
5366 if (unlikely(rtl8169_fragmented_frame(status
))) {
5367 dev
->stats
.rx_dropped
++;
5368 dev
->stats
.rx_length_errors
++;
5369 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5373 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
5374 tp
, pkt_size
, addr
);
5375 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5377 dev
->stats
.rx_dropped
++;
5381 rtl8169_rx_csum(skb
, status
);
5382 skb_put(skb
, pkt_size
);
5383 skb
->protocol
= eth_type_trans(skb
, dev
);
5385 rtl8169_rx_vlan_tag(desc
, skb
);
5387 napi_gro_receive(&tp
->napi
, skb
);
5389 dev
->stats
.rx_bytes
+= pkt_size
;
5390 dev
->stats
.rx_packets
++;
5393 /* Work around for AMD plateform. */
5394 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
5395 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
5401 count
= cur_rx
- tp
->cur_rx
;
5402 tp
->cur_rx
= cur_rx
;
5404 tp
->dirty_rx
+= count
;
5409 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5411 struct net_device
*dev
= dev_instance
;
5412 struct rtl8169_private
*tp
= netdev_priv(dev
);
5413 void __iomem
*ioaddr
= tp
->mmio_addr
;
5417 /* loop handling interrupts until we have no new ones or
5418 * we hit a invalid/hotplug case.
5420 status
= RTL_R16(IntrStatus
);
5421 while (status
&& status
!= 0xffff) {
5424 /* Handle all of the error cases first. These will reset
5425 * the chip, so just exit the loop.
5427 if (unlikely(!netif_running(dev
))) {
5428 rtl8169_hw_reset(tp
);
5432 if (unlikely(status
& RxFIFOOver
)) {
5433 switch (tp
->mac_version
) {
5434 /* Work around for rx fifo overflow */
5435 case RTL_GIGA_MAC_VER_11
:
5436 case RTL_GIGA_MAC_VER_22
:
5437 case RTL_GIGA_MAC_VER_26
:
5438 netif_stop_queue(dev
);
5439 rtl8169_tx_timeout(dev
);
5441 /* Testers needed. */
5442 case RTL_GIGA_MAC_VER_17
:
5443 case RTL_GIGA_MAC_VER_19
:
5444 case RTL_GIGA_MAC_VER_20
:
5445 case RTL_GIGA_MAC_VER_21
:
5446 case RTL_GIGA_MAC_VER_23
:
5447 case RTL_GIGA_MAC_VER_24
:
5448 case RTL_GIGA_MAC_VER_27
:
5449 case RTL_GIGA_MAC_VER_28
:
5450 case RTL_GIGA_MAC_VER_31
:
5451 /* Experimental science. Pktgen proof. */
5452 case RTL_GIGA_MAC_VER_12
:
5453 case RTL_GIGA_MAC_VER_25
:
5454 if (status
== RxFIFOOver
)
5462 if (unlikely(status
& SYSErr
)) {
5463 rtl8169_pcierr_interrupt(dev
);
5467 if (status
& LinkChg
)
5468 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
5470 /* We need to see the lastest version of tp->intr_mask to
5471 * avoid ignoring an MSI interrupt and having to wait for
5472 * another event which may never come.
5475 if (status
& tp
->intr_mask
& tp
->napi_event
) {
5476 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
5477 tp
->intr_mask
= ~tp
->napi_event
;
5479 if (likely(napi_schedule_prep(&tp
->napi
)))
5480 __napi_schedule(&tp
->napi
);
5482 netif_info(tp
, intr
, dev
,
5483 "interrupt %04x in poll\n", status
);
5486 /* We only get a new MSI interrupt when all active irq
5487 * sources on the chip have been acknowledged. So, ack
5488 * everything we've seen and check if new sources have become
5489 * active to avoid blocking all interrupts from the chip.
5492 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
5493 status
= RTL_R16(IntrStatus
);
5496 return IRQ_RETVAL(handled
);
5499 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5501 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5502 struct net_device
*dev
= tp
->dev
;
5503 void __iomem
*ioaddr
= tp
->mmio_addr
;
5506 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
5507 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
5509 if (work_done
< budget
) {
5510 napi_complete(napi
);
5512 /* We need for force the visibility of tp->intr_mask
5513 * for other CPUs, as we can loose an MSI interrupt
5514 * and potentially wait for a retransmit timeout if we don't.
5515 * The posted write to IntrMask is safe, as it will
5516 * eventually make it to the chip and we won't loose anything
5519 tp
->intr_mask
= 0xffff;
5521 RTL_W16(IntrMask
, tp
->intr_event
);
5527 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5529 struct rtl8169_private
*tp
= netdev_priv(dev
);
5531 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5534 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5535 RTL_W32(RxMissed
, 0);
5538 static void rtl8169_down(struct net_device
*dev
)
5540 struct rtl8169_private
*tp
= netdev_priv(dev
);
5541 void __iomem
*ioaddr
= tp
->mmio_addr
;
5543 del_timer_sync(&tp
->timer
);
5545 netif_stop_queue(dev
);
5547 napi_disable(&tp
->napi
);
5549 spin_lock_irq(&tp
->lock
);
5551 rtl8169_hw_reset(tp
);
5553 * At this point device interrupts can not be enabled in any function,
5554 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5555 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5557 rtl8169_rx_missed(dev
, ioaddr
);
5559 spin_unlock_irq(&tp
->lock
);
5561 synchronize_irq(dev
->irq
);
5563 /* Give a racing hard_start_xmit a few cycles to complete. */
5564 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5566 rtl8169_tx_clear(tp
);
5568 rtl8169_rx_clear(tp
);
5570 rtl_pll_power_down(tp
);
5573 static int rtl8169_close(struct net_device
*dev
)
5575 struct rtl8169_private
*tp
= netdev_priv(dev
);
5576 struct pci_dev
*pdev
= tp
->pci_dev
;
5578 pm_runtime_get_sync(&pdev
->dev
);
5580 /* Update counters before going down */
5581 rtl8169_update_counters(dev
);
5585 free_irq(dev
->irq
, dev
);
5587 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5589 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5591 tp
->TxDescArray
= NULL
;
5592 tp
->RxDescArray
= NULL
;
5594 pm_runtime_put_sync(&pdev
->dev
);
5599 static void rtl_set_rx_mode(struct net_device
*dev
)
5601 struct rtl8169_private
*tp
= netdev_priv(dev
);
5602 void __iomem
*ioaddr
= tp
->mmio_addr
;
5603 unsigned long flags
;
5604 u32 mc_filter
[2]; /* Multicast hash filter */
5608 if (dev
->flags
& IFF_PROMISC
) {
5609 /* Unconditionally log net taps. */
5610 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5612 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5614 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5615 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5616 (dev
->flags
& IFF_ALLMULTI
)) {
5617 /* Too many to filter perfectly -- accept all multicasts. */
5618 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5619 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5621 struct netdev_hw_addr
*ha
;
5623 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5624 mc_filter
[1] = mc_filter
[0] = 0;
5625 netdev_for_each_mc_addr(ha
, dev
) {
5626 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5627 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
5628 rx_mode
|= AcceptMulticast
;
5632 spin_lock_irqsave(&tp
->lock
, flags
);
5634 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
5636 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
5637 u32 data
= mc_filter
[0];
5639 mc_filter
[0] = swab32(mc_filter
[1]);
5640 mc_filter
[1] = swab32(data
);
5643 RTL_W32(MAR0
+ 4, mc_filter
[1]);
5644 RTL_W32(MAR0
+ 0, mc_filter
[0]);
5646 RTL_W32(RxConfig
, tmp
);
5648 spin_unlock_irqrestore(&tp
->lock
, flags
);
5652 * rtl8169_get_stats - Get rtl8169 read/write statistics
5653 * @dev: The Ethernet Device to get statistics for
5655 * Get TX/RX statistics for rtl8169
5657 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
5659 struct rtl8169_private
*tp
= netdev_priv(dev
);
5660 void __iomem
*ioaddr
= tp
->mmio_addr
;
5661 unsigned long flags
;
5663 if (netif_running(dev
)) {
5664 spin_lock_irqsave(&tp
->lock
, flags
);
5665 rtl8169_rx_missed(dev
, ioaddr
);
5666 spin_unlock_irqrestore(&tp
->lock
, flags
);
5672 static void rtl8169_net_suspend(struct net_device
*dev
)
5674 struct rtl8169_private
*tp
= netdev_priv(dev
);
5676 if (!netif_running(dev
))
5679 rtl_pll_power_down(tp
);
5681 netif_device_detach(dev
);
5682 netif_stop_queue(dev
);
5687 static int rtl8169_suspend(struct device
*device
)
5689 struct pci_dev
*pdev
= to_pci_dev(device
);
5690 struct net_device
*dev
= pci_get_drvdata(pdev
);
5692 rtl8169_net_suspend(dev
);
5697 static void __rtl8169_resume(struct net_device
*dev
)
5699 struct rtl8169_private
*tp
= netdev_priv(dev
);
5701 netif_device_attach(dev
);
5703 rtl_pll_power_up(tp
);
5705 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5708 static int rtl8169_resume(struct device
*device
)
5710 struct pci_dev
*pdev
= to_pci_dev(device
);
5711 struct net_device
*dev
= pci_get_drvdata(pdev
);
5712 struct rtl8169_private
*tp
= netdev_priv(dev
);
5714 rtl8169_init_phy(dev
, tp
);
5716 if (netif_running(dev
))
5717 __rtl8169_resume(dev
);
5722 static int rtl8169_runtime_suspend(struct device
*device
)
5724 struct pci_dev
*pdev
= to_pci_dev(device
);
5725 struct net_device
*dev
= pci_get_drvdata(pdev
);
5726 struct rtl8169_private
*tp
= netdev_priv(dev
);
5728 if (!tp
->TxDescArray
)
5731 spin_lock_irq(&tp
->lock
);
5732 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
5733 __rtl8169_set_wol(tp
, WAKE_ANY
);
5734 spin_unlock_irq(&tp
->lock
);
5736 rtl8169_net_suspend(dev
);
5741 static int rtl8169_runtime_resume(struct device
*device
)
5743 struct pci_dev
*pdev
= to_pci_dev(device
);
5744 struct net_device
*dev
= pci_get_drvdata(pdev
);
5745 struct rtl8169_private
*tp
= netdev_priv(dev
);
5747 if (!tp
->TxDescArray
)
5750 spin_lock_irq(&tp
->lock
);
5751 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
5752 tp
->saved_wolopts
= 0;
5753 spin_unlock_irq(&tp
->lock
);
5755 rtl8169_init_phy(dev
, tp
);
5757 __rtl8169_resume(dev
);
5762 static int rtl8169_runtime_idle(struct device
*device
)
5764 struct pci_dev
*pdev
= to_pci_dev(device
);
5765 struct net_device
*dev
= pci_get_drvdata(pdev
);
5766 struct rtl8169_private
*tp
= netdev_priv(dev
);
5768 return tp
->TxDescArray
? -EBUSY
: 0;
5771 static const struct dev_pm_ops rtl8169_pm_ops
= {
5772 .suspend
= rtl8169_suspend
,
5773 .resume
= rtl8169_resume
,
5774 .freeze
= rtl8169_suspend
,
5775 .thaw
= rtl8169_resume
,
5776 .poweroff
= rtl8169_suspend
,
5777 .restore
= rtl8169_resume
,
5778 .runtime_suspend
= rtl8169_runtime_suspend
,
5779 .runtime_resume
= rtl8169_runtime_resume
,
5780 .runtime_idle
= rtl8169_runtime_idle
,
5783 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5785 #else /* !CONFIG_PM */
5787 #define RTL8169_PM_OPS NULL
5789 #endif /* !CONFIG_PM */
5791 static void rtl_shutdown(struct pci_dev
*pdev
)
5793 struct net_device
*dev
= pci_get_drvdata(pdev
);
5794 struct rtl8169_private
*tp
= netdev_priv(dev
);
5795 void __iomem
*ioaddr
= tp
->mmio_addr
;
5797 rtl8169_net_suspend(dev
);
5799 /* Restore original MAC address */
5800 rtl_rar_set(tp
, dev
->perm_addr
);
5802 spin_lock_irq(&tp
->lock
);
5804 rtl8169_hw_reset(tp
);
5806 spin_unlock_irq(&tp
->lock
);
5808 if (system_state
== SYSTEM_POWER_OFF
) {
5809 /* WoL fails with 8168b when the receiver is disabled. */
5810 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
5811 tp
->mac_version
== RTL_GIGA_MAC_VER_12
||
5812 tp
->mac_version
== RTL_GIGA_MAC_VER_17
) &&
5813 (tp
->features
& RTL_FEATURE_WOL
)) {
5814 pci_clear_master(pdev
);
5816 RTL_W8(ChipCmd
, CmdRxEnb
);
5821 pci_wake_from_d3(pdev
, true);
5822 pci_set_power_state(pdev
, PCI_D3hot
);
5826 static struct pci_driver rtl8169_pci_driver
= {
5828 .id_table
= rtl8169_pci_tbl
,
5829 .probe
= rtl8169_init_one
,
5830 .remove
= __devexit_p(rtl8169_remove_one
),
5831 .shutdown
= rtl_shutdown
,
5832 .driver
.pm
= RTL8169_PM_OPS
,
5835 static int __init
rtl8169_init_module(void)
5837 return pci_register_driver(&rtl8169_pci_driver
);
5840 static void __exit
rtl8169_cleanup_module(void)
5842 pci_unregister_driver(&rtl8169_pci_driver
);
5845 module_init(rtl8169_init_module
);
5846 module_exit(rtl8169_cleanup_module
);