drivers/scsi/qla4xxx/ql4_def.h

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2010 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7
   8 #ifndef __QL4_DEF_H
   9 #define __QL4_DEF_H
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/module.h>
  15 #include <linux/list.h>
  16 #include <linux/pci.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/sched.h>
  19 #include <linux/slab.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/mempool.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/mutex.h>
  27 #include <linux/aer.h>
  28 #include <linux/bsg-lib.h>
  29
  30 #include <net/tcp.h>
  31 #include <scsi/scsi.h>
  32 #include <scsi/scsi_host.h>
  33 #include <scsi/scsi_device.h>
  34 #include <scsi/scsi_cmnd.h>
  35 #include <scsi/scsi_transport.h>
  36 #include <scsi/scsi_transport_iscsi.h>
  37 #include <scsi/scsi_bsg_iscsi.h>
  38 #include <scsi/scsi_netlink.h>
  39 #include <scsi/libiscsi.h>
  40
  41 #include "ql4_dbg.h"
  42 #include "ql4_nx.h"
  43 #include "ql4_fw.h"
  44 #include "ql4_nvram.h"
  45
  46 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
  47 #define PCI_DEVICE_ID_QLOGIC_ISP4010    0x4010
  48 #endif
  49
  50 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
  51 #define PCI_DEVICE_ID_QLOGIC_ISP4022    0x4022
  52 #endif
  53
  54 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
  55 #define PCI_DEVICE_ID_QLOGIC_ISP4032    0x4032
  56 #endif
  57
  58 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
  59 #define PCI_DEVICE_ID_QLOGIC_ISP8022    0x8022
  60 #endif
  61
  62 #define ISP4XXX_PCI_FN_1        0x1
  63 #define ISP4XXX_PCI_FN_2        0x3
  64
  65 #define QLA_SUCCESS                     0
  66 #define QLA_ERROR                       1
  67
  68 /*
  69  * Data bit definitions
  70  */
  71 #define BIT_0   0x1
  72 #define BIT_1   0x2
  73 #define BIT_2   0x4
  74 #define BIT_3   0x8
  75 #define BIT_4   0x10
  76 #define BIT_5   0x20
  77 #define BIT_6   0x40
  78 #define BIT_7   0x80
  79 #define BIT_8   0x100
  80 #define BIT_9   0x200
  81 #define BIT_10  0x400
  82 #define BIT_11  0x800
  83 #define BIT_12  0x1000
  84 #define BIT_13  0x2000
  85 #define BIT_14  0x4000
  86 #define BIT_15  0x8000
  87 #define BIT_16  0x10000
  88 #define BIT_17  0x20000
  89 #define BIT_18  0x40000
  90 #define BIT_19  0x80000
  91 #define BIT_20  0x100000
  92 #define BIT_21  0x200000
  93 #define BIT_22  0x400000
  94 #define BIT_23  0x800000
  95 #define BIT_24  0x1000000
  96 #define BIT_25  0x2000000
  97 #define BIT_26  0x4000000
  98 #define BIT_27  0x8000000
  99 #define BIT_28  0x10000000
 100 #define BIT_29  0x20000000
 101 #define BIT_30  0x40000000
 102 #define BIT_31  0x80000000
 103
 104 /**
 105  * Macros to help code, maintain, etc.
 106  **/
 107 #define ql4_printk(level, ha, format, arg...) \
 108         dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
 109
 110
 111 /*
 112  * Host adapter default definitions
 113  ***********************************/
 114 #define MAX_HBAS                16
 115 #define MAX_BUSES               1
 116 #define MAX_TARGETS             MAX_DEV_DB_ENTRIES
 117 #define MAX_LUNS                0xffff
 118 #define MAX_AEN_ENTRIES         MAX_DEV_DB_ENTRIES
 119 #define MAX_DDB_ENTRIES         MAX_DEV_DB_ENTRIES
 120 #define MAX_PDU_ENTRIES         32
 121 #define INVALID_ENTRY           0xFFFF
 122 #define MAX_CMDS_TO_RISC        1024
 123 #define MAX_SRBS                MAX_CMDS_TO_RISC
 124 #define MBOX_AEN_REG_COUNT      8
 125 #define MAX_INIT_RETRIES        5
 126
 127 /*
 128  * Buffer sizes
 129  */
 130 #define REQUEST_QUEUE_DEPTH             MAX_CMDS_TO_RISC
 131 #define RESPONSE_QUEUE_DEPTH            64
 132 #define QUEUE_SIZE                      64
 133 #define DMA_BUFFER_SIZE                 512
 134
 135 /*
 136  * Misc
 137  */
 138 #define MAC_ADDR_LEN                    6       /* in bytes */
 139 #define IP_ADDR_LEN                     4       /* in bytes */
 140 #define IPv6_ADDR_LEN                   16      /* IPv6 address size */
 141 #define DRIVER_NAME                     "qla4xxx"
 142
 143 #define MAX_LINKED_CMDS_PER_LUN         3
 144 #define MAX_REQS_SERVICED_PER_INTR      1
 145
 146 #define ISCSI_IPADDR_SIZE               4       /* IP address size */
 147 #define ISCSI_ALIAS_SIZE                32      /* ISCSI Alias name size */
 148 #define ISCSI_NAME_SIZE                 0xE0    /* ISCSI Name size */
 149
 150 #define QL4_SESS_RECOVERY_TMO           30      /* iSCSI session */
 151                                                 /* recovery timeout */
 152
 153 #define LSDW(x) ((u32)((u64)(x)))
 154 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
 155
 156 /*
 157  * Retry & Timeout Values
 158  */
 159 #define MBOX_TOV                        60
 160 #define SOFT_RESET_TOV                  30
 161 #define RESET_INTR_TOV                  3
 162 #define SEMAPHORE_TOV                   10
 163 #define ADAPTER_INIT_TOV                30
 164 #define ADAPTER_RESET_TOV               180
 165 #define EXTEND_CMD_TOV                  60
 166 #define WAIT_CMD_TOV                    30
 167 #define EH_WAIT_CMD_TOV                 120
 168 #define FIRMWARE_UP_TOV                 60
 169 #define RESET_FIRMWARE_TOV              30
 170 #define LOGOUT_TOV                      10
 171 #define IOCB_TOV_MARGIN                 10
 172 #define RELOGIN_TOV                     18
 173 #define ISNS_DEREG_TOV                  5
 174 #define HBA_ONLINE_TOV                  30
 175
 176 #define MAX_RESET_HA_RETRIES            2
 177
 178 #define CMD_SP(Cmnd)                    ((Cmnd)->SCp.ptr)
 179
 180 /*
 181  * SCSI Request Block structure  (srb)  that is placed
 182  * on cmd->SCp location of every I/O     [We have 22 bytes available]
 183  */
 184 struct srb {
 185         struct list_head list;  /* (8)   */
 186         struct scsi_qla_host *ha;       /* HA the SP is queued on */
 187         struct ddb_entry *ddb;
 188         uint16_t flags;         /* (1) Status flags. */
 189
 190 #define SRB_DMA_VALID           BIT_3   /* DMA Buffer mapped. */
 191 #define SRB_GOT_SENSE           BIT_4   /* sense data received. */
 192         uint8_t state;          /* (1) Status flags. */
 193
 194 #define SRB_NO_QUEUE_STATE       0      /* Request is in between states */
 195 #define SRB_FREE_STATE           1
 196 #define SRB_ACTIVE_STATE         3
 197 #define SRB_ACTIVE_TIMEOUT_STATE 4
 198 #define SRB_SUSPENDED_STATE      7      /* Request in suspended state */
 199
 200         struct scsi_cmnd *cmd;  /* (4) SCSI command block */
 201         dma_addr_t dma_handle;  /* (4) for unmap of single transfers */
 202         struct kref srb_ref;    /* reference count for this srb */
 203         uint8_t err_id;         /* error id */
 204 #define SRB_ERR_PORT       1    /* Request failed because "port down" */
 205 #define SRB_ERR_LOOP       2    /* Request failed because "loop down" */
 206 #define SRB_ERR_DEVICE     3    /* Request failed because "device error" */
 207 #define SRB_ERR_OTHER      4
 208
 209         uint16_t reserved;
 210         uint16_t iocb_tov;
 211         uint16_t iocb_cnt;      /* Number of used iocbs */
 212         uint16_t cc_stat;
 213
 214         /* Used for extended sense / status continuation */
 215         uint8_t *req_sense_ptr;
 216         uint16_t req_sense_len;
 217         uint16_t reserved2;
 218 };
 219
 220 /*
 221  * Asynchronous Event Queue structure
 222  */
 223 struct aen {
 224         uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
 225 };
 226
 227 struct ql4_aen_log {
 228         int count;
 229         struct aen entry[MAX_AEN_ENTRIES];
 230 };
 231
 232 /*
 233  * Device Database (DDB) structure
 234  */
 235 struct ddb_entry {
 236         struct scsi_qla_host *ha;
 237         struct iscsi_cls_session *sess;
 238         struct iscsi_cls_conn *conn;
 239
 240         uint16_t fw_ddb_index;  /* DDB firmware index */
 241         uint32_t fw_ddb_device_state; /* F/W Device State  -- see ql4_fw.h */
 242 };
 243
 244 /*
 245  * DDB states.
 246  */
 247 #define DDB_STATE_DEAD          0       /* We can no longer talk to
 248                                          * this device */
 249 #define DDB_STATE_ONLINE        1       /* Device ready to accept
 250                                          * commands */
 251 #define DDB_STATE_MISSING       2       /* Device logged off, trying
 252                                          * to re-login */
 253
 254 /*
 255  * DDB flags.
 256  */
 257 #define DF_RELOGIN              0       /* Relogin to device */
 258 #define DF_ISNS_DISCOVERED      2       /* Device was discovered via iSNS */
 259 #define DF_FO_MASKED            3
 260
 261
 262
 263 struct ql82xx_hw_data {
 264         /* Offsets for flash/nvram access (set to ~0 if not used). */
 265         uint32_t flash_conf_off;
 266         uint32_t flash_data_off;
 267
 268         uint32_t fdt_wrt_disable;
 269         uint32_t fdt_erase_cmd;
 270         uint32_t fdt_block_size;
 271         uint32_t fdt_unprotect_sec_cmd;
 272         uint32_t fdt_protect_sec_cmd;
 273
 274         uint32_t flt_region_flt;
 275         uint32_t flt_region_fdt;
 276         uint32_t flt_region_boot;
 277         uint32_t flt_region_bootload;
 278         uint32_t flt_region_fw;
 279
 280         uint32_t flt_iscsi_param;
 281         uint32_t reserved;
 282 };
 283
 284 struct qla4_8xxx_legacy_intr_set {
 285         uint32_t int_vec_bit;
 286         uint32_t tgt_status_reg;
 287         uint32_t tgt_mask_reg;
 288         uint32_t pci_int_reg;
 289 };
 290
 291 /* MSI-X Support */
 292
 293 #define QLA_MSIX_DEFAULT        0x00
 294 #define QLA_MSIX_RSP_Q          0x01
 295
 296 #define QLA_MSIX_ENTRIES        2
 297 #define QLA_MIDX_DEFAULT        0
 298 #define QLA_MIDX_RSP_Q          1
 299
 300 struct ql4_msix_entry {
 301         int have_irq;
 302         uint16_t msix_vector;
 303         uint16_t msix_entry;
 304 };
 305
 306 /*
 307  * ISP Operations
 308  */
 309 struct isp_operations {
 310         int (*iospace_config) (struct scsi_qla_host *ha);
 311         void (*pci_config) (struct scsi_qla_host *);
 312         void (*disable_intrs) (struct scsi_qla_host *);
 313         void (*enable_intrs) (struct scsi_qla_host *);
 314         int (*start_firmware) (struct scsi_qla_host *);
 315         irqreturn_t (*intr_handler) (int , void *);
 316         void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
 317         int (*reset_chip) (struct scsi_qla_host *);
 318         int (*reset_firmware) (struct scsi_qla_host *);
 319         void (*queue_iocb) (struct scsi_qla_host *);
 320         void (*complete_iocb) (struct scsi_qla_host *);
 321         uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
 322         uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
 323         int (*get_sys_info) (struct scsi_qla_host *);
 324 };
 325
 326 /*qla4xxx ipaddress configuration details */
 327 struct ipaddress_config {
 328         uint16_t ipv4_options;
 329         uint16_t tcp_options;
 330         uint16_t ipv4_vlan_tag;
 331         uint8_t ipv4_addr_state;
 332         uint8_t ip_address[IP_ADDR_LEN];
 333         uint8_t subnet_mask[IP_ADDR_LEN];
 334         uint8_t gateway[IP_ADDR_LEN];
 335         uint32_t ipv6_options;
 336         uint32_t ipv6_addl_options;
 337         uint8_t ipv6_link_local_state;
 338         uint8_t ipv6_addr0_state;
 339         uint8_t ipv6_addr1_state;
 340         uint8_t ipv6_default_router_state;
 341         uint16_t ipv6_vlan_tag;
 342         struct in6_addr ipv6_link_local_addr;
 343         struct in6_addr ipv6_addr0;
 344         struct in6_addr ipv6_addr1;
 345         struct in6_addr ipv6_default_router_addr;
 346         uint16_t eth_mtu_size;
 347         uint16_t ipv4_port;
 348         uint16_t ipv6_port;
 349 };
 350
 351 #define QL4_CHAP_MAX_NAME_LEN 256
 352 #define QL4_CHAP_MAX_SECRET_LEN 100
 353
 354 struct ql4_chap_format {
 355         u8  intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
 356         u8  intr_secret[QL4_CHAP_MAX_SECRET_LEN];
 357         u8  target_chap_name[QL4_CHAP_MAX_NAME_LEN];
 358         u8  target_secret[QL4_CHAP_MAX_SECRET_LEN];
 359         u16 intr_chap_name_length;
 360         u16 intr_secret_length;
 361         u16 target_chap_name_length;
 362         u16 target_secret_length;
 363 };
 364
 365 struct ip_address_format {
 366         u8 ip_type;
 367         u8 ip_address[16];
 368 };
 369
 370 struct  ql4_conn_info {
 371         u16     dest_port;
 372         struct  ip_address_format dest_ipaddr;
 373         struct  ql4_chap_format chap;
 374 };
 375
 376 struct ql4_boot_session_info {
 377         u8      target_name[224];
 378         struct  ql4_conn_info conn_list[1];
 379 };
 380
 381 struct ql4_boot_tgt_info {
 382         struct ql4_boot_session_info boot_pri_sess;
 383         struct ql4_boot_session_info boot_sec_sess;
 384 };
 385
 386 /*
 387  * Linux Host Adapter structure
 388  */
 389 struct scsi_qla_host {
 390         /* Linux adapter configuration data */
 391         unsigned long flags;
 392
 393 #define AF_ONLINE                       0 /* 0x00000001 */
 394 #define AF_INIT_DONE                    1 /* 0x00000002 */
 395 #define AF_MBOX_COMMAND                 2 /* 0x00000004 */
 396 #define AF_MBOX_COMMAND_DONE            3 /* 0x00000008 */
 397 #define AF_INTERRUPTS_ON                6 /* 0x00000040 */
 398 #define AF_GET_CRASH_RECORD             7 /* 0x00000080 */
 399 #define AF_LINK_UP                      8 /* 0x00000100 */
 400 #define AF_IRQ_ATTACHED                 10 /* 0x00000400 */
 401 #define AF_DISABLE_ACB_COMPLETE         11 /* 0x00000800 */
 402 #define AF_HA_REMOVAL                   12 /* 0x00001000 */
 403 #define AF_INTx_ENABLED                 15 /* 0x00008000 */
 404 #define AF_MSI_ENABLED                  16 /* 0x00010000 */
 405 #define AF_MSIX_ENABLED                 17 /* 0x00020000 */
 406 #define AF_MBOX_COMMAND_NOPOLL          18 /* 0x00040000 */
 407 #define AF_FW_RECOVERY                  19 /* 0x00080000 */
 408 #define AF_EEH_BUSY                     20 /* 0x00100000 */
 409 #define AF_PCI_CHANNEL_IO_PERM_FAILURE  21 /* 0x00200000 */
 410
 411         unsigned long dpc_flags;
 412
 413 #define DPC_RESET_HA                    1 /* 0x00000002 */
 414 #define DPC_RETRY_RESET_HA              2 /* 0x00000004 */
 415 #define DPC_RELOGIN_DEVICE              3 /* 0x00000008 */
 416 #define DPC_RESET_HA_FW_CONTEXT         4 /* 0x00000010 */
 417 #define DPC_RESET_HA_INTR               5 /* 0x00000020 */
 418 #define DPC_ISNS_RESTART                7 /* 0x00000080 */
 419 #define DPC_AEN                         9 /* 0x00000200 */
 420 #define DPC_GET_DHCP_IP_ADDR            15 /* 0x00008000 */
 421 #define DPC_LINK_CHANGED                18 /* 0x00040000 */
 422 #define DPC_RESET_ACTIVE                20 /* 0x00040000 */
 423 #define DPC_HA_UNRECOVERABLE            21 /* 0x00080000 ISP-82xx only*/
 424 #define DPC_HA_NEED_QUIESCENT           22 /* 0x00100000 ISP-82xx only*/
 425
 426
 427         struct Scsi_Host *host; /* pointer to host data */
 428         uint32_t tot_ddbs;
 429
 430         uint16_t iocb_cnt;
 431
 432         /* SRB cache. */
 433 #define SRB_MIN_REQ     128
 434         mempool_t *srb_mempool;
 435
 436         /* pci information */
 437         struct pci_dev *pdev;
 438
 439         struct isp_reg __iomem *reg; /* Base I/O address */
 440         unsigned long pio_address;
 441         unsigned long pio_length;
 442 #define MIN_IOBASE_LEN          0x100
 443
 444         uint16_t req_q_count;
 445
 446         unsigned long host_no;
 447
 448         /* NVRAM registers */
 449         struct eeprom_data *nvram;
 450         spinlock_t hardware_lock ____cacheline_aligned;
 451         uint32_t eeprom_cmd_data;
 452
 453         /* Counters for general statistics */
 454         uint64_t isr_count;
 455         uint64_t adapter_error_count;
 456         uint64_t device_error_count;
 457         uint64_t total_io_count;
 458         uint64_t total_mbytes_xferred;
 459         uint64_t link_failure_count;
 460         uint64_t invalid_crc_count;
 461         uint32_t bytes_xfered;
 462         uint32_t spurious_int_count;
 463         uint32_t aborted_io_count;
 464         uint32_t io_timeout_count;
 465         uint32_t mailbox_timeout_count;
 466         uint32_t seconds_since_last_intr;
 467         uint32_t seconds_since_last_heartbeat;
 468         uint32_t mac_index;
 469
 470         /* Info Needed for Management App */
 471         /* --- From GetFwVersion --- */
 472         uint32_t firmware_version[2];
 473         uint32_t patch_number;
 474         uint32_t build_number;
 475         uint32_t board_id;
 476
 477         /* --- From Init_FW --- */
 478         /* init_cb_t *init_cb; */
 479         uint16_t firmware_options;
 480         uint8_t alias[32];
 481         uint8_t name_string[256];
 482         uint8_t heartbeat_interval;
 483
 484         /* --- From FlashSysInfo --- */
 485         uint8_t my_mac[MAC_ADDR_LEN];
 486         uint8_t serial_number[16];
 487         uint16_t port_num;
 488         /* --- From GetFwState --- */
 489         uint32_t firmware_state;
 490         uint32_t addl_fw_state;
 491
 492         /* Linux kernel thread */
 493         struct workqueue_struct *dpc_thread;
 494         struct work_struct dpc_work;
 495
 496         /* Linux timer thread */
 497         struct timer_list timer;
 498         uint32_t timer_active;
 499
 500         /* Recovery Timers */
 501         atomic_t check_relogin_timeouts;
 502         uint32_t retry_reset_ha_cnt;
 503         uint32_t isp_reset_timer;       /* reset test timer */
 504         uint32_t nic_reset_timer;       /* simulated nic reset test timer */
 505         int eh_start;
 506         struct list_head free_srb_q;
 507         uint16_t free_srb_q_count;
 508         uint16_t num_srbs_allocated;
 509
 510         /* DMA Memory Block */
 511         void *queues;
 512         dma_addr_t queues_dma;
 513         unsigned long queues_len;
 514
 515 #define MEM_ALIGN_VALUE \
 516             ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
 517              sizeof(struct queue_entry))
 518         /* request and response queue variables */
 519         dma_addr_t request_dma;
 520         struct queue_entry *request_ring;
 521         struct queue_entry *request_ptr;
 522         dma_addr_t response_dma;
 523         struct queue_entry *response_ring;
 524         struct queue_entry *response_ptr;
 525         dma_addr_t shadow_regs_dma;
 526         struct shadow_regs *shadow_regs;
 527         uint16_t request_in;    /* Current indexes. */
 528         uint16_t request_out;
 529         uint16_t response_in;
 530         uint16_t response_out;
 531
 532         /* aen queue variables */
 533         uint16_t aen_q_count;   /* Number of available aen_q entries */
 534         uint16_t aen_in;        /* Current indexes */
 535         uint16_t aen_out;
 536         struct aen aen_q[MAX_AEN_ENTRIES];
 537
 538         struct ql4_aen_log aen_log;/* tracks all aens */
 539
 540         /* This mutex protects several threads to do mailbox commands
 541          * concurrently.
 542          */
 543         struct mutex  mbox_sem;
 544
 545         /* temporary mailbox status registers */
 546         volatile uint8_t mbox_status_count;
 547         volatile uint32_t mbox_status[MBOX_REG_COUNT];
 548
 549         /* FW ddb index map */
 550         struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
 551
 552         /* Saved srb for status continuation entry processing */
 553         struct srb *status_srb;
 554
 555         uint8_t acb_version;
 556
 557         /* qla82xx specific fields */
 558         struct device_reg_82xx  __iomem *qla4_8xxx_reg; /* Base I/O address */
 559         unsigned long nx_pcibase;       /* Base I/O address */
 560         uint8_t *nx_db_rd_ptr;          /* Doorbell read pointer */
 561         unsigned long nx_db_wr_ptr;     /* Door bell write pointer */
 562         unsigned long first_page_group_start;
 563         unsigned long first_page_group_end;
 564
 565         uint32_t crb_win;
 566         uint32_t curr_window;
 567         uint32_t ddr_mn_window;
 568         unsigned long mn_win_crb;
 569         unsigned long ms_win_crb;
 570         int qdr_sn_window;
 571         rwlock_t hw_lock;
 572         uint16_t func_num;
 573         int link_width;
 574
 575         struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
 576         u32 nx_crb_mask;
 577
 578         uint8_t revision_id;
 579         uint32_t fw_heartbeat_counter;
 580
 581         struct isp_operations *isp_ops;
 582         struct ql82xx_hw_data hw;
 583
 584         struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
 585
 586         uint32_t nx_dev_init_timeout;
 587         uint32_t nx_reset_timeout;
 588
 589         struct completion mbx_intr_comp;
 590
 591         struct ipaddress_config ip_config;
 592         struct iscsi_iface *iface_ipv4;
 593         struct iscsi_iface *iface_ipv6_0;
 594         struct iscsi_iface *iface_ipv6_1;
 595
 596         /* --- From About Firmware --- */
 597         uint16_t iscsi_major;
 598         uint16_t iscsi_minor;
 599         uint16_t bootload_major;
 600         uint16_t bootload_minor;
 601         uint16_t bootload_patch;
 602         uint16_t bootload_build;
 603
 604         uint32_t flash_state;
 605 #define QLFLASH_WAITING         0
 606 #define QLFLASH_READING         1
 607 #define QLFLASH_WRITING         2
 608         struct dma_pool *chap_dma_pool;
 609 #define CHAP_DMA_BLOCK_SIZE    512
 610         struct workqueue_struct *task_wq;
 611         unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
 612 #define SYSFS_FLAG_FW_SEL_BOOT 2
 613         struct iscsi_boot_kset *boot_kset;
 614         struct ql4_boot_tgt_info boot_tgt;
 615         uint16_t phy_port_num;
 616         uint16_t phy_port_cnt;
 617         uint16_t iscsi_pci_func_cnt;
 618         uint8_t model_name[16];
 619 };
 620
 621 struct ql4_task_data {
 622         struct scsi_qla_host *ha;
 623         uint8_t iocb_req_cnt;
 624         dma_addr_t data_dma;
 625         void *req_buffer;
 626         dma_addr_t req_dma;
 627         void *resp_buffer;
 628         dma_addr_t resp_dma;
 629         uint32_t resp_len;
 630         struct iscsi_task *task;
 631         struct passthru_status sts;
 632         struct work_struct task_work;
 633 };
 634
 635 struct qla_endpoint {
 636         struct Scsi_Host *host;
 637         struct sockaddr dst_addr;
 638 };
 639
 640 struct qla_conn {
 641         struct qla_endpoint *qla_ep;
 642 };
 643
 644 static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
 645 {
 646         return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
 647 }
 648
 649 static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
 650 {
 651         return ((ha->ip_config.ipv6_options &
 652                 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
 653 }
 654
 655 static inline int is_qla4010(struct scsi_qla_host *ha)
 656 {
 657         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
 658 }
 659
 660 static inline int is_qla4022(struct scsi_qla_host *ha)
 661 {
 662         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
 663 }
 664
 665 static inline int is_qla4032(struct scsi_qla_host *ha)
 666 {
 667         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
 668 }
 669
 670 static inline int is_qla8022(struct scsi_qla_host *ha)
 671 {
 672         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
 673 }
 674
 675 /* Note: Currently AER/EEH is now supported only for 8022 cards
 676  * This function needs to be updated when AER/EEH is enabled
 677  * for other cards.
 678  */
 679 static inline int is_aer_supported(struct scsi_qla_host *ha)
 680 {
 681         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
 682 }
 683
 684 static inline int adapter_up(struct scsi_qla_host *ha)
 685 {
 686         return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
 687                 (test_bit(AF_LINK_UP, &ha->flags) != 0);
 688 }
 689
 690 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
 691 {
 692         return (struct scsi_qla_host *)iscsi_host_priv(shost);
 693 }
 694
 695 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
 696 {
 697         return (is_qla4010(ha) ?
 698                 &ha->reg->u1.isp4010.nvram :
 699                 &ha->reg->u1.isp4022.semaphore);
 700 }
 701
 702 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
 703 {
 704         return (is_qla4010(ha) ?
 705                 &ha->reg->u1.isp4010.nvram :
 706                 &ha->reg->u1.isp4022.nvram);
 707 }
 708
 709 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
 710 {
 711         return (is_qla4010(ha) ?
 712                 &ha->reg->u2.isp4010.ext_hw_conf :
 713                 &ha->reg->u2.isp4022.p0.ext_hw_conf);
 714 }
 715
 716 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
 717 {
 718         return (is_qla4010(ha) ?
 719                 &ha->reg->u2.isp4010.port_status :
 720                 &ha->reg->u2.isp4022.p0.port_status);
 721 }
 722
 723 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
 724 {
 725         return (is_qla4010(ha) ?
 726                 &ha->reg->u2.isp4010.port_ctrl :
 727                 &ha->reg->u2.isp4022.p0.port_ctrl);
 728 }
 729
 730 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
 731 {
 732         return (is_qla4010(ha) ?
 733                 &ha->reg->u2.isp4010.port_err_status :
 734                 &ha->reg->u2.isp4022.p0.port_err_status);
 735 }
 736
 737 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
 738 {
 739         return (is_qla4010(ha) ?
 740                 &ha->reg->u2.isp4010.gp_out :
 741                 &ha->reg->u2.isp4022.p0.gp_out);
 742 }
 743
 744 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
 745 {
 746         return (is_qla4010(ha) ?
 747                 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
 748                 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
 749 }
 750
 751 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
 752 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
 753 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
 754
 755 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
 756 {
 757         if (is_qla4010(a))
 758                 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
 759                                            QL4010_FLASH_SEM_BITS);
 760         else
 761                 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
 762                                            (QL4022_RESOURCE_BITS_BASE_CODE |
 763                                             (a->mac_index)) << 13);
 764 }
 765
 766 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
 767 {
 768         if (is_qla4010(a))
 769                 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
 770         else
 771                 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
 772 }
 773
 774 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
 775 {
 776         if (is_qla4010(a))
 777                 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
 778                                            QL4010_NVRAM_SEM_BITS);
 779         else
 780                 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
 781                                            (QL4022_RESOURCE_BITS_BASE_CODE |
 782                                             (a->mac_index)) << 10);
 783 }
 784
 785 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
 786 {
 787         if (is_qla4010(a))
 788                 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
 789         else
 790                 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
 791 }
 792
 793 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
 794 {
 795         if (is_qla4010(a))
 796                 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
 797                                        QL4010_DRVR_SEM_BITS);
 798         else
 799                 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
 800                                        (QL4022_RESOURCE_BITS_BASE_CODE |
 801                                         (a->mac_index)) << 1);
 802 }
 803
 804 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
 805 {
 806         if (is_qla4010(a))
 807                 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
 808         else
 809                 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
 810 }
 811
 812 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
 813 {
 814         return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
 815                test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
 816                test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
 817                test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
 818                test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
 819                test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
 820
 821 }
 822 /*---------------------------------------------------------------------------*/
 823
 824 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
 825 #define PRESERVE_DDB_LIST       0
 826 #define REBUILD_DDB_LIST        1
 827
 828 /* Defines for process_aen() */
 829 #define PROCESS_ALL_AENS         0
 830 #define FLUSH_DDB_CHANGED_AENS   1
 831
 832 #endif  /*_QLA4XXX_H */