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KVM: SVM: Implement workaround for Erratum 383
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / svm.c
blob49dabc138f5c8298653726b0998dbd3e00208ea9
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "irq.h"
19 #include "mmu.h"
20 #include "kvm_cache_regs.h"
21 #include "x86.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
30
31 #include <asm/tlbflush.h>
32 #include <asm/desc.h>
33
34 #include <asm/virtext.h>
35 #include "trace.h"
36
37 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38
39 MODULE_AUTHOR("Qumranet");
40 MODULE_LICENSE("GPL");
41
42 #define IOPM_ALLOC_ORDER 2
43 #define MSRPM_ALLOC_ORDER 1
44
45 #define SEG_TYPE_LDT 2
46 #define SEG_TYPE_BUSY_TSS16 3
47
48 #define SVM_FEATURE_NPT (1 << 0)
49 #define SVM_FEATURE_LBRV (1 << 1)
50 #define SVM_FEATURE_SVML (1 << 2)
51 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
52
53 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56
57 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
59 static bool erratum_383_found __read_mostly;
60
61 static const u32 host_save_user_msrs[] = {
62 #ifdef CONFIG_X86_64
63 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
64 MSR_FS_BASE,
65 #endif
66 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
67 };
68
69 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
70
71 struct kvm_vcpu;
72
73 struct nested_state {
74 struct vmcb *hsave;
75 u64 hsave_msr;
76 u64 vmcb;
77
78 /* These are the merged vectors */
79 u32 *msrpm;
80
81 /* gpa pointers to the real vectors */
82 u64 vmcb_msrpm;
83
84 /* A VMEXIT is required but not yet emulated */
85 bool exit_required;
86
87 /* cache for intercepts of the guest */
88 u16 intercept_cr_read;
89 u16 intercept_cr_write;
90 u16 intercept_dr_read;
91 u16 intercept_dr_write;
92 u32 intercept_exceptions;
93 u64 intercept;
94
95 };
96
97 struct vcpu_svm {
98 struct kvm_vcpu vcpu;
99 struct vmcb *vmcb;
100 unsigned long vmcb_pa;
101 struct svm_cpu_data *svm_data;
102 uint64_t asid_generation;
103 uint64_t sysenter_esp;
104 uint64_t sysenter_eip;
105
106 u64 next_rip;
107
108 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
109 u64 host_gs_base;
110
111 u32 *msrpm;
112
113 struct nested_state nested;
114
115 bool nmi_singlestep;
116 };
117
118 /* enable NPT for AMD64 and X86 with PAE */
119 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
120 static bool npt_enabled = true;
121 #else
122 static bool npt_enabled = false;
123 #endif
124 static int npt = 1;
125
126 module_param(npt, int, S_IRUGO);
127
128 static int nested = 1;
129 module_param(nested, int, S_IRUGO);
130
131 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
132 static void svm_complete_interrupts(struct vcpu_svm *svm);
133
134 static int nested_svm_exit_handled(struct vcpu_svm *svm);
135 static int nested_svm_intercept(struct vcpu_svm *svm);
136 static int nested_svm_vmexit(struct vcpu_svm *svm);
137 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
138 bool has_error_code, u32 error_code);
139
140 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
141 {
142 return container_of(vcpu, struct vcpu_svm, vcpu);
143 }
144
145 static inline bool is_nested(struct vcpu_svm *svm)
146 {
147 return svm->nested.vmcb;
148 }
149
150 static inline void enable_gif(struct vcpu_svm *svm)
151 {
152 svm->vcpu.arch.hflags |= HF_GIF_MASK;
153 }
154
155 static inline void disable_gif(struct vcpu_svm *svm)
156 {
157 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
158 }
159
160 static inline bool gif_set(struct vcpu_svm *svm)
161 {
162 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
163 }
164
165 static unsigned long iopm_base;
166
167 struct kvm_ldttss_desc {
168 u16 limit0;
169 u16 base0;
170 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
171 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
172 u32 base3;
173 u32 zero1;
174 } __attribute__((packed));
175
176 struct svm_cpu_data {
177 int cpu;
178
179 u64 asid_generation;
180 u32 max_asid;
181 u32 next_asid;
182 struct kvm_ldttss_desc *tss_desc;
183
184 struct page *save_area;
185 };
186
187 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
188 static uint32_t svm_features;
189
190 struct svm_init_data {
191 int cpu;
192 int r;
193 };
194
195 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
196
197 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
198 #define MSRS_RANGE_SIZE 2048
199 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
200
201 #define MAX_INST_SIZE 15
202
203 static inline u32 svm_has(u32 feat)
204 {
205 return svm_features & feat;
206 }
207
208 static inline void clgi(void)
209 {
210 asm volatile (__ex(SVM_CLGI));
211 }
212
213 static inline void stgi(void)
214 {
215 asm volatile (__ex(SVM_STGI));
216 }
217
218 static inline void invlpga(unsigned long addr, u32 asid)
219 {
220 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
221 }
222
223 static inline void force_new_asid(struct kvm_vcpu *vcpu)
224 {
225 to_svm(vcpu)->asid_generation--;
226 }
227
228 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
229 {
230 force_new_asid(vcpu);
231 }
232
233 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
234 {
235 if (!npt_enabled && !(efer & EFER_LMA))
236 efer &= ~EFER_LME;
237
238 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
239 vcpu->arch.efer = efer;
240 }
241
242 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
243 bool has_error_code, u32 error_code)
244 {
245 struct vcpu_svm *svm = to_svm(vcpu);
246
247 /* If we are within a nested VM we'd better #VMEXIT and let the
248 guest handle the exception */
249 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
250 return;
251
252 svm->vmcb->control.event_inj = nr
253 | SVM_EVTINJ_VALID
254 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
255 | SVM_EVTINJ_TYPE_EXEPT;
256 svm->vmcb->control.event_inj_err = error_code;
257 }
258
259 static int is_external_interrupt(u32 info)
260 {
261 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
262 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
263 }
264
265 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
266 {
267 struct vcpu_svm *svm = to_svm(vcpu);
268 u32 ret = 0;
269
270 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
271 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
272 return ret & mask;
273 }
274
275 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
276 {
277 struct vcpu_svm *svm = to_svm(vcpu);
278
279 if (mask == 0)
280 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
281 else
282 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
283
284 }
285
286 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
287 {
288 struct vcpu_svm *svm = to_svm(vcpu);
289
290 if (!svm->next_rip) {
291 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
292 EMULATE_DONE)
293 printk(KERN_DEBUG "%s: NOP\n", __func__);
294 return;
295 }
296 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
297 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
298 __func__, kvm_rip_read(vcpu), svm->next_rip);
299
300 kvm_rip_write(vcpu, svm->next_rip);
301 svm_set_interrupt_shadow(vcpu, 0);
302 }
303
304 static void svm_init_erratum_383(void)
305 {
306 u32 low, high;
307 int err;
308 u64 val;
309
310 /* Only Fam10h is affected */
311 if (boot_cpu_data.x86 != 0x10)
312 return;
313
314 /* Use _safe variants to not break nested virtualization */
315 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
316 if (err)
317 return;
318
319 val |= (1ULL << 47);
320
321 low = lower_32_bits(val);
322 high = upper_32_bits(val);
323
324 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
325
326 erratum_383_found = true;
327 }
328
329 static int has_svm(void)
330 {
331 const char *msg;
332
333 if (!cpu_has_svm(&msg)) {
334 printk(KERN_INFO "has_svm: %s\n", msg);
335 return 0;
336 }
337
338 return 1;
339 }
340
341 static void svm_hardware_disable(void *garbage)
342 {
343 cpu_svm_disable();
344 }
345
346 static int svm_hardware_enable(void *garbage)
347 {
348
349 struct svm_cpu_data *sd;
350 uint64_t efer;
351 struct descriptor_table gdt_descr;
352 struct desc_struct *gdt;
353 int me = raw_smp_processor_id();
354
355 rdmsrl(MSR_EFER, efer);
356 if (efer & EFER_SVME)
357 return -EBUSY;
358
359 if (!has_svm()) {
360 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
361 me);
362 return -EINVAL;
363 }
364 sd = per_cpu(svm_data, me);
365
366 if (!sd) {
367 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
368 me);
369 return -EINVAL;
370 }
371
372 sd->asid_generation = 1;
373 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
374 sd->next_asid = sd->max_asid + 1;
375
376 kvm_get_gdt(&gdt_descr);
377 gdt = (struct desc_struct *)gdt_descr.base;
378 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
379
380 wrmsrl(MSR_EFER, efer | EFER_SVME);
381
382 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
383
384 svm_init_erratum_383();
385
386 return 0;
387 }
388
389 static void svm_cpu_uninit(int cpu)
390 {
391 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
392
393 if (!sd)
394 return;
395
396 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
397 __free_page(sd->save_area);
398 kfree(sd);
399 }
400
401 static int svm_cpu_init(int cpu)
402 {
403 struct svm_cpu_data *sd;
404 int r;
405
406 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
407 if (!sd)
408 return -ENOMEM;
409 sd->cpu = cpu;
410 sd->save_area = alloc_page(GFP_KERNEL);
411 r = -ENOMEM;
412 if (!sd->save_area)
413 goto err_1;
414
415 per_cpu(svm_data, cpu) = sd;
416
417 return 0;
418
419 err_1:
420 kfree(sd);
421 return r;
422
423 }
424
425 static void set_msr_interception(u32 *msrpm, unsigned msr,
426 int read, int write)
427 {
428 int i;
429
430 for (i = 0; i < NUM_MSR_MAPS; i++) {
431 if (msr >= msrpm_ranges[i] &&
432 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
433 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
434 msrpm_ranges[i]) * 2;
435
436 u32 *base = msrpm + (msr_offset / 32);
437 u32 msr_shift = msr_offset % 32;
438 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
439 *base = (*base & ~(0x3 << msr_shift)) |
440 (mask << msr_shift);
441 return;
442 }
443 }
444 BUG();
445 }
446
447 static void svm_vcpu_init_msrpm(u32 *msrpm)
448 {
449 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
450
451 #ifdef CONFIG_X86_64
452 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
453 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
454 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
455 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
456 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
457 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
458 #endif
459 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
460 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
461 }
462
463 static void svm_enable_lbrv(struct vcpu_svm *svm)
464 {
465 u32 *msrpm = svm->msrpm;
466
467 svm->vmcb->control.lbr_ctl = 1;
468 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
469 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
470 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
471 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
472 }
473
474 static void svm_disable_lbrv(struct vcpu_svm *svm)
475 {
476 u32 *msrpm = svm->msrpm;
477
478 svm->vmcb->control.lbr_ctl = 0;
479 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
480 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
481 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
482 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
483 }
484
485 static __init int svm_hardware_setup(void)
486 {
487 int cpu;
488 struct page *iopm_pages;
489 void *iopm_va;
490 int r;
491
492 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
493
494 if (!iopm_pages)
495 return -ENOMEM;
496
497 iopm_va = page_address(iopm_pages);
498 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
499 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
500
501 if (boot_cpu_has(X86_FEATURE_NX))
502 kvm_enable_efer_bits(EFER_NX);
503
504 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
505 kvm_enable_efer_bits(EFER_FFXSR);
506
507 if (nested) {
508 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
509 kvm_enable_efer_bits(EFER_SVME);
510 }
511
512 for_each_possible_cpu(cpu) {
513 r = svm_cpu_init(cpu);
514 if (r)
515 goto err;
516 }
517
518 svm_features = cpuid_edx(SVM_CPUID_FUNC);
519
520 if (!svm_has(SVM_FEATURE_NPT))
521 npt_enabled = false;
522
523 if (npt_enabled && !npt) {
524 printk(KERN_INFO "kvm: Nested Paging disabled\n");
525 npt_enabled = false;
526 }
527
528 if (npt_enabled) {
529 printk(KERN_INFO "kvm: Nested Paging enabled\n");
530 kvm_enable_tdp();
531 } else
532 kvm_disable_tdp();
533
534 return 0;
535
536 err:
537 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
538 iopm_base = 0;
539 return r;
540 }
541
542 static __exit void svm_hardware_unsetup(void)
543 {
544 int cpu;
545
546 for_each_possible_cpu(cpu)
547 svm_cpu_uninit(cpu);
548
549 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
550 iopm_base = 0;
551 }
552
553 static void init_seg(struct vmcb_seg *seg)
554 {
555 seg->selector = 0;
556 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
557 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
558 seg->limit = 0xffff;
559 seg->base = 0;
560 }
561
562 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
563 {
564 seg->selector = 0;
565 seg->attrib = SVM_SELECTOR_P_MASK | type;
566 seg->limit = 0xffff;
567 seg->base = 0;
568 }
569
570 static void init_vmcb(struct vcpu_svm *svm)
571 {
572 struct vmcb_control_area *control = &svm->vmcb->control;
573 struct vmcb_save_area *save = &svm->vmcb->save;
574
575 svm->vcpu.fpu_active = 1;
576
577 control->intercept_cr_read = INTERCEPT_CR0_MASK |
578 INTERCEPT_CR3_MASK |
579 INTERCEPT_CR4_MASK;
580
581 control->intercept_cr_write = INTERCEPT_CR0_MASK |
582 INTERCEPT_CR3_MASK |
583 INTERCEPT_CR4_MASK |
584 INTERCEPT_CR8_MASK;
585
586 control->intercept_dr_read = INTERCEPT_DR0_MASK |
587 INTERCEPT_DR1_MASK |
588 INTERCEPT_DR2_MASK |
589 INTERCEPT_DR3_MASK |
590 INTERCEPT_DR4_MASK |
591 INTERCEPT_DR5_MASK |
592 INTERCEPT_DR6_MASK |
593 INTERCEPT_DR7_MASK;
594
595 control->intercept_dr_write = INTERCEPT_DR0_MASK |
596 INTERCEPT_DR1_MASK |
597 INTERCEPT_DR2_MASK |
598 INTERCEPT_DR3_MASK |
599 INTERCEPT_DR4_MASK |
600 INTERCEPT_DR5_MASK |
601 INTERCEPT_DR6_MASK |
602 INTERCEPT_DR7_MASK;
603
604 control->intercept_exceptions = (1 << PF_VECTOR) |
605 (1 << UD_VECTOR) |
606 (1 << MC_VECTOR);
607
608
609 control->intercept = (1ULL << INTERCEPT_INTR) |
610 (1ULL << INTERCEPT_NMI) |
611 (1ULL << INTERCEPT_SMI) |
612 (1ULL << INTERCEPT_SELECTIVE_CR0) |
613 (1ULL << INTERCEPT_CPUID) |
614 (1ULL << INTERCEPT_INVD) |
615 (1ULL << INTERCEPT_HLT) |
616 (1ULL << INTERCEPT_INVLPG) |
617 (1ULL << INTERCEPT_INVLPGA) |
618 (1ULL << INTERCEPT_IOIO_PROT) |
619 (1ULL << INTERCEPT_MSR_PROT) |
620 (1ULL << INTERCEPT_TASK_SWITCH) |
621 (1ULL << INTERCEPT_SHUTDOWN) |
622 (1ULL << INTERCEPT_VMRUN) |
623 (1ULL << INTERCEPT_VMMCALL) |
624 (1ULL << INTERCEPT_VMLOAD) |
625 (1ULL << INTERCEPT_VMSAVE) |
626 (1ULL << INTERCEPT_STGI) |
627 (1ULL << INTERCEPT_CLGI) |
628 (1ULL << INTERCEPT_SKINIT) |
629 (1ULL << INTERCEPT_WBINVD) |
630 (1ULL << INTERCEPT_MONITOR) |
631 (1ULL << INTERCEPT_MWAIT);
632
633 control->iopm_base_pa = iopm_base;
634 control->msrpm_base_pa = __pa(svm->msrpm);
635 control->tsc_offset = 0;
636 control->int_ctl = V_INTR_MASKING_MASK;
637
638 init_seg(&save->es);
639 init_seg(&save->ss);
640 init_seg(&save->ds);
641 init_seg(&save->fs);
642 init_seg(&save->gs);
643
644 save->cs.selector = 0xf000;
645 /* Executable/Readable Code Segment */
646 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
647 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
648 save->cs.limit = 0xffff;
649 /*
650 * cs.base should really be 0xffff0000, but vmx can't handle that, so
651 * be consistent with it.
652 *
653 * Replace when we have real mode working for vmx.
654 */
655 save->cs.base = 0xf0000;
656
657 save->gdtr.limit = 0xffff;
658 save->idtr.limit = 0xffff;
659
660 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
661 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
662
663 save->efer = EFER_SVME;
664 save->dr6 = 0xffff0ff0;
665 save->dr7 = 0x400;
666 save->rflags = 2;
667 save->rip = 0x0000fff0;
668 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
669
670 /* This is the guest-visible cr0 value.
671 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
672 */
673 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
674 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
675
676 save->cr4 = X86_CR4_PAE;
677 /* rdx = ?? */
678
679 if (npt_enabled) {
680 /* Setup VMCB for Nested Paging */
681 control->nested_ctl = 1;
682 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
683 (1ULL << INTERCEPT_INVLPG));
684 control->intercept_exceptions &= ~(1 << PF_VECTOR);
685 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
686 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
687 save->g_pat = 0x0007040600070406ULL;
688 save->cr3 = 0;
689 save->cr4 = 0;
690 }
691 force_new_asid(&svm->vcpu);
692
693 svm->nested.vmcb = 0;
694 svm->vcpu.arch.hflags = 0;
695
696 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
697 control->pause_filter_count = 3000;
698 control->intercept |= (1ULL << INTERCEPT_PAUSE);
699 }
700
701 enable_gif(svm);
702 }
703
704 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
705 {
706 struct vcpu_svm *svm = to_svm(vcpu);
707
708 init_vmcb(svm);
709
710 if (!kvm_vcpu_is_bsp(vcpu)) {
711 kvm_rip_write(vcpu, 0);
712 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
713 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
714 }
715 vcpu->arch.regs_avail = ~0;
716 vcpu->arch.regs_dirty = ~0;
717
718 return 0;
719 }
720
721 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
722 {
723 struct vcpu_svm *svm;
724 struct page *page;
725 struct page *msrpm_pages;
726 struct page *hsave_page;
727 struct page *nested_msrpm_pages;
728 int err;
729
730 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
731 if (!svm) {
732 err = -ENOMEM;
733 goto out;
734 }
735
736 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
737 if (err)
738 goto free_svm;
739
740 err = -ENOMEM;
741 page = alloc_page(GFP_KERNEL);
742 if (!page)
743 goto uninit;
744
745 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
746 if (!msrpm_pages)
747 goto free_page1;
748
749 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
750 if (!nested_msrpm_pages)
751 goto free_page2;
752
753 hsave_page = alloc_page(GFP_KERNEL);
754 if (!hsave_page)
755 goto free_page3;
756
757 svm->nested.hsave = page_address(hsave_page);
758
759 svm->msrpm = page_address(msrpm_pages);
760 svm_vcpu_init_msrpm(svm->msrpm);
761
762 svm->nested.msrpm = page_address(nested_msrpm_pages);
763
764 svm->vmcb = page_address(page);
765 clear_page(svm->vmcb);
766 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
767 svm->asid_generation = 0;
768 init_vmcb(svm);
769
770 fx_init(&svm->vcpu);
771 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
772 if (kvm_vcpu_is_bsp(&svm->vcpu))
773 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
774
775 return &svm->vcpu;
776
777 free_page3:
778 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
779 free_page2:
780 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
781 free_page1:
782 __free_page(page);
783 uninit:
784 kvm_vcpu_uninit(&svm->vcpu);
785 free_svm:
786 kmem_cache_free(kvm_vcpu_cache, svm);
787 out:
788 return ERR_PTR(err);
789 }
790
791 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
792 {
793 struct vcpu_svm *svm = to_svm(vcpu);
794
795 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
796 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
797 __free_page(virt_to_page(svm->nested.hsave));
798 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
799 kvm_vcpu_uninit(vcpu);
800 kmem_cache_free(kvm_vcpu_cache, svm);
801 }
802
803 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
804 {
805 struct vcpu_svm *svm = to_svm(vcpu);
806 int i;
807
808 if (unlikely(cpu != vcpu->cpu)) {
809 u64 delta;
810
811 if (check_tsc_unstable()) {
812 /*
813 * Make sure that the guest sees a monotonically
814 * increasing TSC.
815 */
816 delta = vcpu->arch.host_tsc - native_read_tsc();
817 svm->vmcb->control.tsc_offset += delta;
818 if (is_nested(svm))
819 svm->nested.hsave->control.tsc_offset += delta;
820 }
821 vcpu->cpu = cpu;
822 kvm_migrate_timers(vcpu);
823 svm->asid_generation = 0;
824 }
825
826 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
827 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
828 }
829
830 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
831 {
832 struct vcpu_svm *svm = to_svm(vcpu);
833 int i;
834
835 ++vcpu->stat.host_state_reload;
836 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
837 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
838
839 vcpu->arch.host_tsc = native_read_tsc();
840 }
841
842 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
843 {
844 return to_svm(vcpu)->vmcb->save.rflags;
845 }
846
847 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
848 {
849 to_svm(vcpu)->vmcb->save.rflags = rflags;
850 }
851
852 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
853 {
854 switch (reg) {
855 case VCPU_EXREG_PDPTR:
856 BUG_ON(!npt_enabled);
857 load_pdptrs(vcpu, vcpu->arch.cr3);
858 break;
859 default:
860 BUG();
861 }
862 }
863
864 static void svm_set_vintr(struct vcpu_svm *svm)
865 {
866 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
867 }
868
869 static void svm_clear_vintr(struct vcpu_svm *svm)
870 {
871 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
872 }
873
874 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
875 {
876 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
877
878 switch (seg) {
879 case VCPU_SREG_CS: return &save->cs;
880 case VCPU_SREG_DS: return &save->ds;
881 case VCPU_SREG_ES: return &save->es;
882 case VCPU_SREG_FS: return &save->fs;
883 case VCPU_SREG_GS: return &save->gs;
884 case VCPU_SREG_SS: return &save->ss;
885 case VCPU_SREG_TR: return &save->tr;
886 case VCPU_SREG_LDTR: return &save->ldtr;
887 }
888 BUG();
889 return NULL;
890 }
891
892 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
893 {
894 struct vmcb_seg *s = svm_seg(vcpu, seg);
895
896 return s->base;
897 }
898
899 static void svm_get_segment(struct kvm_vcpu *vcpu,
900 struct kvm_segment *var, int seg)
901 {
902 struct vmcb_seg *s = svm_seg(vcpu, seg);
903
904 var->base = s->base;
905 var->limit = s->limit;
906 var->selector = s->selector;
907 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
908 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
909 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
910 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
911 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
912 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
913 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
914 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
915
916 /* AMD's VMCB does not have an explicit unusable field, so emulate it
917 * for cross vendor migration purposes by "not present"
918 */
919 var->unusable = !var->present || (var->type == 0);
920
921 switch (seg) {
922 case VCPU_SREG_CS:
923 /*
924 * SVM always stores 0 for the 'G' bit in the CS selector in
925 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
926 * Intel's VMENTRY has a check on the 'G' bit.
927 */
928 var->g = s->limit > 0xfffff;
929 break;
930 case VCPU_SREG_TR:
931 /*
932 * Work around a bug where the busy flag in the tr selector
933 * isn't exposed
934 */
935 var->type |= 0x2;
936 break;
937 case VCPU_SREG_DS:
938 case VCPU_SREG_ES:
939 case VCPU_SREG_FS:
940 case VCPU_SREG_GS:
941 /*
942 * The accessed bit must always be set in the segment
943 * descriptor cache, although it can be cleared in the
944 * descriptor, the cached bit always remains at 1. Since
945 * Intel has a check on this, set it here to support
946 * cross-vendor migration.
947 */
948 if (!var->unusable)
949 var->type |= 0x1;
950 break;
951 case VCPU_SREG_SS:
952 /* On AMD CPUs sometimes the DB bit in the segment
953 * descriptor is left as 1, although the whole segment has
954 * been made unusable. Clear it here to pass an Intel VMX
955 * entry check when cross vendor migrating.
956 */
957 if (var->unusable)
958 var->db = 0;
959 break;
960 }
961 }
962
963 static int svm_get_cpl(struct kvm_vcpu *vcpu)
964 {
965 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
966
967 return save->cpl;
968 }
969
970 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
971 {
972 struct vcpu_svm *svm = to_svm(vcpu);
973
974 dt->limit = svm->vmcb->save.idtr.limit;
975 dt->base = svm->vmcb->save.idtr.base;
976 }
977
978 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
979 {
980 struct vcpu_svm *svm = to_svm(vcpu);
981
982 svm->vmcb->save.idtr.limit = dt->limit;
983 svm->vmcb->save.idtr.base = dt->base ;
984 }
985
986 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
987 {
988 struct vcpu_svm *svm = to_svm(vcpu);
989
990 dt->limit = svm->vmcb->save.gdtr.limit;
991 dt->base = svm->vmcb->save.gdtr.base;
992 }
993
994 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
995 {
996 struct vcpu_svm *svm = to_svm(vcpu);
997
998 svm->vmcb->save.gdtr.limit = dt->limit;
999 svm->vmcb->save.gdtr.base = dt->base ;
1000 }
1001
1002 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1003 {
1004 }
1005
1006 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1007 {
1008 }
1009
1010 static void update_cr0_intercept(struct vcpu_svm *svm)
1011 {
1012 ulong gcr0 = svm->vcpu.arch.cr0;
1013 u64 *hcr0 = &svm->vmcb->save.cr0;
1014
1015 if (!svm->vcpu.fpu_active)
1016 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1017 else
1018 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1019 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1020
1021
1022 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1023 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1024 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1025 } else {
1026 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1027 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1028 }
1029 }
1030
1031 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1032 {
1033 struct vcpu_svm *svm = to_svm(vcpu);
1034
1035 #ifdef CONFIG_X86_64
1036 if (vcpu->arch.efer & EFER_LME) {
1037 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1038 vcpu->arch.efer |= EFER_LMA;
1039 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1040 }
1041
1042 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1043 vcpu->arch.efer &= ~EFER_LMA;
1044 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1045 }
1046 }
1047 #endif
1048 vcpu->arch.cr0 = cr0;
1049
1050 if (!npt_enabled)
1051 cr0 |= X86_CR0_PG | X86_CR0_WP;
1052
1053 if (!vcpu->fpu_active)
1054 cr0 |= X86_CR0_TS;
1055 /*
1056 * re-enable caching here because the QEMU bios
1057 * does not do it - this results in some delay at
1058 * reboot
1059 */
1060 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1061 svm->vmcb->save.cr0 = cr0;
1062 update_cr0_intercept(svm);
1063 }
1064
1065 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1066 {
1067 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1068 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1069
1070 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1071 force_new_asid(vcpu);
1072
1073 vcpu->arch.cr4 = cr4;
1074 if (!npt_enabled)
1075 cr4 |= X86_CR4_PAE;
1076 cr4 |= host_cr4_mce;
1077 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1078 }
1079
1080 static void svm_set_segment(struct kvm_vcpu *vcpu,
1081 struct kvm_segment *var, int seg)
1082 {
1083 struct vcpu_svm *svm = to_svm(vcpu);
1084 struct vmcb_seg *s = svm_seg(vcpu, seg);
1085
1086 s->base = var->base;
1087 s->limit = var->limit;
1088 s->selector = var->selector;
1089 if (var->unusable)
1090 s->attrib = 0;
1091 else {
1092 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1093 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1094 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1095 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1096 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1097 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1098 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1099 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1100 }
1101 if (seg == VCPU_SREG_CS)
1102 svm->vmcb->save.cpl
1103 = (svm->vmcb->save.cs.attrib
1104 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1105
1106 }
1107
1108 static void update_db_intercept(struct kvm_vcpu *vcpu)
1109 {
1110 struct vcpu_svm *svm = to_svm(vcpu);
1111
1112 svm->vmcb->control.intercept_exceptions &=
1113 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1114
1115 if (svm->nmi_singlestep)
1116 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1117
1118 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1119 if (vcpu->guest_debug &
1120 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1121 svm->vmcb->control.intercept_exceptions |=
1122 1 << DB_VECTOR;
1123 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1124 svm->vmcb->control.intercept_exceptions |=
1125 1 << BP_VECTOR;
1126 } else
1127 vcpu->guest_debug = 0;
1128 }
1129
1130 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1131 {
1132 struct vcpu_svm *svm = to_svm(vcpu);
1133
1134 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1135 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1136 else
1137 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1138
1139 update_db_intercept(vcpu);
1140 }
1141
1142 static void load_host_msrs(struct kvm_vcpu *vcpu)
1143 {
1144 #ifdef CONFIG_X86_64
1145 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1146 #endif
1147 }
1148
1149 static void save_host_msrs(struct kvm_vcpu *vcpu)
1150 {
1151 #ifdef CONFIG_X86_64
1152 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1153 #endif
1154 }
1155
1156 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1157 {
1158 if (sd->next_asid > sd->max_asid) {
1159 ++sd->asid_generation;
1160 sd->next_asid = 1;
1161 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1162 }
1163
1164 svm->asid_generation = sd->asid_generation;
1165 svm->vmcb->control.asid = sd->next_asid++;
1166 }
1167
1168 static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
1169 {
1170 struct vcpu_svm *svm = to_svm(vcpu);
1171
1172 switch (dr) {
1173 case 0 ... 3:
1174 *dest = vcpu->arch.db[dr];
1175 break;
1176 case 4:
1177 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1178 return EMULATE_FAIL; /* will re-inject UD */
1179 /* fall through */
1180 case 6:
1181 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1182 *dest = vcpu->arch.dr6;
1183 else
1184 *dest = svm->vmcb->save.dr6;
1185 break;
1186 case 5:
1187 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1188 return EMULATE_FAIL; /* will re-inject UD */
1189 /* fall through */
1190 case 7:
1191 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1192 *dest = vcpu->arch.dr7;
1193 else
1194 *dest = svm->vmcb->save.dr7;
1195 break;
1196 }
1197
1198 return EMULATE_DONE;
1199 }
1200
1201 static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
1202 {
1203 struct vcpu_svm *svm = to_svm(vcpu);
1204
1205 switch (dr) {
1206 case 0 ... 3:
1207 vcpu->arch.db[dr] = value;
1208 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1209 vcpu->arch.eff_db[dr] = value;
1210 break;
1211 case 4:
1212 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1213 return EMULATE_FAIL; /* will re-inject UD */
1214 /* fall through */
1215 case 6:
1216 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1217 break;
1218 case 5:
1219 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1220 return EMULATE_FAIL; /* will re-inject UD */
1221 /* fall through */
1222 case 7:
1223 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1224 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1225 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1226 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1227 }
1228 break;
1229 }
1230
1231 return EMULATE_DONE;
1232 }
1233
1234 static int pf_interception(struct vcpu_svm *svm)
1235 {
1236 u64 fault_address;
1237 u32 error_code;
1238
1239 fault_address = svm->vmcb->control.exit_info_2;
1240 error_code = svm->vmcb->control.exit_info_1;
1241
1242 trace_kvm_page_fault(fault_address, error_code);
1243 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1244 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1245 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1246 }
1247
1248 static int db_interception(struct vcpu_svm *svm)
1249 {
1250 struct kvm_run *kvm_run = svm->vcpu.run;
1251
1252 if (!(svm->vcpu.guest_debug &
1253 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1254 !svm->nmi_singlestep) {
1255 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1256 return 1;
1257 }
1258
1259 if (svm->nmi_singlestep) {
1260 svm->nmi_singlestep = false;
1261 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1262 svm->vmcb->save.rflags &=
1263 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1264 update_db_intercept(&svm->vcpu);
1265 }
1266
1267 if (svm->vcpu.guest_debug &
1268 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1269 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1270 kvm_run->debug.arch.pc =
1271 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1272 kvm_run->debug.arch.exception = DB_VECTOR;
1273 return 0;
1274 }
1275
1276 return 1;
1277 }
1278
1279 static int bp_interception(struct vcpu_svm *svm)
1280 {
1281 struct kvm_run *kvm_run = svm->vcpu.run;
1282
1283 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1284 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1285 kvm_run->debug.arch.exception = BP_VECTOR;
1286 return 0;
1287 }
1288
1289 static int ud_interception(struct vcpu_svm *svm)
1290 {
1291 int er;
1292
1293 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1294 if (er != EMULATE_DONE)
1295 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1296 return 1;
1297 }
1298
1299 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1300 {
1301 struct vcpu_svm *svm = to_svm(vcpu);
1302 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1303 svm->vcpu.fpu_active = 1;
1304 update_cr0_intercept(svm);
1305 }
1306
1307 static int nm_interception(struct vcpu_svm *svm)
1308 {
1309 svm_fpu_activate(&svm->vcpu);
1310 return 1;
1311 }
1312
1313 static bool is_erratum_383(void)
1314 {
1315 int err, i;
1316 u64 value;
1317
1318 if (!erratum_383_found)
1319 return false;
1320
1321 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1322 if (err)
1323 return false;
1324
1325 /* Bit 62 may or may not be set for this mce */
1326 value &= ~(1ULL << 62);
1327
1328 if (value != 0xb600000000010015ULL)
1329 return false;
1330
1331 /* Clear MCi_STATUS registers */
1332 for (i = 0; i < 6; ++i)
1333 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1334
1335 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1336 if (!err) {
1337 u32 low, high;
1338
1339 value &= ~(1ULL << 2);
1340 low = lower_32_bits(value);
1341 high = upper_32_bits(value);
1342
1343 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1344 }
1345
1346 /* Flush tlb to evict multi-match entries */
1347 __flush_tlb_all();
1348
1349 return true;
1350 }
1351
1352 static void svm_handle_mce(struct vcpu_svm *svm)
1353 {
1354 if (is_erratum_383()) {
1355 /*
1356 * Erratum 383 triggered. Guest state is corrupt so kill the
1357 * guest.
1358 */
1359 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1360
1361 set_bit(KVM_REQ_TRIPLE_FAULT, &svm->vcpu.requests);
1362
1363 return;
1364 }
1365
1366 /*
1367 * On an #MC intercept the MCE handler is not called automatically in
1368 * the host. So do it by hand here.
1369 */
1370 asm volatile (
1371 "int $0x12\n");
1372 /* not sure if we ever come back to this point */
1373
1374 return;
1375 }
1376
1377 static int mc_interception(struct vcpu_svm *svm)
1378 {
1379 return 1;
1380 }
1381
1382 static int shutdown_interception(struct vcpu_svm *svm)
1383 {
1384 struct kvm_run *kvm_run = svm->vcpu.run;
1385
1386 /*
1387 * VMCB is undefined after a SHUTDOWN intercept
1388 * so reinitialize it.
1389 */
1390 clear_page(svm->vmcb);
1391 init_vmcb(svm);
1392
1393 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1394 return 0;
1395 }
1396
1397 static int io_interception(struct vcpu_svm *svm)
1398 {
1399 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1400 int size, in, string;
1401 unsigned port;
1402
1403 ++svm->vcpu.stat.io_exits;
1404
1405 svm->next_rip = svm->vmcb->control.exit_info_2;
1406
1407 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1408
1409 if (string) {
1410 if (emulate_instruction(&svm->vcpu,
1411 0, 0, 0) == EMULATE_DO_MMIO)
1412 return 0;
1413 return 1;
1414 }
1415
1416 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1417 port = io_info >> 16;
1418 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1419
1420 skip_emulated_instruction(&svm->vcpu);
1421 return kvm_emulate_pio(&svm->vcpu, in, size, port);
1422 }
1423
1424 static int nmi_interception(struct vcpu_svm *svm)
1425 {
1426 return 1;
1427 }
1428
1429 static int intr_interception(struct vcpu_svm *svm)
1430 {
1431 ++svm->vcpu.stat.irq_exits;
1432 return 1;
1433 }
1434
1435 static int nop_on_interception(struct vcpu_svm *svm)
1436 {
1437 return 1;
1438 }
1439
1440 static int halt_interception(struct vcpu_svm *svm)
1441 {
1442 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1443 skip_emulated_instruction(&svm->vcpu);
1444 return kvm_emulate_halt(&svm->vcpu);
1445 }
1446
1447 static int vmmcall_interception(struct vcpu_svm *svm)
1448 {
1449 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1450 skip_emulated_instruction(&svm->vcpu);
1451 kvm_emulate_hypercall(&svm->vcpu);
1452 return 1;
1453 }
1454
1455 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1456 {
1457 if (!(svm->vcpu.arch.efer & EFER_SVME)
1458 || !is_paging(&svm->vcpu)) {
1459 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1460 return 1;
1461 }
1462
1463 if (svm->vmcb->save.cpl) {
1464 kvm_inject_gp(&svm->vcpu, 0);
1465 return 1;
1466 }
1467
1468 return 0;
1469 }
1470
1471 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1472 bool has_error_code, u32 error_code)
1473 {
1474 int vmexit;
1475
1476 if (!is_nested(svm))
1477 return 0;
1478
1479 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1480 svm->vmcb->control.exit_code_hi = 0;
1481 svm->vmcb->control.exit_info_1 = error_code;
1482 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1483
1484 vmexit = nested_svm_intercept(svm);
1485 if (vmexit == NESTED_EXIT_DONE)
1486 svm->nested.exit_required = true;
1487
1488 return vmexit;
1489 }
1490
1491 /* This function returns true if it is save to enable the irq window */
1492 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1493 {
1494 if (!is_nested(svm))
1495 return true;
1496
1497 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1498 return true;
1499
1500 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1501 return false;
1502
1503 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1504
1505 if (svm->nested.intercept & 1ULL) {
1506 /*
1507 * The #vmexit can't be emulated here directly because this
1508 * code path runs with irqs and preemtion disabled. A
1509 * #vmexit emulation might sleep. Only signal request for
1510 * the #vmexit here.
1511 */
1512 svm->nested.exit_required = true;
1513 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1514 return false;
1515 }
1516
1517 return true;
1518 }
1519
1520 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1521 {
1522 struct page *page;
1523
1524 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1525 if (is_error_page(page))
1526 goto error;
1527
1528 *_page = page;
1529
1530 return kmap(page);
1531
1532 error:
1533 kvm_release_page_clean(page);
1534 kvm_inject_gp(&svm->vcpu, 0);
1535
1536 return NULL;
1537 }
1538
1539 static void nested_svm_unmap(struct page *page)
1540 {
1541 kunmap(page);
1542 kvm_release_page_dirty(page);
1543 }
1544
1545 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1546 {
1547 u32 param = svm->vmcb->control.exit_info_1 & 1;
1548 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1549 bool ret = false;
1550 u32 t0, t1;
1551 u8 val;
1552
1553 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1554 return false;
1555
1556 switch (msr) {
1557 case 0 ... 0x1fff:
1558 t0 = (msr * 2) % 8;
1559 t1 = msr / 8;
1560 break;
1561 case 0xc0000000 ... 0xc0001fff:
1562 t0 = (8192 + msr - 0xc0000000) * 2;
1563 t1 = (t0 / 8);
1564 t0 %= 8;
1565 break;
1566 case 0xc0010000 ... 0xc0011fff:
1567 t0 = (16384 + msr - 0xc0010000) * 2;
1568 t1 = (t0 / 8);
1569 t0 %= 8;
1570 break;
1571 default:
1572 ret = true;
1573 goto out;
1574 }
1575
1576 if (!kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + t1, &val, 1))
1577 ret = val & ((1 << param) << t0);
1578
1579 out:
1580 return ret;
1581 }
1582
1583 static int nested_svm_exit_special(struct vcpu_svm *svm)
1584 {
1585 u32 exit_code = svm->vmcb->control.exit_code;
1586
1587 switch (exit_code) {
1588 case SVM_EXIT_INTR:
1589 case SVM_EXIT_NMI:
1590 return NESTED_EXIT_HOST;
1591 /* For now we are always handling NPFs when using them */
1592 case SVM_EXIT_NPF:
1593 if (npt_enabled)
1594 return NESTED_EXIT_HOST;
1595 break;
1596 /* When we're shadowing, trap PFs */
1597 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1598 if (!npt_enabled)
1599 return NESTED_EXIT_HOST;
1600 break;
1601 default:
1602 break;
1603 }
1604
1605 return NESTED_EXIT_CONTINUE;
1606 }
1607
1608 /*
1609 * If this function returns true, this #vmexit was already handled
1610 */
1611 static int nested_svm_intercept(struct vcpu_svm *svm)
1612 {
1613 u32 exit_code = svm->vmcb->control.exit_code;
1614 int vmexit = NESTED_EXIT_HOST;
1615
1616 switch (exit_code) {
1617 case SVM_EXIT_MSR:
1618 vmexit = nested_svm_exit_handled_msr(svm);
1619 break;
1620 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1621 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1622 if (svm->nested.intercept_cr_read & cr_bits)
1623 vmexit = NESTED_EXIT_DONE;
1624 break;
1625 }
1626 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1627 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1628 if (svm->nested.intercept_cr_write & cr_bits)
1629 vmexit = NESTED_EXIT_DONE;
1630 break;
1631 }
1632 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1633 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1634 if (svm->nested.intercept_dr_read & dr_bits)
1635 vmexit = NESTED_EXIT_DONE;
1636 break;
1637 }
1638 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1639 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1640 if (svm->nested.intercept_dr_write & dr_bits)
1641 vmexit = NESTED_EXIT_DONE;
1642 break;
1643 }
1644 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1645 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1646 if (svm->nested.intercept_exceptions & excp_bits)
1647 vmexit = NESTED_EXIT_DONE;
1648 break;
1649 }
1650 default: {
1651 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1652 if (svm->nested.intercept & exit_bits)
1653 vmexit = NESTED_EXIT_DONE;
1654 }
1655 }
1656
1657 return vmexit;
1658 }
1659
1660 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1661 {
1662 int vmexit;
1663
1664 vmexit = nested_svm_intercept(svm);
1665
1666 if (vmexit == NESTED_EXIT_DONE)
1667 nested_svm_vmexit(svm);
1668
1669 return vmexit;
1670 }
1671
1672 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1673 {
1674 struct vmcb_control_area *dst = &dst_vmcb->control;
1675 struct vmcb_control_area *from = &from_vmcb->control;
1676
1677 dst->intercept_cr_read = from->intercept_cr_read;
1678 dst->intercept_cr_write = from->intercept_cr_write;
1679 dst->intercept_dr_read = from->intercept_dr_read;
1680 dst->intercept_dr_write = from->intercept_dr_write;
1681 dst->intercept_exceptions = from->intercept_exceptions;
1682 dst->intercept = from->intercept;
1683 dst->iopm_base_pa = from->iopm_base_pa;
1684 dst->msrpm_base_pa = from->msrpm_base_pa;
1685 dst->tsc_offset = from->tsc_offset;
1686 dst->asid = from->asid;
1687 dst->tlb_ctl = from->tlb_ctl;
1688 dst->int_ctl = from->int_ctl;
1689 dst->int_vector = from->int_vector;
1690 dst->int_state = from->int_state;
1691 dst->exit_code = from->exit_code;
1692 dst->exit_code_hi = from->exit_code_hi;
1693 dst->exit_info_1 = from->exit_info_1;
1694 dst->exit_info_2 = from->exit_info_2;
1695 dst->exit_int_info = from->exit_int_info;
1696 dst->exit_int_info_err = from->exit_int_info_err;
1697 dst->nested_ctl = from->nested_ctl;
1698 dst->event_inj = from->event_inj;
1699 dst->event_inj_err = from->event_inj_err;
1700 dst->nested_cr3 = from->nested_cr3;
1701 dst->lbr_ctl = from->lbr_ctl;
1702 }
1703
1704 static int nested_svm_vmexit(struct vcpu_svm *svm)
1705 {
1706 struct vmcb *nested_vmcb;
1707 struct vmcb *hsave = svm->nested.hsave;
1708 struct vmcb *vmcb = svm->vmcb;
1709 struct page *page;
1710
1711 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1712 vmcb->control.exit_info_1,
1713 vmcb->control.exit_info_2,
1714 vmcb->control.exit_int_info,
1715 vmcb->control.exit_int_info_err);
1716
1717 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1718 if (!nested_vmcb)
1719 return 1;
1720
1721 /* Give the current vmcb to the guest */
1722 disable_gif(svm);
1723
1724 nested_vmcb->save.es = vmcb->save.es;
1725 nested_vmcb->save.cs = vmcb->save.cs;
1726 nested_vmcb->save.ss = vmcb->save.ss;
1727 nested_vmcb->save.ds = vmcb->save.ds;
1728 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1729 nested_vmcb->save.idtr = vmcb->save.idtr;
1730 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
1731 if (npt_enabled)
1732 nested_vmcb->save.cr3 = vmcb->save.cr3;
1733 else
1734 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
1735 nested_vmcb->save.cr2 = vmcb->save.cr2;
1736 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
1737 nested_vmcb->save.rflags = vmcb->save.rflags;
1738 nested_vmcb->save.rip = vmcb->save.rip;
1739 nested_vmcb->save.rsp = vmcb->save.rsp;
1740 nested_vmcb->save.rax = vmcb->save.rax;
1741 nested_vmcb->save.dr7 = vmcb->save.dr7;
1742 nested_vmcb->save.dr6 = vmcb->save.dr6;
1743 nested_vmcb->save.cpl = vmcb->save.cpl;
1744
1745 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1746 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1747 nested_vmcb->control.int_state = vmcb->control.int_state;
1748 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1749 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1750 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1751 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1752 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1753 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1754
1755 /*
1756 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1757 * to make sure that we do not lose injected events. So check event_inj
1758 * here and copy it to exit_int_info if it is valid.
1759 * Exit_int_info and event_inj can't be both valid because the case
1760 * below only happens on a VMRUN instruction intercept which has
1761 * no valid exit_int_info set.
1762 */
1763 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1764 struct vmcb_control_area *nc = &nested_vmcb->control;
1765
1766 nc->exit_int_info = vmcb->control.event_inj;
1767 nc->exit_int_info_err = vmcb->control.event_inj_err;
1768 }
1769
1770 nested_vmcb->control.tlb_ctl = 0;
1771 nested_vmcb->control.event_inj = 0;
1772 nested_vmcb->control.event_inj_err = 0;
1773
1774 /* We always set V_INTR_MASKING and remember the old value in hflags */
1775 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1776 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1777
1778 /* Restore the original control entries */
1779 copy_vmcb_control_area(vmcb, hsave);
1780
1781 kvm_clear_exception_queue(&svm->vcpu);
1782 kvm_clear_interrupt_queue(&svm->vcpu);
1783
1784 /* Restore selected save entries */
1785 svm->vmcb->save.es = hsave->save.es;
1786 svm->vmcb->save.cs = hsave->save.cs;
1787 svm->vmcb->save.ss = hsave->save.ss;
1788 svm->vmcb->save.ds = hsave->save.ds;
1789 svm->vmcb->save.gdtr = hsave->save.gdtr;
1790 svm->vmcb->save.idtr = hsave->save.idtr;
1791 svm->vmcb->save.rflags = hsave->save.rflags;
1792 svm_set_efer(&svm->vcpu, hsave->save.efer);
1793 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1794 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1795 if (npt_enabled) {
1796 svm->vmcb->save.cr3 = hsave->save.cr3;
1797 svm->vcpu.arch.cr3 = hsave->save.cr3;
1798 } else {
1799 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1800 }
1801 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1802 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1803 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1804 svm->vmcb->save.dr7 = 0;
1805 svm->vmcb->save.cpl = 0;
1806 svm->vmcb->control.exit_int_info = 0;
1807
1808 /* Exit nested SVM mode */
1809 svm->nested.vmcb = 0;
1810
1811 nested_svm_unmap(page);
1812
1813 kvm_mmu_reset_context(&svm->vcpu);
1814 kvm_mmu_load(&svm->vcpu);
1815
1816 return 0;
1817 }
1818
1819 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1820 {
1821 u32 *nested_msrpm;
1822 struct page *page;
1823 int i;
1824
1825 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
1826 if (!nested_msrpm)
1827 return false;
1828
1829 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1830 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1831
1832 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1833
1834 nested_svm_unmap(page);
1835
1836 return true;
1837 }
1838
1839 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1840 {
1841 struct vmcb *nested_vmcb;
1842 struct vmcb *hsave = svm->nested.hsave;
1843 struct vmcb *vmcb = svm->vmcb;
1844 struct page *page;
1845
1846 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1847 if (!nested_vmcb)
1848 return false;
1849
1850 /* nested_vmcb is our indicator if nested SVM is activated */
1851 svm->nested.vmcb = svm->vmcb->save.rax;
1852
1853 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1854 nested_vmcb->save.rip,
1855 nested_vmcb->control.int_ctl,
1856 nested_vmcb->control.event_inj,
1857 nested_vmcb->control.nested_ctl);
1858
1859 /* Clear internal status */
1860 kvm_clear_exception_queue(&svm->vcpu);
1861 kvm_clear_interrupt_queue(&svm->vcpu);
1862
1863 /* Save the old vmcb, so we don't need to pick what we save, but
1864 can restore everything when a VMEXIT occurs */
1865 hsave->save.es = vmcb->save.es;
1866 hsave->save.cs = vmcb->save.cs;
1867 hsave->save.ss = vmcb->save.ss;
1868 hsave->save.ds = vmcb->save.ds;
1869 hsave->save.gdtr = vmcb->save.gdtr;
1870 hsave->save.idtr = vmcb->save.idtr;
1871 hsave->save.efer = svm->vcpu.arch.efer;
1872 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
1873 hsave->save.cr4 = svm->vcpu.arch.cr4;
1874 hsave->save.rflags = vmcb->save.rflags;
1875 hsave->save.rip = svm->next_rip;
1876 hsave->save.rsp = vmcb->save.rsp;
1877 hsave->save.rax = vmcb->save.rax;
1878 if (npt_enabled)
1879 hsave->save.cr3 = vmcb->save.cr3;
1880 else
1881 hsave->save.cr3 = svm->vcpu.arch.cr3;
1882
1883 copy_vmcb_control_area(hsave, vmcb);
1884
1885 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1886 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1887 else
1888 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1889
1890 /* Load the nested guest state */
1891 svm->vmcb->save.es = nested_vmcb->save.es;
1892 svm->vmcb->save.cs = nested_vmcb->save.cs;
1893 svm->vmcb->save.ss = nested_vmcb->save.ss;
1894 svm->vmcb->save.ds = nested_vmcb->save.ds;
1895 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1896 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1897 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1898 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1899 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1900 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1901 if (npt_enabled) {
1902 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1903 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1904 } else {
1905 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1906 kvm_mmu_reset_context(&svm->vcpu);
1907 }
1908 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1909 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1910 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1911 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1912 /* In case we don't even reach vcpu_run, the fields are not updated */
1913 svm->vmcb->save.rax = nested_vmcb->save.rax;
1914 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1915 svm->vmcb->save.rip = nested_vmcb->save.rip;
1916 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1917 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1918 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1919
1920 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1921
1922 /* cache intercepts */
1923 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1924 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1925 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1926 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1927 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1928 svm->nested.intercept = nested_vmcb->control.intercept;
1929
1930 force_new_asid(&svm->vcpu);
1931 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1932 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1933 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1934 else
1935 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1936
1937 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
1938 /* We only want the cr8 intercept bits of the guest */
1939 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
1940 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1941 }
1942
1943 /* We don't want to see VMMCALLs from a nested guest */
1944 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
1945
1946 /* We don't want a nested guest to be more powerful than the guest,
1947 so all intercepts are ORed */
1948 svm->vmcb->control.intercept_cr_read |=
1949 nested_vmcb->control.intercept_cr_read;
1950 svm->vmcb->control.intercept_cr_write |=
1951 nested_vmcb->control.intercept_cr_write;
1952 svm->vmcb->control.intercept_dr_read |=
1953 nested_vmcb->control.intercept_dr_read;
1954 svm->vmcb->control.intercept_dr_write |=
1955 nested_vmcb->control.intercept_dr_write;
1956 svm->vmcb->control.intercept_exceptions |=
1957 nested_vmcb->control.intercept_exceptions;
1958
1959 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1960
1961 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
1962 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1963 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1964 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1965 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1966 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1967
1968 nested_svm_unmap(page);
1969
1970 enable_gif(svm);
1971
1972 return true;
1973 }
1974
1975 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1976 {
1977 to_vmcb->save.fs = from_vmcb->save.fs;
1978 to_vmcb->save.gs = from_vmcb->save.gs;
1979 to_vmcb->save.tr = from_vmcb->save.tr;
1980 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1981 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1982 to_vmcb->save.star = from_vmcb->save.star;
1983 to_vmcb->save.lstar = from_vmcb->save.lstar;
1984 to_vmcb->save.cstar = from_vmcb->save.cstar;
1985 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1986 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1987 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1988 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1989 }
1990
1991 static int vmload_interception(struct vcpu_svm *svm)
1992 {
1993 struct vmcb *nested_vmcb;
1994 struct page *page;
1995
1996 if (nested_svm_check_permissions(svm))
1997 return 1;
1998
1999 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2000 skip_emulated_instruction(&svm->vcpu);
2001
2002 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2003 if (!nested_vmcb)
2004 return 1;
2005
2006 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2007 nested_svm_unmap(page);
2008
2009 return 1;
2010 }
2011
2012 static int vmsave_interception(struct vcpu_svm *svm)
2013 {
2014 struct vmcb *nested_vmcb;
2015 struct page *page;
2016
2017 if (nested_svm_check_permissions(svm))
2018 return 1;
2019
2020 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2021 skip_emulated_instruction(&svm->vcpu);
2022
2023 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2024 if (!nested_vmcb)
2025 return 1;
2026
2027 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2028 nested_svm_unmap(page);
2029
2030 return 1;
2031 }
2032
2033 static int vmrun_interception(struct vcpu_svm *svm)
2034 {
2035 if (nested_svm_check_permissions(svm))
2036 return 1;
2037
2038 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2039 skip_emulated_instruction(&svm->vcpu);
2040
2041 if (!nested_svm_vmrun(svm))
2042 return 1;
2043
2044 if (!nested_svm_vmrun_msrpm(svm))
2045 goto failed;
2046
2047 return 1;
2048
2049 failed:
2050
2051 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2052 svm->vmcb->control.exit_code_hi = 0;
2053 svm->vmcb->control.exit_info_1 = 0;
2054 svm->vmcb->control.exit_info_2 = 0;
2055
2056 nested_svm_vmexit(svm);
2057
2058 return 1;
2059 }
2060
2061 static int stgi_interception(struct vcpu_svm *svm)
2062 {
2063 if (nested_svm_check_permissions(svm))
2064 return 1;
2065
2066 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2067 skip_emulated_instruction(&svm->vcpu);
2068
2069 enable_gif(svm);
2070
2071 return 1;
2072 }
2073
2074 static int clgi_interception(struct vcpu_svm *svm)
2075 {
2076 if (nested_svm_check_permissions(svm))
2077 return 1;
2078
2079 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2080 skip_emulated_instruction(&svm->vcpu);
2081
2082 disable_gif(svm);
2083
2084 /* After a CLGI no interrupts should come */
2085 svm_clear_vintr(svm);
2086 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2087
2088 return 1;
2089 }
2090
2091 static int invlpga_interception(struct vcpu_svm *svm)
2092 {
2093 struct kvm_vcpu *vcpu = &svm->vcpu;
2094
2095 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2096 vcpu->arch.regs[VCPU_REGS_RAX]);
2097
2098 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2099 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2100
2101 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2102 skip_emulated_instruction(&svm->vcpu);
2103 return 1;
2104 }
2105
2106 static int skinit_interception(struct vcpu_svm *svm)
2107 {
2108 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2109
2110 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2111 return 1;
2112 }
2113
2114 static int invalid_op_interception(struct vcpu_svm *svm)
2115 {
2116 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2117 return 1;
2118 }
2119
2120 static int task_switch_interception(struct vcpu_svm *svm)
2121 {
2122 u16 tss_selector;
2123 int reason;
2124 int int_type = svm->vmcb->control.exit_int_info &
2125 SVM_EXITINTINFO_TYPE_MASK;
2126 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2127 uint32_t type =
2128 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2129 uint32_t idt_v =
2130 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2131
2132 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2133
2134 if (svm->vmcb->control.exit_info_2 &
2135 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2136 reason = TASK_SWITCH_IRET;
2137 else if (svm->vmcb->control.exit_info_2 &
2138 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2139 reason = TASK_SWITCH_JMP;
2140 else if (idt_v)
2141 reason = TASK_SWITCH_GATE;
2142 else
2143 reason = TASK_SWITCH_CALL;
2144
2145 if (reason == TASK_SWITCH_GATE) {
2146 switch (type) {
2147 case SVM_EXITINTINFO_TYPE_NMI:
2148 svm->vcpu.arch.nmi_injected = false;
2149 break;
2150 case SVM_EXITINTINFO_TYPE_EXEPT:
2151 kvm_clear_exception_queue(&svm->vcpu);
2152 break;
2153 case SVM_EXITINTINFO_TYPE_INTR:
2154 kvm_clear_interrupt_queue(&svm->vcpu);
2155 break;
2156 default:
2157 break;
2158 }
2159 }
2160
2161 if (reason != TASK_SWITCH_GATE ||
2162 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2163 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2164 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2165 skip_emulated_instruction(&svm->vcpu);
2166
2167 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2168 }
2169
2170 static int cpuid_interception(struct vcpu_svm *svm)
2171 {
2172 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2173 kvm_emulate_cpuid(&svm->vcpu);
2174 return 1;
2175 }
2176
2177 static int iret_interception(struct vcpu_svm *svm)
2178 {
2179 ++svm->vcpu.stat.nmi_window_exits;
2180 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2181 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2182 return 1;
2183 }
2184
2185 static int invlpg_interception(struct vcpu_svm *svm)
2186 {
2187 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2188 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2189 return 1;
2190 }
2191
2192 static int emulate_on_interception(struct vcpu_svm *svm)
2193 {
2194 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2195 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2196 return 1;
2197 }
2198
2199 static int cr8_write_interception(struct vcpu_svm *svm)
2200 {
2201 struct kvm_run *kvm_run = svm->vcpu.run;
2202
2203 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2204 /* instruction emulation calls kvm_set_cr8() */
2205 emulate_instruction(&svm->vcpu, 0, 0, 0);
2206 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2207 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2208 return 1;
2209 }
2210 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2211 return 1;
2212 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2213 return 0;
2214 }
2215
2216 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2217 {
2218 struct vcpu_svm *svm = to_svm(vcpu);
2219
2220 switch (ecx) {
2221 case MSR_IA32_TSC: {
2222 u64 tsc_offset;
2223
2224 if (is_nested(svm))
2225 tsc_offset = svm->nested.hsave->control.tsc_offset;
2226 else
2227 tsc_offset = svm->vmcb->control.tsc_offset;
2228
2229 *data = tsc_offset + native_read_tsc();
2230 break;
2231 }
2232 case MSR_K6_STAR:
2233 *data = svm->vmcb->save.star;
2234 break;
2235 #ifdef CONFIG_X86_64
2236 case MSR_LSTAR:
2237 *data = svm->vmcb->save.lstar;
2238 break;
2239 case MSR_CSTAR:
2240 *data = svm->vmcb->save.cstar;
2241 break;
2242 case MSR_KERNEL_GS_BASE:
2243 *data = svm->vmcb->save.kernel_gs_base;
2244 break;
2245 case MSR_SYSCALL_MASK:
2246 *data = svm->vmcb->save.sfmask;
2247 break;
2248 #endif
2249 case MSR_IA32_SYSENTER_CS:
2250 *data = svm->vmcb->save.sysenter_cs;
2251 break;
2252 case MSR_IA32_SYSENTER_EIP:
2253 *data = svm->sysenter_eip;
2254 break;
2255 case MSR_IA32_SYSENTER_ESP:
2256 *data = svm->sysenter_esp;
2257 break;
2258 /* Nobody will change the following 5 values in the VMCB so
2259 we can safely return them on rdmsr. They will always be 0
2260 until LBRV is implemented. */
2261 case MSR_IA32_DEBUGCTLMSR:
2262 *data = svm->vmcb->save.dbgctl;
2263 break;
2264 case MSR_IA32_LASTBRANCHFROMIP:
2265 *data = svm->vmcb->save.br_from;
2266 break;
2267 case MSR_IA32_LASTBRANCHTOIP:
2268 *data = svm->vmcb->save.br_to;
2269 break;
2270 case MSR_IA32_LASTINTFROMIP:
2271 *data = svm->vmcb->save.last_excp_from;
2272 break;
2273 case MSR_IA32_LASTINTTOIP:
2274 *data = svm->vmcb->save.last_excp_to;
2275 break;
2276 case MSR_VM_HSAVE_PA:
2277 *data = svm->nested.hsave_msr;
2278 break;
2279 case MSR_VM_CR:
2280 *data = 0;
2281 break;
2282 case MSR_IA32_UCODE_REV:
2283 *data = 0x01000065;
2284 break;
2285 default:
2286 return kvm_get_msr_common(vcpu, ecx, data);
2287 }
2288 return 0;
2289 }
2290
2291 static int rdmsr_interception(struct vcpu_svm *svm)
2292 {
2293 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2294 u64 data;
2295
2296 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2297 trace_kvm_msr_read_ex(ecx);
2298 kvm_inject_gp(&svm->vcpu, 0);
2299 } else {
2300 trace_kvm_msr_read(ecx, data);
2301
2302 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2303 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2304 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2305 skip_emulated_instruction(&svm->vcpu);
2306 }
2307 return 1;
2308 }
2309
2310 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2311 {
2312 struct vcpu_svm *svm = to_svm(vcpu);
2313
2314 switch (ecx) {
2315 case MSR_IA32_TSC: {
2316 u64 tsc_offset = data - native_read_tsc();
2317 u64 g_tsc_offset = 0;
2318
2319 if (is_nested(svm)) {
2320 g_tsc_offset = svm->vmcb->control.tsc_offset -
2321 svm->nested.hsave->control.tsc_offset;
2322 svm->nested.hsave->control.tsc_offset = tsc_offset;
2323 }
2324
2325 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2326
2327 break;
2328 }
2329 case MSR_K6_STAR:
2330 svm->vmcb->save.star = data;
2331 break;
2332 #ifdef CONFIG_X86_64
2333 case MSR_LSTAR:
2334 svm->vmcb->save.lstar = data;
2335 break;
2336 case MSR_CSTAR:
2337 svm->vmcb->save.cstar = data;
2338 break;
2339 case MSR_KERNEL_GS_BASE:
2340 svm->vmcb->save.kernel_gs_base = data;
2341 break;
2342 case MSR_SYSCALL_MASK:
2343 svm->vmcb->save.sfmask = data;
2344 break;
2345 #endif
2346 case MSR_IA32_SYSENTER_CS:
2347 svm->vmcb->save.sysenter_cs = data;
2348 break;
2349 case MSR_IA32_SYSENTER_EIP:
2350 svm->sysenter_eip = data;
2351 svm->vmcb->save.sysenter_eip = data;
2352 break;
2353 case MSR_IA32_SYSENTER_ESP:
2354 svm->sysenter_esp = data;
2355 svm->vmcb->save.sysenter_esp = data;
2356 break;
2357 case MSR_IA32_DEBUGCTLMSR:
2358 if (!svm_has(SVM_FEATURE_LBRV)) {
2359 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2360 __func__, data);
2361 break;
2362 }
2363 if (data & DEBUGCTL_RESERVED_BITS)
2364 return 1;
2365
2366 svm->vmcb->save.dbgctl = data;
2367 if (data & (1ULL<<0))
2368 svm_enable_lbrv(svm);
2369 else
2370 svm_disable_lbrv(svm);
2371 break;
2372 case MSR_VM_HSAVE_PA:
2373 svm->nested.hsave_msr = data;
2374 break;
2375 case MSR_VM_CR:
2376 case MSR_VM_IGNNE:
2377 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2378 break;
2379 default:
2380 return kvm_set_msr_common(vcpu, ecx, data);
2381 }
2382 return 0;
2383 }
2384
2385 static int wrmsr_interception(struct vcpu_svm *svm)
2386 {
2387 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2388 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2389 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2390
2391
2392 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2393 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2394 trace_kvm_msr_write_ex(ecx, data);
2395 kvm_inject_gp(&svm->vcpu, 0);
2396 } else {
2397 trace_kvm_msr_write(ecx, data);
2398 skip_emulated_instruction(&svm->vcpu);
2399 }
2400 return 1;
2401 }
2402
2403 static int msr_interception(struct vcpu_svm *svm)
2404 {
2405 if (svm->vmcb->control.exit_info_1)
2406 return wrmsr_interception(svm);
2407 else
2408 return rdmsr_interception(svm);
2409 }
2410
2411 static int interrupt_window_interception(struct vcpu_svm *svm)
2412 {
2413 struct kvm_run *kvm_run = svm->vcpu.run;
2414
2415 svm_clear_vintr(svm);
2416 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2417 /*
2418 * If the user space waits to inject interrupts, exit as soon as
2419 * possible
2420 */
2421 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2422 kvm_run->request_interrupt_window &&
2423 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2424 ++svm->vcpu.stat.irq_window_exits;
2425 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2426 return 0;
2427 }
2428
2429 return 1;
2430 }
2431
2432 static int pause_interception(struct vcpu_svm *svm)
2433 {
2434 kvm_vcpu_on_spin(&(svm->vcpu));
2435 return 1;
2436 }
2437
2438 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2439 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2440 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2441 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2442 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2443 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2444 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2445 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2446 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2447 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2448 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2449 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2450 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2451 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2452 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2453 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2454 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2455 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2456 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2457 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2458 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2459 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2460 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2461 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2462 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2463 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2464 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2465 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2466 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2467 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2468 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2469 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2470 [SVM_EXIT_INTR] = intr_interception,
2471 [SVM_EXIT_NMI] = nmi_interception,
2472 [SVM_EXIT_SMI] = nop_on_interception,
2473 [SVM_EXIT_INIT] = nop_on_interception,
2474 [SVM_EXIT_VINTR] = interrupt_window_interception,
2475 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2476 [SVM_EXIT_CPUID] = cpuid_interception,
2477 [SVM_EXIT_IRET] = iret_interception,
2478 [SVM_EXIT_INVD] = emulate_on_interception,
2479 [SVM_EXIT_PAUSE] = pause_interception,
2480 [SVM_EXIT_HLT] = halt_interception,
2481 [SVM_EXIT_INVLPG] = invlpg_interception,
2482 [SVM_EXIT_INVLPGA] = invlpga_interception,
2483 [SVM_EXIT_IOIO] = io_interception,
2484 [SVM_EXIT_MSR] = msr_interception,
2485 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2486 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2487 [SVM_EXIT_VMRUN] = vmrun_interception,
2488 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2489 [SVM_EXIT_VMLOAD] = vmload_interception,
2490 [SVM_EXIT_VMSAVE] = vmsave_interception,
2491 [SVM_EXIT_STGI] = stgi_interception,
2492 [SVM_EXIT_CLGI] = clgi_interception,
2493 [SVM_EXIT_SKINIT] = skinit_interception,
2494 [SVM_EXIT_WBINVD] = emulate_on_interception,
2495 [SVM_EXIT_MONITOR] = invalid_op_interception,
2496 [SVM_EXIT_MWAIT] = invalid_op_interception,
2497 [SVM_EXIT_NPF] = pf_interception,
2498 };
2499
2500 static int handle_exit(struct kvm_vcpu *vcpu)
2501 {
2502 struct vcpu_svm *svm = to_svm(vcpu);
2503 struct kvm_run *kvm_run = vcpu->run;
2504 u32 exit_code = svm->vmcb->control.exit_code;
2505
2506 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2507
2508 if (unlikely(svm->nested.exit_required)) {
2509 nested_svm_vmexit(svm);
2510 svm->nested.exit_required = false;
2511
2512 return 1;
2513 }
2514
2515 if (is_nested(svm)) {
2516 int vmexit;
2517
2518 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2519 svm->vmcb->control.exit_info_1,
2520 svm->vmcb->control.exit_info_2,
2521 svm->vmcb->control.exit_int_info,
2522 svm->vmcb->control.exit_int_info_err);
2523
2524 vmexit = nested_svm_exit_special(svm);
2525
2526 if (vmexit == NESTED_EXIT_CONTINUE)
2527 vmexit = nested_svm_exit_handled(svm);
2528
2529 if (vmexit == NESTED_EXIT_DONE)
2530 return 1;
2531 }
2532
2533 svm_complete_interrupts(svm);
2534
2535 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2536 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2537 if (npt_enabled)
2538 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2539
2540 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2541 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2542 kvm_run->fail_entry.hardware_entry_failure_reason
2543 = svm->vmcb->control.exit_code;
2544 return 0;
2545 }
2546
2547 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2548 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2549 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2550 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2551 "exit_code 0x%x\n",
2552 __func__, svm->vmcb->control.exit_int_info,
2553 exit_code);
2554
2555 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2556 || !svm_exit_handlers[exit_code]) {
2557 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2558 kvm_run->hw.hardware_exit_reason = exit_code;
2559 return 0;
2560 }
2561
2562 return svm_exit_handlers[exit_code](svm);
2563 }
2564
2565 static void reload_tss(struct kvm_vcpu *vcpu)
2566 {
2567 int cpu = raw_smp_processor_id();
2568
2569 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2570 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2571 load_TR_desc();
2572 }
2573
2574 static void pre_svm_run(struct vcpu_svm *svm)
2575 {
2576 int cpu = raw_smp_processor_id();
2577
2578 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2579
2580 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2581 /* FIXME: handle wraparound of asid_generation */
2582 if (svm->asid_generation != sd->asid_generation)
2583 new_asid(svm, sd);
2584 }
2585
2586 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2587 {
2588 struct vcpu_svm *svm = to_svm(vcpu);
2589
2590 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2591 vcpu->arch.hflags |= HF_NMI_MASK;
2592 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2593 ++vcpu->stat.nmi_injections;
2594 }
2595
2596 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2597 {
2598 struct vmcb_control_area *control;
2599
2600 trace_kvm_inj_virq(irq);
2601
2602 ++svm->vcpu.stat.irq_injections;
2603 control = &svm->vmcb->control;
2604 control->int_vector = irq;
2605 control->int_ctl &= ~V_INTR_PRIO_MASK;
2606 control->int_ctl |= V_IRQ_MASK |
2607 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2608 }
2609
2610 static void svm_set_irq(struct kvm_vcpu *vcpu)
2611 {
2612 struct vcpu_svm *svm = to_svm(vcpu);
2613
2614 BUG_ON(!(gif_set(svm)));
2615
2616 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2617 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2618 }
2619
2620 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2621 {
2622 struct vcpu_svm *svm = to_svm(vcpu);
2623
2624 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2625 return;
2626
2627 if (irr == -1)
2628 return;
2629
2630 if (tpr >= irr)
2631 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2632 }
2633
2634 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2635 {
2636 struct vcpu_svm *svm = to_svm(vcpu);
2637 struct vmcb *vmcb = svm->vmcb;
2638 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2639 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2640 }
2641
2642 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2643 {
2644 struct vcpu_svm *svm = to_svm(vcpu);
2645
2646 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2647 }
2648
2649 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2650 {
2651 struct vcpu_svm *svm = to_svm(vcpu);
2652
2653 if (masked) {
2654 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2655 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2656 } else {
2657 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2658 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2659 }
2660 }
2661
2662 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2663 {
2664 struct vcpu_svm *svm = to_svm(vcpu);
2665 struct vmcb *vmcb = svm->vmcb;
2666 int ret;
2667
2668 if (!gif_set(svm) ||
2669 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2670 return 0;
2671
2672 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2673
2674 if (is_nested(svm))
2675 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2676
2677 return ret;
2678 }
2679
2680 static void enable_irq_window(struct kvm_vcpu *vcpu)
2681 {
2682 struct vcpu_svm *svm = to_svm(vcpu);
2683
2684 /* In case GIF=0 we can't rely on the CPU to tell us when
2685 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2686 * The next time we get that intercept, this function will be
2687 * called again though and we'll get the vintr intercept. */
2688 if (gif_set(svm) && nested_svm_intr(svm)) {
2689 svm_set_vintr(svm);
2690 svm_inject_irq(svm, 0x0);
2691 }
2692 }
2693
2694 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2695 {
2696 struct vcpu_svm *svm = to_svm(vcpu);
2697
2698 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2699 == HF_NMI_MASK)
2700 return; /* IRET will cause a vm exit */
2701
2702 /* Something prevents NMI from been injected. Single step over
2703 possible problem (IRET or exception injection or interrupt
2704 shadow) */
2705 svm->nmi_singlestep = true;
2706 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2707 update_db_intercept(vcpu);
2708 }
2709
2710 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2711 {
2712 return 0;
2713 }
2714
2715 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2716 {
2717 force_new_asid(vcpu);
2718 }
2719
2720 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2721 {
2722 }
2723
2724 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2725 {
2726 struct vcpu_svm *svm = to_svm(vcpu);
2727
2728 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2729 return;
2730
2731 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2732 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2733 kvm_set_cr8(vcpu, cr8);
2734 }
2735 }
2736
2737 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2738 {
2739 struct vcpu_svm *svm = to_svm(vcpu);
2740 u64 cr8;
2741
2742 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2743 return;
2744
2745 cr8 = kvm_get_cr8(vcpu);
2746 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2747 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2748 }
2749
2750 static void svm_complete_interrupts(struct vcpu_svm *svm)
2751 {
2752 u8 vector;
2753 int type;
2754 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2755
2756 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2757 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2758
2759 svm->vcpu.arch.nmi_injected = false;
2760 kvm_clear_exception_queue(&svm->vcpu);
2761 kvm_clear_interrupt_queue(&svm->vcpu);
2762
2763 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2764 return;
2765
2766 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2767 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2768
2769 switch (type) {
2770 case SVM_EXITINTINFO_TYPE_NMI:
2771 svm->vcpu.arch.nmi_injected = true;
2772 break;
2773 case SVM_EXITINTINFO_TYPE_EXEPT:
2774 /* In case of software exception do not reinject an exception
2775 vector, but re-execute and instruction instead */
2776 if (is_nested(svm))
2777 break;
2778 if (kvm_exception_is_soft(vector))
2779 break;
2780 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2781 u32 err = svm->vmcb->control.exit_int_info_err;
2782 kvm_queue_exception_e(&svm->vcpu, vector, err);
2783
2784 } else
2785 kvm_queue_exception(&svm->vcpu, vector);
2786 break;
2787 case SVM_EXITINTINFO_TYPE_INTR:
2788 kvm_queue_interrupt(&svm->vcpu, vector, false);
2789 break;
2790 default:
2791 break;
2792 }
2793 }
2794
2795 #ifdef CONFIG_X86_64
2796 #define R "r"
2797 #else
2798 #define R "e"
2799 #endif
2800
2801 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2802 {
2803 struct vcpu_svm *svm = to_svm(vcpu);
2804 u16 fs_selector;
2805 u16 gs_selector;
2806 u16 ldt_selector;
2807
2808 /*
2809 * A vmexit emulation is required before the vcpu can be executed
2810 * again.
2811 */
2812 if (unlikely(svm->nested.exit_required))
2813 return;
2814
2815 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2816 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2817 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2818
2819 pre_svm_run(svm);
2820
2821 sync_lapic_to_cr8(vcpu);
2822
2823 save_host_msrs(vcpu);
2824 fs_selector = kvm_read_fs();
2825 gs_selector = kvm_read_gs();
2826 ldt_selector = kvm_read_ldt();
2827 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2828 /* required for live migration with NPT */
2829 if (npt_enabled)
2830 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2831
2832 clgi();
2833
2834 local_irq_enable();
2835
2836 asm volatile (
2837 "push %%"R"bp; \n\t"
2838 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2839 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2840 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2841 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2842 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2843 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2844 #ifdef CONFIG_X86_64
2845 "mov %c[r8](%[svm]), %%r8 \n\t"
2846 "mov %c[r9](%[svm]), %%r9 \n\t"
2847 "mov %c[r10](%[svm]), %%r10 \n\t"
2848 "mov %c[r11](%[svm]), %%r11 \n\t"
2849 "mov %c[r12](%[svm]), %%r12 \n\t"
2850 "mov %c[r13](%[svm]), %%r13 \n\t"
2851 "mov %c[r14](%[svm]), %%r14 \n\t"
2852 "mov %c[r15](%[svm]), %%r15 \n\t"
2853 #endif
2854
2855 /* Enter guest mode */
2856 "push %%"R"ax \n\t"
2857 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2858 __ex(SVM_VMLOAD) "\n\t"
2859 __ex(SVM_VMRUN) "\n\t"
2860 __ex(SVM_VMSAVE) "\n\t"
2861 "pop %%"R"ax \n\t"
2862
2863 /* Save guest registers, load host registers */
2864 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2865 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2866 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2867 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2868 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2869 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2870 #ifdef CONFIG_X86_64
2871 "mov %%r8, %c[r8](%[svm]) \n\t"
2872 "mov %%r9, %c[r9](%[svm]) \n\t"
2873 "mov %%r10, %c[r10](%[svm]) \n\t"
2874 "mov %%r11, %c[r11](%[svm]) \n\t"
2875 "mov %%r12, %c[r12](%[svm]) \n\t"
2876 "mov %%r13, %c[r13](%[svm]) \n\t"
2877 "mov %%r14, %c[r14](%[svm]) \n\t"
2878 "mov %%r15, %c[r15](%[svm]) \n\t"
2879 #endif
2880 "pop %%"R"bp"
2881 :
2882 : [svm]"a"(svm),
2883 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2884 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2885 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2886 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2887 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2888 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2889 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2890 #ifdef CONFIG_X86_64
2891 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2892 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2893 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2894 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2895 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2896 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2897 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2898 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2899 #endif
2900 : "cc", "memory"
2901 , R"bx", R"cx", R"dx", R"si", R"di"
2902 #ifdef CONFIG_X86_64
2903 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2904 #endif
2905 );
2906
2907 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2908 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2909 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2910 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2911
2912 kvm_load_fs(fs_selector);
2913 kvm_load_gs(gs_selector);
2914 kvm_load_ldt(ldt_selector);
2915 load_host_msrs(vcpu);
2916
2917 reload_tss(vcpu);
2918
2919 local_irq_disable();
2920
2921 stgi();
2922
2923 sync_cr8_to_lapic(vcpu);
2924
2925 svm->next_rip = 0;
2926
2927 if (npt_enabled) {
2928 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2929 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2930 }
2931
2932 /*
2933 * We need to handle MC intercepts here before the vcpu has a chance to
2934 * change the physical cpu
2935 */
2936 if (unlikely(svm->vmcb->control.exit_code ==
2937 SVM_EXIT_EXCP_BASE + MC_VECTOR))
2938 svm_handle_mce(svm);
2939 }
2940
2941 #undef R
2942
2943 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2944 {
2945 struct vcpu_svm *svm = to_svm(vcpu);
2946
2947 if (npt_enabled) {
2948 svm->vmcb->control.nested_cr3 = root;
2949 force_new_asid(vcpu);
2950 return;
2951 }
2952
2953 svm->vmcb->save.cr3 = root;
2954 force_new_asid(vcpu);
2955 }
2956
2957 static int is_disabled(void)
2958 {
2959 u64 vm_cr;
2960
2961 rdmsrl(MSR_VM_CR, vm_cr);
2962 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2963 return 1;
2964
2965 return 0;
2966 }
2967
2968 static void
2969 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2970 {
2971 /*
2972 * Patch in the VMMCALL instruction:
2973 */
2974 hypercall[0] = 0x0f;
2975 hypercall[1] = 0x01;
2976 hypercall[2] = 0xd9;
2977 }
2978
2979 static void svm_check_processor_compat(void *rtn)
2980 {
2981 *(int *)rtn = 0;
2982 }
2983
2984 static bool svm_cpu_has_accelerated_tpr(void)
2985 {
2986 return false;
2987 }
2988
2989 static int get_npt_level(void)
2990 {
2991 #ifdef CONFIG_X86_64
2992 return PT64_ROOT_LEVEL;
2993 #else
2994 return PT32E_ROOT_LEVEL;
2995 #endif
2996 }
2997
2998 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2999 {
3000 return 0;
3001 }
3002
3003 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3004 {
3005 }
3006
3007 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3008 {
3009 switch (func) {
3010 case 0x8000000A:
3011 entry->eax = 1; /* SVM revision 1 */
3012 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3013 ASID emulation to nested SVM */
3014 entry->ecx = 0; /* Reserved */
3015 entry->edx = 0; /* Do not support any additional features */
3016
3017 break;
3018 }
3019 }
3020
3021 static const struct trace_print_flags svm_exit_reasons_str[] = {
3022 { SVM_EXIT_READ_CR0, "read_cr0" },
3023 { SVM_EXIT_READ_CR3, "read_cr3" },
3024 { SVM_EXIT_READ_CR4, "read_cr4" },
3025 { SVM_EXIT_READ_CR8, "read_cr8" },
3026 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3027 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3028 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3029 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3030 { SVM_EXIT_READ_DR0, "read_dr0" },
3031 { SVM_EXIT_READ_DR1, "read_dr1" },
3032 { SVM_EXIT_READ_DR2, "read_dr2" },
3033 { SVM_EXIT_READ_DR3, "read_dr3" },
3034 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3035 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3036 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3037 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3038 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3039 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3040 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3041 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3042 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3043 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3044 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3045 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3046 { SVM_EXIT_INTR, "interrupt" },
3047 { SVM_EXIT_NMI, "nmi" },
3048 { SVM_EXIT_SMI, "smi" },
3049 { SVM_EXIT_INIT, "init" },
3050 { SVM_EXIT_VINTR, "vintr" },
3051 { SVM_EXIT_CPUID, "cpuid" },
3052 { SVM_EXIT_INVD, "invd" },
3053 { SVM_EXIT_HLT, "hlt" },
3054 { SVM_EXIT_INVLPG, "invlpg" },
3055 { SVM_EXIT_INVLPGA, "invlpga" },
3056 { SVM_EXIT_IOIO, "io" },
3057 { SVM_EXIT_MSR, "msr" },
3058 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3059 { SVM_EXIT_SHUTDOWN, "shutdown" },
3060 { SVM_EXIT_VMRUN, "vmrun" },
3061 { SVM_EXIT_VMMCALL, "hypercall" },
3062 { SVM_EXIT_VMLOAD, "vmload" },
3063 { SVM_EXIT_VMSAVE, "vmsave" },
3064 { SVM_EXIT_STGI, "stgi" },
3065 { SVM_EXIT_CLGI, "clgi" },
3066 { SVM_EXIT_SKINIT, "skinit" },
3067 { SVM_EXIT_WBINVD, "wbinvd" },
3068 { SVM_EXIT_MONITOR, "monitor" },
3069 { SVM_EXIT_MWAIT, "mwait" },
3070 { SVM_EXIT_NPF, "npf" },
3071 { -1, NULL }
3072 };
3073
3074 static int svm_get_lpage_level(void)
3075 {
3076 return PT_PDPE_LEVEL;
3077 }
3078
3079 static bool svm_rdtscp_supported(void)
3080 {
3081 return false;
3082 }
3083
3084 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3085 {
3086 struct vcpu_svm *svm = to_svm(vcpu);
3087
3088 update_cr0_intercept(svm);
3089 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3090 }
3091
3092 static struct kvm_x86_ops svm_x86_ops = {
3093 .cpu_has_kvm_support = has_svm,
3094 .disabled_by_bios = is_disabled,
3095 .hardware_setup = svm_hardware_setup,
3096 .hardware_unsetup = svm_hardware_unsetup,
3097 .check_processor_compatibility = svm_check_processor_compat,
3098 .hardware_enable = svm_hardware_enable,
3099 .hardware_disable = svm_hardware_disable,
3100 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3101
3102 .vcpu_create = svm_create_vcpu,
3103 .vcpu_free = svm_free_vcpu,
3104 .vcpu_reset = svm_vcpu_reset,
3105
3106 .prepare_guest_switch = svm_prepare_guest_switch,
3107 .vcpu_load = svm_vcpu_load,
3108 .vcpu_put = svm_vcpu_put,
3109
3110 .set_guest_debug = svm_guest_debug,
3111 .get_msr = svm_get_msr,
3112 .set_msr = svm_set_msr,
3113 .get_segment_base = svm_get_segment_base,
3114 .get_segment = svm_get_segment,
3115 .set_segment = svm_set_segment,
3116 .get_cpl = svm_get_cpl,
3117 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3118 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3119 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3120 .set_cr0 = svm_set_cr0,
3121 .set_cr3 = svm_set_cr3,
3122 .set_cr4 = svm_set_cr4,
3123 .set_efer = svm_set_efer,
3124 .get_idt = svm_get_idt,
3125 .set_idt = svm_set_idt,
3126 .get_gdt = svm_get_gdt,
3127 .set_gdt = svm_set_gdt,
3128 .get_dr = svm_get_dr,
3129 .set_dr = svm_set_dr,
3130 .cache_reg = svm_cache_reg,
3131 .get_rflags = svm_get_rflags,
3132 .set_rflags = svm_set_rflags,
3133 .fpu_activate = svm_fpu_activate,
3134 .fpu_deactivate = svm_fpu_deactivate,
3135
3136 .tlb_flush = svm_flush_tlb,
3137
3138 .run = svm_vcpu_run,
3139 .handle_exit = handle_exit,
3140 .skip_emulated_instruction = skip_emulated_instruction,
3141 .set_interrupt_shadow = svm_set_interrupt_shadow,
3142 .get_interrupt_shadow = svm_get_interrupt_shadow,
3143 .patch_hypercall = svm_patch_hypercall,
3144 .set_irq = svm_set_irq,
3145 .set_nmi = svm_inject_nmi,
3146 .queue_exception = svm_queue_exception,
3147 .interrupt_allowed = svm_interrupt_allowed,
3148 .nmi_allowed = svm_nmi_allowed,
3149 .get_nmi_mask = svm_get_nmi_mask,
3150 .set_nmi_mask = svm_set_nmi_mask,
3151 .enable_nmi_window = enable_nmi_window,
3152 .enable_irq_window = enable_irq_window,
3153 .update_cr8_intercept = update_cr8_intercept,
3154
3155 .set_tss_addr = svm_set_tss_addr,
3156 .get_tdp_level = get_npt_level,
3157 .get_mt_mask = svm_get_mt_mask,
3158
3159 .exit_reasons_str = svm_exit_reasons_str,
3160 .get_lpage_level = svm_get_lpage_level,
3161
3162 .cpuid_update = svm_cpuid_update,
3163
3164 .rdtscp_supported = svm_rdtscp_supported,
3165
3166 .set_supported_cpuid = svm_set_supported_cpuid,
3167 };
3168
3169 static int __init svm_init(void)
3170 {
3171 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3172 THIS_MODULE);
3173 }
3174
3175 static void __exit svm_exit(void)
3176 {
3177 kvm_exit();
3178 }
3179
3180 module_init(svm_init)
3181 module_exit(svm_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree