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Revert "iwlagn: Support new 5000 microcode."
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / skge.c
blob5b07e002f4e9079aeab31b92967c679a390dbdd1
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/in.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
35 #include <linux/ip.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/debugfs.h>
40 #include <linux/sched.h>
41 #include <linux/seq_file.h>
42 #include <linux/mii.h>
43 #include <linux/dmi.h>
44 #include <asm/irq.h>
45
46 #include "skge.h"
47
48 #define DRV_NAME "skge"
49 #define DRV_VERSION "1.13"
50 #define PFX DRV_NAME " "
51
52 #define DEFAULT_TX_RING_SIZE 128
53 #define DEFAULT_RX_RING_SIZE 512
54 #define MAX_TX_RING_SIZE 1024
55 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
56 #define MAX_RX_RING_SIZE 4096
57 #define RX_COPY_THRESHOLD 128
58 #define RX_BUF_SIZE 1536
59 #define PHY_RETRIES 1000
60 #define ETH_JUMBO_MTU 9000
61 #define TX_WATCHDOG (5 * HZ)
62 #define NAPI_WEIGHT 64
63 #define BLINK_MS 250
64 #define LINK_HZ HZ
65
66 #define SKGE_EEPROM_MAGIC 0x9933aabb
67
68
69 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
70 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
71 MODULE_LICENSE("GPL");
72 MODULE_VERSION(DRV_VERSION);
73
74 static const u32 default_msg
75 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
76 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
77
78 static int debug = -1; /* defaults above */
79 module_param(debug, int, 0);
80 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
81
82 static const struct pci_device_id skge_id_table[] = {
83 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
84 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
85 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
86 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
87 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
88 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
89 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
90 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
91 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
92 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
93 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
94 { 0 }
95 };
96 MODULE_DEVICE_TABLE(pci, skge_id_table);
97
98 static int skge_up(struct net_device *dev);
99 static int skge_down(struct net_device *dev);
100 static void skge_phy_reset(struct skge_port *skge);
101 static void skge_tx_clean(struct net_device *dev);
102 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
103 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
104 static void genesis_get_stats(struct skge_port *skge, u64 *data);
105 static void yukon_get_stats(struct skge_port *skge, u64 *data);
106 static void yukon_init(struct skge_hw *hw, int port);
107 static void genesis_mac_init(struct skge_hw *hw, int port);
108 static void genesis_link_up(struct skge_port *skge);
109 static void skge_set_multicast(struct net_device *dev);
110
111 /* Avoid conditionals by using array */
112 static const int txqaddr[] = { Q_XA1, Q_XA2 };
113 static const int rxqaddr[] = { Q_R1, Q_R2 };
114 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
115 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
116 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
117 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
118
119 static int skge_get_regs_len(struct net_device *dev)
120 {
121 return 0x4000;
122 }
123
124 /*
125 * Returns copy of whole control register region
126 * Note: skip RAM address register because accessing it will
127 * cause bus hangs!
128 */
129 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
130 void *p)
131 {
132 const struct skge_port *skge = netdev_priv(dev);
133 const void __iomem *io = skge->hw->regs;
134
135 regs->version = 1;
136 memset(p, 0, regs->len);
137 memcpy_fromio(p, io, B3_RAM_ADDR);
138
139 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
140 regs->len - B3_RI_WTO_R1);
141 }
142
143 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
144 static u32 wol_supported(const struct skge_hw *hw)
145 {
146 if (hw->chip_id == CHIP_ID_GENESIS)
147 return 0;
148
149 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
150 return 0;
151
152 return WAKE_MAGIC | WAKE_PHY;
153 }
154
155 static void skge_wol_init(struct skge_port *skge)
156 {
157 struct skge_hw *hw = skge->hw;
158 int port = skge->port;
159 u16 ctrl;
160
161 skge_write16(hw, B0_CTST, CS_RST_CLR);
162 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
163
164 /* Turn on Vaux */
165 skge_write8(hw, B0_POWER_CTRL,
166 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
167
168 /* WA code for COMA mode -- clear PHY reset */
169 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
170 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
171 u32 reg = skge_read32(hw, B2_GP_IO);
172 reg |= GP_DIR_9;
173 reg &= ~GP_IO_9;
174 skge_write32(hw, B2_GP_IO, reg);
175 }
176
177 skge_write32(hw, SK_REG(port, GPHY_CTRL),
178 GPC_DIS_SLEEP |
179 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
180 GPC_ANEG_1 | GPC_RST_SET);
181
182 skge_write32(hw, SK_REG(port, GPHY_CTRL),
183 GPC_DIS_SLEEP |
184 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
185 GPC_ANEG_1 | GPC_RST_CLR);
186
187 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
188
189 /* Force to 10/100 skge_reset will re-enable on resume */
190 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
191 PHY_AN_100FULL | PHY_AN_100HALF |
192 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
193 /* no 1000 HD/FD */
194 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
195 gm_phy_write(hw, port, PHY_MARV_CTRL,
196 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
197 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
198
199
200 /* Set GMAC to no flow control and auto update for speed/duplex */
201 gma_write16(hw, port, GM_GP_CTRL,
202 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
203 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
204
205 /* Set WOL address */
206 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
207 skge->netdev->dev_addr, ETH_ALEN);
208
209 /* Turn on appropriate WOL control bits */
210 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
211 ctrl = 0;
212 if (skge->wol & WAKE_PHY)
213 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
214 else
215 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
216
217 if (skge->wol & WAKE_MAGIC)
218 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
219 else
220 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
221
222 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
223 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
224
225 /* block receiver */
226 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
227 }
228
229 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
230 {
231 struct skge_port *skge = netdev_priv(dev);
232
233 wol->supported = wol_supported(skge->hw);
234 wol->wolopts = skge->wol;
235 }
236
237 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
238 {
239 struct skge_port *skge = netdev_priv(dev);
240 struct skge_hw *hw = skge->hw;
241
242 if ((wol->wolopts & ~wol_supported(hw))
243 || !device_can_wakeup(&hw->pdev->dev))
244 return -EOPNOTSUPP;
245
246 skge->wol = wol->wolopts;
247
248 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
249
250 return 0;
251 }
252
253 /* Determine supported/advertised modes based on hardware.
254 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
255 */
256 static u32 skge_supported_modes(const struct skge_hw *hw)
257 {
258 u32 supported;
259
260 if (hw->copper) {
261 supported = SUPPORTED_10baseT_Half
262 | SUPPORTED_10baseT_Full
263 | SUPPORTED_100baseT_Half
264 | SUPPORTED_100baseT_Full
265 | SUPPORTED_1000baseT_Half
266 | SUPPORTED_1000baseT_Full
267 | SUPPORTED_Autoneg| SUPPORTED_TP;
268
269 if (hw->chip_id == CHIP_ID_GENESIS)
270 supported &= ~(SUPPORTED_10baseT_Half
271 | SUPPORTED_10baseT_Full
272 | SUPPORTED_100baseT_Half
273 | SUPPORTED_100baseT_Full);
274
275 else if (hw->chip_id == CHIP_ID_YUKON)
276 supported &= ~SUPPORTED_1000baseT_Half;
277 } else
278 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
279 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
280
281 return supported;
282 }
283
284 static int skge_get_settings(struct net_device *dev,
285 struct ethtool_cmd *ecmd)
286 {
287 struct skge_port *skge = netdev_priv(dev);
288 struct skge_hw *hw = skge->hw;
289
290 ecmd->transceiver = XCVR_INTERNAL;
291 ecmd->supported = skge_supported_modes(hw);
292
293 if (hw->copper) {
294 ecmd->port = PORT_TP;
295 ecmd->phy_address = hw->phy_addr;
296 } else
297 ecmd->port = PORT_FIBRE;
298
299 ecmd->advertising = skge->advertising;
300 ecmd->autoneg = skge->autoneg;
301 ecmd->speed = skge->speed;
302 ecmd->duplex = skge->duplex;
303 return 0;
304 }
305
306 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
307 {
308 struct skge_port *skge = netdev_priv(dev);
309 const struct skge_hw *hw = skge->hw;
310 u32 supported = skge_supported_modes(hw);
311 int err = 0;
312
313 if (ecmd->autoneg == AUTONEG_ENABLE) {
314 ecmd->advertising = supported;
315 skge->duplex = -1;
316 skge->speed = -1;
317 } else {
318 u32 setting;
319
320 switch (ecmd->speed) {
321 case SPEED_1000:
322 if (ecmd->duplex == DUPLEX_FULL)
323 setting = SUPPORTED_1000baseT_Full;
324 else if (ecmd->duplex == DUPLEX_HALF)
325 setting = SUPPORTED_1000baseT_Half;
326 else
327 return -EINVAL;
328 break;
329 case SPEED_100:
330 if (ecmd->duplex == DUPLEX_FULL)
331 setting = SUPPORTED_100baseT_Full;
332 else if (ecmd->duplex == DUPLEX_HALF)
333 setting = SUPPORTED_100baseT_Half;
334 else
335 return -EINVAL;
336 break;
337
338 case SPEED_10:
339 if (ecmd->duplex == DUPLEX_FULL)
340 setting = SUPPORTED_10baseT_Full;
341 else if (ecmd->duplex == DUPLEX_HALF)
342 setting = SUPPORTED_10baseT_Half;
343 else
344 return -EINVAL;
345 break;
346 default:
347 return -EINVAL;
348 }
349
350 if ((setting & supported) == 0)
351 return -EINVAL;
352
353 skge->speed = ecmd->speed;
354 skge->duplex = ecmd->duplex;
355 }
356
357 skge->autoneg = ecmd->autoneg;
358 skge->advertising = ecmd->advertising;
359
360 if (netif_running(dev)) {
361 skge_down(dev);
362 err = skge_up(dev);
363 if (err) {
364 dev_close(dev);
365 return err;
366 }
367 }
368
369 return (0);
370 }
371
372 static void skge_get_drvinfo(struct net_device *dev,
373 struct ethtool_drvinfo *info)
374 {
375 struct skge_port *skge = netdev_priv(dev);
376
377 strcpy(info->driver, DRV_NAME);
378 strcpy(info->version, DRV_VERSION);
379 strcpy(info->fw_version, "N/A");
380 strcpy(info->bus_info, pci_name(skge->hw->pdev));
381 }
382
383 static const struct skge_stat {
384 char name[ETH_GSTRING_LEN];
385 u16 xmac_offset;
386 u16 gma_offset;
387 } skge_stats[] = {
388 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
389 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
390
391 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
392 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
393 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
394 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
395 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
396 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
397 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
398 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
399
400 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
401 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
402 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
403 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
404 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
405 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
406
407 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
408 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
409 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
410 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
411 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
412 };
413
414 static int skge_get_sset_count(struct net_device *dev, int sset)
415 {
416 switch (sset) {
417 case ETH_SS_STATS:
418 return ARRAY_SIZE(skge_stats);
419 default:
420 return -EOPNOTSUPP;
421 }
422 }
423
424 static void skge_get_ethtool_stats(struct net_device *dev,
425 struct ethtool_stats *stats, u64 *data)
426 {
427 struct skge_port *skge = netdev_priv(dev);
428
429 if (skge->hw->chip_id == CHIP_ID_GENESIS)
430 genesis_get_stats(skge, data);
431 else
432 yukon_get_stats(skge, data);
433 }
434
435 /* Use hardware MIB variables for critical path statistics and
436 * transmit feedback not reported at interrupt.
437 * Other errors are accounted for in interrupt handler.
438 */
439 static struct net_device_stats *skge_get_stats(struct net_device *dev)
440 {
441 struct skge_port *skge = netdev_priv(dev);
442 u64 data[ARRAY_SIZE(skge_stats)];
443
444 if (skge->hw->chip_id == CHIP_ID_GENESIS)
445 genesis_get_stats(skge, data);
446 else
447 yukon_get_stats(skge, data);
448
449 dev->stats.tx_bytes = data[0];
450 dev->stats.rx_bytes = data[1];
451 dev->stats.tx_packets = data[2] + data[4] + data[6];
452 dev->stats.rx_packets = data[3] + data[5] + data[7];
453 dev->stats.multicast = data[3] + data[5];
454 dev->stats.collisions = data[10];
455 dev->stats.tx_aborted_errors = data[12];
456
457 return &dev->stats;
458 }
459
460 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
461 {
462 int i;
463
464 switch (stringset) {
465 case ETH_SS_STATS:
466 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
467 memcpy(data + i * ETH_GSTRING_LEN,
468 skge_stats[i].name, ETH_GSTRING_LEN);
469 break;
470 }
471 }
472
473 static void skge_get_ring_param(struct net_device *dev,
474 struct ethtool_ringparam *p)
475 {
476 struct skge_port *skge = netdev_priv(dev);
477
478 p->rx_max_pending = MAX_RX_RING_SIZE;
479 p->tx_max_pending = MAX_TX_RING_SIZE;
480 p->rx_mini_max_pending = 0;
481 p->rx_jumbo_max_pending = 0;
482
483 p->rx_pending = skge->rx_ring.count;
484 p->tx_pending = skge->tx_ring.count;
485 p->rx_mini_pending = 0;
486 p->rx_jumbo_pending = 0;
487 }
488
489 static int skge_set_ring_param(struct net_device *dev,
490 struct ethtool_ringparam *p)
491 {
492 struct skge_port *skge = netdev_priv(dev);
493 int err = 0;
494
495 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
496 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
497 return -EINVAL;
498
499 skge->rx_ring.count = p->rx_pending;
500 skge->tx_ring.count = p->tx_pending;
501
502 if (netif_running(dev)) {
503 skge_down(dev);
504 err = skge_up(dev);
505 if (err)
506 dev_close(dev);
507 }
508
509 return err;
510 }
511
512 static u32 skge_get_msglevel(struct net_device *netdev)
513 {
514 struct skge_port *skge = netdev_priv(netdev);
515 return skge->msg_enable;
516 }
517
518 static void skge_set_msglevel(struct net_device *netdev, u32 value)
519 {
520 struct skge_port *skge = netdev_priv(netdev);
521 skge->msg_enable = value;
522 }
523
524 static int skge_nway_reset(struct net_device *dev)
525 {
526 struct skge_port *skge = netdev_priv(dev);
527
528 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
529 return -EINVAL;
530
531 skge_phy_reset(skge);
532 return 0;
533 }
534
535 static int skge_set_sg(struct net_device *dev, u32 data)
536 {
537 struct skge_port *skge = netdev_priv(dev);
538 struct skge_hw *hw = skge->hw;
539
540 if (hw->chip_id == CHIP_ID_GENESIS && data)
541 return -EOPNOTSUPP;
542 return ethtool_op_set_sg(dev, data);
543 }
544
545 static int skge_set_tx_csum(struct net_device *dev, u32 data)
546 {
547 struct skge_port *skge = netdev_priv(dev);
548 struct skge_hw *hw = skge->hw;
549
550 if (hw->chip_id == CHIP_ID_GENESIS && data)
551 return -EOPNOTSUPP;
552
553 return ethtool_op_set_tx_csum(dev, data);
554 }
555
556 static u32 skge_get_rx_csum(struct net_device *dev)
557 {
558 struct skge_port *skge = netdev_priv(dev);
559
560 return skge->rx_csum;
561 }
562
563 /* Only Yukon supports checksum offload. */
564 static int skge_set_rx_csum(struct net_device *dev, u32 data)
565 {
566 struct skge_port *skge = netdev_priv(dev);
567
568 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
569 return -EOPNOTSUPP;
570
571 skge->rx_csum = data;
572 return 0;
573 }
574
575 static void skge_get_pauseparam(struct net_device *dev,
576 struct ethtool_pauseparam *ecmd)
577 {
578 struct skge_port *skge = netdev_priv(dev);
579
580 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
581 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
582 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
583
584 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
585 }
586
587 static int skge_set_pauseparam(struct net_device *dev,
588 struct ethtool_pauseparam *ecmd)
589 {
590 struct skge_port *skge = netdev_priv(dev);
591 struct ethtool_pauseparam old;
592 int err = 0;
593
594 skge_get_pauseparam(dev, &old);
595
596 if (ecmd->autoneg != old.autoneg)
597 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
598 else {
599 if (ecmd->rx_pause && ecmd->tx_pause)
600 skge->flow_control = FLOW_MODE_SYMMETRIC;
601 else if (ecmd->rx_pause && !ecmd->tx_pause)
602 skge->flow_control = FLOW_MODE_SYM_OR_REM;
603 else if (!ecmd->rx_pause && ecmd->tx_pause)
604 skge->flow_control = FLOW_MODE_LOC_SEND;
605 else
606 skge->flow_control = FLOW_MODE_NONE;
607 }
608
609 if (netif_running(dev)) {
610 skge_down(dev);
611 err = skge_up(dev);
612 if (err) {
613 dev_close(dev);
614 return err;
615 }
616 }
617
618 return 0;
619 }
620
621 /* Chip internal frequency for clock calculations */
622 static inline u32 hwkhz(const struct skge_hw *hw)
623 {
624 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
625 }
626
627 /* Chip HZ to microseconds */
628 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
629 {
630 return (ticks * 1000) / hwkhz(hw);
631 }
632
633 /* Microseconds to chip HZ */
634 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
635 {
636 return hwkhz(hw) * usec / 1000;
637 }
638
639 static int skge_get_coalesce(struct net_device *dev,
640 struct ethtool_coalesce *ecmd)
641 {
642 struct skge_port *skge = netdev_priv(dev);
643 struct skge_hw *hw = skge->hw;
644 int port = skge->port;
645
646 ecmd->rx_coalesce_usecs = 0;
647 ecmd->tx_coalesce_usecs = 0;
648
649 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
650 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
651 u32 msk = skge_read32(hw, B2_IRQM_MSK);
652
653 if (msk & rxirqmask[port])
654 ecmd->rx_coalesce_usecs = delay;
655 if (msk & txirqmask[port])
656 ecmd->tx_coalesce_usecs = delay;
657 }
658
659 return 0;
660 }
661
662 /* Note: interrupt timer is per board, but can turn on/off per port */
663 static int skge_set_coalesce(struct net_device *dev,
664 struct ethtool_coalesce *ecmd)
665 {
666 struct skge_port *skge = netdev_priv(dev);
667 struct skge_hw *hw = skge->hw;
668 int port = skge->port;
669 u32 msk = skge_read32(hw, B2_IRQM_MSK);
670 u32 delay = 25;
671
672 if (ecmd->rx_coalesce_usecs == 0)
673 msk &= ~rxirqmask[port];
674 else if (ecmd->rx_coalesce_usecs < 25 ||
675 ecmd->rx_coalesce_usecs > 33333)
676 return -EINVAL;
677 else {
678 msk |= rxirqmask[port];
679 delay = ecmd->rx_coalesce_usecs;
680 }
681
682 if (ecmd->tx_coalesce_usecs == 0)
683 msk &= ~txirqmask[port];
684 else if (ecmd->tx_coalesce_usecs < 25 ||
685 ecmd->tx_coalesce_usecs > 33333)
686 return -EINVAL;
687 else {
688 msk |= txirqmask[port];
689 delay = min(delay, ecmd->rx_coalesce_usecs);
690 }
691
692 skge_write32(hw, B2_IRQM_MSK, msk);
693 if (msk == 0)
694 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
695 else {
696 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
697 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
698 }
699 return 0;
700 }
701
702 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
703 static void skge_led(struct skge_port *skge, enum led_mode mode)
704 {
705 struct skge_hw *hw = skge->hw;
706 int port = skge->port;
707
708 spin_lock_bh(&hw->phy_lock);
709 if (hw->chip_id == CHIP_ID_GENESIS) {
710 switch (mode) {
711 case LED_MODE_OFF:
712 if (hw->phy_type == SK_PHY_BCOM)
713 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
714 else {
715 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
716 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
717 }
718 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
719 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
720 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
721 break;
722
723 case LED_MODE_ON:
724 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
725 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
726
727 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
728 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
729
730 break;
731
732 case LED_MODE_TST:
733 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
734 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
735 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
736
737 if (hw->phy_type == SK_PHY_BCOM)
738 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
739 else {
740 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
741 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
742 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
743 }
744
745 }
746 } else {
747 switch (mode) {
748 case LED_MODE_OFF:
749 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
750 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
751 PHY_M_LED_MO_DUP(MO_LED_OFF) |
752 PHY_M_LED_MO_10(MO_LED_OFF) |
753 PHY_M_LED_MO_100(MO_LED_OFF) |
754 PHY_M_LED_MO_1000(MO_LED_OFF) |
755 PHY_M_LED_MO_RX(MO_LED_OFF));
756 break;
757 case LED_MODE_ON:
758 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
759 PHY_M_LED_PULS_DUR(PULS_170MS) |
760 PHY_M_LED_BLINK_RT(BLINK_84MS) |
761 PHY_M_LEDC_TX_CTRL |
762 PHY_M_LEDC_DP_CTRL);
763
764 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
765 PHY_M_LED_MO_RX(MO_LED_OFF) |
766 (skge->speed == SPEED_100 ?
767 PHY_M_LED_MO_100(MO_LED_ON) : 0));
768 break;
769 case LED_MODE_TST:
770 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
771 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
772 PHY_M_LED_MO_DUP(MO_LED_ON) |
773 PHY_M_LED_MO_10(MO_LED_ON) |
774 PHY_M_LED_MO_100(MO_LED_ON) |
775 PHY_M_LED_MO_1000(MO_LED_ON) |
776 PHY_M_LED_MO_RX(MO_LED_ON));
777 }
778 }
779 spin_unlock_bh(&hw->phy_lock);
780 }
781
782 /* blink LED's for finding board */
783 static int skge_phys_id(struct net_device *dev, u32 data)
784 {
785 struct skge_port *skge = netdev_priv(dev);
786 unsigned long ms;
787 enum led_mode mode = LED_MODE_TST;
788
789 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
790 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
791 else
792 ms = data * 1000;
793
794 while (ms > 0) {
795 skge_led(skge, mode);
796 mode ^= LED_MODE_TST;
797
798 if (msleep_interruptible(BLINK_MS))
799 break;
800 ms -= BLINK_MS;
801 }
802
803 /* back to regular LED state */
804 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
805
806 return 0;
807 }
808
809 static int skge_get_eeprom_len(struct net_device *dev)
810 {
811 struct skge_port *skge = netdev_priv(dev);
812 u32 reg2;
813
814 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
815 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
816 }
817
818 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
819 {
820 u32 val;
821
822 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
823
824 do {
825 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
826 } while (!(offset & PCI_VPD_ADDR_F));
827
828 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
829 return val;
830 }
831
832 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
833 {
834 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
835 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
836 offset | PCI_VPD_ADDR_F);
837
838 do {
839 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
840 } while (offset & PCI_VPD_ADDR_F);
841 }
842
843 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
844 u8 *data)
845 {
846 struct skge_port *skge = netdev_priv(dev);
847 struct pci_dev *pdev = skge->hw->pdev;
848 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
849 int length = eeprom->len;
850 u16 offset = eeprom->offset;
851
852 if (!cap)
853 return -EINVAL;
854
855 eeprom->magic = SKGE_EEPROM_MAGIC;
856
857 while (length > 0) {
858 u32 val = skge_vpd_read(pdev, cap, offset);
859 int n = min_t(int, length, sizeof(val));
860
861 memcpy(data, &val, n);
862 length -= n;
863 data += n;
864 offset += n;
865 }
866 return 0;
867 }
868
869 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
870 u8 *data)
871 {
872 struct skge_port *skge = netdev_priv(dev);
873 struct pci_dev *pdev = skge->hw->pdev;
874 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
875 int length = eeprom->len;
876 u16 offset = eeprom->offset;
877
878 if (!cap)
879 return -EINVAL;
880
881 if (eeprom->magic != SKGE_EEPROM_MAGIC)
882 return -EINVAL;
883
884 while (length > 0) {
885 u32 val;
886 int n = min_t(int, length, sizeof(val));
887
888 if (n < sizeof(val))
889 val = skge_vpd_read(pdev, cap, offset);
890 memcpy(&val, data, n);
891
892 skge_vpd_write(pdev, cap, offset, val);
893
894 length -= n;
895 data += n;
896 offset += n;
897 }
898 return 0;
899 }
900
901 static const struct ethtool_ops skge_ethtool_ops = {
902 .get_settings = skge_get_settings,
903 .set_settings = skge_set_settings,
904 .get_drvinfo = skge_get_drvinfo,
905 .get_regs_len = skge_get_regs_len,
906 .get_regs = skge_get_regs,
907 .get_wol = skge_get_wol,
908 .set_wol = skge_set_wol,
909 .get_msglevel = skge_get_msglevel,
910 .set_msglevel = skge_set_msglevel,
911 .nway_reset = skge_nway_reset,
912 .get_link = ethtool_op_get_link,
913 .get_eeprom_len = skge_get_eeprom_len,
914 .get_eeprom = skge_get_eeprom,
915 .set_eeprom = skge_set_eeprom,
916 .get_ringparam = skge_get_ring_param,
917 .set_ringparam = skge_set_ring_param,
918 .get_pauseparam = skge_get_pauseparam,
919 .set_pauseparam = skge_set_pauseparam,
920 .get_coalesce = skge_get_coalesce,
921 .set_coalesce = skge_set_coalesce,
922 .set_sg = skge_set_sg,
923 .set_tx_csum = skge_set_tx_csum,
924 .get_rx_csum = skge_get_rx_csum,
925 .set_rx_csum = skge_set_rx_csum,
926 .get_strings = skge_get_strings,
927 .phys_id = skge_phys_id,
928 .get_sset_count = skge_get_sset_count,
929 .get_ethtool_stats = skge_get_ethtool_stats,
930 };
931
932 /*
933 * Allocate ring elements and chain them together
934 * One-to-one association of board descriptors with ring elements
935 */
936 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
937 {
938 struct skge_tx_desc *d;
939 struct skge_element *e;
940 int i;
941
942 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
943 if (!ring->start)
944 return -ENOMEM;
945
946 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
947 e->desc = d;
948 if (i == ring->count - 1) {
949 e->next = ring->start;
950 d->next_offset = base;
951 } else {
952 e->next = e + 1;
953 d->next_offset = base + (i+1) * sizeof(*d);
954 }
955 }
956 ring->to_use = ring->to_clean = ring->start;
957
958 return 0;
959 }
960
961 /* Allocate and setup a new buffer for receiving */
962 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
963 struct sk_buff *skb, unsigned int bufsize)
964 {
965 struct skge_rx_desc *rd = e->desc;
966 u64 map;
967
968 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
969 PCI_DMA_FROMDEVICE);
970
971 rd->dma_lo = map;
972 rd->dma_hi = map >> 32;
973 e->skb = skb;
974 rd->csum1_start = ETH_HLEN;
975 rd->csum2_start = ETH_HLEN;
976 rd->csum1 = 0;
977 rd->csum2 = 0;
978
979 wmb();
980
981 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
982 pci_unmap_addr_set(e, mapaddr, map);
983 pci_unmap_len_set(e, maplen, bufsize);
984 }
985
986 /* Resume receiving using existing skb,
987 * Note: DMA address is not changed by chip.
988 * MTU not changed while receiver active.
989 */
990 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
991 {
992 struct skge_rx_desc *rd = e->desc;
993
994 rd->csum2 = 0;
995 rd->csum2_start = ETH_HLEN;
996
997 wmb();
998
999 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
1000 }
1001
1002
1003 /* Free all buffers in receive ring, assumes receiver stopped */
1004 static void skge_rx_clean(struct skge_port *skge)
1005 {
1006 struct skge_hw *hw = skge->hw;
1007 struct skge_ring *ring = &skge->rx_ring;
1008 struct skge_element *e;
1009
1010 e = ring->start;
1011 do {
1012 struct skge_rx_desc *rd = e->desc;
1013 rd->control = 0;
1014 if (e->skb) {
1015 pci_unmap_single(hw->pdev,
1016 pci_unmap_addr(e, mapaddr),
1017 pci_unmap_len(e, maplen),
1018 PCI_DMA_FROMDEVICE);
1019 dev_kfree_skb(e->skb);
1020 e->skb = NULL;
1021 }
1022 } while ((e = e->next) != ring->start);
1023 }
1024
1025
1026 /* Allocate buffers for receive ring
1027 * For receive: to_clean is next received frame.
1028 */
1029 static int skge_rx_fill(struct net_device *dev)
1030 {
1031 struct skge_port *skge = netdev_priv(dev);
1032 struct skge_ring *ring = &skge->rx_ring;
1033 struct skge_element *e;
1034
1035 e = ring->start;
1036 do {
1037 struct sk_buff *skb;
1038
1039 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1040 GFP_KERNEL);
1041 if (!skb)
1042 return -ENOMEM;
1043
1044 skb_reserve(skb, NET_IP_ALIGN);
1045 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
1046 } while ( (e = e->next) != ring->start);
1047
1048 ring->to_clean = ring->start;
1049 return 0;
1050 }
1051
1052 static const char *skge_pause(enum pause_status status)
1053 {
1054 switch(status) {
1055 case FLOW_STAT_NONE:
1056 return "none";
1057 case FLOW_STAT_REM_SEND:
1058 return "rx only";
1059 case FLOW_STAT_LOC_SEND:
1060 return "tx_only";
1061 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1062 return "both";
1063 default:
1064 return "indeterminated";
1065 }
1066 }
1067
1068
1069 static void skge_link_up(struct skge_port *skge)
1070 {
1071 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1072 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1073
1074 netif_carrier_on(skge->netdev);
1075 netif_wake_queue(skge->netdev);
1076
1077 if (netif_msg_link(skge)) {
1078 printk(KERN_INFO PFX
1079 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1080 skge->netdev->name, skge->speed,
1081 skge->duplex == DUPLEX_FULL ? "full" : "half",
1082 skge_pause(skge->flow_status));
1083 }
1084 }
1085
1086 static void skge_link_down(struct skge_port *skge)
1087 {
1088 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1089 netif_carrier_off(skge->netdev);
1090 netif_stop_queue(skge->netdev);
1091
1092 if (netif_msg_link(skge))
1093 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
1094 }
1095
1096
1097 static void xm_link_down(struct skge_hw *hw, int port)
1098 {
1099 struct net_device *dev = hw->dev[port];
1100 struct skge_port *skge = netdev_priv(dev);
1101
1102 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1103
1104 if (netif_carrier_ok(dev))
1105 skge_link_down(skge);
1106 }
1107
1108 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1109 {
1110 int i;
1111
1112 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1113 *val = xm_read16(hw, port, XM_PHY_DATA);
1114
1115 if (hw->phy_type == SK_PHY_XMAC)
1116 goto ready;
1117
1118 for (i = 0; i < PHY_RETRIES; i++) {
1119 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1120 goto ready;
1121 udelay(1);
1122 }
1123
1124 return -ETIMEDOUT;
1125 ready:
1126 *val = xm_read16(hw, port, XM_PHY_DATA);
1127
1128 return 0;
1129 }
1130
1131 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1132 {
1133 u16 v = 0;
1134 if (__xm_phy_read(hw, port, reg, &v))
1135 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1136 hw->dev[port]->name);
1137 return v;
1138 }
1139
1140 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1141 {
1142 int i;
1143
1144 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1145 for (i = 0; i < PHY_RETRIES; i++) {
1146 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1147 goto ready;
1148 udelay(1);
1149 }
1150 return -EIO;
1151
1152 ready:
1153 xm_write16(hw, port, XM_PHY_DATA, val);
1154 for (i = 0; i < PHY_RETRIES; i++) {
1155 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1156 return 0;
1157 udelay(1);
1158 }
1159 return -ETIMEDOUT;
1160 }
1161
1162 static void genesis_init(struct skge_hw *hw)
1163 {
1164 /* set blink source counter */
1165 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1166 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1167
1168 /* configure mac arbiter */
1169 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1170
1171 /* configure mac arbiter timeout values */
1172 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1173 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1174 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1175 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1176
1177 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1178 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1179 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1180 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1181
1182 /* configure packet arbiter timeout */
1183 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1184 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1185 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1186 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1187 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1188 }
1189
1190 static void genesis_reset(struct skge_hw *hw, int port)
1191 {
1192 const u8 zero[8] = { 0 };
1193 u32 reg;
1194
1195 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1196
1197 /* reset the statistics module */
1198 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1199 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1200 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1201 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1202 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1203
1204 /* disable Broadcom PHY IRQ */
1205 if (hw->phy_type == SK_PHY_BCOM)
1206 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1207
1208 xm_outhash(hw, port, XM_HSM, zero);
1209
1210 /* Flush TX and RX fifo */
1211 reg = xm_read32(hw, port, XM_MODE);
1212 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1213 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1214 }
1215
1216
1217 /* Convert mode to MII values */
1218 static const u16 phy_pause_map[] = {
1219 [FLOW_MODE_NONE] = 0,
1220 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1221 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1222 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1223 };
1224
1225 /* special defines for FIBER (88E1011S only) */
1226 static const u16 fiber_pause_map[] = {
1227 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1228 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1229 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1230 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1231 };
1232
1233
1234 /* Check status of Broadcom phy link */
1235 static void bcom_check_link(struct skge_hw *hw, int port)
1236 {
1237 struct net_device *dev = hw->dev[port];
1238 struct skge_port *skge = netdev_priv(dev);
1239 u16 status;
1240
1241 /* read twice because of latch */
1242 xm_phy_read(hw, port, PHY_BCOM_STAT);
1243 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1244
1245 if ((status & PHY_ST_LSYNC) == 0) {
1246 xm_link_down(hw, port);
1247 return;
1248 }
1249
1250 if (skge->autoneg == AUTONEG_ENABLE) {
1251 u16 lpa, aux;
1252
1253 if (!(status & PHY_ST_AN_OVER))
1254 return;
1255
1256 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1257 if (lpa & PHY_B_AN_RF) {
1258 printk(KERN_NOTICE PFX "%s: remote fault\n",
1259 dev->name);
1260 return;
1261 }
1262
1263 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1264
1265 /* Check Duplex mismatch */
1266 switch (aux & PHY_B_AS_AN_RES_MSK) {
1267 case PHY_B_RES_1000FD:
1268 skge->duplex = DUPLEX_FULL;
1269 break;
1270 case PHY_B_RES_1000HD:
1271 skge->duplex = DUPLEX_HALF;
1272 break;
1273 default:
1274 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1275 dev->name);
1276 return;
1277 }
1278
1279 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1280 switch (aux & PHY_B_AS_PAUSE_MSK) {
1281 case PHY_B_AS_PAUSE_MSK:
1282 skge->flow_status = FLOW_STAT_SYMMETRIC;
1283 break;
1284 case PHY_B_AS_PRR:
1285 skge->flow_status = FLOW_STAT_REM_SEND;
1286 break;
1287 case PHY_B_AS_PRT:
1288 skge->flow_status = FLOW_STAT_LOC_SEND;
1289 break;
1290 default:
1291 skge->flow_status = FLOW_STAT_NONE;
1292 }
1293 skge->speed = SPEED_1000;
1294 }
1295
1296 if (!netif_carrier_ok(dev))
1297 genesis_link_up(skge);
1298 }
1299
1300 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1301 * Phy on for 100 or 10Mbit operation
1302 */
1303 static void bcom_phy_init(struct skge_port *skge)
1304 {
1305 struct skge_hw *hw = skge->hw;
1306 int port = skge->port;
1307 int i;
1308 u16 id1, r, ext, ctl;
1309
1310 /* magic workaround patterns for Broadcom */
1311 static const struct {
1312 u16 reg;
1313 u16 val;
1314 } A1hack[] = {
1315 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1316 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1317 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1318 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1319 }, C0hack[] = {
1320 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1321 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1322 };
1323
1324 /* read Id from external PHY (all have the same address) */
1325 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1326
1327 /* Optimize MDIO transfer by suppressing preamble. */
1328 r = xm_read16(hw, port, XM_MMU_CMD);
1329 r |= XM_MMU_NO_PRE;
1330 xm_write16(hw, port, XM_MMU_CMD,r);
1331
1332 switch (id1) {
1333 case PHY_BCOM_ID1_C0:
1334 /*
1335 * Workaround BCOM Errata for the C0 type.
1336 * Write magic patterns to reserved registers.
1337 */
1338 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1339 xm_phy_write(hw, port,
1340 C0hack[i].reg, C0hack[i].val);
1341
1342 break;
1343 case PHY_BCOM_ID1_A1:
1344 /*
1345 * Workaround BCOM Errata for the A1 type.
1346 * Write magic patterns to reserved registers.
1347 */
1348 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1349 xm_phy_write(hw, port,
1350 A1hack[i].reg, A1hack[i].val);
1351 break;
1352 }
1353
1354 /*
1355 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1356 * Disable Power Management after reset.
1357 */
1358 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1359 r |= PHY_B_AC_DIS_PM;
1360 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1361
1362 /* Dummy read */
1363 xm_read16(hw, port, XM_ISRC);
1364
1365 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1366 ctl = PHY_CT_SP1000; /* always 1000mbit */
1367
1368 if (skge->autoneg == AUTONEG_ENABLE) {
1369 /*
1370 * Workaround BCOM Errata #1 for the C5 type.
1371 * 1000Base-T Link Acquisition Failure in Slave Mode
1372 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1373 */
1374 u16 adv = PHY_B_1000C_RD;
1375 if (skge->advertising & ADVERTISED_1000baseT_Half)
1376 adv |= PHY_B_1000C_AHD;
1377 if (skge->advertising & ADVERTISED_1000baseT_Full)
1378 adv |= PHY_B_1000C_AFD;
1379 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1380
1381 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1382 } else {
1383 if (skge->duplex == DUPLEX_FULL)
1384 ctl |= PHY_CT_DUP_MD;
1385 /* Force to slave */
1386 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1387 }
1388
1389 /* Set autonegotiation pause parameters */
1390 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1391 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1392
1393 /* Handle Jumbo frames */
1394 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1395 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1396 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1397
1398 ext |= PHY_B_PEC_HIGH_LA;
1399
1400 }
1401
1402 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1403 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1404
1405 /* Use link status change interrupt */
1406 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1407 }
1408
1409 static void xm_phy_init(struct skge_port *skge)
1410 {
1411 struct skge_hw *hw = skge->hw;
1412 int port = skge->port;
1413 u16 ctrl = 0;
1414
1415 if (skge->autoneg == AUTONEG_ENABLE) {
1416 if (skge->advertising & ADVERTISED_1000baseT_Half)
1417 ctrl |= PHY_X_AN_HD;
1418 if (skge->advertising & ADVERTISED_1000baseT_Full)
1419 ctrl |= PHY_X_AN_FD;
1420
1421 ctrl |= fiber_pause_map[skge->flow_control];
1422
1423 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1424
1425 /* Restart Auto-negotiation */
1426 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1427 } else {
1428 /* Set DuplexMode in Config register */
1429 if (skge->duplex == DUPLEX_FULL)
1430 ctrl |= PHY_CT_DUP_MD;
1431 /*
1432 * Do NOT enable Auto-negotiation here. This would hold
1433 * the link down because no IDLEs are transmitted
1434 */
1435 }
1436
1437 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1438
1439 /* Poll PHY for status changes */
1440 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1441 }
1442
1443 static int xm_check_link(struct net_device *dev)
1444 {
1445 struct skge_port *skge = netdev_priv(dev);
1446 struct skge_hw *hw = skge->hw;
1447 int port = skge->port;
1448 u16 status;
1449
1450 /* read twice because of latch */
1451 xm_phy_read(hw, port, PHY_XMAC_STAT);
1452 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1453
1454 if ((status & PHY_ST_LSYNC) == 0) {
1455 xm_link_down(hw, port);
1456 return 0;
1457 }
1458
1459 if (skge->autoneg == AUTONEG_ENABLE) {
1460 u16 lpa, res;
1461
1462 if (!(status & PHY_ST_AN_OVER))
1463 return 0;
1464
1465 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1466 if (lpa & PHY_B_AN_RF) {
1467 printk(KERN_NOTICE PFX "%s: remote fault\n",
1468 dev->name);
1469 return 0;
1470 }
1471
1472 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1473
1474 /* Check Duplex mismatch */
1475 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1476 case PHY_X_RS_FD:
1477 skge->duplex = DUPLEX_FULL;
1478 break;
1479 case PHY_X_RS_HD:
1480 skge->duplex = DUPLEX_HALF;
1481 break;
1482 default:
1483 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1484 dev->name);
1485 return 0;
1486 }
1487
1488 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1489 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1490 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1491 (lpa & PHY_X_P_SYM_MD))
1492 skge->flow_status = FLOW_STAT_SYMMETRIC;
1493 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1494 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1495 /* Enable PAUSE receive, disable PAUSE transmit */
1496 skge->flow_status = FLOW_STAT_REM_SEND;
1497 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1498 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1499 /* Disable PAUSE receive, enable PAUSE transmit */
1500 skge->flow_status = FLOW_STAT_LOC_SEND;
1501 else
1502 skge->flow_status = FLOW_STAT_NONE;
1503
1504 skge->speed = SPEED_1000;
1505 }
1506
1507 if (!netif_carrier_ok(dev))
1508 genesis_link_up(skge);
1509 return 1;
1510 }
1511
1512 /* Poll to check for link coming up.
1513 *
1514 * Since internal PHY is wired to a level triggered pin, can't
1515 * get an interrupt when carrier is detected, need to poll for
1516 * link coming up.
1517 */
1518 static void xm_link_timer(unsigned long arg)
1519 {
1520 struct skge_port *skge = (struct skge_port *) arg;
1521 struct net_device *dev = skge->netdev;
1522 struct skge_hw *hw = skge->hw;
1523 int port = skge->port;
1524 int i;
1525 unsigned long flags;
1526
1527 if (!netif_running(dev))
1528 return;
1529
1530 spin_lock_irqsave(&hw->phy_lock, flags);
1531
1532 /*
1533 * Verify that the link by checking GPIO register three times.
1534 * This pin has the signal from the link_sync pin connected to it.
1535 */
1536 for (i = 0; i < 3; i++) {
1537 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1538 goto link_down;
1539 }
1540
1541 /* Re-enable interrupt to detect link down */
1542 if (xm_check_link(dev)) {
1543 u16 msk = xm_read16(hw, port, XM_IMSK);
1544 msk &= ~XM_IS_INP_ASS;
1545 xm_write16(hw, port, XM_IMSK, msk);
1546 xm_read16(hw, port, XM_ISRC);
1547 } else {
1548 link_down:
1549 mod_timer(&skge->link_timer,
1550 round_jiffies(jiffies + LINK_HZ));
1551 }
1552 spin_unlock_irqrestore(&hw->phy_lock, flags);
1553 }
1554
1555 static void genesis_mac_init(struct skge_hw *hw, int port)
1556 {
1557 struct net_device *dev = hw->dev[port];
1558 struct skge_port *skge = netdev_priv(dev);
1559 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1560 int i;
1561 u32 r;
1562 const u8 zero[6] = { 0 };
1563
1564 for (i = 0; i < 10; i++) {
1565 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1566 MFF_SET_MAC_RST);
1567 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1568 goto reset_ok;
1569 udelay(1);
1570 }
1571
1572 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1573
1574 reset_ok:
1575 /* Unreset the XMAC. */
1576 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1577
1578 /*
1579 * Perform additional initialization for external PHYs,
1580 * namely for the 1000baseTX cards that use the XMAC's
1581 * GMII mode.
1582 */
1583 if (hw->phy_type != SK_PHY_XMAC) {
1584 /* Take external Phy out of reset */
1585 r = skge_read32(hw, B2_GP_IO);
1586 if (port == 0)
1587 r |= GP_DIR_0|GP_IO_0;
1588 else
1589 r |= GP_DIR_2|GP_IO_2;
1590
1591 skge_write32(hw, B2_GP_IO, r);
1592
1593 /* Enable GMII interface */
1594 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1595 }
1596
1597
1598 switch(hw->phy_type) {
1599 case SK_PHY_XMAC:
1600 xm_phy_init(skge);
1601 break;
1602 case SK_PHY_BCOM:
1603 bcom_phy_init(skge);
1604 bcom_check_link(hw, port);
1605 }
1606
1607 /* Set Station Address */
1608 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1609
1610 /* We don't use match addresses so clear */
1611 for (i = 1; i < 16; i++)
1612 xm_outaddr(hw, port, XM_EXM(i), zero);
1613
1614 /* Clear MIB counters */
1615 xm_write16(hw, port, XM_STAT_CMD,
1616 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1617 /* Clear two times according to Errata #3 */
1618 xm_write16(hw, port, XM_STAT_CMD,
1619 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1620
1621 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1622 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1623
1624 /* We don't need the FCS appended to the packet. */
1625 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1626 if (jumbo)
1627 r |= XM_RX_BIG_PK_OK;
1628
1629 if (skge->duplex == DUPLEX_HALF) {
1630 /*
1631 * If in manual half duplex mode the other side might be in
1632 * full duplex mode, so ignore if a carrier extension is not seen
1633 * on frames received
1634 */
1635 r |= XM_RX_DIS_CEXT;
1636 }
1637 xm_write16(hw, port, XM_RX_CMD, r);
1638
1639 /* We want short frames padded to 60 bytes. */
1640 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1641
1642 /* Increase threshold for jumbo frames on dual port */
1643 if (hw->ports > 1 && jumbo)
1644 xm_write16(hw, port, XM_TX_THR, 1020);
1645 else
1646 xm_write16(hw, port, XM_TX_THR, 512);
1647
1648 /*
1649 * Enable the reception of all error frames. This is is
1650 * a necessary evil due to the design of the XMAC. The
1651 * XMAC's receive FIFO is only 8K in size, however jumbo
1652 * frames can be up to 9000 bytes in length. When bad
1653 * frame filtering is enabled, the XMAC's RX FIFO operates
1654 * in 'store and forward' mode. For this to work, the
1655 * entire frame has to fit into the FIFO, but that means
1656 * that jumbo frames larger than 8192 bytes will be
1657 * truncated. Disabling all bad frame filtering causes
1658 * the RX FIFO to operate in streaming mode, in which
1659 * case the XMAC will start transferring frames out of the
1660 * RX FIFO as soon as the FIFO threshold is reached.
1661 */
1662 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1663
1664
1665 /*
1666 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1667 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1668 * and 'Octets Rx OK Hi Cnt Ov'.
1669 */
1670 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1671
1672 /*
1673 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1674 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1675 * and 'Octets Tx OK Hi Cnt Ov'.
1676 */
1677 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1678
1679 /* Configure MAC arbiter */
1680 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1681
1682 /* configure timeout values */
1683 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1684 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1685 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1686 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1687
1688 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1689 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1690 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1691 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1692
1693 /* Configure Rx MAC FIFO */
1694 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1695 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1696 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1697
1698 /* Configure Tx MAC FIFO */
1699 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1700 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1701 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1702
1703 if (jumbo) {
1704 /* Enable frame flushing if jumbo frames used */
1705 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1706 } else {
1707 /* enable timeout timers if normal frames */
1708 skge_write16(hw, B3_PA_CTRL,
1709 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1710 }
1711 }
1712
1713 static void genesis_stop(struct skge_port *skge)
1714 {
1715 struct skge_hw *hw = skge->hw;
1716 int port = skge->port;
1717 unsigned retries = 1000;
1718 u16 cmd;
1719
1720 /* Disable Tx and Rx */
1721 cmd = xm_read16(hw, port, XM_MMU_CMD);
1722 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1723 xm_write16(hw, port, XM_MMU_CMD, cmd);
1724
1725 genesis_reset(hw, port);
1726
1727 /* Clear Tx packet arbiter timeout IRQ */
1728 skge_write16(hw, B3_PA_CTRL,
1729 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1730
1731 /* Reset the MAC */
1732 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1733 do {
1734 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1735 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1736 break;
1737 } while (--retries > 0);
1738
1739 /* For external PHYs there must be special handling */
1740 if (hw->phy_type != SK_PHY_XMAC) {
1741 u32 reg = skge_read32(hw, B2_GP_IO);
1742 if (port == 0) {
1743 reg |= GP_DIR_0;
1744 reg &= ~GP_IO_0;
1745 } else {
1746 reg |= GP_DIR_2;
1747 reg &= ~GP_IO_2;
1748 }
1749 skge_write32(hw, B2_GP_IO, reg);
1750 skge_read32(hw, B2_GP_IO);
1751 }
1752
1753 xm_write16(hw, port, XM_MMU_CMD,
1754 xm_read16(hw, port, XM_MMU_CMD)
1755 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1756
1757 xm_read16(hw, port, XM_MMU_CMD);
1758 }
1759
1760
1761 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1762 {
1763 struct skge_hw *hw = skge->hw;
1764 int port = skge->port;
1765 int i;
1766 unsigned long timeout = jiffies + HZ;
1767
1768 xm_write16(hw, port,
1769 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1770
1771 /* wait for update to complete */
1772 while (xm_read16(hw, port, XM_STAT_CMD)
1773 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1774 if (time_after(jiffies, timeout))
1775 break;
1776 udelay(10);
1777 }
1778
1779 /* special case for 64 bit octet counter */
1780 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1781 | xm_read32(hw, port, XM_TXO_OK_LO);
1782 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1783 | xm_read32(hw, port, XM_RXO_OK_LO);
1784
1785 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1786 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1787 }
1788
1789 static void genesis_mac_intr(struct skge_hw *hw, int port)
1790 {
1791 struct net_device *dev = hw->dev[port];
1792 struct skge_port *skge = netdev_priv(dev);
1793 u16 status = xm_read16(hw, port, XM_ISRC);
1794
1795 if (netif_msg_intr(skge))
1796 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1797 dev->name, status);
1798
1799 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1800 xm_link_down(hw, port);
1801 mod_timer(&skge->link_timer, jiffies + 1);
1802 }
1803
1804 if (status & XM_IS_TXF_UR) {
1805 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1806 ++dev->stats.tx_fifo_errors;
1807 }
1808 }
1809
1810 static void genesis_link_up(struct skge_port *skge)
1811 {
1812 struct skge_hw *hw = skge->hw;
1813 int port = skge->port;
1814 u16 cmd, msk;
1815 u32 mode;
1816
1817 cmd = xm_read16(hw, port, XM_MMU_CMD);
1818
1819 /*
1820 * enabling pause frame reception is required for 1000BT
1821 * because the XMAC is not reset if the link is going down
1822 */
1823 if (skge->flow_status == FLOW_STAT_NONE ||
1824 skge->flow_status == FLOW_STAT_LOC_SEND)
1825 /* Disable Pause Frame Reception */
1826 cmd |= XM_MMU_IGN_PF;
1827 else
1828 /* Enable Pause Frame Reception */
1829 cmd &= ~XM_MMU_IGN_PF;
1830
1831 xm_write16(hw, port, XM_MMU_CMD, cmd);
1832
1833 mode = xm_read32(hw, port, XM_MODE);
1834 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1835 skge->flow_status == FLOW_STAT_LOC_SEND) {
1836 /*
1837 * Configure Pause Frame Generation
1838 * Use internal and external Pause Frame Generation.
1839 * Sending pause frames is edge triggered.
1840 * Send a Pause frame with the maximum pause time if
1841 * internal oder external FIFO full condition occurs.
1842 * Send a zero pause time frame to re-start transmission.
1843 */
1844 /* XM_PAUSE_DA = '010000C28001' (default) */
1845 /* XM_MAC_PTIME = 0xffff (maximum) */
1846 /* remember this value is defined in big endian (!) */
1847 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1848
1849 mode |= XM_PAUSE_MODE;
1850 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1851 } else {
1852 /*
1853 * disable pause frame generation is required for 1000BT
1854 * because the XMAC is not reset if the link is going down
1855 */
1856 /* Disable Pause Mode in Mode Register */
1857 mode &= ~XM_PAUSE_MODE;
1858
1859 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1860 }
1861
1862 xm_write32(hw, port, XM_MODE, mode);
1863
1864 /* Turn on detection of Tx underrun */
1865 msk = xm_read16(hw, port, XM_IMSK);
1866 msk &= ~XM_IS_TXF_UR;
1867 xm_write16(hw, port, XM_IMSK, msk);
1868
1869 xm_read16(hw, port, XM_ISRC);
1870
1871 /* get MMU Command Reg. */
1872 cmd = xm_read16(hw, port, XM_MMU_CMD);
1873 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1874 cmd |= XM_MMU_GMII_FD;
1875
1876 /*
1877 * Workaround BCOM Errata (#10523) for all BCom Phys
1878 * Enable Power Management after link up
1879 */
1880 if (hw->phy_type == SK_PHY_BCOM) {
1881 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1882 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1883 & ~PHY_B_AC_DIS_PM);
1884 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1885 }
1886
1887 /* enable Rx/Tx */
1888 xm_write16(hw, port, XM_MMU_CMD,
1889 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1890 skge_link_up(skge);
1891 }
1892
1893
1894 static inline void bcom_phy_intr(struct skge_port *skge)
1895 {
1896 struct skge_hw *hw = skge->hw;
1897 int port = skge->port;
1898 u16 isrc;
1899
1900 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1901 if (netif_msg_intr(skge))
1902 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1903 skge->netdev->name, isrc);
1904
1905 if (isrc & PHY_B_IS_PSE)
1906 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1907 hw->dev[port]->name);
1908
1909 /* Workaround BCom Errata:
1910 * enable and disable loopback mode if "NO HCD" occurs.
1911 */
1912 if (isrc & PHY_B_IS_NO_HDCL) {
1913 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1914 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1915 ctrl | PHY_CT_LOOP);
1916 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1917 ctrl & ~PHY_CT_LOOP);
1918 }
1919
1920 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1921 bcom_check_link(hw, port);
1922
1923 }
1924
1925 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1926 {
1927 int i;
1928
1929 gma_write16(hw, port, GM_SMI_DATA, val);
1930 gma_write16(hw, port, GM_SMI_CTRL,
1931 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1932 for (i = 0; i < PHY_RETRIES; i++) {
1933 udelay(1);
1934
1935 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1936 return 0;
1937 }
1938
1939 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1940 hw->dev[port]->name);
1941 return -EIO;
1942 }
1943
1944 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1945 {
1946 int i;
1947
1948 gma_write16(hw, port, GM_SMI_CTRL,
1949 GM_SMI_CT_PHY_AD(hw->phy_addr)
1950 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1951
1952 for (i = 0; i < PHY_RETRIES; i++) {
1953 udelay(1);
1954 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1955 goto ready;
1956 }
1957
1958 return -ETIMEDOUT;
1959 ready:
1960 *val = gma_read16(hw, port, GM_SMI_DATA);
1961 return 0;
1962 }
1963
1964 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1965 {
1966 u16 v = 0;
1967 if (__gm_phy_read(hw, port, reg, &v))
1968 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1969 hw->dev[port]->name);
1970 return v;
1971 }
1972
1973 /* Marvell Phy Initialization */
1974 static void yukon_init(struct skge_hw *hw, int port)
1975 {
1976 struct skge_port *skge = netdev_priv(hw->dev[port]);
1977 u16 ctrl, ct1000, adv;
1978
1979 if (skge->autoneg == AUTONEG_ENABLE) {
1980 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1981
1982 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1983 PHY_M_EC_MAC_S_MSK);
1984 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1985
1986 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1987
1988 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1989 }
1990
1991 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1992 if (skge->autoneg == AUTONEG_DISABLE)
1993 ctrl &= ~PHY_CT_ANE;
1994
1995 ctrl |= PHY_CT_RESET;
1996 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1997
1998 ctrl = 0;
1999 ct1000 = 0;
2000 adv = PHY_AN_CSMA;
2001
2002 if (skge->autoneg == AUTONEG_ENABLE) {
2003 if (hw->copper) {
2004 if (skge->advertising & ADVERTISED_1000baseT_Full)
2005 ct1000 |= PHY_M_1000C_AFD;
2006 if (skge->advertising & ADVERTISED_1000baseT_Half)
2007 ct1000 |= PHY_M_1000C_AHD;
2008 if (skge->advertising & ADVERTISED_100baseT_Full)
2009 adv |= PHY_M_AN_100_FD;
2010 if (skge->advertising & ADVERTISED_100baseT_Half)
2011 adv |= PHY_M_AN_100_HD;
2012 if (skge->advertising & ADVERTISED_10baseT_Full)
2013 adv |= PHY_M_AN_10_FD;
2014 if (skge->advertising & ADVERTISED_10baseT_Half)
2015 adv |= PHY_M_AN_10_HD;
2016
2017 /* Set Flow-control capabilities */
2018 adv |= phy_pause_map[skge->flow_control];
2019 } else {
2020 if (skge->advertising & ADVERTISED_1000baseT_Full)
2021 adv |= PHY_M_AN_1000X_AFD;
2022 if (skge->advertising & ADVERTISED_1000baseT_Half)
2023 adv |= PHY_M_AN_1000X_AHD;
2024
2025 adv |= fiber_pause_map[skge->flow_control];
2026 }
2027
2028 /* Restart Auto-negotiation */
2029 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2030 } else {
2031 /* forced speed/duplex settings */
2032 ct1000 = PHY_M_1000C_MSE;
2033
2034 if (skge->duplex == DUPLEX_FULL)
2035 ctrl |= PHY_CT_DUP_MD;
2036
2037 switch (skge->speed) {
2038 case SPEED_1000:
2039 ctrl |= PHY_CT_SP1000;
2040 break;
2041 case SPEED_100:
2042 ctrl |= PHY_CT_SP100;
2043 break;
2044 }
2045
2046 ctrl |= PHY_CT_RESET;
2047 }
2048
2049 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2050
2051 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2052 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2053
2054 /* Enable phy interrupt on autonegotiation complete (or link up) */
2055 if (skge->autoneg == AUTONEG_ENABLE)
2056 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2057 else
2058 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2059 }
2060
2061 static void yukon_reset(struct skge_hw *hw, int port)
2062 {
2063 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2064 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2065 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2066 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2067 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2068
2069 gma_write16(hw, port, GM_RX_CTRL,
2070 gma_read16(hw, port, GM_RX_CTRL)
2071 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2072 }
2073
2074 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2075 static int is_yukon_lite_a0(struct skge_hw *hw)
2076 {
2077 u32 reg;
2078 int ret;
2079
2080 if (hw->chip_id != CHIP_ID_YUKON)
2081 return 0;
2082
2083 reg = skge_read32(hw, B2_FAR);
2084 skge_write8(hw, B2_FAR + 3, 0xff);
2085 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2086 skge_write32(hw, B2_FAR, reg);
2087 return ret;
2088 }
2089
2090 static void yukon_mac_init(struct skge_hw *hw, int port)
2091 {
2092 struct skge_port *skge = netdev_priv(hw->dev[port]);
2093 int i;
2094 u32 reg;
2095 const u8 *addr = hw->dev[port]->dev_addr;
2096
2097 /* WA code for COMA mode -- set PHY reset */
2098 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2099 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2100 reg = skge_read32(hw, B2_GP_IO);
2101 reg |= GP_DIR_9 | GP_IO_9;
2102 skge_write32(hw, B2_GP_IO, reg);
2103 }
2104
2105 /* hard reset */
2106 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2107 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2108
2109 /* WA code for COMA mode -- clear PHY reset */
2110 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2111 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2112 reg = skge_read32(hw, B2_GP_IO);
2113 reg |= GP_DIR_9;
2114 reg &= ~GP_IO_9;
2115 skge_write32(hw, B2_GP_IO, reg);
2116 }
2117
2118 /* Set hardware config mode */
2119 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2120 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2121 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2122
2123 /* Clear GMC reset */
2124 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2125 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2126 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2127
2128 if (skge->autoneg == AUTONEG_DISABLE) {
2129 reg = GM_GPCR_AU_ALL_DIS;
2130 gma_write16(hw, port, GM_GP_CTRL,
2131 gma_read16(hw, port, GM_GP_CTRL) | reg);
2132
2133 switch (skge->speed) {
2134 case SPEED_1000:
2135 reg &= ~GM_GPCR_SPEED_100;
2136 reg |= GM_GPCR_SPEED_1000;
2137 break;
2138 case SPEED_100:
2139 reg &= ~GM_GPCR_SPEED_1000;
2140 reg |= GM_GPCR_SPEED_100;
2141 break;
2142 case SPEED_10:
2143 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2144 break;
2145 }
2146
2147 if (skge->duplex == DUPLEX_FULL)
2148 reg |= GM_GPCR_DUP_FULL;
2149 } else
2150 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2151
2152 switch (skge->flow_control) {
2153 case FLOW_MODE_NONE:
2154 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2155 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2156 break;
2157 case FLOW_MODE_LOC_SEND:
2158 /* disable Rx flow-control */
2159 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2160 break;
2161 case FLOW_MODE_SYMMETRIC:
2162 case FLOW_MODE_SYM_OR_REM:
2163 /* enable Tx & Rx flow-control */
2164 break;
2165 }
2166
2167 gma_write16(hw, port, GM_GP_CTRL, reg);
2168 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2169
2170 yukon_init(hw, port);
2171
2172 /* MIB clear */
2173 reg = gma_read16(hw, port, GM_PHY_ADDR);
2174 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2175
2176 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2177 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2178 gma_write16(hw, port, GM_PHY_ADDR, reg);
2179
2180 /* transmit control */
2181 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2182
2183 /* receive control reg: unicast + multicast + no FCS */
2184 gma_write16(hw, port, GM_RX_CTRL,
2185 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2186
2187 /* transmit flow control */
2188 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2189
2190 /* transmit parameter */
2191 gma_write16(hw, port, GM_TX_PARAM,
2192 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2193 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2194 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2195
2196 /* configure the Serial Mode Register */
2197 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2198 | GM_SMOD_VLAN_ENA
2199 | IPG_DATA_VAL(IPG_DATA_DEF);
2200
2201 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2202 reg |= GM_SMOD_JUMBO_ENA;
2203
2204 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2205
2206 /* physical address: used for pause frames */
2207 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2208 /* virtual address for data */
2209 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2210
2211 /* enable interrupt mask for counter overflows */
2212 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2213 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2214 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2215
2216 /* Initialize Mac Fifo */
2217
2218 /* Configure Rx MAC FIFO */
2219 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2220 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2221
2222 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2223 if (is_yukon_lite_a0(hw))
2224 reg &= ~GMF_RX_F_FL_ON;
2225
2226 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2227 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2228 /*
2229 * because Pause Packet Truncation in GMAC is not working
2230 * we have to increase the Flush Threshold to 64 bytes
2231 * in order to flush pause packets in Rx FIFO on Yukon-1
2232 */
2233 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2234
2235 /* Configure Tx MAC FIFO */
2236 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2237 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2238 }
2239
2240 /* Go into power down mode */
2241 static void yukon_suspend(struct skge_hw *hw, int port)
2242 {
2243 u16 ctrl;
2244
2245 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2246 ctrl |= PHY_M_PC_POL_R_DIS;
2247 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2248
2249 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2250 ctrl |= PHY_CT_RESET;
2251 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2252
2253 /* switch IEEE compatible power down mode on */
2254 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2255 ctrl |= PHY_CT_PDOWN;
2256 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2257 }
2258
2259 static void yukon_stop(struct skge_port *skge)
2260 {
2261 struct skge_hw *hw = skge->hw;
2262 int port = skge->port;
2263
2264 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2265 yukon_reset(hw, port);
2266
2267 gma_write16(hw, port, GM_GP_CTRL,
2268 gma_read16(hw, port, GM_GP_CTRL)
2269 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2270 gma_read16(hw, port, GM_GP_CTRL);
2271
2272 yukon_suspend(hw, port);
2273
2274 /* set GPHY Control reset */
2275 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2276 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2277 }
2278
2279 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2280 {
2281 struct skge_hw *hw = skge->hw;
2282 int port = skge->port;
2283 int i;
2284
2285 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2286 | gma_read32(hw, port, GM_TXO_OK_LO);
2287 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2288 | gma_read32(hw, port, GM_RXO_OK_LO);
2289
2290 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2291 data[i] = gma_read32(hw, port,
2292 skge_stats[i].gma_offset);
2293 }
2294
2295 static void yukon_mac_intr(struct skge_hw *hw, int port)
2296 {
2297 struct net_device *dev = hw->dev[port];
2298 struct skge_port *skge = netdev_priv(dev);
2299 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2300
2301 if (netif_msg_intr(skge))
2302 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2303 dev->name, status);
2304
2305 if (status & GM_IS_RX_FF_OR) {
2306 ++dev->stats.rx_fifo_errors;
2307 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2308 }
2309
2310 if (status & GM_IS_TX_FF_UR) {
2311 ++dev->stats.tx_fifo_errors;
2312 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2313 }
2314
2315 }
2316
2317 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2318 {
2319 switch (aux & PHY_M_PS_SPEED_MSK) {
2320 case PHY_M_PS_SPEED_1000:
2321 return SPEED_1000;
2322 case PHY_M_PS_SPEED_100:
2323 return SPEED_100;
2324 default:
2325 return SPEED_10;
2326 }
2327 }
2328
2329 static void yukon_link_up(struct skge_port *skge)
2330 {
2331 struct skge_hw *hw = skge->hw;
2332 int port = skge->port;
2333 u16 reg;
2334
2335 /* Enable Transmit FIFO Underrun */
2336 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2337
2338 reg = gma_read16(hw, port, GM_GP_CTRL);
2339 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2340 reg |= GM_GPCR_DUP_FULL;
2341
2342 /* enable Rx/Tx */
2343 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2344 gma_write16(hw, port, GM_GP_CTRL, reg);
2345
2346 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2347 skge_link_up(skge);
2348 }
2349
2350 static void yukon_link_down(struct skge_port *skge)
2351 {
2352 struct skge_hw *hw = skge->hw;
2353 int port = skge->port;
2354 u16 ctrl;
2355
2356 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2357 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2358 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2359
2360 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2361 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2362 ctrl |= PHY_M_AN_ASP;
2363 /* restore Asymmetric Pause bit */
2364 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2365 }
2366
2367 skge_link_down(skge);
2368
2369 yukon_init(hw, port);
2370 }
2371
2372 static void yukon_phy_intr(struct skge_port *skge)
2373 {
2374 struct skge_hw *hw = skge->hw;
2375 int port = skge->port;
2376 const char *reason = NULL;
2377 u16 istatus, phystat;
2378
2379 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2380 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2381
2382 if (netif_msg_intr(skge))
2383 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2384 skge->netdev->name, istatus, phystat);
2385
2386 if (istatus & PHY_M_IS_AN_COMPL) {
2387 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2388 & PHY_M_AN_RF) {
2389 reason = "remote fault";
2390 goto failed;
2391 }
2392
2393 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2394 reason = "master/slave fault";
2395 goto failed;
2396 }
2397
2398 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2399 reason = "speed/duplex";
2400 goto failed;
2401 }
2402
2403 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2404 ? DUPLEX_FULL : DUPLEX_HALF;
2405 skge->speed = yukon_speed(hw, phystat);
2406
2407 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2408 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2409 case PHY_M_PS_PAUSE_MSK:
2410 skge->flow_status = FLOW_STAT_SYMMETRIC;
2411 break;
2412 case PHY_M_PS_RX_P_EN:
2413 skge->flow_status = FLOW_STAT_REM_SEND;
2414 break;
2415 case PHY_M_PS_TX_P_EN:
2416 skge->flow_status = FLOW_STAT_LOC_SEND;
2417 break;
2418 default:
2419 skge->flow_status = FLOW_STAT_NONE;
2420 }
2421
2422 if (skge->flow_status == FLOW_STAT_NONE ||
2423 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2424 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2425 else
2426 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2427 yukon_link_up(skge);
2428 return;
2429 }
2430
2431 if (istatus & PHY_M_IS_LSP_CHANGE)
2432 skge->speed = yukon_speed(hw, phystat);
2433
2434 if (istatus & PHY_M_IS_DUP_CHANGE)
2435 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2436 if (istatus & PHY_M_IS_LST_CHANGE) {
2437 if (phystat & PHY_M_PS_LINK_UP)
2438 yukon_link_up(skge);
2439 else
2440 yukon_link_down(skge);
2441 }
2442 return;
2443 failed:
2444 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2445 skge->netdev->name, reason);
2446
2447 /* XXX restart autonegotiation? */
2448 }
2449
2450 static void skge_phy_reset(struct skge_port *skge)
2451 {
2452 struct skge_hw *hw = skge->hw;
2453 int port = skge->port;
2454 struct net_device *dev = hw->dev[port];
2455
2456 netif_stop_queue(skge->netdev);
2457 netif_carrier_off(skge->netdev);
2458
2459 spin_lock_bh(&hw->phy_lock);
2460 if (hw->chip_id == CHIP_ID_GENESIS) {
2461 genesis_reset(hw, port);
2462 genesis_mac_init(hw, port);
2463 } else {
2464 yukon_reset(hw, port);
2465 yukon_init(hw, port);
2466 }
2467 spin_unlock_bh(&hw->phy_lock);
2468
2469 skge_set_multicast(dev);
2470 }
2471
2472 /* Basic MII support */
2473 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2474 {
2475 struct mii_ioctl_data *data = if_mii(ifr);
2476 struct skge_port *skge = netdev_priv(dev);
2477 struct skge_hw *hw = skge->hw;
2478 int err = -EOPNOTSUPP;
2479
2480 if (!netif_running(dev))
2481 return -ENODEV; /* Phy still in reset */
2482
2483 switch(cmd) {
2484 case SIOCGMIIPHY:
2485 data->phy_id = hw->phy_addr;
2486
2487 /* fallthru */
2488 case SIOCGMIIREG: {
2489 u16 val = 0;
2490 spin_lock_bh(&hw->phy_lock);
2491 if (hw->chip_id == CHIP_ID_GENESIS)
2492 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2493 else
2494 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2495 spin_unlock_bh(&hw->phy_lock);
2496 data->val_out = val;
2497 break;
2498 }
2499
2500 case SIOCSMIIREG:
2501 spin_lock_bh(&hw->phy_lock);
2502 if (hw->chip_id == CHIP_ID_GENESIS)
2503 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2504 data->val_in);
2505 else
2506 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2507 data->val_in);
2508 spin_unlock_bh(&hw->phy_lock);
2509 break;
2510 }
2511 return err;
2512 }
2513
2514 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2515 {
2516 u32 end;
2517
2518 start /= 8;
2519 len /= 8;
2520 end = start + len - 1;
2521
2522 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2523 skge_write32(hw, RB_ADDR(q, RB_START), start);
2524 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2525 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2526 skge_write32(hw, RB_ADDR(q, RB_END), end);
2527
2528 if (q == Q_R1 || q == Q_R2) {
2529 /* Set thresholds on receive queue's */
2530 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2531 start + (2*len)/3);
2532 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2533 start + (len/3));
2534 } else {
2535 /* Enable store & forward on Tx queue's because
2536 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2537 */
2538 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2539 }
2540
2541 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2542 }
2543
2544 /* Setup Bus Memory Interface */
2545 static void skge_qset(struct skge_port *skge, u16 q,
2546 const struct skge_element *e)
2547 {
2548 struct skge_hw *hw = skge->hw;
2549 u32 watermark = 0x600;
2550 u64 base = skge->dma + (e->desc - skge->mem);
2551
2552 /* optimization to reduce window on 32bit/33mhz */
2553 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2554 watermark /= 2;
2555
2556 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2557 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2558 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2559 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2560 }
2561
2562 static int skge_up(struct net_device *dev)
2563 {
2564 struct skge_port *skge = netdev_priv(dev);
2565 struct skge_hw *hw = skge->hw;
2566 int port = skge->port;
2567 u32 chunk, ram_addr;
2568 size_t rx_size, tx_size;
2569 int err;
2570
2571 if (!is_valid_ether_addr(dev->dev_addr))
2572 return -EINVAL;
2573
2574 if (netif_msg_ifup(skge))
2575 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2576
2577 if (dev->mtu > RX_BUF_SIZE)
2578 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2579 else
2580 skge->rx_buf_size = RX_BUF_SIZE;
2581
2582
2583 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2584 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2585 skge->mem_size = tx_size + rx_size;
2586 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2587 if (!skge->mem)
2588 return -ENOMEM;
2589
2590 BUG_ON(skge->dma & 7);
2591
2592 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2593 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2594 err = -EINVAL;
2595 goto free_pci_mem;
2596 }
2597
2598 memset(skge->mem, 0, skge->mem_size);
2599
2600 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2601 if (err)
2602 goto free_pci_mem;
2603
2604 err = skge_rx_fill(dev);
2605 if (err)
2606 goto free_rx_ring;
2607
2608 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2609 skge->dma + rx_size);
2610 if (err)
2611 goto free_rx_ring;
2612
2613 /* Initialize MAC */
2614 spin_lock_bh(&hw->phy_lock);
2615 if (hw->chip_id == CHIP_ID_GENESIS)
2616 genesis_mac_init(hw, port);
2617 else
2618 yukon_mac_init(hw, port);
2619 spin_unlock_bh(&hw->phy_lock);
2620
2621 /* Configure RAMbuffers - equally between ports and tx/rx */
2622 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2623 ram_addr = hw->ram_offset + 2 * chunk * port;
2624
2625 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2626 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2627
2628 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2629 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2630 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2631
2632 /* Start receiver BMU */
2633 wmb();
2634 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2635 skge_led(skge, LED_MODE_ON);
2636
2637 spin_lock_irq(&hw->hw_lock);
2638 hw->intr_mask |= portmask[port];
2639 skge_write32(hw, B0_IMSK, hw->intr_mask);
2640 spin_unlock_irq(&hw->hw_lock);
2641
2642 napi_enable(&skge->napi);
2643 return 0;
2644
2645 free_rx_ring:
2646 skge_rx_clean(skge);
2647 kfree(skge->rx_ring.start);
2648 free_pci_mem:
2649 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2650 skge->mem = NULL;
2651
2652 return err;
2653 }
2654
2655 /* stop receiver */
2656 static void skge_rx_stop(struct skge_hw *hw, int port)
2657 {
2658 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2659 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2660 RB_RST_SET|RB_DIS_OP_MD);
2661 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2662 }
2663
2664 static int skge_down(struct net_device *dev)
2665 {
2666 struct skge_port *skge = netdev_priv(dev);
2667 struct skge_hw *hw = skge->hw;
2668 int port = skge->port;
2669
2670 if (skge->mem == NULL)
2671 return 0;
2672
2673 if (netif_msg_ifdown(skge))
2674 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2675
2676 netif_tx_disable(dev);
2677
2678 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2679 del_timer_sync(&skge->link_timer);
2680
2681 napi_disable(&skge->napi);
2682 netif_carrier_off(dev);
2683
2684 spin_lock_irq(&hw->hw_lock);
2685 hw->intr_mask &= ~portmask[port];
2686 skge_write32(hw, B0_IMSK, hw->intr_mask);
2687 spin_unlock_irq(&hw->hw_lock);
2688
2689 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2690 if (hw->chip_id == CHIP_ID_GENESIS)
2691 genesis_stop(skge);
2692 else
2693 yukon_stop(skge);
2694
2695 /* Stop transmitter */
2696 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2697 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2698 RB_RST_SET|RB_DIS_OP_MD);
2699
2700
2701 /* Disable Force Sync bit and Enable Alloc bit */
2702 skge_write8(hw, SK_REG(port, TXA_CTRL),
2703 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2704
2705 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2706 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2707 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2708
2709 /* Reset PCI FIFO */
2710 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2711 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2712
2713 /* Reset the RAM Buffer async Tx queue */
2714 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2715
2716 skge_rx_stop(hw, port);
2717
2718 if (hw->chip_id == CHIP_ID_GENESIS) {
2719 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2720 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2721 } else {
2722 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2723 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2724 }
2725
2726 skge_led(skge, LED_MODE_OFF);
2727
2728 netif_tx_lock_bh(dev);
2729 skge_tx_clean(dev);
2730 netif_tx_unlock_bh(dev);
2731
2732 skge_rx_clean(skge);
2733
2734 kfree(skge->rx_ring.start);
2735 kfree(skge->tx_ring.start);
2736 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2737 skge->mem = NULL;
2738 return 0;
2739 }
2740
2741 static inline int skge_avail(const struct skge_ring *ring)
2742 {
2743 smp_mb();
2744 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2745 + (ring->to_clean - ring->to_use) - 1;
2746 }
2747
2748 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2749 struct net_device *dev)
2750 {
2751 struct skge_port *skge = netdev_priv(dev);
2752 struct skge_hw *hw = skge->hw;
2753 struct skge_element *e;
2754 struct skge_tx_desc *td;
2755 int i;
2756 u32 control, len;
2757 u64 map;
2758
2759 if (skb_padto(skb, ETH_ZLEN))
2760 return NETDEV_TX_OK;
2761
2762 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2763 return NETDEV_TX_BUSY;
2764
2765 e = skge->tx_ring.to_use;
2766 td = e->desc;
2767 BUG_ON(td->control & BMU_OWN);
2768 e->skb = skb;
2769 len = skb_headlen(skb);
2770 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2771 pci_unmap_addr_set(e, mapaddr, map);
2772 pci_unmap_len_set(e, maplen, len);
2773
2774 td->dma_lo = map;
2775 td->dma_hi = map >> 32;
2776
2777 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2778 const int offset = skb_transport_offset(skb);
2779
2780 /* This seems backwards, but it is what the sk98lin
2781 * does. Looks like hardware is wrong?
2782 */
2783 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
2784 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2785 control = BMU_TCP_CHECK;
2786 else
2787 control = BMU_UDP_CHECK;
2788
2789 td->csum_offs = 0;
2790 td->csum_start = offset;
2791 td->csum_write = offset + skb->csum_offset;
2792 } else
2793 control = BMU_CHECK;
2794
2795 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2796 control |= BMU_EOF| BMU_IRQ_EOF;
2797 else {
2798 struct skge_tx_desc *tf = td;
2799
2800 control |= BMU_STFWD;
2801 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2802 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2803
2804 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2805 frag->size, PCI_DMA_TODEVICE);
2806
2807 e = e->next;
2808 e->skb = skb;
2809 tf = e->desc;
2810 BUG_ON(tf->control & BMU_OWN);
2811
2812 tf->dma_lo = map;
2813 tf->dma_hi = (u64) map >> 32;
2814 pci_unmap_addr_set(e, mapaddr, map);
2815 pci_unmap_len_set(e, maplen, frag->size);
2816
2817 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2818 }
2819 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2820 }
2821 /* Make sure all the descriptors written */
2822 wmb();
2823 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2824 wmb();
2825
2826 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2827
2828 if (unlikely(netif_msg_tx_queued(skge)))
2829 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2830 dev->name, e - skge->tx_ring.start, skb->len);
2831
2832 skge->tx_ring.to_use = e->next;
2833 smp_wmb();
2834
2835 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2836 pr_debug("%s: transmit queue full\n", dev->name);
2837 netif_stop_queue(dev);
2838 }
2839
2840 return NETDEV_TX_OK;
2841 }
2842
2843
2844 /* Free resources associated with this reing element */
2845 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2846 u32 control)
2847 {
2848 struct pci_dev *pdev = skge->hw->pdev;
2849
2850 /* skb header vs. fragment */
2851 if (control & BMU_STF)
2852 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2853 pci_unmap_len(e, maplen),
2854 PCI_DMA_TODEVICE);
2855 else
2856 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2857 pci_unmap_len(e, maplen),
2858 PCI_DMA_TODEVICE);
2859
2860 if (control & BMU_EOF) {
2861 if (unlikely(netif_msg_tx_done(skge)))
2862 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2863 skge->netdev->name, e - skge->tx_ring.start);
2864
2865 dev_kfree_skb(e->skb);
2866 }
2867 }
2868
2869 /* Free all buffers in transmit ring */
2870 static void skge_tx_clean(struct net_device *dev)
2871 {
2872 struct skge_port *skge = netdev_priv(dev);
2873 struct skge_element *e;
2874
2875 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2876 struct skge_tx_desc *td = e->desc;
2877 skge_tx_free(skge, e, td->control);
2878 td->control = 0;
2879 }
2880
2881 skge->tx_ring.to_clean = e;
2882 }
2883
2884 static void skge_tx_timeout(struct net_device *dev)
2885 {
2886 struct skge_port *skge = netdev_priv(dev);
2887
2888 if (netif_msg_timer(skge))
2889 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2890
2891 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2892 skge_tx_clean(dev);
2893 netif_wake_queue(dev);
2894 }
2895
2896 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2897 {
2898 int err;
2899
2900 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2901 return -EINVAL;
2902
2903 if (!netif_running(dev)) {
2904 dev->mtu = new_mtu;
2905 return 0;
2906 }
2907
2908 skge_down(dev);
2909
2910 dev->mtu = new_mtu;
2911
2912 err = skge_up(dev);
2913 if (err)
2914 dev_close(dev);
2915
2916 return err;
2917 }
2918
2919 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2920
2921 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2922 {
2923 u32 crc, bit;
2924
2925 crc = ether_crc_le(ETH_ALEN, addr);
2926 bit = ~crc & 0x3f;
2927 filter[bit/8] |= 1 << (bit%8);
2928 }
2929
2930 static void genesis_set_multicast(struct net_device *dev)
2931 {
2932 struct skge_port *skge = netdev_priv(dev);
2933 struct skge_hw *hw = skge->hw;
2934 int port = skge->port;
2935 int i, count = dev->mc_count;
2936 struct dev_mc_list *list = dev->mc_list;
2937 u32 mode;
2938 u8 filter[8];
2939
2940 mode = xm_read32(hw, port, XM_MODE);
2941 mode |= XM_MD_ENA_HASH;
2942 if (dev->flags & IFF_PROMISC)
2943 mode |= XM_MD_ENA_PROM;
2944 else
2945 mode &= ~XM_MD_ENA_PROM;
2946
2947 if (dev->flags & IFF_ALLMULTI)
2948 memset(filter, 0xff, sizeof(filter));
2949 else {
2950 memset(filter, 0, sizeof(filter));
2951
2952 if (skge->flow_status == FLOW_STAT_REM_SEND
2953 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2954 genesis_add_filter(filter, pause_mc_addr);
2955
2956 for (i = 0; list && i < count; i++, list = list->next)
2957 genesis_add_filter(filter, list->dmi_addr);
2958 }
2959
2960 xm_write32(hw, port, XM_MODE, mode);
2961 xm_outhash(hw, port, XM_HSM, filter);
2962 }
2963
2964 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2965 {
2966 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2967 filter[bit/8] |= 1 << (bit%8);
2968 }
2969
2970 static void yukon_set_multicast(struct net_device *dev)
2971 {
2972 struct skge_port *skge = netdev_priv(dev);
2973 struct skge_hw *hw = skge->hw;
2974 int port = skge->port;
2975 struct dev_mc_list *list = dev->mc_list;
2976 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2977 || skge->flow_status == FLOW_STAT_SYMMETRIC);
2978 u16 reg;
2979 u8 filter[8];
2980
2981 memset(filter, 0, sizeof(filter));
2982
2983 reg = gma_read16(hw, port, GM_RX_CTRL);
2984 reg |= GM_RXCR_UCF_ENA;
2985
2986 if (dev->flags & IFF_PROMISC) /* promiscuous */
2987 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2988 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2989 memset(filter, 0xff, sizeof(filter));
2990 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
2991 reg &= ~GM_RXCR_MCF_ENA;
2992 else {
2993 int i;
2994 reg |= GM_RXCR_MCF_ENA;
2995
2996 if (rx_pause)
2997 yukon_add_filter(filter, pause_mc_addr);
2998
2999 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3000 yukon_add_filter(filter, list->dmi_addr);
3001 }
3002
3003
3004 gma_write16(hw, port, GM_MC_ADDR_H1,
3005 (u16)filter[0] | ((u16)filter[1] << 8));
3006 gma_write16(hw, port, GM_MC_ADDR_H2,
3007 (u16)filter[2] | ((u16)filter[3] << 8));
3008 gma_write16(hw, port, GM_MC_ADDR_H3,
3009 (u16)filter[4] | ((u16)filter[5] << 8));
3010 gma_write16(hw, port, GM_MC_ADDR_H4,
3011 (u16)filter[6] | ((u16)filter[7] << 8));
3012
3013 gma_write16(hw, port, GM_RX_CTRL, reg);
3014 }
3015
3016 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3017 {
3018 if (hw->chip_id == CHIP_ID_GENESIS)
3019 return status >> XMR_FS_LEN_SHIFT;
3020 else
3021 return status >> GMR_FS_LEN_SHIFT;
3022 }
3023
3024 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3025 {
3026 if (hw->chip_id == CHIP_ID_GENESIS)
3027 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3028 else
3029 return (status & GMR_FS_ANY_ERR) ||
3030 (status & GMR_FS_RX_OK) == 0;
3031 }
3032
3033 static void skge_set_multicast(struct net_device *dev)
3034 {
3035 struct skge_port *skge = netdev_priv(dev);
3036 struct skge_hw *hw = skge->hw;
3037
3038 if (hw->chip_id == CHIP_ID_GENESIS)
3039 genesis_set_multicast(dev);
3040 else
3041 yukon_set_multicast(dev);
3042
3043 }
3044
3045
3046 /* Get receive buffer from descriptor.
3047 * Handles copy of small buffers and reallocation failures
3048 */
3049 static struct sk_buff *skge_rx_get(struct net_device *dev,
3050 struct skge_element *e,
3051 u32 control, u32 status, u16 csum)
3052 {
3053 struct skge_port *skge = netdev_priv(dev);
3054 struct sk_buff *skb;
3055 u16 len = control & BMU_BBC;
3056
3057 if (unlikely(netif_msg_rx_status(skge)))
3058 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
3059 dev->name, e - skge->rx_ring.start,
3060 status, len);
3061
3062 if (len > skge->rx_buf_size)
3063 goto error;
3064
3065 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3066 goto error;
3067
3068 if (bad_phy_status(skge->hw, status))
3069 goto error;
3070
3071 if (phy_length(skge->hw, status) != len)
3072 goto error;
3073
3074 if (len < RX_COPY_THRESHOLD) {
3075 skb = netdev_alloc_skb(dev, len + 2);
3076 if (!skb)
3077 goto resubmit;
3078
3079 skb_reserve(skb, 2);
3080 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3081 pci_unmap_addr(e, mapaddr),
3082 len, PCI_DMA_FROMDEVICE);
3083 skb_copy_from_linear_data(e->skb, skb->data, len);
3084 pci_dma_sync_single_for_device(skge->hw->pdev,
3085 pci_unmap_addr(e, mapaddr),
3086 len, PCI_DMA_FROMDEVICE);
3087 skge_rx_reuse(e, skge->rx_buf_size);
3088 } else {
3089 struct sk_buff *nskb;
3090 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
3091 if (!nskb)
3092 goto resubmit;
3093
3094 skb_reserve(nskb, NET_IP_ALIGN);
3095 pci_unmap_single(skge->hw->pdev,
3096 pci_unmap_addr(e, mapaddr),
3097 pci_unmap_len(e, maplen),
3098 PCI_DMA_FROMDEVICE);
3099 skb = e->skb;
3100 prefetch(skb->data);
3101 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3102 }
3103
3104 skb_put(skb, len);
3105 if (skge->rx_csum) {
3106 skb->csum = csum;
3107 skb->ip_summed = CHECKSUM_COMPLETE;
3108 }
3109
3110 skb->protocol = eth_type_trans(skb, dev);
3111
3112 return skb;
3113 error:
3114
3115 if (netif_msg_rx_err(skge))
3116 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
3117 dev->name, e - skge->rx_ring.start,
3118 control, status);
3119
3120 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3121 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3122 dev->stats.rx_length_errors++;
3123 if (status & XMR_FS_FRA_ERR)
3124 dev->stats.rx_frame_errors++;
3125 if (status & XMR_FS_FCS_ERR)
3126 dev->stats.rx_crc_errors++;
3127 } else {
3128 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3129 dev->stats.rx_length_errors++;
3130 if (status & GMR_FS_FRAGMENT)
3131 dev->stats.rx_frame_errors++;
3132 if (status & GMR_FS_CRC_ERR)
3133 dev->stats.rx_crc_errors++;
3134 }
3135
3136 resubmit:
3137 skge_rx_reuse(e, skge->rx_buf_size);
3138 return NULL;
3139 }
3140
3141 /* Free all buffers in Tx ring which are no longer owned by device */
3142 static void skge_tx_done(struct net_device *dev)
3143 {
3144 struct skge_port *skge = netdev_priv(dev);
3145 struct skge_ring *ring = &skge->tx_ring;
3146 struct skge_element *e;
3147
3148 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3149
3150 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3151 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3152
3153 if (control & BMU_OWN)
3154 break;
3155
3156 skge_tx_free(skge, e, control);
3157 }
3158 skge->tx_ring.to_clean = e;
3159
3160 /* Can run lockless until we need to synchronize to restart queue. */
3161 smp_mb();
3162
3163 if (unlikely(netif_queue_stopped(dev) &&
3164 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3165 netif_tx_lock(dev);
3166 if (unlikely(netif_queue_stopped(dev) &&
3167 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3168 netif_wake_queue(dev);
3169
3170 }
3171 netif_tx_unlock(dev);
3172 }
3173 }
3174
3175 static int skge_poll(struct napi_struct *napi, int to_do)
3176 {
3177 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3178 struct net_device *dev = skge->netdev;
3179 struct skge_hw *hw = skge->hw;
3180 struct skge_ring *ring = &skge->rx_ring;
3181 struct skge_element *e;
3182 int work_done = 0;
3183
3184 skge_tx_done(dev);
3185
3186 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3187
3188 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3189 struct skge_rx_desc *rd = e->desc;
3190 struct sk_buff *skb;
3191 u32 control;
3192
3193 rmb();
3194 control = rd->control;
3195 if (control & BMU_OWN)
3196 break;
3197
3198 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3199 if (likely(skb)) {
3200 netif_receive_skb(skb);
3201
3202 ++work_done;
3203 }
3204 }
3205 ring->to_clean = e;
3206
3207 /* restart receiver */
3208 wmb();
3209 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3210
3211 if (work_done < to_do) {
3212 unsigned long flags;
3213
3214 spin_lock_irqsave(&hw->hw_lock, flags);
3215 __napi_complete(napi);
3216 hw->intr_mask |= napimask[skge->port];
3217 skge_write32(hw, B0_IMSK, hw->intr_mask);
3218 skge_read32(hw, B0_IMSK);
3219 spin_unlock_irqrestore(&hw->hw_lock, flags);
3220 }
3221
3222 return work_done;
3223 }
3224
3225 /* Parity errors seem to happen when Genesis is connected to a switch
3226 * with no other ports present. Heartbeat error??
3227 */
3228 static void skge_mac_parity(struct skge_hw *hw, int port)
3229 {
3230 struct net_device *dev = hw->dev[port];
3231
3232 ++dev->stats.tx_heartbeat_errors;
3233
3234 if (hw->chip_id == CHIP_ID_GENESIS)
3235 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3236 MFF_CLR_PERR);
3237 else
3238 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3239 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3240 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3241 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3242 }
3243
3244 static void skge_mac_intr(struct skge_hw *hw, int port)
3245 {
3246 if (hw->chip_id == CHIP_ID_GENESIS)
3247 genesis_mac_intr(hw, port);
3248 else
3249 yukon_mac_intr(hw, port);
3250 }
3251
3252 /* Handle device specific framing and timeout interrupts */
3253 static void skge_error_irq(struct skge_hw *hw)
3254 {
3255 struct pci_dev *pdev = hw->pdev;
3256 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3257
3258 if (hw->chip_id == CHIP_ID_GENESIS) {
3259 /* clear xmac errors */
3260 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3261 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3262 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3263 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3264 } else {
3265 /* Timestamp (unused) overflow */
3266 if (hwstatus & IS_IRQ_TIST_OV)
3267 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3268 }
3269
3270 if (hwstatus & IS_RAM_RD_PAR) {
3271 dev_err(&pdev->dev, "Ram read data parity error\n");
3272 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3273 }
3274
3275 if (hwstatus & IS_RAM_WR_PAR) {
3276 dev_err(&pdev->dev, "Ram write data parity error\n");
3277 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3278 }
3279
3280 if (hwstatus & IS_M1_PAR_ERR)
3281 skge_mac_parity(hw, 0);
3282
3283 if (hwstatus & IS_M2_PAR_ERR)
3284 skge_mac_parity(hw, 1);
3285
3286 if (hwstatus & IS_R1_PAR_ERR) {
3287 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3288 hw->dev[0]->name);
3289 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3290 }
3291
3292 if (hwstatus & IS_R2_PAR_ERR) {
3293 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3294 hw->dev[1]->name);
3295 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3296 }
3297
3298 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3299 u16 pci_status, pci_cmd;
3300
3301 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3302 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3303
3304 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3305 pci_cmd, pci_status);
3306
3307 /* Write the error bits back to clear them. */
3308 pci_status &= PCI_STATUS_ERROR_BITS;
3309 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3310 pci_write_config_word(pdev, PCI_COMMAND,
3311 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3312 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3313 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3314
3315 /* if error still set then just ignore it */
3316 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3317 if (hwstatus & IS_IRQ_STAT) {
3318 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3319 hw->intr_mask &= ~IS_HW_ERR;
3320 }
3321 }
3322 }
3323
3324 /*
3325 * Interrupt from PHY are handled in tasklet (softirq)
3326 * because accessing phy registers requires spin wait which might
3327 * cause excess interrupt latency.
3328 */
3329 static void skge_extirq(unsigned long arg)
3330 {
3331 struct skge_hw *hw = (struct skge_hw *) arg;
3332 int port;
3333
3334 for (port = 0; port < hw->ports; port++) {
3335 struct net_device *dev = hw->dev[port];
3336
3337 if (netif_running(dev)) {
3338 struct skge_port *skge = netdev_priv(dev);
3339
3340 spin_lock(&hw->phy_lock);
3341 if (hw->chip_id != CHIP_ID_GENESIS)
3342 yukon_phy_intr(skge);
3343 else if (hw->phy_type == SK_PHY_BCOM)
3344 bcom_phy_intr(skge);
3345 spin_unlock(&hw->phy_lock);
3346 }
3347 }
3348
3349 spin_lock_irq(&hw->hw_lock);
3350 hw->intr_mask |= IS_EXT_REG;
3351 skge_write32(hw, B0_IMSK, hw->intr_mask);
3352 skge_read32(hw, B0_IMSK);
3353 spin_unlock_irq(&hw->hw_lock);
3354 }
3355
3356 static irqreturn_t skge_intr(int irq, void *dev_id)
3357 {
3358 struct skge_hw *hw = dev_id;
3359 u32 status;
3360 int handled = 0;
3361
3362 spin_lock(&hw->hw_lock);
3363 /* Reading this register masks IRQ */
3364 status = skge_read32(hw, B0_SP_ISRC);
3365 if (status == 0 || status == ~0)
3366 goto out;
3367
3368 handled = 1;
3369 status &= hw->intr_mask;
3370 if (status & IS_EXT_REG) {
3371 hw->intr_mask &= ~IS_EXT_REG;
3372 tasklet_schedule(&hw->phy_task);
3373 }
3374
3375 if (status & (IS_XA1_F|IS_R1_F)) {
3376 struct skge_port *skge = netdev_priv(hw->dev[0]);
3377 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3378 napi_schedule(&skge->napi);
3379 }
3380
3381 if (status & IS_PA_TO_TX1)
3382 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3383
3384 if (status & IS_PA_TO_RX1) {
3385 ++hw->dev[0]->stats.rx_over_errors;
3386 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3387 }
3388
3389
3390 if (status & IS_MAC1)
3391 skge_mac_intr(hw, 0);
3392
3393 if (hw->dev[1]) {
3394 struct skge_port *skge = netdev_priv(hw->dev[1]);
3395
3396 if (status & (IS_XA2_F|IS_R2_F)) {
3397 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3398 napi_schedule(&skge->napi);
3399 }
3400
3401 if (status & IS_PA_TO_RX2) {
3402 ++hw->dev[1]->stats.rx_over_errors;
3403 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3404 }
3405
3406 if (status & IS_PA_TO_TX2)
3407 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3408
3409 if (status & IS_MAC2)
3410 skge_mac_intr(hw, 1);
3411 }
3412
3413 if (status & IS_HW_ERR)
3414 skge_error_irq(hw);
3415
3416 skge_write32(hw, B0_IMSK, hw->intr_mask);
3417 skge_read32(hw, B0_IMSK);
3418 out:
3419 spin_unlock(&hw->hw_lock);
3420
3421 return IRQ_RETVAL(handled);
3422 }
3423
3424 #ifdef CONFIG_NET_POLL_CONTROLLER
3425 static void skge_netpoll(struct net_device *dev)
3426 {
3427 struct skge_port *skge = netdev_priv(dev);
3428
3429 disable_irq(dev->irq);
3430 skge_intr(dev->irq, skge->hw);
3431 enable_irq(dev->irq);
3432 }
3433 #endif
3434
3435 static int skge_set_mac_address(struct net_device *dev, void *p)
3436 {
3437 struct skge_port *skge = netdev_priv(dev);
3438 struct skge_hw *hw = skge->hw;
3439 unsigned port = skge->port;
3440 const struct sockaddr *addr = p;
3441 u16 ctrl;
3442
3443 if (!is_valid_ether_addr(addr->sa_data))
3444 return -EADDRNOTAVAIL;
3445
3446 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3447
3448 if (!netif_running(dev)) {
3449 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3450 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3451 } else {
3452 /* disable Rx */
3453 spin_lock_bh(&hw->phy_lock);
3454 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3455 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3456
3457 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3458 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3459
3460 if (hw->chip_id == CHIP_ID_GENESIS)
3461 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3462 else {
3463 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3464 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3465 }
3466
3467 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3468 spin_unlock_bh(&hw->phy_lock);
3469 }
3470
3471 return 0;
3472 }
3473
3474 static const struct {
3475 u8 id;
3476 const char *name;
3477 } skge_chips[] = {
3478 { CHIP_ID_GENESIS, "Genesis" },
3479 { CHIP_ID_YUKON, "Yukon" },
3480 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3481 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3482 };
3483
3484 static const char *skge_board_name(const struct skge_hw *hw)
3485 {
3486 int i;
3487 static char buf[16];
3488
3489 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3490 if (skge_chips[i].id == hw->chip_id)
3491 return skge_chips[i].name;
3492
3493 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3494 return buf;
3495 }
3496
3497
3498 /*
3499 * Setup the board data structure, but don't bring up
3500 * the port(s)
3501 */
3502 static int skge_reset(struct skge_hw *hw)
3503 {
3504 u32 reg;
3505 u16 ctst, pci_status;
3506 u8 t8, mac_cfg, pmd_type;
3507 int i;
3508
3509 ctst = skge_read16(hw, B0_CTST);
3510
3511 /* do a SW reset */
3512 skge_write8(hw, B0_CTST, CS_RST_SET);
3513 skge_write8(hw, B0_CTST, CS_RST_CLR);
3514
3515 /* clear PCI errors, if any */
3516 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3517 skge_write8(hw, B2_TST_CTRL2, 0);
3518
3519 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3520 pci_write_config_word(hw->pdev, PCI_STATUS,
3521 pci_status | PCI_STATUS_ERROR_BITS);
3522 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3523 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3524
3525 /* restore CLK_RUN bits (for Yukon-Lite) */
3526 skge_write16(hw, B0_CTST,
3527 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3528
3529 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3530 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3531 pmd_type = skge_read8(hw, B2_PMD_TYP);
3532 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3533
3534 switch (hw->chip_id) {
3535 case CHIP_ID_GENESIS:
3536 switch (hw->phy_type) {
3537 case SK_PHY_XMAC:
3538 hw->phy_addr = PHY_ADDR_XMAC;
3539 break;
3540 case SK_PHY_BCOM:
3541 hw->phy_addr = PHY_ADDR_BCOM;
3542 break;
3543 default:
3544 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3545 hw->phy_type);
3546 return -EOPNOTSUPP;
3547 }
3548 break;
3549
3550 case CHIP_ID_YUKON:
3551 case CHIP_ID_YUKON_LITE:
3552 case CHIP_ID_YUKON_LP:
3553 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3554 hw->copper = 1;
3555
3556 hw->phy_addr = PHY_ADDR_MARV;
3557 break;
3558
3559 default:
3560 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3561 hw->chip_id);
3562 return -EOPNOTSUPP;
3563 }
3564
3565 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3566 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3567 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3568
3569 /* read the adapters RAM size */
3570 t8 = skge_read8(hw, B2_E_0);
3571 if (hw->chip_id == CHIP_ID_GENESIS) {
3572 if (t8 == 3) {
3573 /* special case: 4 x 64k x 36, offset = 0x80000 */
3574 hw->ram_size = 0x100000;
3575 hw->ram_offset = 0x80000;
3576 } else
3577 hw->ram_size = t8 * 512;
3578 }
3579 else if (t8 == 0)
3580 hw->ram_size = 0x20000;
3581 else
3582 hw->ram_size = t8 * 4096;
3583
3584 hw->intr_mask = IS_HW_ERR;
3585
3586 /* Use PHY IRQ for all but fiber based Genesis board */
3587 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3588 hw->intr_mask |= IS_EXT_REG;
3589
3590 if (hw->chip_id == CHIP_ID_GENESIS)
3591 genesis_init(hw);
3592 else {
3593 /* switch power to VCC (WA for VAUX problem) */
3594 skge_write8(hw, B0_POWER_CTRL,
3595 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3596
3597 /* avoid boards with stuck Hardware error bits */
3598 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3599 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3600 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3601 hw->intr_mask &= ~IS_HW_ERR;
3602 }
3603
3604 /* Clear PHY COMA */
3605 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3606 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3607 reg &= ~PCI_PHY_COMA;
3608 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3609 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3610
3611
3612 for (i = 0; i < hw->ports; i++) {
3613 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3614 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3615 }
3616 }
3617
3618 /* turn off hardware timer (unused) */
3619 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3620 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3621 skge_write8(hw, B0_LED, LED_STAT_ON);
3622
3623 /* enable the Tx Arbiters */
3624 for (i = 0; i < hw->ports; i++)
3625 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3626
3627 /* Initialize ram interface */
3628 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3629
3630 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3631 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3632 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3633 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3634 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3635 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3636 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3637 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3638 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3639 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3640 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3641 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3642
3643 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3644
3645 /* Set interrupt moderation for Transmit only
3646 * Receive interrupts avoided by NAPI
3647 */
3648 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3649 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3650 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3651
3652 skge_write32(hw, B0_IMSK, hw->intr_mask);
3653
3654 for (i = 0; i < hw->ports; i++) {
3655 if (hw->chip_id == CHIP_ID_GENESIS)
3656 genesis_reset(hw, i);
3657 else
3658 yukon_reset(hw, i);
3659 }
3660
3661 return 0;
3662 }
3663
3664
3665 #ifdef CONFIG_SKGE_DEBUG
3666
3667 static struct dentry *skge_debug;
3668
3669 static int skge_debug_show(struct seq_file *seq, void *v)
3670 {
3671 struct net_device *dev = seq->private;
3672 const struct skge_port *skge = netdev_priv(dev);
3673 const struct skge_hw *hw = skge->hw;
3674 const struct skge_element *e;
3675
3676 if (!netif_running(dev))
3677 return -ENETDOWN;
3678
3679 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3680 skge_read32(hw, B0_IMSK));
3681
3682 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3683 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3684 const struct skge_tx_desc *t = e->desc;
3685 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3686 t->control, t->dma_hi, t->dma_lo, t->status,
3687 t->csum_offs, t->csum_write, t->csum_start);
3688 }
3689
3690 seq_printf(seq, "\nRx Ring: \n");
3691 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3692 const struct skge_rx_desc *r = e->desc;
3693
3694 if (r->control & BMU_OWN)
3695 break;
3696
3697 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3698 r->control, r->dma_hi, r->dma_lo, r->status,
3699 r->timestamp, r->csum1, r->csum1_start);
3700 }
3701
3702 return 0;
3703 }
3704
3705 static int skge_debug_open(struct inode *inode, struct file *file)
3706 {
3707 return single_open(file, skge_debug_show, inode->i_private);
3708 }
3709
3710 static const struct file_operations skge_debug_fops = {
3711 .owner = THIS_MODULE,
3712 .open = skge_debug_open,
3713 .read = seq_read,
3714 .llseek = seq_lseek,
3715 .release = single_release,
3716 };
3717
3718 /*
3719 * Use network device events to create/remove/rename
3720 * debugfs file entries
3721 */
3722 static int skge_device_event(struct notifier_block *unused,
3723 unsigned long event, void *ptr)
3724 {
3725 struct net_device *dev = ptr;
3726 struct skge_port *skge;
3727 struct dentry *d;
3728
3729 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3730 goto done;
3731
3732 skge = netdev_priv(dev);
3733 switch(event) {
3734 case NETDEV_CHANGENAME:
3735 if (skge->debugfs) {
3736 d = debugfs_rename(skge_debug, skge->debugfs,
3737 skge_debug, dev->name);
3738 if (d)
3739 skge->debugfs = d;
3740 else {
3741 pr_info(PFX "%s: rename failed\n", dev->name);
3742 debugfs_remove(skge->debugfs);
3743 }
3744 }
3745 break;
3746
3747 case NETDEV_GOING_DOWN:
3748 if (skge->debugfs) {
3749 debugfs_remove(skge->debugfs);
3750 skge->debugfs = NULL;
3751 }
3752 break;
3753
3754 case NETDEV_UP:
3755 d = debugfs_create_file(dev->name, S_IRUGO,
3756 skge_debug, dev,
3757 &skge_debug_fops);
3758 if (!d || IS_ERR(d))
3759 pr_info(PFX "%s: debugfs create failed\n",
3760 dev->name);
3761 else
3762 skge->debugfs = d;
3763 break;
3764 }
3765
3766 done:
3767 return NOTIFY_DONE;
3768 }
3769
3770 static struct notifier_block skge_notifier = {
3771 .notifier_call = skge_device_event,
3772 };
3773
3774
3775 static __init void skge_debug_init(void)
3776 {
3777 struct dentry *ent;
3778
3779 ent = debugfs_create_dir("skge", NULL);
3780 if (!ent || IS_ERR(ent)) {
3781 pr_info(PFX "debugfs create directory failed\n");
3782 return;
3783 }
3784
3785 skge_debug = ent;
3786 register_netdevice_notifier(&skge_notifier);
3787 }
3788
3789 static __exit void skge_debug_cleanup(void)
3790 {
3791 if (skge_debug) {
3792 unregister_netdevice_notifier(&skge_notifier);
3793 debugfs_remove(skge_debug);
3794 skge_debug = NULL;
3795 }
3796 }
3797
3798 #else
3799 #define skge_debug_init()
3800 #define skge_debug_cleanup()
3801 #endif
3802
3803 static const struct net_device_ops skge_netdev_ops = {
3804 .ndo_open = skge_up,
3805 .ndo_stop = skge_down,
3806 .ndo_start_xmit = skge_xmit_frame,
3807 .ndo_do_ioctl = skge_ioctl,
3808 .ndo_get_stats = skge_get_stats,
3809 .ndo_tx_timeout = skge_tx_timeout,
3810 .ndo_change_mtu = skge_change_mtu,
3811 .ndo_validate_addr = eth_validate_addr,
3812 .ndo_set_multicast_list = skge_set_multicast,
3813 .ndo_set_mac_address = skge_set_mac_address,
3814 #ifdef CONFIG_NET_POLL_CONTROLLER
3815 .ndo_poll_controller = skge_netpoll,
3816 #endif
3817 };
3818
3819
3820 /* Initialize network device */
3821 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3822 int highmem)
3823 {
3824 struct skge_port *skge;
3825 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3826
3827 if (!dev) {
3828 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3829 return NULL;
3830 }
3831
3832 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3833 dev->netdev_ops = &skge_netdev_ops;
3834 dev->ethtool_ops = &skge_ethtool_ops;
3835 dev->watchdog_timeo = TX_WATCHDOG;
3836 dev->irq = hw->pdev->irq;
3837
3838 if (highmem)
3839 dev->features |= NETIF_F_HIGHDMA;
3840
3841 skge = netdev_priv(dev);
3842 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3843 skge->netdev = dev;
3844 skge->hw = hw;
3845 skge->msg_enable = netif_msg_init(debug, default_msg);
3846
3847 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3848 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3849
3850 /* Auto speed and flow control */
3851 skge->autoneg = AUTONEG_ENABLE;
3852 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3853 skge->duplex = -1;
3854 skge->speed = -1;
3855 skge->advertising = skge_supported_modes(hw);
3856
3857 if (device_can_wakeup(&hw->pdev->dev)) {
3858 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3859 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3860 }
3861
3862 hw->dev[port] = dev;
3863
3864 skge->port = port;
3865
3866 /* Only used for Genesis XMAC */
3867 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3868
3869 if (hw->chip_id != CHIP_ID_GENESIS) {
3870 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3871 skge->rx_csum = 1;
3872 }
3873
3874 /* read the mac address */
3875 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3876 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3877
3878 /* device is off until link detection */
3879 netif_carrier_off(dev);
3880 netif_stop_queue(dev);
3881
3882 return dev;
3883 }
3884
3885 static void __devinit skge_show_addr(struct net_device *dev)
3886 {
3887 const struct skge_port *skge = netdev_priv(dev);
3888
3889 if (netif_msg_probe(skge))
3890 printk(KERN_INFO PFX "%s: addr %pM\n",
3891 dev->name, dev->dev_addr);
3892 }
3893
3894 static int only_32bit_dma;
3895
3896 static int __devinit skge_probe(struct pci_dev *pdev,
3897 const struct pci_device_id *ent)
3898 {
3899 struct net_device *dev, *dev1;
3900 struct skge_hw *hw;
3901 int err, using_dac = 0;
3902
3903 err = pci_enable_device(pdev);
3904 if (err) {
3905 dev_err(&pdev->dev, "cannot enable PCI device\n");
3906 goto err_out;
3907 }
3908
3909 err = pci_request_regions(pdev, DRV_NAME);
3910 if (err) {
3911 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3912 goto err_out_disable_pdev;
3913 }
3914
3915 pci_set_master(pdev);
3916
3917 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3918 using_dac = 1;
3919 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3920 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3921 using_dac = 0;
3922 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3923 }
3924
3925 if (err) {
3926 dev_err(&pdev->dev, "no usable DMA configuration\n");
3927 goto err_out_free_regions;
3928 }
3929
3930 #ifdef __BIG_ENDIAN
3931 /* byte swap descriptors in hardware */
3932 {
3933 u32 reg;
3934
3935 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3936 reg |= PCI_REV_DESC;
3937 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3938 }
3939 #endif
3940
3941 err = -ENOMEM;
3942 /* space for skge@pci:0000:04:00.0 */
3943 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:" )
3944 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3945 if (!hw) {
3946 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3947 goto err_out_free_regions;
3948 }
3949 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3950
3951 hw->pdev = pdev;
3952 spin_lock_init(&hw->hw_lock);
3953 spin_lock_init(&hw->phy_lock);
3954 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3955
3956 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3957 if (!hw->regs) {
3958 dev_err(&pdev->dev, "cannot map device registers\n");
3959 goto err_out_free_hw;
3960 }
3961
3962 err = skge_reset(hw);
3963 if (err)
3964 goto err_out_iounmap;
3965
3966 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3967 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3968 skge_board_name(hw), hw->chip_rev);
3969
3970 dev = skge_devinit(hw, 0, using_dac);
3971 if (!dev)
3972 goto err_out_led_off;
3973
3974 /* Some motherboards are broken and has zero in ROM. */
3975 if (!is_valid_ether_addr(dev->dev_addr))
3976 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3977
3978 err = register_netdev(dev);
3979 if (err) {
3980 dev_err(&pdev->dev, "cannot register net device\n");
3981 goto err_out_free_netdev;
3982 }
3983
3984 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
3985 if (err) {
3986 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3987 dev->name, pdev->irq);
3988 goto err_out_unregister;
3989 }
3990 skge_show_addr(dev);
3991
3992 if (hw->ports > 1) {
3993 dev1 = skge_devinit(hw, 1, using_dac);
3994 if (dev1 && register_netdev(dev1) == 0)
3995 skge_show_addr(dev1);
3996 else {
3997 /* Failure to register second port need not be fatal */
3998 dev_warn(&pdev->dev, "register of second port failed\n");
3999 hw->dev[1] = NULL;
4000 hw->ports = 1;
4001 if (dev1)
4002 free_netdev(dev1);
4003 }
4004 }
4005 pci_set_drvdata(pdev, hw);
4006
4007 return 0;
4008
4009 err_out_unregister:
4010 unregister_netdev(dev);
4011 err_out_free_netdev:
4012 free_netdev(dev);
4013 err_out_led_off:
4014 skge_write16(hw, B0_LED, LED_STAT_OFF);
4015 err_out_iounmap:
4016 iounmap(hw->regs);
4017 err_out_free_hw:
4018 kfree(hw);
4019 err_out_free_regions:
4020 pci_release_regions(pdev);
4021 err_out_disable_pdev:
4022 pci_disable_device(pdev);
4023 pci_set_drvdata(pdev, NULL);
4024 err_out:
4025 return err;
4026 }
4027
4028 static void __devexit skge_remove(struct pci_dev *pdev)
4029 {
4030 struct skge_hw *hw = pci_get_drvdata(pdev);
4031 struct net_device *dev0, *dev1;
4032
4033 if (!hw)
4034 return;
4035
4036 flush_scheduled_work();
4037
4038 if ((dev1 = hw->dev[1]))
4039 unregister_netdev(dev1);
4040 dev0 = hw->dev[0];
4041 unregister_netdev(dev0);
4042
4043 tasklet_disable(&hw->phy_task);
4044
4045 spin_lock_irq(&hw->hw_lock);
4046 hw->intr_mask = 0;
4047 skge_write32(hw, B0_IMSK, 0);
4048 skge_read32(hw, B0_IMSK);
4049 spin_unlock_irq(&hw->hw_lock);
4050
4051 skge_write16(hw, B0_LED, LED_STAT_OFF);
4052 skge_write8(hw, B0_CTST, CS_RST_SET);
4053
4054 free_irq(pdev->irq, hw);
4055 pci_release_regions(pdev);
4056 pci_disable_device(pdev);
4057 if (dev1)
4058 free_netdev(dev1);
4059 free_netdev(dev0);
4060
4061 iounmap(hw->regs);
4062 kfree(hw);
4063 pci_set_drvdata(pdev, NULL);
4064 }
4065
4066 #ifdef CONFIG_PM
4067 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
4068 {
4069 struct skge_hw *hw = pci_get_drvdata(pdev);
4070 int i, err, wol = 0;
4071
4072 if (!hw)
4073 return 0;
4074
4075 err = pci_save_state(pdev);
4076 if (err)
4077 return err;
4078
4079 for (i = 0; i < hw->ports; i++) {
4080 struct net_device *dev = hw->dev[i];
4081 struct skge_port *skge = netdev_priv(dev);
4082
4083 if (netif_running(dev))
4084 skge_down(dev);
4085 if (skge->wol)
4086 skge_wol_init(skge);
4087
4088 wol |= skge->wol;
4089 }
4090
4091 skge_write32(hw, B0_IMSK, 0);
4092
4093 pci_prepare_to_sleep(pdev);
4094
4095 return 0;
4096 }
4097
4098 static int skge_resume(struct pci_dev *pdev)
4099 {
4100 struct skge_hw *hw = pci_get_drvdata(pdev);
4101 int i, err;
4102
4103 if (!hw)
4104 return 0;
4105
4106 err = pci_back_from_sleep(pdev);
4107 if (err)
4108 goto out;
4109
4110 err = pci_restore_state(pdev);
4111 if (err)
4112 goto out;
4113
4114 err = skge_reset(hw);
4115 if (err)
4116 goto out;
4117
4118 for (i = 0; i < hw->ports; i++) {
4119 struct net_device *dev = hw->dev[i];
4120
4121 if (netif_running(dev)) {
4122 err = skge_up(dev);
4123
4124 if (err) {
4125 printk(KERN_ERR PFX "%s: could not up: %d\n",
4126 dev->name, err);
4127 dev_close(dev);
4128 goto out;
4129 }
4130 }
4131 }
4132 out:
4133 return err;
4134 }
4135 #endif
4136
4137 static void skge_shutdown(struct pci_dev *pdev)
4138 {
4139 struct skge_hw *hw = pci_get_drvdata(pdev);
4140 int i, wol = 0;
4141
4142 if (!hw)
4143 return;
4144
4145 for (i = 0; i < hw->ports; i++) {
4146 struct net_device *dev = hw->dev[i];
4147 struct skge_port *skge = netdev_priv(dev);
4148
4149 if (skge->wol)
4150 skge_wol_init(skge);
4151 wol |= skge->wol;
4152 }
4153
4154 if (pci_enable_wake(pdev, PCI_D3cold, wol))
4155 pci_enable_wake(pdev, PCI_D3hot, wol);
4156
4157 pci_disable_device(pdev);
4158 pci_set_power_state(pdev, PCI_D3hot);
4159
4160 }
4161
4162 static struct pci_driver skge_driver = {
4163 .name = DRV_NAME,
4164 .id_table = skge_id_table,
4165 .probe = skge_probe,
4166 .remove = __devexit_p(skge_remove),
4167 #ifdef CONFIG_PM
4168 .suspend = skge_suspend,
4169 .resume = skge_resume,
4170 #endif
4171 .shutdown = skge_shutdown,
4172 };
4173
4174 static struct dmi_system_id skge_32bit_dma_boards[] = {
4175 {
4176 .ident = "Gigabyte nForce boards",
4177 .matches = {
4178 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4179 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4180 },
4181 },
4182 {}
4183 };
4184
4185 static int __init skge_init_module(void)
4186 {
4187 if (dmi_check_system(skge_32bit_dma_boards))
4188 only_32bit_dma = 1;
4189 skge_debug_init();
4190 return pci_register_driver(&skge_driver);
4191 }
4192
4193 static void __exit skge_cleanup_module(void)
4194 {
4195 pci_unregister_driver(&skge_driver);
4196 skge_debug_cleanup();
4197 }
4198
4199 module_init(skge_init_module);
4200 module_exit(skge_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree