2 * Serverworks AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/string.h>
9 #include <linux/slab.h>
10 #include <linux/jiffies.h>
11 #include <linux/agp_backend.h>
14 #define SVWRKS_COMMAND 0x04
15 #define SVWRKS_APSIZE 0x10
16 #define SVWRKS_MMBASE 0x14
17 #define SVWRKS_CACHING 0x4b
18 #define SVWRKS_AGP_ENABLE 0x60
19 #define SVWRKS_FEATURE 0x68
21 #define SVWRKS_SIZE_MASK 0xfe000000
23 /* Memory mapped registers */
24 #define SVWRKS_GART_CACHE 0x02
25 #define SVWRKS_GATTBASE 0x04
26 #define SVWRKS_TLBFLUSH 0x10
27 #define SVWRKS_POSTFLUSH 0x14
28 #define SVWRKS_DIRFLUSH 0x0c
31 struct serverworks_page_map
{
33 unsigned long __iomem
*remapped
;
36 static struct _serverworks_private
{
37 struct pci_dev
*svrwrks_dev
; /* device one */
38 volatile u8 __iomem
*registers
;
39 struct serverworks_page_map
**gatt_pages
;
41 struct serverworks_page_map scratch_dir
;
45 } serverworks_private
;
47 static int serverworks_create_page_map(struct serverworks_page_map
*page_map
)
51 page_map
->real
= (unsigned long *) __get_free_page(GFP_KERNEL
);
52 if (page_map
->real
== NULL
) {
56 set_memory_uc((unsigned long)page_map
->real
, 1);
57 page_map
->remapped
= page_map
->real
;
59 for (i
= 0; i
< PAGE_SIZE
/ sizeof(unsigned long); i
++)
60 writel(agp_bridge
->scratch_page
, page_map
->remapped
+i
);
61 /* Red Pen: Everyone else does pci posting flush here */
66 static void serverworks_free_page_map(struct serverworks_page_map
*page_map
)
68 set_memory_wb((unsigned long)page_map
->real
, 1);
69 free_page((unsigned long) page_map
->real
);
72 static void serverworks_free_gatt_pages(void)
75 struct serverworks_page_map
**tables
;
76 struct serverworks_page_map
*entry
;
78 tables
= serverworks_private
.gatt_pages
;
79 for (i
= 0; i
< serverworks_private
.num_tables
; i
++) {
82 if (entry
->real
!= NULL
) {
83 serverworks_free_page_map(entry
);
91 static int serverworks_create_gatt_pages(int nr_tables
)
93 struct serverworks_page_map
**tables
;
94 struct serverworks_page_map
*entry
;
98 tables
= kzalloc((nr_tables
+ 1) * sizeof(struct serverworks_page_map
*),
103 for (i
= 0; i
< nr_tables
; i
++) {
104 entry
= kzalloc(sizeof(struct serverworks_page_map
), GFP_KERNEL
);
110 retval
= serverworks_create_page_map(entry
);
111 if (retval
!= 0) break;
113 serverworks_private
.num_tables
= nr_tables
;
114 serverworks_private
.gatt_pages
= tables
;
116 if (retval
!= 0) serverworks_free_gatt_pages();
121 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
122 GET_PAGE_DIR_IDX(addr)]->remapped)
124 #ifndef GET_PAGE_DIR_OFF
125 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
128 #ifndef GET_PAGE_DIR_IDX
129 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
130 GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
134 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
137 static int serverworks_create_gatt_table(struct agp_bridge_data
*bridge
)
139 struct aper_size_info_lvl2
*value
;
140 struct serverworks_page_map page_dir
;
145 value
= A_SIZE_LVL2(agp_bridge
->current_size
);
146 retval
= serverworks_create_page_map(&page_dir
);
150 retval
= serverworks_create_page_map(&serverworks_private
.scratch_dir
);
152 serverworks_free_page_map(&page_dir
);
155 /* Create a fake scratch directory */
156 for (i
= 0; i
< 1024; i
++) {
157 writel(agp_bridge
->scratch_page
, serverworks_private
.scratch_dir
.remapped
+i
);
158 writel(virt_to_gart(serverworks_private
.scratch_dir
.real
) | 1, page_dir
.remapped
+i
);
161 retval
= serverworks_create_gatt_pages(value
->num_entries
/ 1024);
163 serverworks_free_page_map(&page_dir
);
164 serverworks_free_page_map(&serverworks_private
.scratch_dir
);
168 agp_bridge
->gatt_table_real
= (u32
*)page_dir
.real
;
169 agp_bridge
->gatt_table
= (u32 __iomem
*)page_dir
.remapped
;
170 agp_bridge
->gatt_bus_addr
= virt_to_gart(page_dir
.real
);
172 /* Get the address for the gart region.
173 * This is a bus address even on the alpha, b/c its
174 * used to program the agp master not the cpu
177 pci_read_config_dword(agp_bridge
->dev
,serverworks_private
.gart_addr_ofs
,&temp
);
178 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
180 /* Calculate the agp offset */
181 for (i
= 0; i
< value
->num_entries
/ 1024; i
++)
182 writel(virt_to_gart(serverworks_private
.gatt_pages
[i
]->real
)|1, page_dir
.remapped
+i
);
187 static int serverworks_free_gatt_table(struct agp_bridge_data
*bridge
)
189 struct serverworks_page_map page_dir
;
191 page_dir
.real
= (unsigned long *)agp_bridge
->gatt_table_real
;
192 page_dir
.remapped
= (unsigned long __iomem
*)agp_bridge
->gatt_table
;
194 serverworks_free_gatt_pages();
195 serverworks_free_page_map(&page_dir
);
196 serverworks_free_page_map(&serverworks_private
.scratch_dir
);
200 static int serverworks_fetch_size(void)
205 struct aper_size_info_lvl2
*values
;
207 values
= A_SIZE_LVL2(agp_bridge
->driver
->aperture_sizes
);
208 pci_read_config_dword(agp_bridge
->dev
,serverworks_private
.gart_addr_ofs
,&temp
);
209 pci_write_config_dword(agp_bridge
->dev
,serverworks_private
.gart_addr_ofs
,
211 pci_read_config_dword(agp_bridge
->dev
,serverworks_private
.gart_addr_ofs
,&temp2
);
212 pci_write_config_dword(agp_bridge
->dev
,serverworks_private
.gart_addr_ofs
,temp
);
213 temp2
&= SVWRKS_SIZE_MASK
;
215 for (i
= 0; i
< agp_bridge
->driver
->num_aperture_sizes
; i
++) {
216 if (temp2
== values
[i
].size_value
) {
217 agp_bridge
->previous_size
=
218 agp_bridge
->current_size
= (void *) (values
+ i
);
220 agp_bridge
->aperture_size_idx
= i
;
221 return values
[i
].size
;
229 * This routine could be implemented by taking the addresses
230 * written to the GATT, and flushing them individually. However
231 * currently it just flushes the whole table. Which is probably
232 * more efficent, since agp_memory blocks can be a large number of
235 static void serverworks_tlbflush(struct agp_memory
*temp
)
237 unsigned long timeout
;
239 writeb(1, serverworks_private
.registers
+SVWRKS_POSTFLUSH
);
240 timeout
= jiffies
+ 3*HZ
;
241 while (readb(serverworks_private
.registers
+SVWRKS_POSTFLUSH
) == 1) {
243 if (time_after(jiffies
, timeout
)) {
244 dev_err(&serverworks_private
.svrwrks_dev
->dev
,
245 "TLB post flush took more than 3 seconds\n");
250 writel(1, serverworks_private
.registers
+SVWRKS_DIRFLUSH
);
251 timeout
= jiffies
+ 3*HZ
;
252 while (readl(serverworks_private
.registers
+SVWRKS_DIRFLUSH
) == 1) {
254 if (time_after(jiffies
, timeout
)) {
255 dev_err(&serverworks_private
.svrwrks_dev
->dev
,
256 "TLB Dir flush took more than 3 seconds\n");
262 static int serverworks_configure(void)
264 struct aper_size_info_lvl2
*current_size
;
269 current_size
= A_SIZE_LVL2(agp_bridge
->current_size
);
271 /* Get the memory mapped registers */
272 pci_read_config_dword(agp_bridge
->dev
, serverworks_private
.mm_addr_ofs
, &temp
);
273 temp
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
274 serverworks_private
.registers
= (volatile u8 __iomem
*) ioremap(temp
, 4096);
275 if (!serverworks_private
.registers
) {
276 dev_err(&agp_bridge
->dev
->dev
, "can't ioremap(%#x)\n", temp
);
280 writeb(0xA, serverworks_private
.registers
+SVWRKS_GART_CACHE
);
281 readb(serverworks_private
.registers
+SVWRKS_GART_CACHE
); /* PCI Posting. */
283 writel(agp_bridge
->gatt_bus_addr
, serverworks_private
.registers
+SVWRKS_GATTBASE
);
284 readl(serverworks_private
.registers
+SVWRKS_GATTBASE
); /* PCI Posting. */
286 cap_reg
= readw(serverworks_private
.registers
+SVWRKS_COMMAND
);
289 writew(cap_reg
, serverworks_private
.registers
+SVWRKS_COMMAND
);
290 readw(serverworks_private
.registers
+SVWRKS_COMMAND
);
292 pci_read_config_byte(serverworks_private
.svrwrks_dev
,SVWRKS_AGP_ENABLE
, &enable_reg
);
293 enable_reg
|= 0x1; /* Agp Enable bit */
294 pci_write_config_byte(serverworks_private
.svrwrks_dev
,SVWRKS_AGP_ENABLE
, enable_reg
);
295 serverworks_tlbflush(NULL
);
297 agp_bridge
->capndx
= pci_find_capability(serverworks_private
.svrwrks_dev
, PCI_CAP_ID_AGP
);
299 /* Fill in the mode register */
300 pci_read_config_dword(serverworks_private
.svrwrks_dev
,
301 agp_bridge
->capndx
+PCI_AGP_STATUS
, &agp_bridge
->mode
);
303 pci_read_config_byte(agp_bridge
->dev
, SVWRKS_CACHING
, &enable_reg
);
305 pci_write_config_byte(agp_bridge
->dev
, SVWRKS_CACHING
, enable_reg
);
307 pci_read_config_byte(agp_bridge
->dev
, SVWRKS_FEATURE
, &enable_reg
);
308 enable_reg
|= (1<<6);
309 pci_write_config_byte(agp_bridge
->dev
,SVWRKS_FEATURE
, enable_reg
);
314 static void serverworks_cleanup(void)
316 iounmap((void __iomem
*) serverworks_private
.registers
);
319 static int serverworks_insert_memory(struct agp_memory
*mem
,
320 off_t pg_start
, int type
)
322 int i
, j
, num_entries
;
323 unsigned long __iomem
*cur_gatt
;
326 num_entries
= A_SIZE_LVL2(agp_bridge
->current_size
)->num_entries
;
328 if (type
!= 0 || mem
->type
!= 0) {
331 if ((pg_start
+ mem
->page_count
) > num_entries
) {
336 while (j
< (pg_start
+ mem
->page_count
)) {
337 addr
= (j
* PAGE_SIZE
) + agp_bridge
->gart_bus_addr
;
338 cur_gatt
= SVRWRKS_GET_GATT(addr
);
339 if (!PGE_EMPTY(agp_bridge
, readl(cur_gatt
+GET_GATT_OFF(addr
))))
344 if (!mem
->is_flushed
) {
345 global_cache_flush();
346 mem
->is_flushed
= true;
349 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
350 addr
= (j
* PAGE_SIZE
) + agp_bridge
->gart_bus_addr
;
351 cur_gatt
= SVRWRKS_GET_GATT(addr
);
352 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
353 phys_to_gart(page_to_phys(mem
->pages
[i
])), mem
->type
),
354 cur_gatt
+GET_GATT_OFF(addr
));
356 serverworks_tlbflush(mem
);
360 static int serverworks_remove_memory(struct agp_memory
*mem
, off_t pg_start
,
364 unsigned long __iomem
*cur_gatt
;
367 if (type
!= 0 || mem
->type
!= 0) {
371 global_cache_flush();
372 serverworks_tlbflush(mem
);
374 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
375 addr
= (i
* PAGE_SIZE
) + agp_bridge
->gart_bus_addr
;
376 cur_gatt
= SVRWRKS_GET_GATT(addr
);
377 writel(agp_bridge
->scratch_page
, cur_gatt
+GET_GATT_OFF(addr
));
380 serverworks_tlbflush(mem
);
384 static const struct gatt_mask serverworks_masks
[] =
386 {.mask
= 1, .type
= 0}
389 static const struct aper_size_info_lvl2 serverworks_sizes
[7] =
391 {2048, 524288, 0x80000000},
392 {1024, 262144, 0xc0000000},
393 {512, 131072, 0xe0000000},
394 {256, 65536, 0xf0000000},
395 {128, 32768, 0xf8000000},
396 {64, 16384, 0xfc000000},
397 {32, 8192, 0xfe000000}
400 static void serverworks_agp_enable(struct agp_bridge_data
*bridge
, u32 mode
)
404 pci_read_config_dword(serverworks_private
.svrwrks_dev
,
405 bridge
->capndx
+ PCI_AGP_STATUS
,
408 command
= agp_collect_device_status(bridge
, mode
, command
);
410 command
&= ~0x10; /* disable FW */
415 pci_write_config_dword(serverworks_private
.svrwrks_dev
,
416 bridge
->capndx
+ PCI_AGP_COMMAND
,
419 agp_device_command(command
, false);
422 static const struct agp_bridge_driver sworks_driver
= {
423 .owner
= THIS_MODULE
,
424 .aperture_sizes
= serverworks_sizes
,
425 .size_type
= LVL2_APER_SIZE
,
426 .num_aperture_sizes
= 7,
427 .configure
= serverworks_configure
,
428 .fetch_size
= serverworks_fetch_size
,
429 .cleanup
= serverworks_cleanup
,
430 .tlb_flush
= serverworks_tlbflush
,
431 .mask_memory
= agp_generic_mask_memory
,
432 .masks
= serverworks_masks
,
433 .agp_enable
= serverworks_agp_enable
,
434 .cache_flush
= global_cache_flush
,
435 .create_gatt_table
= serverworks_create_gatt_table
,
436 .free_gatt_table
= serverworks_free_gatt_table
,
437 .insert_memory
= serverworks_insert_memory
,
438 .remove_memory
= serverworks_remove_memory
,
439 .alloc_by_type
= agp_generic_alloc_by_type
,
440 .free_by_type
= agp_generic_free_by_type
,
441 .agp_alloc_page
= agp_generic_alloc_page
,
442 .agp_alloc_pages
= agp_generic_alloc_pages
,
443 .agp_destroy_page
= agp_generic_destroy_page
,
444 .agp_destroy_pages
= agp_generic_destroy_pages
,
445 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
448 static int __devinit
agp_serverworks_probe(struct pci_dev
*pdev
,
449 const struct pci_device_id
*ent
)
451 struct agp_bridge_data
*bridge
;
452 struct pci_dev
*bridge_dev
;
456 cap_ptr
= pci_find_capability(pdev
, PCI_CAP_ID_AGP
);
458 switch (pdev
->device
) {
460 dev_err(&pdev
->dev
, "ServerWorks CNB20HE is unsupported due to lack of documentation\n");
463 case PCI_DEVICE_ID_SERVERWORKS_HE
:
464 case PCI_DEVICE_ID_SERVERWORKS_LE
:
470 dev_err(&pdev
->dev
, "unsupported Serverworks chipset "
471 "[%04x/%04x]\n", pdev
->vendor
, pdev
->device
);
475 /* Everything is on func 1 here so we are hardcoding function one */
476 bridge_dev
= pci_get_bus_and_slot((unsigned int)pdev
->bus
->number
,
479 dev_info(&pdev
->dev
, "can't find secondary device\n");
483 serverworks_private
.svrwrks_dev
= bridge_dev
;
484 serverworks_private
.gart_addr_ofs
= 0x10;
486 pci_read_config_dword(pdev
, SVWRKS_APSIZE
, &temp
);
487 if (temp
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
488 pci_read_config_dword(pdev
, SVWRKS_APSIZE
+ 4, &temp2
);
490 dev_info(&pdev
->dev
, "64 bit aperture address, "
491 "but top bits are not zero; disabling AGP\n");
494 serverworks_private
.mm_addr_ofs
= 0x18;
496 serverworks_private
.mm_addr_ofs
= 0x14;
498 pci_read_config_dword(pdev
, serverworks_private
.mm_addr_ofs
, &temp
);
499 if (temp
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
500 pci_read_config_dword(pdev
,
501 serverworks_private
.mm_addr_ofs
+ 4, &temp2
);
503 dev_info(&pdev
->dev
, "64 bit MMIO address, but top "
504 "bits are not zero; disabling AGP\n");
509 bridge
= agp_alloc_bridge();
513 bridge
->driver
= &sworks_driver
;
514 bridge
->dev_private_data
= &serverworks_private
,
515 bridge
->dev
= pci_dev_get(pdev
);
517 pci_set_drvdata(pdev
, bridge
);
518 return agp_add_bridge(bridge
);
521 static void __devexit
agp_serverworks_remove(struct pci_dev
*pdev
)
523 struct agp_bridge_data
*bridge
= pci_get_drvdata(pdev
);
525 pci_dev_put(bridge
->dev
);
526 agp_remove_bridge(bridge
);
527 agp_put_bridge(bridge
);
528 pci_dev_put(serverworks_private
.svrwrks_dev
);
529 serverworks_private
.svrwrks_dev
= NULL
;
532 static struct pci_device_id agp_serverworks_pci_table
[] = {
534 .class = (PCI_CLASS_BRIDGE_HOST
<< 8),
536 .vendor
= PCI_VENDOR_ID_SERVERWORKS
,
537 .device
= PCI_ANY_ID
,
538 .subvendor
= PCI_ANY_ID
,
539 .subdevice
= PCI_ANY_ID
,
544 MODULE_DEVICE_TABLE(pci
, agp_serverworks_pci_table
);
546 static struct pci_driver agp_serverworks_pci_driver
= {
547 .name
= "agpgart-serverworks",
548 .id_table
= agp_serverworks_pci_table
,
549 .probe
= agp_serverworks_probe
,
550 .remove
= agp_serverworks_remove
,
553 static int __init
agp_serverworks_init(void)
557 return pci_register_driver(&agp_serverworks_pci_driver
);
560 static void __exit
agp_serverworks_cleanup(void)
562 pci_unregister_driver(&agp_serverworks_pci_driver
);
565 module_init(agp_serverworks_init
);
566 module_exit(agp_serverworks_cleanup
);
568 MODULE_LICENSE("GPL and additional rights");